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[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8978.c
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0d34e915
GL		 1/*
2 * wm8978.c -- WM8978 ALSA SoC Audio Codec driver
3 *
4 * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
6 * Copyright 2006-2009 Wolfson Microelectronics PLC.
7 * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
5a0e3ad6 22#include <linux/slab.h>
0d34e915
GL		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
0d34e915
GL		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <asm/div64.h>
30
31#include "wm8978.h"
32
0d34e915
GL		 33/* wm8978 register cache. Note that register 0 is not included in the cache. */
34static const u16 wm8978_reg[WM8978_CACHEREGNUM] = {
35 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */
36 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */
37 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */
38 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */
39 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */
40 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */
41 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */
42 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */
43 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */
44 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */
45 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */
46 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */
47 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */
48 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */
49 0x0001, 0x0001, /* 0x38...0x3b */
50};
51
52/* codec private data */
53struct wm8978_priv {
f0fba2ad 54 enum snd_soc_control_type control_type;
0d34e915
GL		 55 unsigned int f_pllout;
56 unsigned int f_mclk;
57 unsigned int f_256fs;
58 unsigned int f_opclk;
b0580913 59 int mclk_idx;
0d34e915 60 enum wm8978_sysclk_src sysclk;
0d34e915
GL		 61};
62
63static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
64static const char *wm8978_eqmode[] = {"Capture", "Playback"};
65static const char *wm8978_bw[] = {"Narrow", "Wide"};
66static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
67static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
68static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
69static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
70static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
71static const char *wm8978_alc3[] = {"ALC", "Limiter"};
72static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
73
74static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
75 wm8978_companding);
76static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
77 wm8978_companding);
78static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
79static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
80static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
81static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
82static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
83static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
84static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
85static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
86static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
87static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
88static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
89
90static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
91static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
92static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
93static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
94static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
1916a2aa 95static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
0d34e915
GL		 96
97static const struct snd_kcontrol_new wm8978_snd_controls[] = {
98
99 SOC_SINGLE("Digital Loopback Switch",
100 WM8978_COMPANDING_CONTROL, 0, 1, 0),
101
102 SOC_ENUM("ADC Companding", adc_compand),
103 SOC_ENUM("DAC Companding", dac_compand),
104
105 SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
106
107 SOC_DOUBLE_R_TLV("PCM Volume",
108 WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
109 0, 255, 0, digital_tlv),
110
111 SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
112 SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
113 SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
114
115 SOC_DOUBLE_R_TLV("ADC Volume",
116 WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
117 0, 255, 0, digital_tlv),
118
119 SOC_ENUM("Equaliser Function", eqmode),
120 SOC_ENUM("EQ1 Cut Off", eq1),
121 SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv),
122
123 SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw),
124 SOC_ENUM("EQ2 Cut Off", eq2),
125 SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv),
126
127 SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw),
128 SOC_ENUM("EQ3 Cut Off", eq3),
129 SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv),
130
131 SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw),
132 SOC_ENUM("EQ4 Cut Off", eq4),
133 SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv),
134
135 SOC_ENUM("EQ5 Cut Off", eq5),
136 SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
137
138 SOC_SINGLE("DAC Playback Limiter Switch",
139 WM8978_DAC_LIMITER_1, 8, 1, 0),
140 SOC_SINGLE("DAC Playback Limiter Decay",
141 WM8978_DAC_LIMITER_1, 4, 15, 0),
142 SOC_SINGLE("DAC Playback Limiter Attack",
143 WM8978_DAC_LIMITER_1, 0, 15, 0),
144
145 SOC_SINGLE("DAC Playback Limiter Threshold",
146 WM8978_DAC_LIMITER_2, 4, 7, 0),
1916a2aa
MB		 147 SOC_SINGLE_TLV("DAC Playback Limiter Volume",
148 WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
0d34e915
GL		 149
150 SOC_ENUM("ALC Enable Switch", alc1),
151 SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
152 SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
153
c8fb034c 154 SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0),
0d34e915
GL		 155 SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
156
157 SOC_ENUM("ALC Capture Mode", alc3),
c8fb034c
MB		 158 SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0),
159 SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0),
0d34e915
GL		 160
161 SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
162 SOC_SINGLE("ALC Capture Noise Gate Threshold",
163 WM8978_NOISE_GATE, 0, 7, 0),
164
165 SOC_DOUBLE_R("Capture PGA ZC Switch",
166 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
167 7, 1, 0),
168
169 /* OUT1 - Headphones */
170 SOC_DOUBLE_R("Headphone Playback ZC Switch",
171 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
172
173 SOC_DOUBLE_R_TLV("Headphone Playback Volume",
174 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
175 0, 63, 0, spk_tlv),
176
177 /* OUT2 - Speakers */
178 SOC_DOUBLE_R("Speaker Playback ZC Switch",
179 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
180
181 SOC_DOUBLE_R_TLV("Speaker Playback Volume",
182 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
183 0, 63, 0, spk_tlv),
184
185 /* OUT3/4 - Line Output */
186 SOC_DOUBLE_R("Line Playback Switch",
187 WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
188
189 /* Mixer #3: Boost (Input) mixer */
190 SOC_DOUBLE_R("PGA Boost (+20dB)",
191 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
192 8, 1, 0),
193 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
194 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
195 4, 7, 0, boost_tlv),
196 SOC_DOUBLE_R_TLV("Aux Boost Volume",
197 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
198 0, 7, 0, boost_tlv),
199
200 /* Input PGA volume */
201 SOC_DOUBLE_R_TLV("Input PGA Volume",
202 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
203 0, 63, 0, inpga_tlv),
204
205 /* Headphone */
206 SOC_DOUBLE_R("Headphone Switch",
207 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
208
209 /* Speaker */
210 SOC_DOUBLE_R("Speaker Switch",
211 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
b2c3e923
GL		 212
213 /* DAC / ADC oversampling */
c8fb034c
MB		 214 SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL,
215 5, 1, 0),
216 SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL,
217 5, 1, 0),
0d34e915
GL		 218};
219
220/* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
221static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
222 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
223 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
224 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
225};
226
227static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
228 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
229 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
230 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
231};
232
233/* OUT3/OUT4 Mixer not implemented */
234
235/* Mixer #2: Input PGA Mute */
236static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
237 SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
238 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
239 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
240};
241static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
242 SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
243 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
244 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
245};
246
247static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
248 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
249 WM8978_POWER_MANAGEMENT_3, 0, 0),
250 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
251 WM8978_POWER_MANAGEMENT_3, 1, 0),
252 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
253 WM8978_POWER_MANAGEMENT_2, 0, 0),
254 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
255 WM8978_POWER_MANAGEMENT_2, 1, 0),
256
257 /* Mixer #1: OUT1,2 */
258 SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
259 2, 0, wm8978_left_out_mixer),
260 SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
261 3, 0, wm8978_right_out_mixer),
262
263 SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
264 2, 0, wm8978_left_input_mixer),
265 SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
266 3, 0, wm8978_right_input_mixer),
267
268 SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
269 4, 0, NULL, 0),
270 SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
271 5, 0, NULL, 0),
272
273 SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
274 6, 1, NULL, 0),
275 SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
276 6, 1, NULL, 0),
277
278 SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
279 7, 0, NULL, 0),
280 SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
281 8, 0, NULL, 0),
282
283 SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
284 6, 0, NULL, 0),
285 SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
286 5, 0, NULL, 0),
287
288 SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
289 8, 0, NULL, 0),
290
291 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
292
293 SND_SOC_DAPM_INPUT("LMICN"),
294 SND_SOC_DAPM_INPUT("LMICP"),
295 SND_SOC_DAPM_INPUT("RMICN"),
296 SND_SOC_DAPM_INPUT("RMICP"),
297 SND_SOC_DAPM_INPUT("LAUX"),
298 SND_SOC_DAPM_INPUT("RAUX"),
299 SND_SOC_DAPM_INPUT("L2"),
300 SND_SOC_DAPM_INPUT("R2"),
301 SND_SOC_DAPM_OUTPUT("LHP"),
302 SND_SOC_DAPM_OUTPUT("RHP"),
303 SND_SOC_DAPM_OUTPUT("LSPK"),
304 SND_SOC_DAPM_OUTPUT("RSPK"),
305};
306
307static const struct snd_soc_dapm_route audio_map[] = {
308 /* Output mixer */
309 {"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
310 {"Right Output Mixer", "Aux Playback Switch", "RAUX"},
311 {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
312
313 {"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
314 {"Left Output Mixer", "Aux Playback Switch", "LAUX"},
315 {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
316
317 /* Outputs */
318 {"Right Headphone Out", NULL, "Right Output Mixer"},
319 {"RHP", NULL, "Right Headphone Out"},
320
321 {"Left Headphone Out", NULL, "Left Output Mixer"},
322 {"LHP", NULL, "Left Headphone Out"},
323
324 {"Right Speaker Out", NULL, "Right Output Mixer"},
325 {"RSPK", NULL, "Right Speaker Out"},
326
327 {"Left Speaker Out", NULL, "Left Output Mixer"},
328 {"LSPK", NULL, "Left Speaker Out"},
329
330 /* Boost Mixer */
331 {"Right ADC", NULL, "Right Boost Mixer"},
332
333 {"Right Boost Mixer", NULL, "RAUX"},
334 {"Right Boost Mixer", NULL, "Right Capture PGA"},
335 {"Right Boost Mixer", NULL, "R2"},
336
337 {"Left ADC", NULL, "Left Boost Mixer"},
338
339 {"Left Boost Mixer", NULL, "LAUX"},
340 {"Left Boost Mixer", NULL, "Left Capture PGA"},
341 {"Left Boost Mixer", NULL, "L2"},
342
343 /* Input PGA */
344 {"Right Capture PGA", NULL, "Right Input Mixer"},
345 {"Left Capture PGA", NULL, "Left Input Mixer"},
346
347 {"Right Input Mixer", "R2 Switch", "R2"},
348 {"Right Input Mixer", "MicN Switch", "RMICN"},
349 {"Right Input Mixer", "MicP Switch", "RMICP"},
350
351 {"Left Input Mixer", "L2 Switch", "L2"},
352 {"Left Input Mixer", "MicN Switch", "LMICN"},
353 {"Left Input Mixer", "MicP Switch", "LMICP"},
354};
355
356static int wm8978_add_widgets(struct snd_soc_codec *codec)
357{
ce6120cc 358 struct snd_soc_dapm_context *dapm = &codec->dapm;
0d34e915 359
ce6120cc
LG		 360 snd_soc_dapm_new_controls(dapm, wm8978_dapm_widgets,
361 ARRAY_SIZE(wm8978_dapm_widgets));
0d34e915 362 /* set up the WM8978 audio map */
ce6120cc 363 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
0d34e915
GL		 364
365 return 0;
366}
367
368/* PLL divisors */
369struct wm8978_pll_div {
370 u32 k;
371 u8 n;
372 u8 div2;
373};
374
375#define FIXED_PLL_SIZE (1 << 24)
376
f0fba2ad
LG		 377static void pll_factors(struct snd_soc_codec *codec,
378 struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source)
0d34e915
GL		 379{
380 u64 k_part;
381 unsigned int k, n_div, n_mod;
382
383 n_div = target / source;
384 if (n_div < 6) {
385 source >>= 1;
386 pll_div->div2 = 1;
387 n_div = target / source;
388 } else {
389 pll_div->div2 = 0;
390 }
391
392 if (n_div < 6 || n_div > 12)
f0fba2ad 393 dev_warn(codec->dev,
0d34e915
GL		 394 "WM8978 N value exceeds recommended range! N = %u\n",
395 n_div);
396
397 pll_div->n = n_div;
398 n_mod = target - source * n_div;
399 k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
400
401 do_div(k_part, source);
402
403 k = k_part & 0xFFFFFFFF;
404
405 pll_div->k = k;
406}
b0580913
GL		 407
408/* MCLK dividers */
409static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12};
410static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1};
411
412/*
413 * find index >= idx, such that, for a given f_out,
414 * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
415 * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
416 * generalised for f_opclk with suitable coefficient arrays, but currently
417 * the OPCLK divisor is calculated directly, not iteratively.
418 */
419static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
420 unsigned int *f_pllout)
421{
422 int i;
423
424 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
425 unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
426 mclk_denominator[i];
427 if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
428 *f_pllout = f_pllout_x4 / 4;
429 return i;
430 }
431 }
432
433 return -EINVAL;
434}
435
0d34e915
GL		 436/*
437 * Calculate internal frequencies and dividers, according to Figure 40
438 * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
439 */
440static int wm8978_configure_pll(struct snd_soc_codec *codec)
441{
b2c812e2 442 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 443 struct wm8978_pll_div pll_div;
444 unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
445 f_256fs = wm8978->f_256fs;
b0580913 446 unsigned int f2;
0d34e915
GL		 447
448 if (!f_mclk)
449 return -EINVAL;
450
451 if (f_opclk) {
b0580913
GL		 452 unsigned int opclk_div;
453 /* Cannot set up MCLK divider now, do later */
454 wm8978->mclk_idx = -1;
455
0d34e915
GL		 456 /*
457 * The user needs OPCLK. Choose OPCLKDIV to put
458 * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
459 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
460 * prescale = 1, or prescale = 2. Prescale is calculated inside
461 * pll_factors(). We have to select f_PLLOUT, such that
462 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
463 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
464 */
465 if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
466 return -EINVAL;
467
468 if (4 * f_opclk < 3 * f_mclk)
469 /* Have to use OPCLKDIV */
470 opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
471 else
472 opclk_div = 1;
473
474 dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
475
476 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30,
477 (opclk_div - 1) << 4);
478
479 wm8978->f_pllout = f_opclk * opclk_div;
480 } else if (f_256fs) {
481 /*
b0580913 482 * Not using OPCLK, but PLL is used for the codec, choose R:
0d34e915
GL		 483 * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
484 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
485 * prescale = 1, or prescale = 2. Prescale is calculated inside
486 * pll_factors(). We have to select f_PLLOUT, such that
487 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
488 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
489 * must be 3.781MHz <= f_MCLK <= 32.768MHz
490 */
b0580913
GL		 491 int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
492 if (idx < 0)
493 return idx;
0d34e915 494
b0580913 495 wm8978->mclk_idx = idx;
0d34e915
GL		 496
497 /* GPIO1 into default mode as input - before configuring PLL */
498 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
499 } else {
500 return -EINVAL;
501 }
502
503 f2 = wm8978->f_pllout * 4;
504
505 dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
506 wm8978->f_mclk, wm8978->f_pllout);
507
f0fba2ad 508 pll_factors(codec, &pll_div, f2, wm8978->f_mclk);
0d34e915
GL		 509
510 dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
511 __func__, pll_div.n, pll_div.k, pll_div.div2);
512
513 /* Turn PLL off for configuration... */
514 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
515
516 snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
517 snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18);
518 snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
519 snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff);
520
521 /* ...and on again */
522 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
523
524 if (f_opclk)
525 /* Output PLL (OPCLK) to GPIO1 */
526 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4);
527
528 return 0;
529}
530
531/*
532 * Configure WM8978 clock dividers.
533 */
534static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
535 int div_id, int div)
536{
537 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 538 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 539 int ret = 0;
540
541 switch (div_id) {
542 case WM8978_OPCLKRATE:
543 wm8978->f_opclk = div;
544
545 if (wm8978->f_mclk)
b0580913
GL		 546 /*
547 * We know the MCLK frequency, the user has requested
548 * OPCLK, configure the PLL based on that and start it
549 * and OPCLK immediately. We will configure PLL to match
550 * user-requested OPCLK frquency as good as possible.
551 * In fact, it is likely, that matching the sampling
552 * rate, when it becomes known, is more important, and
553 * we will not be reconfiguring PLL then, because we
554 * must not interrupt OPCLK. But it should be fine,
555 * because typically the user will request OPCLK to run
556 * at 256fs or 512fs, and for these cases we will also
557 * find an exact MCLK divider configuration - it will
558 * be equal to or double the OPCLK divisor.
559 */
0d34e915
GL		 560 ret = wm8978_configure_pll(codec);
561 break;
0d34e915
GL		 562 case WM8978_BCLKDIV:
563 if (div & ~0x1c)
564 return -EINVAL;
565 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div);
566 break;
567 default:
568 return -EINVAL;
569 }
570
571 dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
572
573 return ret;
574}
575
576/*
577 * @freq: when .set_pll() us not used, freq is codec MCLK input frequency
578 */
579static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
580 unsigned int freq, int dir)
581{
582 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 583 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 584 int ret = 0;
585
586 dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
587
588 if (freq) {
589 wm8978->f_mclk = freq;
590
591 /* Even if MCLK is used for system clock, might have to drive OPCLK */
592 if (wm8978->f_opclk)
593 ret = wm8978_configure_pll(codec);
594
595 /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */
596
597 if (!ret)
598 wm8978->sysclk = clk_id;
599 }
600
601 if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
602 /* Clock CODEC directly from MCLK */
603 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
604
605 /* GPIO1 into default mode as input - before configuring PLL */
606 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
607
608 /* Turn off PLL */
609 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
610 wm8978->sysclk = WM8978_MCLK;
611 wm8978->f_pllout = 0;
612 wm8978->f_opclk = 0;
613 }
614
615 return ret;
616}
617
618/*
619 * Set ADC and Voice DAC format.
620 */
621static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
622{
623 struct snd_soc_codec *codec = codec_dai->codec;
624 /*
625 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
626 * Data Format mask = 0x18: all will be calculated anew
627 */
628 u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198;
629 u16 clk = snd_soc_read(codec, WM8978_CLOCKING);
630
631 dev_dbg(codec->dev, "%s\n", __func__);
632
633 /* set master/slave audio interface */
634 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
635 case SND_SOC_DAIFMT_CBM_CFM:
636 clk |= 1;
637 break;
638 case SND_SOC_DAIFMT_CBS_CFS:
639 clk &= ~1;
640 break;
641 default:
642 return -EINVAL;
643 }
644
645 /* interface format */
646 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
647 case SND_SOC_DAIFMT_I2S:
648 iface |= 0x10;
649 break;
650 case SND_SOC_DAIFMT_RIGHT_J:
651 break;
652 case SND_SOC_DAIFMT_LEFT_J:
653 iface |= 0x8;
654 break;
655 case SND_SOC_DAIFMT_DSP_A:
656 iface |= 0x18;
657 break;
658 default:
659 return -EINVAL;
660 }
661
662 /* clock inversion */
663 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
664 case SND_SOC_DAIFMT_NB_NF:
665 break;
666 case SND_SOC_DAIFMT_IB_IF:
667 iface |= 0x180;
668 break;
669 case SND_SOC_DAIFMT_IB_NF:
670 iface |= 0x100;
671 break;
672 case SND_SOC_DAIFMT_NB_IF:
673 iface |= 0x80;
674 break;
675 default:
676 return -EINVAL;
677 }
678
679 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface);
680 snd_soc_write(codec, WM8978_CLOCKING, clk);
681
682 return 0;
683}
684
0d34e915
GL		 685/*
686 * Set PCM DAI bit size and sample rate.
687 */
688static int wm8978_hw_params(struct snd_pcm_substream *substream,
689 struct snd_pcm_hw_params *params,
690 struct snd_soc_dai *dai)
691{
692 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 693 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 694 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 695 /* Word length mask = 0x60 */
696 u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
697 /* Sampling rate mask = 0xe (for filters) */
698 u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe;
699 u16 clking = snd_soc_read(codec, WM8978_CLOCKING);
700 enum wm8978_sysclk_src current_clk_id = clking & 0x100 ?
701 WM8978_PLL : WM8978_MCLK;
702 unsigned int f_sel, diff, diff_best = INT_MAX;
703 int i, best = 0;
704
705 if (!wm8978->f_mclk)
706 return -EINVAL;
707
708 /* bit size */
709 switch (params_format(params)) {
710 case SNDRV_PCM_FORMAT_S16_LE:
711 break;
712 case SNDRV_PCM_FORMAT_S20_3LE:
713 iface_ctl |= 0x20;
714 break;
715 case SNDRV_PCM_FORMAT_S24_LE:
716 iface_ctl |= 0x40;
717 break;
718 case SNDRV_PCM_FORMAT_S32_LE:
719 iface_ctl |= 0x60;
720 break;
721 }
722
723 /* filter coefficient */
724 switch (params_rate(params)) {
725 case 8000:
726 add_ctl |= 0x5 << 1;
727 break;
728 case 11025:
729 add_ctl |= 0x4 << 1;
730 break;
731 case 16000:
732 add_ctl |= 0x3 << 1;
733 break;
734 case 22050:
735 add_ctl |= 0x2 << 1;
736 break;
737 case 32000:
738 add_ctl |= 0x1 << 1;
739 break;
740 case 44100:
741 case 48000:
742 break;
743 }
744
745 /* Sampling rate is known now, can configure the MCLK divider */
746 wm8978->f_256fs = params_rate(params) * 256;
747
748 if (wm8978->sysclk == WM8978_MCLK) {
b0580913 749 wm8978->mclk_idx = -1;
0d34e915
GL		 750 f_sel = wm8978->f_mclk;
751 } else {
752 if (!wm8978->f_pllout) {
b0580913 753 /* We only enter here, if OPCLK is not used */
0d34e915
GL		 754 int ret = wm8978_configure_pll(codec);
755 if (ret < 0)
756 return ret;
757 }
758 f_sel = wm8978->f_pllout;
759 }
760
b0580913
GL		 761 if (wm8978->mclk_idx < 0) {
762 /* Either MCLK is used directly, or OPCLK is used */
763 if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
764 return -EINVAL;
0d34e915 765
b0580913
GL		 766 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
767 diff = abs(wm8978->f_256fs * 3 -
768 f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
0d34e915 769
b0580913
GL		 770 if (diff < diff_best) {
771 diff_best = diff;
772 best = i;
773 }
0d34e915 774
b0580913
GL		 775 if (!diff)
776 break;
777 }
778 } else {
779 /* OPCLK not used, codec driven by PLL */
780 best = wm8978->mclk_idx;
781 diff = 0;
0d34e915
GL		 782 }
783
784 if (diff)
b0580913
GL		 785 dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n",
786 f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
787 wm8978->sysclk == WM8978_MCLK ?
788 ", consider using PLL" : "");
0d34e915
GL		 789
790 dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__,
791 params_format(params), params_rate(params), best);
792
793 /* MCLK divisor mask = 0xe0 */
794 snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5);
795
796 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl);
797 snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl);
798
799 if (wm8978->sysclk != current_clk_id) {
800 if (wm8978->sysclk == WM8978_PLL)
801 /* Run CODEC from PLL instead of MCLK */
802 snd_soc_update_bits(codec, WM8978_CLOCKING,
803 0x100, 0x100);
804 else
805 /* Clock CODEC directly from MCLK */
806 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
807 }
808
809 return 0;
810}
811
812static int wm8978_mute(struct snd_soc_dai *dai, int mute)
813{
814 struct snd_soc_codec *codec = dai->codec;
815
816 dev_dbg(codec->dev, "%s: %d\n", __func__, mute);
817
818 if (mute)
819 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40);
820 else
821 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0);
822
823 return 0;
824}
825
826static int wm8978_set_bias_level(struct snd_soc_codec *codec,
827 enum snd_soc_bias_level level)
828{
829 u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3;
830
831 switch (level) {
832 case SND_SOC_BIAS_ON:
833 case SND_SOC_BIAS_PREPARE:
834 power1 |= 1; /* VMID 75k */
835 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
836 break;
837 case SND_SOC_BIAS_STANDBY:
838 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
839 power1 |= 0xc;
840
ce6120cc 841 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0d34e915
GL		 842 /* Initial cap charge at VMID 5k */
843 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
844 power1 | 0x3);
845 mdelay(100);
846 }
847
848 power1 |= 0x2; /* VMID 500k */
849 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
850 break;
851 case SND_SOC_BIAS_OFF:
852 /* Preserve PLL - OPCLK may be used by someone */
853 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
854 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0);
855 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0);
856 break;
857 }
858
859 dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
860
ce6120cc 861 codec->dapm.bias_level = level;
0d34e915
GL		 862 return 0;
863}
864
865#define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
866 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
867
868static struct snd_soc_dai_ops wm8978_dai_ops = {
869 .hw_params = wm8978_hw_params,
870 .digital_mute = wm8978_mute,
871 .set_fmt = wm8978_set_dai_fmt,
872 .set_clkdiv = wm8978_set_dai_clkdiv,
873 .set_sysclk = wm8978_set_dai_sysclk,
874};
875
876/* Also supports 12kHz */
f0fba2ad
LG		 877static struct snd_soc_dai_driver wm8978_dai = {
878 .name = "wm8978-hifi",
0d34e915
GL		 879 .playback = {
880 .stream_name = "Playback",
881 .channels_min = 1,
882 .channels_max = 2,
883 .rates = SNDRV_PCM_RATE_8000_48000,
884 .formats = WM8978_FORMATS,
885 },
886 .capture = {
887 .stream_name = "Capture",
888 .channels_min = 1,
889 .channels_max = 2,
890 .rates = SNDRV_PCM_RATE_8000_48000,
891 .formats = WM8978_FORMATS,
892 },
893 .ops = &wm8978_dai_ops,
894};
0d34e915 895
f0fba2ad 896static int wm8978_suspend(struct snd_soc_codec *codec, pm_message_t state)
0d34e915 897{
0d34e915
GL		 898 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
899 /* Also switch PLL off */
900 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0);
0d34e915
GL		 901
902 return 0;
903}
904
f0fba2ad 905static int wm8978_resume(struct snd_soc_codec *codec)
0d34e915 906{
b2c812e2 907 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 908 int i;
909 u16 *cache = codec->reg_cache;
910
0d34e915
GL		 911 /* Sync reg_cache with the hardware */
912 for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) {
913 if (i == WM8978_RESET)
914 continue;
915 if (cache[i] != wm8978_reg[i])
916 snd_soc_write(codec, i, cache[i]);
917 }
918
919 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
920
921 if (wm8978->f_pllout)
922 /* Switch PLL on */
923 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
924
925 return 0;
926}
927
0d34e915
GL		 928/*
929 * These registers contain an "update" bit - bit 8. This means, for example,
930 * that one can write new DAC digital volume for both channels, but only when
931 * the update bit is set, will also the volume be updated - simultaneously for
932 * both channels.
933 */
934static const int update_reg[] = {
935 WM8978_LEFT_DAC_DIGITAL_VOLUME,
936 WM8978_RIGHT_DAC_DIGITAL_VOLUME,
937 WM8978_LEFT_ADC_DIGITAL_VOLUME,
938 WM8978_RIGHT_ADC_DIGITAL_VOLUME,
939 WM8978_LEFT_INP_PGA_CONTROL,
940 WM8978_RIGHT_INP_PGA_CONTROL,
941 WM8978_LOUT1_HP_CONTROL,
942 WM8978_ROUT1_HP_CONTROL,
943 WM8978_LOUT2_SPK_CONTROL,
944 WM8978_ROUT2_SPK_CONTROL,
945};
946
f0fba2ad 947static int wm8978_probe(struct snd_soc_codec *codec)
0d34e915 948{
f0fba2ad
LG		 949 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
950 int ret = 0, i;
0d34e915
GL		 951
952 /*
953 * Set default system clock to PLL, it is more precise, this is also the
954 * default hardware setting
955 */
956 wm8978->sysclk = WM8978_PLL;
0d34e915
GL		 957 ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
958 if (ret < 0) {
959 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 960 return ret;
0d34e915
GL		 961 }
962
0d34e915
GL		 963 /*
964 * Set the update bit in all registers, that have one. This way all
965 * writes to those registers will also cause the update bit to be
966 * written.
967 */
968 for (i = 0; i < ARRAY_SIZE(update_reg); i++)
a1b3b5ee 969 snd_soc_update_bits(codec, update_reg[i], 0x100, 0x100);
0d34e915
GL		 970
971 /* Reset the codec */
972 ret = snd_soc_write(codec, WM8978_RESET, 0);
973 if (ret < 0) {
974 dev_err(codec->dev, "Failed to issue reset\n");
f0fba2ad 975 return ret;
0d34e915
GL		 976 }
977
0d34e915
GL		 978 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
979
f0fba2ad
LG		 980 snd_soc_add_controls(codec, wm8978_snd_controls,
981 ARRAY_SIZE(wm8978_snd_controls));
982 wm8978_add_widgets(codec);
0d34e915
GL		 983
984 return 0;
0d34e915
GL		 985}
986
f0fba2ad
LG		 987/* power down chip */
988static int wm8978_remove(struct snd_soc_codec *codec)
0d34e915 989{
f0fba2ad
LG		 990 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
991 return 0;
0d34e915
GL		 992}
993
f0fba2ad
LG		 994static struct snd_soc_codec_driver soc_codec_dev_wm8978 = {
995 .probe = wm8978_probe,
996 .remove = wm8978_remove,
997 .suspend = wm8978_suspend,
998 .resume = wm8978_resume,
999 .set_bias_level = wm8978_set_bias_level,
1000 .reg_cache_size = ARRAY_SIZE(wm8978_reg),
1001 .reg_word_size = sizeof(u16),
1002 .reg_cache_default = wm8978_reg,
1003};
1004
1005#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
0d34e915
GL		 1006static __devinit int wm8978_i2c_probe(struct i2c_client *i2c,
1007 const struct i2c_device_id *id)
1008{
1009 struct wm8978_priv *wm8978;
f0fba2ad 1010 int ret;
0d34e915
GL		 1011
1012 wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL);
1013 if (wm8978 == NULL)
1014 return -ENOMEM;
1015
0d34e915 1016 i2c_set_clientdata(i2c, wm8978);
0d34e915 1017
f0fba2ad
LG		 1018 ret = snd_soc_register_codec(&i2c->dev,
1019 &soc_codec_dev_wm8978, &wm8978_dai, 1);
d484366b
AL		 1020 if (ret < 0)
1021 kfree(wm8978);
d484366b 1022 return ret;
0d34e915
GL		 1023}
1024
1025static __devexit int wm8978_i2c_remove(struct i2c_client *client)
1026{
f0fba2ad
LG		 1027 snd_soc_unregister_codec(&client->dev);
1028 kfree(i2c_get_clientdata(client));
0d34e915
GL		 1029 return 0;
1030}
1031
1032static const struct i2c_device_id wm8978_i2c_id[] = {
1033 { "wm8978", 0 },
1034 { }
1035};
1036MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
1037
1038static struct i2c_driver wm8978_i2c_driver = {
1039 .driver = {
5250a503 1040 .name = "wm8978",
0d34e915
GL		 1041 .owner = THIS_MODULE,
1042 },
1043 .probe = wm8978_i2c_probe,
1044 .remove = __devexit_p(wm8978_i2c_remove),
1045 .id_table = wm8978_i2c_id,
1046};
f0fba2ad 1047#endif
0d34e915
GL		 1048
1049static int __init wm8978_modinit(void)
1050{
f0fba2ad
LG		 1051 int ret = 0;
1052#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1053 ret = i2c_add_driver(&wm8978_i2c_driver);
1054 if (ret != 0) {
1055 printk(KERN_ERR "Failed to register WM8978 I2C driver: %d\n",
1056 ret);
1057 }
1058#endif
1059 return ret;
0d34e915
GL		 1060}
1061module_init(wm8978_modinit);
1062
1063static void __exit wm8978_exit(void)
1064{
f0fba2ad 1065#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
0d34e915 1066 i2c_del_driver(&wm8978_i2c_driver);
f0fba2ad 1067#endif
0d34e915
GL		 1068}
1069module_exit(wm8978_exit);
1070
1071MODULE_DESCRIPTION("ASoC WM8978 codec driver");
1072MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1073MODULE_LICENSE("GPL");
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