projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 6b3860b0 DP |
1 | /* |
| 2 | * wm8983.c -- WM8983 ALSA SoC Audio driver | |
| 3 | * | |
| 4 | * Copyright 2011 Wolfson Microelectronics plc | |
| 5 | * | |
| 6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/module.h> | |
| 14 | #include <linux/moduleparam.h> | |
| 15 | #include <linux/init.h> | |
| 16 | #include <linux/delay.h> | |
| 17 | #include <linux/pm.h> | |
| 18 | #include <linux/i2c.h> | |
| 2ee01ac6 | 19 | #include <linux/regmap.h> |
| 6b3860b0 DP |
20 | #include <linux/spi/spi.h> |
| 21 | #include <linux/slab.h> | |
| 22 | #include <sound/core.h> | |
| 23 | #include <sound/pcm.h> | |
| 24 | #include <sound/pcm_params.h> | |
| 25 | #include <sound/soc.h> | |
| 26 | #include <sound/initval.h> | |
| 27 | #include <sound/tlv.h> | |
| 28 | ||
| 29 | #include "wm8983.h" | |
| 30 | ||
| 2ee01ac6 MB |
31 | static const struct reg_default wm8983_defaults[] = { |
| 32 | { 0x01, 0x0000 }, /* R1 - Power management 1 */ | |
| 33 | { 0x02, 0x0000 }, /* R2 - Power management 2 */ | |
| 34 | { 0x03, 0x0000 }, /* R3 - Power management 3 */ | |
| 35 | { 0x04, 0x0050 }, /* R4 - Audio Interface */ | |
| 36 | { 0x05, 0x0000 }, /* R5 - Companding control */ | |
| 37 | { 0x06, 0x0140 }, /* R6 - Clock Gen control */ | |
| 38 | { 0x07, 0x0000 }, /* R7 - Additional control */ | |
| 39 | { 0x08, 0x0000 }, /* R8 - GPIO Control */ | |
| 40 | { 0x09, 0x0000 }, /* R9 - Jack Detect Control 1 */ | |
| 41 | { 0x0A, 0x0000 }, /* R10 - DAC Control */ | |
| 42 | { 0x0B, 0x00FF }, /* R11 - Left DAC digital Vol */ | |
| 43 | { 0x0C, 0x00FF }, /* R12 - Right DAC digital vol */ | |
| 44 | { 0x0D, 0x0000 }, /* R13 - Jack Detect Control 2 */ | |
| 45 | { 0x0E, 0x0100 }, /* R14 - ADC Control */ | |
| 46 | { 0x0F, 0x00FF }, /* R15 - Left ADC Digital Vol */ | |
| 47 | { 0x10, 0x00FF }, /* R16 - Right ADC Digital Vol */ | |
| 48 | { 0x12, 0x012C }, /* R18 - EQ1 - low shelf */ | |
| 49 | { 0x13, 0x002C }, /* R19 - EQ2 - peak 1 */ | |
| 50 | { 0x14, 0x002C }, /* R20 - EQ3 - peak 2 */ | |
| 51 | { 0x15, 0x002C }, /* R21 - EQ4 - peak 3 */ | |
| 52 | { 0x16, 0x002C }, /* R22 - EQ5 - high shelf */ | |
| 53 | { 0x18, 0x0032 }, /* R24 - DAC Limiter 1 */ | |
| 54 | { 0x19, 0x0000 }, /* R25 - DAC Limiter 2 */ | |
| 55 | { 0x1B, 0x0000 }, /* R27 - Notch Filter 1 */ | |
| 56 | { 0x1C, 0x0000 }, /* R28 - Notch Filter 2 */ | |
| 57 | { 0x1D, 0x0000 }, /* R29 - Notch Filter 3 */ | |
| 58 | { 0x1E, 0x0000 }, /* R30 - Notch Filter 4 */ | |
| 59 | { 0x20, 0x0038 }, /* R32 - ALC control 1 */ | |
| 60 | { 0x21, 0x000B }, /* R33 - ALC control 2 */ | |
| 61 | { 0x22, 0x0032 }, /* R34 - ALC control 3 */ | |
| 62 | { 0x23, 0x0000 }, /* R35 - Noise Gate */ | |
| 63 | { 0x24, 0x0008 }, /* R36 - PLL N */ | |
| 64 | { 0x25, 0x000C }, /* R37 - PLL K 1 */ | |
| 65 | { 0x26, 0x0093 }, /* R38 - PLL K 2 */ | |
| 66 | { 0x27, 0x00E9 }, /* R39 - PLL K 3 */ | |
| 67 | { 0x29, 0x0000 }, /* R41 - 3D control */ | |
| 68 | { 0x2A, 0x0000 }, /* R42 - OUT4 to ADC */ | |
| 69 | { 0x2B, 0x0000 }, /* R43 - Beep control */ | |
| 70 | { 0x2C, 0x0033 }, /* R44 - Input ctrl */ | |
| 71 | { 0x2D, 0x0010 }, /* R45 - Left INP PGA gain ctrl */ | |
| 72 | { 0x2E, 0x0010 }, /* R46 - Right INP PGA gain ctrl */ | |
| 73 | { 0x2F, 0x0100 }, /* R47 - Left ADC BOOST ctrl */ | |
| 74 | { 0x30, 0x0100 }, /* R48 - Right ADC BOOST ctrl */ | |
| 75 | { 0x31, 0x0002 }, /* R49 - Output ctrl */ | |
| 76 | { 0x32, 0x0001 }, /* R50 - Left mixer ctrl */ | |
| 77 | { 0x33, 0x0001 }, /* R51 - Right mixer ctrl */ | |
| 78 | { 0x34, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */ | |
| 79 | { 0x35, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */ | |
| 80 | { 0x36, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */ | |
| 81 | { 0x37, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */ | |
| 82 | { 0x38, 0x0001 }, /* R56 - OUT3 mixer ctrl */ | |
| 83 | { 0x39, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */ | |
| 84 | { 0x3D, 0x0000 }, /* R61 - BIAS CTRL */ | |
| 6b3860b0 DP |
85 | }; |
| 86 | ||
| 87 | static const struct wm8983_reg_access { | |
| 88 | u16 read; /* Mask of readable bits */ | |
| 89 | u16 write; /* Mask of writable bits */ | |
| 90 | } wm8983_access_masks[WM8983_MAX_REGISTER + 1] = { | |
| 91 | [0x00] = { 0x0000, 0x01FF }, /* R0 - Software Reset */ | |
| 92 | [0x01] = { 0x0000, 0x01FF }, /* R1 - Power management 1 */ | |
| 93 | [0x02] = { 0x0000, 0x01FF }, /* R2 - Power management 2 */ | |
| 94 | [0x03] = { 0x0000, 0x01EF }, /* R3 - Power management 3 */ | |
| 95 | [0x04] = { 0x0000, 0x01FF }, /* R4 - Audio Interface */ | |
| 96 | [0x05] = { 0x0000, 0x003F }, /* R5 - Companding control */ | |
| 97 | [0x06] = { 0x0000, 0x01FD }, /* R6 - Clock Gen control */ | |
| 98 | [0x07] = { 0x0000, 0x000F }, /* R7 - Additional control */ | |
| 99 | [0x08] = { 0x0000, 0x003F }, /* R8 - GPIO Control */ | |
| 100 | [0x09] = { 0x0000, 0x0070 }, /* R9 - Jack Detect Control 1 */ | |
| 101 | [0x0A] = { 0x0000, 0x004F }, /* R10 - DAC Control */ | |
| 102 | [0x0B] = { 0x0000, 0x01FF }, /* R11 - Left DAC digital Vol */ | |
| 103 | [0x0C] = { 0x0000, 0x01FF }, /* R12 - Right DAC digital vol */ | |
| 104 | [0x0D] = { 0x0000, 0x00FF }, /* R13 - Jack Detect Control 2 */ | |
| 105 | [0x0E] = { 0x0000, 0x01FB }, /* R14 - ADC Control */ | |
| 106 | [0x0F] = { 0x0000, 0x01FF }, /* R15 - Left ADC Digital Vol */ | |
| 107 | [0x10] = { 0x0000, 0x01FF }, /* R16 - Right ADC Digital Vol */ | |
| 108 | [0x12] = { 0x0000, 0x017F }, /* R18 - EQ1 - low shelf */ | |
| 109 | [0x13] = { 0x0000, 0x017F }, /* R19 - EQ2 - peak 1 */ | |
| 110 | [0x14] = { 0x0000, 0x017F }, /* R20 - EQ3 - peak 2 */ | |
| 111 | [0x15] = { 0x0000, 0x017F }, /* R21 - EQ4 - peak 3 */ | |
| 112 | [0x16] = { 0x0000, 0x007F }, /* R22 - EQ5 - high shelf */ | |
| 113 | [0x18] = { 0x0000, 0x01FF }, /* R24 - DAC Limiter 1 */ | |
| 114 | [0x19] = { 0x0000, 0x007F }, /* R25 - DAC Limiter 2 */ | |
| 115 | [0x1B] = { 0x0000, 0x01FF }, /* R27 - Notch Filter 1 */ | |
| 116 | [0x1C] = { 0x0000, 0x017F }, /* R28 - Notch Filter 2 */ | |
| 117 | [0x1D] = { 0x0000, 0x017F }, /* R29 - Notch Filter 3 */ | |
| 118 | [0x1E] = { 0x0000, 0x017F }, /* R30 - Notch Filter 4 */ | |
| 119 | [0x20] = { 0x0000, 0x01BF }, /* R32 - ALC control 1 */ | |
| 120 | [0x21] = { 0x0000, 0x00FF }, /* R33 - ALC control 2 */ | |
| 121 | [0x22] = { 0x0000, 0x01FF }, /* R34 - ALC control 3 */ | |
| 122 | [0x23] = { 0x0000, 0x000F }, /* R35 - Noise Gate */ | |
| 123 | [0x24] = { 0x0000, 0x001F }, /* R36 - PLL N */ | |
| 124 | [0x25] = { 0x0000, 0x003F }, /* R37 - PLL K 1 */ | |
| 125 | [0x26] = { 0x0000, 0x01FF }, /* R38 - PLL K 2 */ | |
| 126 | [0x27] = { 0x0000, 0x01FF }, /* R39 - PLL K 3 */ | |
| 127 | [0x29] = { 0x0000, 0x000F }, /* R41 - 3D control */ | |
| 128 | [0x2A] = { 0x0000, 0x01E7 }, /* R42 - OUT4 to ADC */ | |
| 129 | [0x2B] = { 0x0000, 0x01BF }, /* R43 - Beep control */ | |
| 130 | [0x2C] = { 0x0000, 0x0177 }, /* R44 - Input ctrl */ | |
| 131 | [0x2D] = { 0x0000, 0x01FF }, /* R45 - Left INP PGA gain ctrl */ | |
| 132 | [0x2E] = { 0x0000, 0x01FF }, /* R46 - Right INP PGA gain ctrl */ | |
| 133 | [0x2F] = { 0x0000, 0x0177 }, /* R47 - Left ADC BOOST ctrl */ | |
| 134 | [0x30] = { 0x0000, 0x0177 }, /* R48 - Right ADC BOOST ctrl */ | |
| 135 | [0x31] = { 0x0000, 0x007F }, /* R49 - Output ctrl */ | |
| 136 | [0x32] = { 0x0000, 0x01FF }, /* R50 - Left mixer ctrl */ | |
| 137 | [0x33] = { 0x0000, 0x01FF }, /* R51 - Right mixer ctrl */ | |
| 138 | [0x34] = { 0x0000, 0x01FF }, /* R52 - LOUT1 (HP) volume ctrl */ | |
| 139 | [0x35] = { 0x0000, 0x01FF }, /* R53 - ROUT1 (HP) volume ctrl */ | |
| 140 | [0x36] = { 0x0000, 0x01FF }, /* R54 - LOUT2 (SPK) volume ctrl */ | |
| 141 | [0x37] = { 0x0000, 0x01FF }, /* R55 - ROUT2 (SPK) volume ctrl */ | |
| 142 | [0x38] = { 0x0000, 0x004F }, /* R56 - OUT3 mixer ctrl */ | |
| 143 | [0x39] = { 0x0000, 0x00FF }, /* R57 - OUT4 (MONO) mix ctrl */ | |
| 144 | [0x3D] = { 0x0000, 0x0100 } /* R61 - BIAS CTRL */ | |
| 145 | }; | |
| 146 | ||
| 147 | /* vol/gain update regs */ | |
| 148 | static const int vol_update_regs[] = { | |
| 149 | WM8983_LEFT_DAC_DIGITAL_VOL, | |
| 150 | WM8983_RIGHT_DAC_DIGITAL_VOL, | |
| 151 | WM8983_LEFT_ADC_DIGITAL_VOL, | |
| 152 | WM8983_RIGHT_ADC_DIGITAL_VOL, | |
| 153 | WM8983_LOUT1_HP_VOLUME_CTRL, | |
| 154 | WM8983_ROUT1_HP_VOLUME_CTRL, | |
| 155 | WM8983_LOUT2_SPK_VOLUME_CTRL, | |
| 156 | WM8983_ROUT2_SPK_VOLUME_CTRL, | |
| 157 | WM8983_LEFT_INP_PGA_GAIN_CTRL, | |
| 158 | WM8983_RIGHT_INP_PGA_GAIN_CTRL | |
| 159 | }; | |
| 160 | ||
| 161 | struct wm8983_priv { | |
| 2ee01ac6 | 162 | struct regmap *regmap; |
| 6b3860b0 DP |
163 | u32 sysclk; |
| 164 | u32 bclk; | |
| 165 | }; | |
| 166 | ||
| 167 | static const struct { | |
| 168 | int div; | |
| 169 | int ratio; | |
| 170 | } fs_ratios[] = { | |
| 171 | { 10, 128 }, | |
| 172 | { 15, 192 }, | |
| 173 | { 20, 256 }, | |
| 174 | { 30, 384 }, | |
| 175 | { 40, 512 }, | |
| 176 | { 60, 768 }, | |
| 177 | { 80, 1024 }, | |
| 178 | { 120, 1536 } | |
| 179 | }; | |
| 180 | ||
| 181 | static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 }; | |
| 182 | ||
| 183 | static const int bclk_divs[] = { | |
| 184 | 1, 2, 4, 8, 16, 32 | |
| 185 | }; | |
| 186 | ||
| 187 | static int eqmode_get(struct snd_kcontrol *kcontrol, | |
| 188 | struct snd_ctl_elem_value *ucontrol); | |
| 189 | static int eqmode_put(struct snd_kcontrol *kcontrol, | |
| 190 | struct snd_ctl_elem_value *ucontrol); | |
| 191 | ||
| 192 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1); | |
| 193 | static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1); | |
| 194 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); | |
| 195 | static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0); | |
| 196 | static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0); | |
| 197 | static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0); | |
| 198 | static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0); | |
| 199 | static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0); | |
| 200 | static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0); | |
| 201 | static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1); | |
| 202 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
| 203 | static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0); | |
| 204 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); | |
| 205 | static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0); | |
| 206 | ||
| 207 | static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" }; | |
| ae170688 | 208 | static SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7, alc_sel_text); |
| 6b3860b0 DP |
209 | |
| 210 | static const char *alc_mode_text[] = { "ALC", "Limiter" }; | |
| ae170688 | 211 | static SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8, alc_mode_text); |
| 6b3860b0 DP |
212 | |
| 213 | static const char *filter_mode_text[] = { "Audio", "Application" }; | |
| ae170688 TI |
214 | static SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7, |
| 215 | filter_mode_text); | |
| 6b3860b0 DP |
216 | |
| 217 | static const char *eq_bw_text[] = { "Narrow", "Wide" }; | |
| 218 | static const char *eqmode_text[] = { "Capture", "Playback" }; | |
| ae170688 | 219 | static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text); |
| 6b3860b0 DP |
220 | |
| 221 | static const char *eq1_cutoff_text[] = { | |
| 222 | "80Hz", "105Hz", "135Hz", "175Hz" | |
| 223 | }; | |
| ae170688 TI |
224 | static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5, |
| 225 | eq1_cutoff_text); | |
| 6b3860b0 DP |
226 | static const char *eq2_cutoff_text[] = { |
| 227 | "230Hz", "300Hz", "385Hz", "500Hz" | |
| 228 | }; | |
| ae170688 TI |
229 | static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text); |
| 230 | static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5, eq2_cutoff_text); | |
| 6b3860b0 DP |
231 | static const char *eq3_cutoff_text[] = { |
| 232 | "650Hz", "850Hz", "1.1kHz", "1.4kHz" | |
| 233 | }; | |
| ae170688 TI |
234 | static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text); |
| 235 | static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5, eq3_cutoff_text); | |
| 6b3860b0 DP |
236 | static const char *eq4_cutoff_text[] = { |
| 237 | "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" | |
| 238 | }; | |
| ae170688 TI |
239 | static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text); |
| 240 | static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5, eq4_cutoff_text); | |
| 6b3860b0 DP |
241 | static const char *eq5_cutoff_text[] = { |
| 242 | "5.3kHz", "6.9kHz", "9kHz", "11.7kHz" | |
| 243 | }; | |
| ae170688 TI |
244 | static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5, |
| 245 | eq5_cutoff_text); | |
| 6b3860b0 | 246 | |
| 6b3860b0 DP |
247 | static const char *depth_3d_text[] = { |
| 248 | "Off", | |
| 249 | "6.67%", | |
| 250 | "13.3%", | |
| 251 | "20%", | |
| 252 | "26.7%", | |
| 253 | "33.3%", | |
| 254 | "40%", | |
| 255 | "46.6%", | |
| 256 | "53.3%", | |
| 257 | "60%", | |
| 258 | "66.7%", | |
| 259 | "73.3%", | |
| 260 | "80%", | |
| 261 | "86.7%", | |
| 262 | "93.3%", | |
| 263 | "100%" | |
| 264 | }; | |
| ae170688 TI |
265 | static SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0, |
| 266 | depth_3d_text); | |
| 6b3860b0 DP |
267 | |
| 268 | static const struct snd_kcontrol_new wm8983_snd_controls[] = { | |
| 269 | SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL, | |
| 270 | 0, 1, 0), | |
| 271 | ||
| 272 | SOC_ENUM("ALC Capture Function", alc_sel), | |
| 273 | SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1, | |
| 274 | 3, 7, 0, alc_max_tlv), | |
| 275 | SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1, | |
| 276 | 0, 7, 0, alc_min_tlv), | |
| 277 | SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2, | |
| 278 | 0, 15, 0, alc_tar_tlv), | |
| 279 | SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0), | |
| 280 | SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0), | |
| 281 | SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0), | |
| 282 | SOC_ENUM("ALC Mode", alc_mode), | |
| 283 | SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE, | |
| 284 | 3, 1, 0), | |
| 285 | SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE, | |
| 286 | 0, 7, 1), | |
| 287 | ||
| 288 | SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL, | |
| 289 | WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv), | |
| 290 | SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL, | |
| 291 | WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0), | |
| 292 | SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL, | |
| 293 | WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv), | |
| 294 | ||
| 295 | SOC_DOUBLE_R_TLV("Capture PGA Boost Volume", | |
| 296 | WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL, | |
| 297 | 8, 1, 0, pga_boost_tlv), | |
| 298 | ||
| 299 | SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0), | |
| 300 | SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0), | |
| 301 | ||
| 302 | SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL, | |
| 303 | WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv), | |
| 304 | ||
| 305 | SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0), | |
| 306 | SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0), | |
| 307 | SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0), | |
| 308 | SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2, | |
| 309 | 4, 7, 1, lim_thresh_tlv), | |
| 310 | SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2, | |
| 311 | 0, 12, 0, lim_boost_tlv), | |
| 312 | SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0), | |
| 313 | SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0), | |
| 314 | SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0), | |
| 315 | ||
| 316 | SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL, | |
| 317 | WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv), | |
| 318 | SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL, | |
| 319 | WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0), | |
| 320 | SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL, | |
| 321 | WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1), | |
| 322 | ||
| 323 | SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL, | |
| 324 | WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv), | |
| 325 | SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL, | |
| 326 | WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0), | |
| 327 | SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL, | |
| 328 | WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1), | |
| 329 | ||
| 330 | SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL, | |
| 331 | 6, 1, 1), | |
| 332 | ||
| 333 | SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, | |
| 334 | 6, 1, 1), | |
| 335 | ||
| 336 | SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0), | |
| 337 | SOC_ENUM("High Pass Filter Mode", filter_mode), | |
| 338 | SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0), | |
| 339 | ||
| 340 | SOC_DOUBLE_R_TLV("Aux Bypass Volume", | |
| 341 | WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0, | |
| 342 | aux_tlv), | |
| 343 | ||
| 344 | SOC_DOUBLE_R_TLV("Input PGA Bypass Volume", | |
| 345 | WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0, | |
| 346 | bypass_tlv), | |
| 347 | ||
| 348 | SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put), | |
| 349 | SOC_ENUM("EQ1 Cutoff", eq1_cutoff), | |
| 350 | SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv), | |
| c46d5c04 | 351 | SOC_ENUM("EQ2 Bandwidth", eq2_bw), |
| 6b3860b0 DP |
352 | SOC_ENUM("EQ2 Cutoff", eq2_cutoff), |
| 353 | SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv), | |
| c46d5c04 | 354 | SOC_ENUM("EQ3 Bandwidth", eq3_bw), |
| 6b3860b0 DP |
355 | SOC_ENUM("EQ3 Cutoff", eq3_cutoff), |
| 356 | SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv), | |
| c46d5c04 | 357 | SOC_ENUM("EQ4 Bandwidth", eq4_bw), |
| 6b3860b0 DP |
358 | SOC_ENUM("EQ4 Cutoff", eq4_cutoff), |
| 359 | SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv), | |
| 360 | SOC_ENUM("EQ5 Cutoff", eq5_cutoff), | |
| 361 | SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv), | |
| 362 | ||
| 363 | SOC_ENUM("3D Depth", depth_3d), | |
| 6b3860b0 DP |
364 | }; |
| 365 | ||
| 366 | static const struct snd_kcontrol_new left_out_mixer[] = { | |
| 367 | SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0), | |
| 368 | SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0), | |
| 369 | SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0), | |
| 370 | }; | |
| 371 | ||
| 372 | static const struct snd_kcontrol_new right_out_mixer[] = { | |
| 373 | SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0), | |
| 374 | SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0), | |
| 375 | SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0), | |
| 376 | }; | |
| 377 | ||
| 378 | static const struct snd_kcontrol_new left_input_mixer[] = { | |
| 379 | SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0), | |
| 380 | SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0), | |
| 381 | SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0), | |
| 382 | }; | |
| 383 | ||
| 384 | static const struct snd_kcontrol_new right_input_mixer[] = { | |
| 385 | SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0), | |
| 386 | SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0), | |
| 387 | SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0), | |
| 388 | }; | |
| 389 | ||
| 390 | static const struct snd_kcontrol_new left_boost_mixer[] = { | |
| 391 | SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL, | |
| 392 | 4, 7, 0, boost_tlv), | |
| 393 | SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL, | |
| 394 | 0, 7, 0, boost_tlv) | |
| 395 | }; | |
| 396 | ||
| 397 | static const struct snd_kcontrol_new out3_mixer[] = { | |
| 398 | SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL, | |
| 399 | 1, 1, 0), | |
| 400 | SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL, | |
| 401 | 0, 1, 0), | |
| 402 | }; | |
| 403 | ||
| 404 | static const struct snd_kcontrol_new out4_mixer[] = { | |
| 405 | SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, | |
| 406 | 4, 1, 0), | |
| 407 | SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, | |
| 408 | 1, 1, 0), | |
| 409 | SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, | |
| 410 | 3, 1, 0), | |
| 411 | SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL, | |
| 412 | 0, 1, 0), | |
| 413 | }; | |
| 414 | ||
| 415 | static const struct snd_kcontrol_new right_boost_mixer[] = { | |
| 416 | SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL, | |
| 417 | 4, 7, 0, boost_tlv), | |
| 418 | SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL, | |
| 419 | 0, 7, 0, boost_tlv) | |
| 420 | }; | |
| 421 | ||
| 422 | static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = { | |
| 423 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3, | |
| 424 | 0, 0), | |
| 425 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3, | |
| 426 | 1, 0), | |
| 427 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2, | |
| 428 | 0, 0), | |
| 429 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2, | |
| 430 | 1, 0), | |
| 431 | ||
| 432 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3, | |
| 433 | 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)), | |
| 434 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3, | |
| 435 | 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)), | |
| 436 | ||
| 437 | SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2, | |
| 438 | 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)), | |
| 439 | SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2, | |
| 440 | 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)), | |
| 441 | ||
| 442 | SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2, | |
| 443 | 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)), | |
| 444 | SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2, | |
| 445 | 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)), | |
| 446 | ||
| 447 | SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1, | |
| 448 | 6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)), | |
| 449 | ||
| 450 | SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1, | |
| 451 | 7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)), | |
| 452 | ||
| 453 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL, | |
| 454 | 6, 1, NULL, 0), | |
| 455 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL, | |
| 456 | 6, 1, NULL, 0), | |
| 457 | ||
| 458 | SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2, | |
| 459 | 7, 0, NULL, 0), | |
| 460 | SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2, | |
| 461 | 8, 0, NULL, 0), | |
| 462 | ||
| 463 | SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3, | |
| 464 | 5, 0, NULL, 0), | |
| 465 | SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3, | |
| 466 | 6, 0, NULL, 0), | |
| 467 | ||
| 468 | SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3, | |
| 469 | 7, 0, NULL, 0), | |
| 470 | ||
| 471 | SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3, | |
| 472 | 8, 0, NULL, 0), | |
| 473 | ||
| 605b151a MB |
474 | SND_SOC_DAPM_SUPPLY("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0, |
| 475 | NULL, 0), | |
| 6b3860b0 DP |
476 | |
| 477 | SND_SOC_DAPM_INPUT("LIN"), | |
| 478 | SND_SOC_DAPM_INPUT("LIP"), | |
| 479 | SND_SOC_DAPM_INPUT("RIN"), | |
| 480 | SND_SOC_DAPM_INPUT("RIP"), | |
| 481 | SND_SOC_DAPM_INPUT("AUXL"), | |
| 482 | SND_SOC_DAPM_INPUT("AUXR"), | |
| 483 | SND_SOC_DAPM_INPUT("L2"), | |
| 484 | SND_SOC_DAPM_INPUT("R2"), | |
| 485 | SND_SOC_DAPM_OUTPUT("HPL"), | |
| 486 | SND_SOC_DAPM_OUTPUT("HPR"), | |
| 487 | SND_SOC_DAPM_OUTPUT("SPKL"), | |
| 488 | SND_SOC_DAPM_OUTPUT("SPKR"), | |
| 489 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
| 490 | SND_SOC_DAPM_OUTPUT("OUT4") | |
| 491 | }; | |
| 492 | ||
| 493 | static const struct snd_soc_dapm_route wm8983_audio_map[] = { | |
| 494 | { "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" }, | |
| 495 | { "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" }, | |
| 496 | ||
| 497 | { "OUT3 Out", NULL, "OUT3 Mixer" }, | |
| 498 | { "OUT3", NULL, "OUT3 Out" }, | |
| 499 | ||
| 500 | { "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" }, | |
| 501 | { "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" }, | |
| 502 | { "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" }, | |
| 503 | { "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" }, | |
| 504 | ||
| 505 | { "OUT4 Out", NULL, "OUT4 Mixer" }, | |
| 506 | { "OUT4", NULL, "OUT4 Out" }, | |
| 507 | ||
| 508 | { "Right Output Mixer", "PCM Switch", "Right DAC" }, | |
| 509 | { "Right Output Mixer", "Aux Switch", "AUXR" }, | |
| 510 | { "Right Output Mixer", "Line Switch", "Right Boost Mixer" }, | |
| 511 | ||
| 512 | { "Left Output Mixer", "PCM Switch", "Left DAC" }, | |
| 513 | { "Left Output Mixer", "Aux Switch", "AUXL" }, | |
| 514 | { "Left Output Mixer", "Line Switch", "Left Boost Mixer" }, | |
| 515 | ||
| 516 | { "Right Headphone Out", NULL, "Right Output Mixer" }, | |
| 517 | { "HPR", NULL, "Right Headphone Out" }, | |
| 518 | ||
| 519 | { "Left Headphone Out", NULL, "Left Output Mixer" }, | |
| 520 | { "HPL", NULL, "Left Headphone Out" }, | |
| 521 | ||
| 522 | { "Right Speaker Out", NULL, "Right Output Mixer" }, | |
| 523 | { "SPKR", NULL, "Right Speaker Out" }, | |
| 524 | ||
| 525 | { "Left Speaker Out", NULL, "Left Output Mixer" }, | |
| 526 | { "SPKL", NULL, "Left Speaker Out" }, | |
| 527 | ||
| 528 | { "Right ADC", NULL, "Right Boost Mixer" }, | |
| 529 | ||
| 530 | { "Right Boost Mixer", "AUXR Volume", "AUXR" }, | |
| 531 | { "Right Boost Mixer", NULL, "Right Capture PGA" }, | |
| 532 | { "Right Boost Mixer", "R2 Volume", "R2" }, | |
| 533 | ||
| 534 | { "Left ADC", NULL, "Left Boost Mixer" }, | |
| 535 | ||
| 536 | { "Left Boost Mixer", "AUXL Volume", "AUXL" }, | |
| 537 | { "Left Boost Mixer", NULL, "Left Capture PGA" }, | |
| 538 | { "Left Boost Mixer", "L2 Volume", "L2" }, | |
| 539 | ||
| 540 | { "Right Capture PGA", NULL, "Right Input Mixer" }, | |
| 541 | { "Left Capture PGA", NULL, "Left Input Mixer" }, | |
| 542 | ||
| 543 | { "Right Input Mixer", "R2 Switch", "R2" }, | |
| 544 | { "Right Input Mixer", "MicN Switch", "RIN" }, | |
| 545 | { "Right Input Mixer", "MicP Switch", "RIP" }, | |
| 546 | ||
| 547 | { "Left Input Mixer", "L2 Switch", "L2" }, | |
| 548 | { "Left Input Mixer", "MicN Switch", "LIN" }, | |
| 549 | { "Left Input Mixer", "MicP Switch", "LIP" }, | |
| 550 | }; | |
| 551 | ||
| 552 | static int eqmode_get(struct snd_kcontrol *kcontrol, | |
| 553 | struct snd_ctl_elem_value *ucontrol) | |
| 554 | { | |
| 555 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
| 556 | unsigned int reg; | |
| 557 | ||
| 558 | reg = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF); | |
| 559 | if (reg & WM8983_EQ3DMODE) | |
| 560 | ucontrol->value.integer.value[0] = 1; | |
| 561 | else | |
| 562 | ucontrol->value.integer.value[0] = 0; | |
| 563 | ||
| 564 | return 0; | |
| 565 | } | |
| 566 | ||
| 567 | static int eqmode_put(struct snd_kcontrol *kcontrol, | |
| 568 | struct snd_ctl_elem_value *ucontrol) | |
| 569 | { | |
| 570 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
| 571 | unsigned int regpwr2, regpwr3; | |
| 572 | unsigned int reg_eq; | |
| 573 | ||
| 574 | if (ucontrol->value.integer.value[0] != 0 | |
| 575 | && ucontrol->value.integer.value[0] != 1) | |
| 576 | return -EINVAL; | |
| 577 | ||
| 578 | reg_eq = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF); | |
| 579 | switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) { | |
| 580 | case 0: | |
| 581 | if (!ucontrol->value.integer.value[0]) | |
| 582 | return 0; | |
| 583 | break; | |
| 584 | case 1: | |
| 585 | if (ucontrol->value.integer.value[0]) | |
| 586 | return 0; | |
| 587 | break; | |
| 588 | } | |
| 589 | ||
| 590 | regpwr2 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_2); | |
| 591 | regpwr3 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_3); | |
| 592 | /* disable the DACs and ADCs */ | |
| 593 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_2, | |
| 594 | WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0); | |
| 595 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_3, | |
| 596 | WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0); | |
| 597 | /* set the desired eqmode */ | |
| 598 | snd_soc_update_bits(codec, WM8983_EQ1_LOW_SHELF, | |
| 599 | WM8983_EQ3DMODE_MASK, | |
| 600 | ucontrol->value.integer.value[0] | |
| 601 | << WM8983_EQ3DMODE_SHIFT); | |
| 602 | /* restore DAC/ADC configuration */ | |
| 603 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, regpwr2); | |
| 604 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, regpwr3); | |
| 605 | return 0; | |
| 606 | } | |
| 607 | ||
| 2ee01ac6 | 608 | static bool wm8983_readable(struct device *dev, unsigned int reg) |
| 6b3860b0 DP |
609 | { |
| 610 | if (reg > WM8983_MAX_REGISTER) | |
| 611 | return 0; | |
| 612 | ||
| 613 | return wm8983_access_masks[reg].read != 0; | |
| 614 | } | |
| 615 | ||
| 616 | static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute) | |
| 617 | { | |
| 618 | struct snd_soc_codec *codec = dai->codec; | |
| 619 | ||
| 620 | return snd_soc_update_bits(codec, WM8983_DAC_CONTROL, | |
| 621 | WM8983_SOFTMUTE_MASK, | |
| 622 | !!mute << WM8983_SOFTMUTE_SHIFT); | |
| 623 | } | |
| 624 | ||
| 625 | static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
| 626 | { | |
| 627 | struct snd_soc_codec *codec = dai->codec; | |
| 628 | u16 format, master, bcp, lrp; | |
| 629 | ||
| 630 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
| 631 | case SND_SOC_DAIFMT_I2S: | |
| 632 | format = 0x2; | |
| 633 | break; | |
| 634 | case SND_SOC_DAIFMT_RIGHT_J: | |
| 635 | format = 0x0; | |
| 636 | break; | |
| 637 | case SND_SOC_DAIFMT_LEFT_J: | |
| 638 | format = 0x1; | |
| 639 | break; | |
| 640 | case SND_SOC_DAIFMT_DSP_A: | |
| 641 | case SND_SOC_DAIFMT_DSP_B: | |
| 642 | format = 0x3; | |
| 643 | break; | |
| 644 | default: | |
| 645 | dev_err(dai->dev, "Unknown dai format\n"); | |
| 646 | return -EINVAL; | |
| 647 | } | |
| 648 | ||
| 649 | snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE, | |
| 650 | WM8983_FMT_MASK, format << WM8983_FMT_SHIFT); | |
| 651 | ||
| 652 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
| 653 | case SND_SOC_DAIFMT_CBM_CFM: | |
| 654 | master = 1; | |
| 655 | break; | |
| 656 | case SND_SOC_DAIFMT_CBS_CFS: | |
| 657 | master = 0; | |
| 658 | break; | |
| 659 | default: | |
| 660 | dev_err(dai->dev, "Unknown master/slave configuration\n"); | |
| 661 | return -EINVAL; | |
| 662 | } | |
| 663 | ||
| 664 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, | |
| 665 | WM8983_MS_MASK, master << WM8983_MS_SHIFT); | |
| 666 | ||
| 667 | /* FIXME: We don't currently support DSP A/B modes */ | |
| 668 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
| 669 | case SND_SOC_DAIFMT_DSP_A: | |
| 670 | case SND_SOC_DAIFMT_DSP_B: | |
| 671 | dev_err(dai->dev, "DSP A/B modes are not supported\n"); | |
| 672 | return -EINVAL; | |
| 673 | default: | |
| 674 | break; | |
| 675 | } | |
| 676 | ||
| 677 | bcp = lrp = 0; | |
| 678 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
| 679 | case SND_SOC_DAIFMT_NB_NF: | |
| 680 | break; | |
| 681 | case SND_SOC_DAIFMT_IB_IF: | |
| 682 | bcp = lrp = 1; | |
| 683 | break; | |
| 684 | case SND_SOC_DAIFMT_IB_NF: | |
| 685 | bcp = 1; | |
| 686 | break; | |
| 687 | case SND_SOC_DAIFMT_NB_IF: | |
| 688 | lrp = 1; | |
| 689 | break; | |
| 690 | default: | |
| 691 | dev_err(dai->dev, "Unknown polarity configuration\n"); | |
| 692 | return -EINVAL; | |
| 693 | } | |
| 694 | ||
| 695 | snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE, | |
| 696 | WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT); | |
| 697 | snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE, | |
| 698 | WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT); | |
| 699 | return 0; | |
| 700 | } | |
| 701 | ||
| 702 | static int wm8983_hw_params(struct snd_pcm_substream *substream, | |
| 703 | struct snd_pcm_hw_params *params, | |
| 704 | struct snd_soc_dai *dai) | |
| 705 | { | |
| 706 | int i; | |
| 707 | struct snd_soc_codec *codec = dai->codec; | |
| 708 | struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec); | |
| 709 | u16 blen, srate_idx; | |
| 710 | u32 tmp; | |
| 711 | int srate_best; | |
| 712 | int ret; | |
| 713 | ||
| 714 | ret = snd_soc_params_to_bclk(params); | |
| 715 | if (ret < 0) { | |
| 716 | dev_err(codec->dev, "Failed to convert params to bclk: %d\n", ret); | |
| 717 | return ret; | |
| 718 | } | |
| 719 | ||
| 720 | wm8983->bclk = ret; | |
| 721 | ||
| 722 | switch (params_format(params)) { | |
| 723 | case SNDRV_PCM_FORMAT_S16_LE: | |
| 724 | blen = 0x0; | |
| 725 | break; | |
| 726 | case SNDRV_PCM_FORMAT_S20_3LE: | |
| 727 | blen = 0x1; | |
| 728 | break; | |
| 729 | case SNDRV_PCM_FORMAT_S24_LE: | |
| 730 | blen = 0x2; | |
| 731 | break; | |
| 732 | case SNDRV_PCM_FORMAT_S32_LE: | |
| 733 | blen = 0x3; | |
| 734 | break; | |
| 735 | default: | |
| 736 | dev_err(dai->dev, "Unsupported word length %u\n", | |
| 737 | params_format(params)); | |
| 738 | return -EINVAL; | |
| 739 | } | |
| 740 | ||
| 741 | snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE, | |
| 742 | WM8983_WL_MASK, blen << WM8983_WL_SHIFT); | |
| 743 | ||
| 744 | /* | |
| 745 | * match to the nearest possible sample rate and rely | |
| 746 | * on the array index to configure the SR register | |
| 747 | */ | |
| 748 | srate_idx = 0; | |
| 749 | srate_best = abs(srates[0] - params_rate(params)); | |
| 750 | for (i = 1; i < ARRAY_SIZE(srates); ++i) { | |
| 751 | if (abs(srates[i] - params_rate(params)) >= srate_best) | |
| 752 | continue; | |
| 753 | srate_idx = i; | |
| 754 | srate_best = abs(srates[i] - params_rate(params)); | |
| 755 | } | |
| 756 | ||
| 757 | dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]); | |
| 758 | snd_soc_update_bits(codec, WM8983_ADDITIONAL_CONTROL, | |
| 759 | WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT); | |
| 760 | ||
| 761 | dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk); | |
| 762 | dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk); | |
| 763 | ||
| 764 | for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) { | |
| 765 | if (wm8983->sysclk / params_rate(params) | |
| 766 | == fs_ratios[i].ratio) | |
| 767 | break; | |
| 768 | } | |
| 769 | ||
| 770 | if (i == ARRAY_SIZE(fs_ratios)) { | |
| 771 | dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n", | |
| 772 | wm8983->sysclk, params_rate(params)); | |
| 773 | return -EINVAL; | |
| 774 | } | |
| 775 | ||
| 776 | dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio); | |
| 777 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, | |
| 778 | WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT); | |
| 779 | ||
| 780 | /* select the appropriate bclk divider */ | |
| 781 | tmp = (wm8983->sysclk / fs_ratios[i].div) * 10; | |
| 782 | for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) { | |
| 783 | if (wm8983->bclk == tmp / bclk_divs[i]) | |
| 784 | break; | |
| 785 | } | |
| 786 | ||
| 787 | if (i == ARRAY_SIZE(bclk_divs)) { | |
| 788 | dev_err(dai->dev, "No matching BCLK divider found\n"); | |
| 789 | return -EINVAL; | |
| 790 | } | |
| 791 | ||
| 792 | dev_dbg(dai->dev, "BCLK div = %d\n", i); | |
| 793 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, | |
| 794 | WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT); | |
| 795 | ||
| 796 | return 0; | |
| 797 | } | |
| 798 | ||
| 799 | struct pll_div { | |
| 800 | u32 div2:1; | |
| 801 | u32 n:4; | |
| 802 | u32 k:24; | |
| 803 | }; | |
| 804 | ||
| 805 | #define FIXED_PLL_SIZE ((1ULL << 24) * 10) | |
| 806 | static int pll_factors(struct pll_div *pll_div, unsigned int target, | |
| 807 | unsigned int source) | |
| 808 | { | |
| 809 | u64 Kpart; | |
| 810 | unsigned long int K, Ndiv, Nmod; | |
| 811 | ||
| 812 | pll_div->div2 = 0; | |
| 813 | Ndiv = target / source; | |
| 814 | if (Ndiv < 6) { | |
| 815 | source >>= 1; | |
| 816 | pll_div->div2 = 1; | |
| 817 | Ndiv = target / source; | |
| 818 | } | |
| 819 | ||
| 820 | if (Ndiv < 6 || Ndiv > 12) { | |
| 821 | printk(KERN_ERR "%s: WM8983 N value is not within" | |
| 822 | " the recommended range: %lu\n", __func__, Ndiv); | |
| 823 | return -EINVAL; | |
| 824 | } | |
| 825 | pll_div->n = Ndiv; | |
| 826 | ||
| 827 | Nmod = target % source; | |
| 828 | Kpart = FIXED_PLL_SIZE * (u64)Nmod; | |
| 829 | ||
| 830 | do_div(Kpart, source); | |
| 831 | ||
| 832 | K = Kpart & 0xffffffff; | |
| 833 | if ((K % 10) >= 5) | |
| 834 | K += 5; | |
| 835 | K /= 10; | |
| 836 | pll_div->k = K; | |
| 837 | return 0; | |
| 838 | } | |
| 839 | ||
| 840 | static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id, | |
| 841 | int source, unsigned int freq_in, | |
| 842 | unsigned int freq_out) | |
| 843 | { | |
| 844 | int ret; | |
| 845 | struct snd_soc_codec *codec; | |
| 846 | struct pll_div pll_div; | |
| 847 | ||
| 848 | codec = dai->codec; | |
| 6757d8cc FE |
849 | if (!freq_in || !freq_out) { |
| 850 | /* disable the PLL */ | |
| 851 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, | |
| 852 | WM8983_PLLEN_MASK, 0); | |
| 853 | return 0; | |
| 854 | } else { | |
| 6b3860b0 DP |
855 | ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); |
| 856 | if (ret) | |
| 857 | return ret; | |
| 6b3860b0 | 858 | |
| 6757d8cc FE |
859 | /* disable the PLL before re-programming it */ |
| 860 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, | |
| 861 | WM8983_PLLEN_MASK, 0); | |
| 862 | ||
| 863 | /* set PLLN and PRESCALE */ | |
| 864 | snd_soc_write(codec, WM8983_PLL_N, | |
| 865 | (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT) | |
| 866 | | pll_div.n); | |
| 867 | /* set PLLK */ | |
| 868 | snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff); | |
| 869 | snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff); | |
| 870 | snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18)); | |
| 871 | /* enable the PLL */ | |
| 872 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, | |
| 873 | WM8983_PLLEN_MASK, WM8983_PLLEN); | |
| 874 | } | |
| 6b3860b0 | 875 | |
| 6b3860b0 DP |
876 | return 0; |
| 877 | } | |
| 878 | ||
| 879 | static int wm8983_set_sysclk(struct snd_soc_dai *dai, | |
| 880 | int clk_id, unsigned int freq, int dir) | |
| 881 | { | |
| 882 | struct snd_soc_codec *codec = dai->codec; | |
| 883 | struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec); | |
| 884 | ||
| 885 | switch (clk_id) { | |
| 886 | case WM8983_CLKSRC_MCLK: | |
| 887 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, | |
| 888 | WM8983_CLKSEL_MASK, 0); | |
| 889 | break; | |
| 890 | case WM8983_CLKSRC_PLL: | |
| 891 | snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL, | |
| 892 | WM8983_CLKSEL_MASK, WM8983_CLKSEL); | |
| 893 | break; | |
| 894 | default: | |
| 895 | dev_err(dai->dev, "Unknown clock source: %d\n", clk_id); | |
| 896 | return -EINVAL; | |
| 897 | } | |
| 898 | ||
| 899 | wm8983->sysclk = freq; | |
| 900 | return 0; | |
| 901 | } | |
| 902 | ||
| 903 | static int wm8983_set_bias_level(struct snd_soc_codec *codec, | |
| 904 | enum snd_soc_bias_level level) | |
| 905 | { | |
| 2ee01ac6 | 906 | struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec); |
| 6b3860b0 DP |
907 | int ret; |
| 908 | ||
| 909 | switch (level) { | |
| 910 | case SND_SOC_BIAS_ON: | |
| 911 | case SND_SOC_BIAS_PREPARE: | |
| 912 | /* VMID at 100k */ | |
| 913 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, | |
| 914 | WM8983_VMIDSEL_MASK, | |
| 915 | 1 << WM8983_VMIDSEL_SHIFT); | |
| 916 | break; | |
| 917 | case SND_SOC_BIAS_STANDBY: | |
| 918 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
| 2ee01ac6 | 919 | ret = regcache_sync(wm8983->regmap); |
| 6b3860b0 DP |
920 | if (ret < 0) { |
| 921 | dev_err(codec->dev, "Failed to sync cache: %d\n", ret); | |
| 922 | return ret; | |
| 923 | } | |
| 924 | /* enable anti-pop features */ | |
| 925 | snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC, | |
| 926 | WM8983_POBCTRL_MASK | WM8983_DELEN_MASK, | |
| 927 | WM8983_POBCTRL | WM8983_DELEN); | |
| 928 | /* enable thermal shutdown */ | |
| 929 | snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL, | |
| 930 | WM8983_TSDEN_MASK, WM8983_TSDEN); | |
| 931 | /* enable BIASEN */ | |
| 932 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, | |
| 933 | WM8983_BIASEN_MASK, WM8983_BIASEN); | |
| 934 | /* VMID at 100k */ | |
| 935 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, | |
| 936 | WM8983_VMIDSEL_MASK, | |
| 937 | 1 << WM8983_VMIDSEL_SHIFT); | |
| 938 | msleep(250); | |
| 939 | /* disable anti-pop features */ | |
| 940 | snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC, | |
| 941 | WM8983_POBCTRL_MASK | | |
| 942 | WM8983_DELEN_MASK, 0); | |
| 943 | } | |
| 944 | ||
| 945 | /* VMID at 500k */ | |
| 946 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, | |
| 947 | WM8983_VMIDSEL_MASK, | |
| 948 | 2 << WM8983_VMIDSEL_SHIFT); | |
| 949 | break; | |
| 950 | case SND_SOC_BIAS_OFF: | |
| 951 | /* disable thermal shutdown */ | |
| 952 | snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL, | |
| 953 | WM8983_TSDEN_MASK, 0); | |
| 954 | /* disable VMIDSEL and BIASEN */ | |
| 955 | snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, | |
| 956 | WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK, | |
| 957 | 0); | |
| 958 | /* wait for VMID to discharge */ | |
| 959 | msleep(100); | |
| 960 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_1, 0); | |
| 961 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, 0); | |
| 962 | snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, 0); | |
| 963 | break; | |
| 964 | } | |
| 965 | ||
| 966 | codec->dapm.bias_level = level; | |
| 967 | return 0; | |
| 968 | } | |
| 969 | ||
| 970 | #ifdef CONFIG_PM | |
| 84b315ee | 971 | static int wm8983_suspend(struct snd_soc_codec *codec) |
| 6b3860b0 DP |
972 | { |
| 973 | wm8983_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
| 974 | return 0; | |
| 975 | } | |
| 976 | ||
| 977 | static int wm8983_resume(struct snd_soc_codec *codec) | |
| 978 | { | |
| 979 | wm8983_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
| 980 | return 0; | |
| 981 | } | |
| 982 | #else | |
| 983 | #define wm8983_suspend NULL | |
| 984 | #define wm8983_resume NULL | |
| 985 | #endif | |
| 986 | ||
| 987 | static int wm8983_remove(struct snd_soc_codec *codec) | |
| 988 | { | |
| 989 | wm8983_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
| 990 | return 0; | |
| 991 | } | |
| 992 | ||
| 993 | static int wm8983_probe(struct snd_soc_codec *codec) | |
| 994 | { | |
| 995 | int ret; | |
| 6b3860b0 DP |
996 | int i; |
| 997 | ||
| 2ee01ac6 | 998 | ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP); |
| 6b3860b0 DP |
999 | if (ret < 0) { |
| 1000 | dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); | |
| 1001 | return ret; | |
| 1002 | } | |
| 1003 | ||
| 6f25e4ee | 1004 | ret = snd_soc_write(codec, WM8983_SOFTWARE_RESET, 0); |
| 6b3860b0 DP |
1005 | if (ret < 0) { |
| 1006 | dev_err(codec->dev, "Failed to issue reset: %d\n", ret); | |
| 1007 | return ret; | |
| 1008 | } | |
| 1009 | ||
| 1010 | /* set the vol/gain update bits */ | |
| 1011 | for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i) | |
| 1012 | snd_soc_update_bits(codec, vol_update_regs[i], | |
| 1013 | 0x100, 0x100); | |
| 1014 | ||
| 1015 | /* mute all outputs and set PGAs to minimum gain */ | |
| 1016 | for (i = WM8983_LOUT1_HP_VOLUME_CTRL; | |
| 1017 | i <= WM8983_OUT4_MONO_MIX_CTRL; ++i) | |
| 1018 | snd_soc_update_bits(codec, i, 0x40, 0x40); | |
| 1019 | ||
| 1020 | /* enable soft mute */ | |
| 1021 | snd_soc_update_bits(codec, WM8983_DAC_CONTROL, | |
| 1022 | WM8983_SOFTMUTE_MASK, | |
| 1023 | WM8983_SOFTMUTE); | |
| 1024 | ||
| 1025 | /* enable BIASCUT */ | |
| 1026 | snd_soc_update_bits(codec, WM8983_BIAS_CTRL, | |
| 1027 | WM8983_BIASCUT, WM8983_BIASCUT); | |
| 1028 | return 0; | |
| 1029 | } | |
| 1030 | ||
| 85e7652d | 1031 | static const struct snd_soc_dai_ops wm8983_dai_ops = { |
| 6b3860b0 DP |
1032 | .digital_mute = wm8983_dac_mute, |
| 1033 | .hw_params = wm8983_hw_params, | |
| 1034 | .set_fmt = wm8983_set_fmt, | |
| 1035 | .set_sysclk = wm8983_set_sysclk, | |
| 1036 | .set_pll = wm8983_set_pll | |
| 1037 | }; | |
| 1038 | ||
| 1039 | #define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
| 1040 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
| 1041 | ||
| 1042 | static struct snd_soc_dai_driver wm8983_dai = { | |
| 1043 | .name = "wm8983-hifi", | |
| 1044 | .playback = { | |
| 1045 | .stream_name = "Playback", | |
| 1046 | .channels_min = 2, | |
| 1047 | .channels_max = 2, | |
| 1048 | .rates = SNDRV_PCM_RATE_8000_48000, | |
| 1049 | .formats = WM8983_FORMATS, | |
| 1050 | }, | |
| 1051 | .capture = { | |
| 1052 | .stream_name = "Capture", | |
| 1053 | .channels_min = 2, | |
| 1054 | .channels_max = 2, | |
| 1055 | .rates = SNDRV_PCM_RATE_8000_48000, | |
| 1056 | .formats = WM8983_FORMATS, | |
| 1057 | }, | |
| 1058 | .ops = &wm8983_dai_ops, | |
| 1059 | .symmetric_rates = 1 | |
| 1060 | }; | |
| 1061 | ||
| 1062 | static struct snd_soc_codec_driver soc_codec_dev_wm8983 = { | |
| 1063 | .probe = wm8983_probe, | |
| 1064 | .remove = wm8983_remove, | |
| 1065 | .suspend = wm8983_suspend, | |
| 1066 | .resume = wm8983_resume, | |
| 1067 | .set_bias_level = wm8983_set_bias_level, | |
| 6b3860b0 DP |
1068 | .controls = wm8983_snd_controls, |
| 1069 | .num_controls = ARRAY_SIZE(wm8983_snd_controls), | |
| 1070 | .dapm_widgets = wm8983_dapm_widgets, | |
| 1071 | .num_dapm_widgets = ARRAY_SIZE(wm8983_dapm_widgets), | |
| 1072 | .dapm_routes = wm8983_audio_map, | |
| 1073 | .num_dapm_routes = ARRAY_SIZE(wm8983_audio_map), | |
| 2ee01ac6 MB |
1074 | }; |
| 1075 | ||
| 1076 | static const struct regmap_config wm8983_regmap = { | |
| 1077 | .reg_bits = 7, | |
| 1078 | .val_bits = 9, | |
| 1079 | ||
| 1080 | .reg_defaults = wm8983_defaults, | |
| 1081 | .num_reg_defaults = ARRAY_SIZE(wm8983_defaults), | |
| 1082 | .cache_type = REGCACHE_RBTREE, | |
| 1083 | ||
| 1084 | .readable_reg = wm8983_readable, | |
| 6b3860b0 DP |
1085 | }; |
| 1086 | ||
| 1087 | #if defined(CONFIG_SPI_MASTER) | |
| 7a79e94e | 1088 | static int wm8983_spi_probe(struct spi_device *spi) |
| 6b3860b0 DP |
1089 | { |
| 1090 | struct wm8983_priv *wm8983; | |
| 1091 | int ret; | |
| 1092 | ||
| d6e2dc15 | 1093 | wm8983 = devm_kzalloc(&spi->dev, sizeof *wm8983, GFP_KERNEL); |
| 6b3860b0 DP |
1094 | if (!wm8983) |
| 1095 | return -ENOMEM; | |
| 1096 | ||
| 2ee01ac6 MB |
1097 | wm8983->regmap = devm_regmap_init_spi(spi, &wm8983_regmap); |
| 1098 | if (IS_ERR(wm8983->regmap)) { | |
| 1099 | ret = PTR_ERR(wm8983->regmap); | |
| 1100 | dev_err(&spi->dev, "Failed to init regmap: %d\n", ret); | |
| 1101 | return ret; | |
| 1102 | } | |
| 1103 | ||
| 6b3860b0 DP |
1104 | spi_set_drvdata(spi, wm8983); |
| 1105 | ||
| 1106 | ret = snd_soc_register_codec(&spi->dev, | |
| 1107 | &soc_codec_dev_wm8983, &wm8983_dai, 1); | |
| 6b3860b0 DP |
1108 | return ret; |
| 1109 | } | |
| 1110 | ||
| 7a79e94e | 1111 | static int wm8983_spi_remove(struct spi_device *spi) |
| 6b3860b0 DP |
1112 | { |
| 1113 | snd_soc_unregister_codec(&spi->dev); | |
| 6b3860b0 DP |
1114 | return 0; |
| 1115 | } | |
| 1116 | ||
| 1117 | static struct spi_driver wm8983_spi_driver = { | |
| 1118 | .driver = { | |
| 1119 | .name = "wm8983", | |
| 1120 | .owner = THIS_MODULE, | |
| 1121 | }, | |
| 1122 | .probe = wm8983_spi_probe, | |
| 7a79e94e | 1123 | .remove = wm8983_spi_remove |
| 6b3860b0 DP |
1124 | }; |
| 1125 | #endif | |
| 1126 | ||
| 1127 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
| 7a79e94e BP |
1128 | static int wm8983_i2c_probe(struct i2c_client *i2c, |
| 1129 | const struct i2c_device_id *id) | |
| 6b3860b0 DP |
1130 | { |
| 1131 | struct wm8983_priv *wm8983; | |
| 1132 | int ret; | |
| 1133 | ||
| d6e2dc15 | 1134 | wm8983 = devm_kzalloc(&i2c->dev, sizeof *wm8983, GFP_KERNEL); |
| 6b3860b0 DP |
1135 | if (!wm8983) |
| 1136 | return -ENOMEM; | |
| 1137 | ||
| 2ee01ac6 MB |
1138 | wm8983->regmap = devm_regmap_init_i2c(i2c, &wm8983_regmap); |
| 1139 | if (IS_ERR(wm8983->regmap)) { | |
| 1140 | ret = PTR_ERR(wm8983->regmap); | |
| 1141 | dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); | |
| 1142 | return ret; | |
| 1143 | } | |
| 1144 | ||
| 6b3860b0 DP |
1145 | i2c_set_clientdata(i2c, wm8983); |
| 1146 | ||
| 1147 | ret = snd_soc_register_codec(&i2c->dev, | |
| 1148 | &soc_codec_dev_wm8983, &wm8983_dai, 1); | |
| d6e2dc15 | 1149 | |
| 6b3860b0 DP |
1150 | return ret; |
| 1151 | } | |
| 1152 | ||
| 7a79e94e | 1153 | static int wm8983_i2c_remove(struct i2c_client *client) |
| 6b3860b0 DP |
1154 | { |
| 1155 | snd_soc_unregister_codec(&client->dev); | |
| 6b3860b0 DP |
1156 | return 0; |
| 1157 | } | |
| 1158 | ||
| 1159 | static const struct i2c_device_id wm8983_i2c_id[] = { | |
| 1160 | { "wm8983", 0 }, | |
| 1161 | { } | |
| 1162 | }; | |
| 1163 | MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id); | |
| 1164 | ||
| 1165 | static struct i2c_driver wm8983_i2c_driver = { | |
| 1166 | .driver = { | |
| 1167 | .name = "wm8983", | |
| 1168 | .owner = THIS_MODULE, | |
| 1169 | }, | |
| 1170 | .probe = wm8983_i2c_probe, | |
| 7a79e94e | 1171 | .remove = wm8983_i2c_remove, |
| 6b3860b0 DP |
1172 | .id_table = wm8983_i2c_id |
| 1173 | }; | |
| 1174 | #endif | |
| 1175 | ||
| 1176 | static int __init wm8983_modinit(void) | |
| 1177 | { | |
| 1178 | int ret = 0; | |
| 1179 | ||
| 1180 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
| 1181 | ret = i2c_add_driver(&wm8983_i2c_driver); | |
| 1182 | if (ret) { | |
| 1183 | printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n", | |
| 1184 | ret); | |
| 1185 | } | |
| 1186 | #endif | |
| 1187 | #if defined(CONFIG_SPI_MASTER) | |
| 1188 | ret = spi_register_driver(&wm8983_spi_driver); | |
| 1189 | if (ret != 0) { | |
| 1190 | printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n", | |
| 1191 | ret); | |
| 1192 | } | |
| 1193 | #endif | |
| 1194 | return ret; | |
| 1195 | } | |
| 1196 | module_init(wm8983_modinit); | |
| 1197 | ||
| 1198 | static void __exit wm8983_exit(void) | |
| 1199 | { | |
| 1200 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
| 1201 | i2c_del_driver(&wm8983_i2c_driver); | |
| 1202 | #endif | |
| 1203 | #if defined(CONFIG_SPI_MASTER) | |
| 1204 | spi_unregister_driver(&wm8983_spi_driver); | |
| 1205 | #endif | |
| 1206 | } | |
| 1207 | module_exit(wm8983_exit); | |
| 1208 | ||
| 1209 | MODULE_DESCRIPTION("ASoC WM8983 driver"); | |
| 1210 | MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); | |
| 1211 | MODULE_LICENSE("GPL"); |