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[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / wm8985.c
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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
6d6f8b83 2/*
811e66de 3 * wm8985.c -- WM8985 / WM8758 ALSA SoC Audio driver
6d6f8b83
DP		 4 *
5 * Copyright 2010 Wolfson Microelectronics plc
6d6f8b83
DP		 6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
811e66de
PK		 8 * WM8758 support:
9 * Copyright: 2016 Barix AG
10 * Author: Petr Kulhavy <petr@barix.com>
11 *
6d6f8b83
DP		 12 * TODO:
13 * o Add OUT3/OUT4 mixer controls.
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/pm.h>
21#include <linux/i2c.h>
411a3450 22#include <linux/regmap.h>
6d6f8b83
DP		 23#include <linux/regulator/consumer.h>
24#include <linux/spi/spi.h>
25#include <linux/slab.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
6d6f8b83
DP		 30#include <sound/initval.h>
31#include <sound/tlv.h>
32
33#include "wm8985.h"
34
35#define WM8985_NUM_SUPPLIES 4
36static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
37 "DCVDD",
38 "DBVDD",
39 "AVDD1",
40 "AVDD2"
41};
42
811e66de
PK		 43enum wm8985_type {
44 WM8985,
45 WM8758,
46};
47
411a3450
MB		 48static const struct reg_default wm8985_reg_defaults[] = {
49 { 1, 0x0000 }, /* R1 - Power management 1 */
50 { 2, 0x0000 }, /* R2 - Power management 2 */
51 { 3, 0x0000 }, /* R3 - Power management 3 */
52 { 4, 0x0050 }, /* R4 - Audio Interface */
53 { 5, 0x0000 }, /* R5 - Companding control */
54 { 6, 0x0140 }, /* R6 - Clock Gen control */
55 { 7, 0x0000 }, /* R7 - Additional control */
56 { 8, 0x0000 }, /* R8 - GPIO Control */
57 { 9, 0x0000 }, /* R9 - Jack Detect Control 1 */
58 { 10, 0x0000 }, /* R10 - DAC Control */
59 { 11, 0x00FF }, /* R11 - Left DAC digital Vol */
60 { 12, 0x00FF }, /* R12 - Right DAC digital vol */
61 { 13, 0x0000 }, /* R13 - Jack Detect Control 2 */
62 { 14, 0x0100 }, /* R14 - ADC Control */
63 { 15, 0x00FF }, /* R15 - Left ADC Digital Vol */
64 { 16, 0x00FF }, /* R16 - Right ADC Digital Vol */
65 { 18, 0x012C }, /* R18 - EQ1 - low shelf */
66 { 19, 0x002C }, /* R19 - EQ2 - peak 1 */
67 { 20, 0x002C }, /* R20 - EQ3 - peak 2 */
68 { 21, 0x002C }, /* R21 - EQ4 - peak 3 */
69 { 22, 0x002C }, /* R22 - EQ5 - high shelf */
70 { 24, 0x0032 }, /* R24 - DAC Limiter 1 */
71 { 25, 0x0000 }, /* R25 - DAC Limiter 2 */
72 { 27, 0x0000 }, /* R27 - Notch Filter 1 */
73 { 28, 0x0000 }, /* R28 - Notch Filter 2 */
74 { 29, 0x0000 }, /* R29 - Notch Filter 3 */
75 { 30, 0x0000 }, /* R30 - Notch Filter 4 */
76 { 32, 0x0038 }, /* R32 - ALC control 1 */
77 { 33, 0x000B }, /* R33 - ALC control 2 */
78 { 34, 0x0032 }, /* R34 - ALC control 3 */
79 { 35, 0x0000 }, /* R35 - Noise Gate */
80 { 36, 0x0008 }, /* R36 - PLL N */
81 { 37, 0x000C }, /* R37 - PLL K 1 */
82 { 38, 0x0093 }, /* R38 - PLL K 2 */
83 { 39, 0x00E9 }, /* R39 - PLL K 3 */
84 { 41, 0x0000 }, /* R41 - 3D control */
85 { 42, 0x0000 }, /* R42 - OUT4 to ADC */
86 { 43, 0x0000 }, /* R43 - Beep control */
87 { 44, 0x0033 }, /* R44 - Input ctrl */
88 { 45, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
89 { 46, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
90 { 47, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
91 { 48, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
92 { 49, 0x0002 }, /* R49 - Output ctrl */
93 { 50, 0x0001 }, /* R50 - Left mixer ctrl */
94 { 51, 0x0001 }, /* R51 - Right mixer ctrl */
95 { 52, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
96 { 53, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
97 { 54, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
98 { 55, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
99 { 56, 0x0001 }, /* R56 - OUT3 mixer ctrl */
100 { 57, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
101 { 60, 0x0004 }, /* R60 - OUTPUT ctrl */
102 { 61, 0x0000 }, /* R61 - BIAS CTRL */
6d6f8b83
DP		 103};
104
411a3450
MB		 105static bool wm8985_writeable(struct device *dev, unsigned int reg)
106{
107 switch (reg) {
108 case WM8985_SOFTWARE_RESET:
109 case WM8985_POWER_MANAGEMENT_1:
110 case WM8985_POWER_MANAGEMENT_2:
111 case WM8985_POWER_MANAGEMENT_3:
112 case WM8985_AUDIO_INTERFACE:
113 case WM8985_COMPANDING_CONTROL:
114 case WM8985_CLOCK_GEN_CONTROL:
115 case WM8985_ADDITIONAL_CONTROL:
116 case WM8985_GPIO_CONTROL:
117 case WM8985_JACK_DETECT_CONTROL_1:
118 case WM8985_DAC_CONTROL:
119 case WM8985_LEFT_DAC_DIGITAL_VOL:
120 case WM8985_RIGHT_DAC_DIGITAL_VOL:
121 case WM8985_JACK_DETECT_CONTROL_2:
122 case WM8985_ADC_CONTROL:
123 case WM8985_LEFT_ADC_DIGITAL_VOL:
124 case WM8985_RIGHT_ADC_DIGITAL_VOL:
125 case WM8985_EQ1_LOW_SHELF:
126 case WM8985_EQ2_PEAK_1:
127 case WM8985_EQ3_PEAK_2:
128 case WM8985_EQ4_PEAK_3:
129 case WM8985_EQ5_HIGH_SHELF:
130 case WM8985_DAC_LIMITER_1:
131 case WM8985_DAC_LIMITER_2:
132 case WM8985_NOTCH_FILTER_1:
133 case WM8985_NOTCH_FILTER_2:
134 case WM8985_NOTCH_FILTER_3:
135 case WM8985_NOTCH_FILTER_4:
136 case WM8985_ALC_CONTROL_1:
137 case WM8985_ALC_CONTROL_2:
138 case WM8985_ALC_CONTROL_3:
139 case WM8985_NOISE_GATE:
140 case WM8985_PLL_N:
141 case WM8985_PLL_K_1:
142 case WM8985_PLL_K_2:
143 case WM8985_PLL_K_3:
144 case WM8985_3D_CONTROL:
145 case WM8985_OUT4_TO_ADC:
146 case WM8985_BEEP_CONTROL:
147 case WM8985_INPUT_CTRL:
148 case WM8985_LEFT_INP_PGA_GAIN_CTRL:
149 case WM8985_RIGHT_INP_PGA_GAIN_CTRL:
150 case WM8985_LEFT_ADC_BOOST_CTRL:
151 case WM8985_RIGHT_ADC_BOOST_CTRL:
152 case WM8985_OUTPUT_CTRL0:
153 case WM8985_LEFT_MIXER_CTRL:
154 case WM8985_RIGHT_MIXER_CTRL:
155 case WM8985_LOUT1_HP_VOLUME_CTRL:
156 case WM8985_ROUT1_HP_VOLUME_CTRL:
157 case WM8985_LOUT2_SPK_VOLUME_CTRL:
158 case WM8985_ROUT2_SPK_VOLUME_CTRL:
159 case WM8985_OUT3_MIXER_CTRL:
160 case WM8985_OUT4_MONO_MIX_CTRL:
161 case WM8985_OUTPUT_CTRL1:
162 case WM8985_BIAS_CTRL:
163 return true;
164 default:
165 return false;
166 }
167}
168
6d6f8b83
DP		 169/*
170 * latch bit 8 of these registers to ensure instant
171 * volume updates
172 */
173static const int volume_update_regs[] = {
174 WM8985_LEFT_DAC_DIGITAL_VOL,
175 WM8985_RIGHT_DAC_DIGITAL_VOL,
176 WM8985_LEFT_ADC_DIGITAL_VOL,
177 WM8985_RIGHT_ADC_DIGITAL_VOL,
178 WM8985_LOUT2_SPK_VOLUME_CTRL,
179 WM8985_ROUT2_SPK_VOLUME_CTRL,
180 WM8985_LOUT1_HP_VOLUME_CTRL,
181 WM8985_ROUT1_HP_VOLUME_CTRL,
182 WM8985_LEFT_INP_PGA_GAIN_CTRL,
183 WM8985_RIGHT_INP_PGA_GAIN_CTRL
184};
185
186struct wm8985_priv {
411a3450 187 struct regmap *regmap;
6d6f8b83 188 struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
811e66de 189 enum wm8985_type dev_type;
6d6f8b83
DP		 190 unsigned int sysclk;
191 unsigned int bclk;
192};
193
194static const struct {
195 int div;
196 int ratio;
197} fs_ratios[] = {
198 { 10, 128 },
199 { 15, 192 },
200 { 20, 256 },
201 { 30, 384 },
202 { 40, 512 },
203 { 60, 768 },
204 { 80, 1024 },
205 { 120, 1536 }
206};
207
208static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
209
210static const int bclk_divs[] = {
211 1, 2, 4, 8, 16, 32
212};
213
214static int eqmode_get(struct snd_kcontrol *kcontrol,
215 struct snd_ctl_elem_value *ucontrol);
216static int eqmode_put(struct snd_kcontrol *kcontrol,
217 struct snd_ctl_elem_value *ucontrol);
218
219static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
220static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
221static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
222static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
223static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
224static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
225static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
226static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
227static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
228static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
229static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
230static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
231static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
232static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
233
234static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
d0a4eec1 235static SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7, alc_sel_text);
6d6f8b83
DP		 236
237static const char *alc_mode_text[] = { "ALC", "Limiter" };
d0a4eec1 238static SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8, alc_mode_text);
6d6f8b83
DP		 239
240static const char *filter_mode_text[] = { "Audio", "Application" };
d0a4eec1
TI		 241static SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
242 filter_mode_text);
6d6f8b83
DP		 243
244static const char *eq_bw_text[] = { "Narrow", "Wide" };
245static const char *eqmode_text[] = { "Capture", "Playback" };
d0a4eec1 246static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
d1454e6f 247
6d6f8b83
DP		 248static const char *eq1_cutoff_text[] = {
249 "80Hz", "105Hz", "135Hz", "175Hz"
250};
d0a4eec1
TI		 251static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
252 eq1_cutoff_text);
6d6f8b83
DP		 253static const char *eq2_cutoff_text[] = {
254 "230Hz", "300Hz", "385Hz", "500Hz"
255};
d0a4eec1
TI		 256static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
257static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5, eq2_cutoff_text);
6d6f8b83
DP		 258static const char *eq3_cutoff_text[] = {
259 "650Hz", "850Hz", "1.1kHz", "1.4kHz"
260};
d0a4eec1
TI		 261static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
262static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
263 eq3_cutoff_text);
6d6f8b83
DP		 264static const char *eq4_cutoff_text[] = {
265 "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
266};
d0a4eec1
TI		 267static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
268static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5, eq4_cutoff_text);
6d6f8b83
DP		 269static const char *eq5_cutoff_text[] = {
270 "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
271};
d0a4eec1 272static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
6d6f8b83
DP		 273 eq5_cutoff_text);
274
275static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
d0a4eec1 276static SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
6d6f8b83
DP		 277
278static const char *depth_3d_text[] = {
279 "Off",
280 "6.67%",
281 "13.3%",
282 "20%",
283 "26.7%",
284 "33.3%",
285 "40%",
286 "46.6%",
287 "53.3%",
288 "60%",
289 "66.7%",
290 "73.3%",
291 "80%",
292 "86.7%",
293 "93.3%",
294 "100%"
295};
d0a4eec1 296static SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0, depth_3d_text);
6d6f8b83 297
811e66de 298static const struct snd_kcontrol_new wm8985_common_snd_controls[] = {
6d6f8b83
DP		 299 SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
300 0, 1, 0),
301
302 SOC_ENUM("ALC Capture Function", alc_sel),
303 SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
304 3, 7, 0, alc_max_tlv),
305 SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
306 0, 7, 0, alc_min_tlv),
307 SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
308 0, 15, 0, alc_tar_tlv),
309 SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
310 SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
311 SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
312 SOC_ENUM("ALC Mode", alc_mode),
313 SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
314 3, 1, 0),
315 SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
316 0, 7, 1),
317
318 SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
319 WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
320 SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
321 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
322 SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
323 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
324
325 SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
326 WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
327 8, 1, 0, pga_boost_tlv),
328
329 SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
330 SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
331
332 SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
333 WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
334
335 SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
336 SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
337 SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
338 SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
339 4, 7, 1, lim_thresh_tlv),
340 SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
341 0, 12, 0, lim_boost_tlv),
342 SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
343 SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
344 SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
345
346 SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
347 WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
348 SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
349 WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
350 SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
351 WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
352
353 SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
354 WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
355 SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
356 WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
357 SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
358 WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
359
360 SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
361 SOC_ENUM("High Pass Filter Mode", filter_mode),
362 SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
363
6d6f8b83
DP		 364 SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
365 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
366 bypass_tlv),
367
368 SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
369 SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
370 SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
c46d5c04 371 SOC_ENUM("EQ2 Bandwidth", eq2_bw),
6d6f8b83
DP		 372 SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
373 SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
c46d5c04 374 SOC_ENUM("EQ3 Bandwidth", eq3_bw),
6d6f8b83
DP		 375 SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
376 SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
c46d5c04 377 SOC_ENUM("EQ4 Bandwidth", eq4_bw),
6d6f8b83
DP		 378 SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
379 SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
380 SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
381 SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
382
383 SOC_ENUM("3D Depth", depth_3d),
811e66de
PK		 384};
385
386static const struct snd_kcontrol_new wm8985_specific_snd_controls[] = {
387 SOC_DOUBLE_R_TLV("Aux Bypass Volume",
388 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
389 aux_tlv),
6d6f8b83
DP		 390
391 SOC_ENUM("Speaker Mode", speaker_mode)
392};
393
394static const struct snd_kcontrol_new left_out_mixer[] = {
395 SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
6d6f8b83 396 SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
811e66de
PK		 397
398 /* --- WM8985 only --- */
399 SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
6d6f8b83
DP		 400};
401
402static const struct snd_kcontrol_new right_out_mixer[] = {
403 SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
6d6f8b83 404 SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
811e66de
PK		 405
406 /* --- WM8985 only --- */
407 SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
6d6f8b83
DP		 408};
409
410static const struct snd_kcontrol_new left_input_mixer[] = {
411 SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
412 SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
413 SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
414};
415
416static const struct snd_kcontrol_new right_input_mixer[] = {
417 SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
418 SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
419 SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
420};
421
422static const struct snd_kcontrol_new left_boost_mixer[] = {
423 SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
424 4, 7, 0, boost_tlv),
811e66de
PK		 425
426 /* --- WM8985 only --- */
6d6f8b83
DP		 427 SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
428 0, 7, 0, boost_tlv)
429};
430
431static const struct snd_kcontrol_new right_boost_mixer[] = {
432 SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
433 4, 7, 0, boost_tlv),
811e66de
PK		 434
435 /* --- WM8985 only --- */
6d6f8b83
DP		 436 SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
437 0, 7, 0, boost_tlv)
438};
439
811e66de 440static const struct snd_soc_dapm_widget wm8985_common_dapm_widgets[] = {
6d6f8b83
DP		 441 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
442 0, 0),
443 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
444 1, 0),
445 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
446 0, 0),
447 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
448 1, 0),
449
6d6f8b83
DP		 450 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
451 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
452 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
453 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
454
6d6f8b83
DP		 455 SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
456 6, 1, NULL, 0),
457 SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
458 6, 1, NULL, 0),
459
460 SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
461 7, 0, NULL, 0),
462 SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
463 8, 0, NULL, 0),
464
465 SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
466 5, 0, NULL, 0),
467 SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
468 6, 0, NULL, 0),
469
812f8a35
MB		 470 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
471 NULL, 0),
6d6f8b83
DP		 472
473 SND_SOC_DAPM_INPUT("LIN"),
474 SND_SOC_DAPM_INPUT("LIP"),
475 SND_SOC_DAPM_INPUT("RIN"),
476 SND_SOC_DAPM_INPUT("RIP"),
6d6f8b83
DP		 477 SND_SOC_DAPM_INPUT("L2"),
478 SND_SOC_DAPM_INPUT("R2"),
479 SND_SOC_DAPM_OUTPUT("HPL"),
480 SND_SOC_DAPM_OUTPUT("HPR"),
481 SND_SOC_DAPM_OUTPUT("SPKL"),
482 SND_SOC_DAPM_OUTPUT("SPKR")
483};
484
811e66de
PK		 485static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
486 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
487 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
488 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
489 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
490
491 SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
492 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
493 SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
494 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
495
496 SND_SOC_DAPM_INPUT("AUXL"),
497 SND_SOC_DAPM_INPUT("AUXR"),
498};
499
500static const struct snd_soc_dapm_widget wm8758_dapm_widgets[] = {
501 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
502 2, 0, left_out_mixer,
503 ARRAY_SIZE(left_out_mixer) - 1),
504 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
505 3, 0, right_out_mixer,
506 ARRAY_SIZE(right_out_mixer) - 1),
507
508 SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
509 4, 0, left_boost_mixer,
510 ARRAY_SIZE(left_boost_mixer) - 1),
511 SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
512 5, 0, right_boost_mixer,
513 ARRAY_SIZE(right_boost_mixer) - 1),
514};
515
516static const struct snd_soc_dapm_route wm8985_common_dapm_routes[] = {
6d6f8b83 517 { "Right Output Mixer", "PCM Switch", "Right DAC" },
6d6f8b83
DP		 518 { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
519
520 { "Left Output Mixer", "PCM Switch", "Left DAC" },
6d6f8b83
DP		 521 { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
522
523 { "Right Headphone Out", NULL, "Right Output Mixer" },
524 { "HPR", NULL, "Right Headphone Out" },
525
526 { "Left Headphone Out", NULL, "Left Output Mixer" },
527 { "HPL", NULL, "Left Headphone Out" },
528
529 { "Right Speaker Out", NULL, "Right Output Mixer" },
530 { "SPKR", NULL, "Right Speaker Out" },
531
532 { "Left Speaker Out", NULL, "Left Output Mixer" },
533 { "SPKL", NULL, "Left Speaker Out" },
534
535 { "Right ADC", NULL, "Right Boost Mixer" },
536
6d6f8b83
DP		 537 { "Right Boost Mixer", NULL, "Right Capture PGA" },
538 { "Right Boost Mixer", "R2 Volume", "R2" },
539
540 { "Left ADC", NULL, "Left Boost Mixer" },
541
6d6f8b83
DP		 542 { "Left Boost Mixer", NULL, "Left Capture PGA" },
543 { "Left Boost Mixer", "L2 Volume", "L2" },
544
545 { "Right Capture PGA", NULL, "Right Input Mixer" },
546 { "Left Capture PGA", NULL, "Left Input Mixer" },
547
548 { "Right Input Mixer", "R2 Switch", "R2" },
549 { "Right Input Mixer", "MicN Switch", "RIN" },
550 { "Right Input Mixer", "MicP Switch", "RIP" },
551
552 { "Left Input Mixer", "L2 Switch", "L2" },
553 { "Left Input Mixer", "MicN Switch", "LIN" },
554 { "Left Input Mixer", "MicP Switch", "LIP" },
555};
811e66de
PK		 556static const struct snd_soc_dapm_route wm8985_aux_dapm_routes[] = {
557 { "Right Output Mixer", "Aux Switch", "AUXR" },
558 { "Left Output Mixer", "Aux Switch", "AUXL" },
559
560 { "Right Boost Mixer", "AUXR Volume", "AUXR" },
561 { "Left Boost Mixer", "AUXL Volume", "AUXL" },
562};
563
cbc23b74 564static int wm8985_add_widgets(struct snd_soc_component *component)
811e66de 565{
cbc23b74
KM		 566 struct wm8985_priv *wm8985 = snd_soc_component_get_drvdata(component);
567 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
811e66de
PK		 568
569 switch (wm8985->dev_type) {
570 case WM8758:
571 snd_soc_dapm_new_controls(dapm, wm8758_dapm_widgets,
572 ARRAY_SIZE(wm8758_dapm_widgets));
573 break;
574
575 case WM8985:
cbc23b74 576 snd_soc_add_component_controls(component, wm8985_specific_snd_controls,
811e66de
PK		 577 ARRAY_SIZE(wm8985_specific_snd_controls));
578
579 snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
580 ARRAY_SIZE(wm8985_dapm_widgets));
581 snd_soc_dapm_add_routes(dapm, wm8985_aux_dapm_routes,
582 ARRAY_SIZE(wm8985_aux_dapm_routes));
583 break;
584 }
585
586 return 0;
587}
6d6f8b83
DP		 588
589static int eqmode_get(struct snd_kcontrol *kcontrol,
590 struct snd_ctl_elem_value *ucontrol)
591{
cbc23b74 592 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
6d6f8b83
DP		 593 unsigned int reg;
594
cbc23b74 595 reg = snd_soc_component_read32(component, WM8985_EQ1_LOW_SHELF);
6d6f8b83 596 if (reg & WM8985_EQ3DMODE)
251d6047 597 ucontrol->value.enumerated.item[0] = 1;
6d6f8b83 598 else
251d6047 599 ucontrol->value.enumerated.item[0] = 0;
6d6f8b83
DP		 600
601 return 0;
602}
603
604static int eqmode_put(struct snd_kcontrol *kcontrol,
605 struct snd_ctl_elem_value *ucontrol)
606{
cbc23b74 607 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
6d6f8b83
DP		 608 unsigned int regpwr2, regpwr3;
609 unsigned int reg_eq;
610
251d6047
TI		 611 if (ucontrol->value.enumerated.item[0] != 0
612 && ucontrol->value.enumerated.item[0] != 1)
6d6f8b83
DP		 613 return -EINVAL;
614
cbc23b74 615 reg_eq = snd_soc_component_read32(component, WM8985_EQ1_LOW_SHELF);
6d6f8b83
DP		 616 switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
617 case 0:
251d6047 618 if (!ucontrol->value.enumerated.item[0])
6d6f8b83
DP		 619 return 0;
620 break;
621 case 1:
251d6047 622 if (ucontrol->value.enumerated.item[0])
6d6f8b83
DP		 623 return 0;
624 break;
625 }
626
cbc23b74
KM		 627 regpwr2 = snd_soc_component_read32(component, WM8985_POWER_MANAGEMENT_2);
628 regpwr3 = snd_soc_component_read32(component, WM8985_POWER_MANAGEMENT_3);
6d6f8b83 629 /* disable the DACs and ADCs */
cbc23b74 630 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_2,
6d6f8b83 631 WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
cbc23b74 632 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_3,
6d6f8b83 633 WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
cbc23b74 634 snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
6d6f8b83
DP		 635 WM8985_M128ENB_MASK, WM8985_M128ENB);
636 /* set the desired eqmode */
cbc23b74 637 snd_soc_component_update_bits(component, WM8985_EQ1_LOW_SHELF,
6d6f8b83 638 WM8985_EQ3DMODE_MASK,
251d6047 639 ucontrol->value.enumerated.item[0]
6d6f8b83
DP		 640 << WM8985_EQ3DMODE_SHIFT);
641 /* restore DAC/ADC configuration */
cbc23b74
KM		 642 snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, regpwr2);
643 snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, regpwr3);
6d6f8b83
DP		 644 return 0;
645}
646
cbc23b74 647static int wm8985_reset(struct snd_soc_component *component)
6d6f8b83 648{
cbc23b74 649 return snd_soc_component_write(component, WM8985_SOFTWARE_RESET, 0x0);
6d6f8b83
DP		 650}
651
652static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute)
653{
cbc23b74 654 struct snd_soc_component *component = dai->component;
6d6f8b83 655
cbc23b74 656 return snd_soc_component_update_bits(component, WM8985_DAC_CONTROL,
6d6f8b83
DP		 657 WM8985_SOFTMUTE_MASK,
658 !!mute << WM8985_SOFTMUTE_SHIFT);
659}
660
661static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
662{
cbc23b74 663 struct snd_soc_component *component;
6d6f8b83
DP		 664 u16 format, master, bcp, lrp;
665
cbc23b74 666 component = dai->component;
6d6f8b83
DP		 667
668 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
669 case SND_SOC_DAIFMT_I2S:
670 format = 0x2;
671 break;
672 case SND_SOC_DAIFMT_RIGHT_J:
673 format = 0x0;
674 break;
675 case SND_SOC_DAIFMT_LEFT_J:
676 format = 0x1;
677 break;
678 case SND_SOC_DAIFMT_DSP_A:
679 case SND_SOC_DAIFMT_DSP_B:
680 format = 0x3;
681 break;
682 default:
683 dev_err(dai->dev, "Unknown dai format\n");
684 return -EINVAL;
685 }
686
cbc23b74 687 snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
6d6f8b83
DP		 688 WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
689
690 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
691 case SND_SOC_DAIFMT_CBM_CFM:
692 master = 1;
693 break;
694 case SND_SOC_DAIFMT_CBS_CFS:
695 master = 0;
696 break;
697 default:
698 dev_err(dai->dev, "Unknown master/slave configuration\n");
699 return -EINVAL;
700 }
701
cbc23b74 702 snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
6d6f8b83
DP		 703 WM8985_MS_MASK, master << WM8985_MS_SHIFT);
704
705 /* frame inversion is not valid for dsp modes */
706 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
707 case SND_SOC_DAIFMT_DSP_A:
708 case SND_SOC_DAIFMT_DSP_B:
709 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
710 case SND_SOC_DAIFMT_IB_IF:
711 case SND_SOC_DAIFMT_NB_IF:
712 return -EINVAL;
713 default:
714 break;
715 }
716 break;
717 default:
718 break;
719 }
720
721 bcp = lrp = 0;
722 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
723 case SND_SOC_DAIFMT_NB_NF:
724 break;
725 case SND_SOC_DAIFMT_IB_IF:
726 bcp = lrp = 1;
727 break;
728 case SND_SOC_DAIFMT_IB_NF:
729 bcp = 1;
730 break;
731 case SND_SOC_DAIFMT_NB_IF:
732 lrp = 1;
733 break;
734 default:
735 dev_err(dai->dev, "Unknown polarity configuration\n");
736 return -EINVAL;
737 }
738
cbc23b74 739 snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
6d6f8b83 740 WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
cbc23b74 741 snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
6d6f8b83
DP		 742 WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
743 return 0;
744}
745
746static int wm8985_hw_params(struct snd_pcm_substream *substream,
747 struct snd_pcm_hw_params *params,
748 struct snd_soc_dai *dai)
749{
cf1ff501 750 int i;
cbc23b74 751 struct snd_soc_component *component;
6d6f8b83
DP		 752 struct wm8985_priv *wm8985;
753 u16 blen, srate_idx;
754 unsigned int tmp;
755 int srate_best;
756
cbc23b74
KM		 757 component = dai->component;
758 wm8985 = snd_soc_component_get_drvdata(component);
6d6f8b83
DP		 759
760 wm8985->bclk = snd_soc_params_to_bclk(params);
761 if ((int)wm8985->bclk < 0)
762 return wm8985->bclk;
763
c37642c7
MB		 764 switch (params_width(params)) {
765 case 16:
6d6f8b83
DP		 766 blen = 0x0;
767 break;
c37642c7 768 case 20:
6d6f8b83
DP		 769 blen = 0x1;
770 break;
c37642c7 771 case 24:
6d6f8b83
DP		 772 blen = 0x2;
773 break;
c37642c7 774 case 32:
6d6f8b83
DP		 775 blen = 0x3;
776 break;
777 default:
778 dev_err(dai->dev, "Unsupported word length %u\n",
c37642c7 779 params_width(params));
6d6f8b83
DP		 780 return -EINVAL;
781 }
782
cbc23b74 783 snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
6d6f8b83
DP		 784 WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
785
786 /*
787 * match to the nearest possible sample rate and rely
788 * on the array index to configure the SR register
789 */
790 srate_idx = 0;
791 srate_best = abs(srates[0] - params_rate(params));
792 for (i = 1; i < ARRAY_SIZE(srates); ++i) {
793 if (abs(srates[i] - params_rate(params)) >= srate_best)
794 continue;
795 srate_idx = i;
796 srate_best = abs(srates[i] - params_rate(params));
797 }
798
799 dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
cbc23b74 800 snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
6d6f8b83
DP		 801 WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
802
803 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
804 dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
805
806 for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
807 if (wm8985->sysclk / params_rate(params)
808 == fs_ratios[i].ratio)
809 break;
810 }
811
812 if (i == ARRAY_SIZE(fs_ratios)) {
813 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
814 wm8985->sysclk, params_rate(params));
815 return -EINVAL;
816 }
817
818 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
cbc23b74 819 snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
6d6f8b83
DP		 820 WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
821
822 /* select the appropriate bclk divider */
823 tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
824 for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
825 if (wm8985->bclk == tmp / bclk_divs[i])
826 break;
827 }
828
829 if (i == ARRAY_SIZE(bclk_divs)) {
830 dev_err(dai->dev, "No matching BCLK divider found\n");
831 return -EINVAL;
832 }
833
834 dev_dbg(dai->dev, "BCLK div = %d\n", i);
cbc23b74 835 snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
6d6f8b83
DP		 836 WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
837 return 0;
838}
839
840struct pll_div {
841 u32 div2:1;
842 u32 n:4;
843 u32 k:24;
844};
845
846#define FIXED_PLL_SIZE ((1ULL << 24) * 10)
847static int pll_factors(struct pll_div *pll_div, unsigned int target,
848 unsigned int source)
849{
850 u64 Kpart;
851 unsigned long int K, Ndiv, Nmod;
852
853 pll_div->div2 = 0;
854 Ndiv = target / source;
855 if (Ndiv < 6) {
856 source >>= 1;
857 pll_div->div2 = 1;
858 Ndiv = target / source;
859 }
860
861 if (Ndiv < 6 || Ndiv > 12) {
862 printk(KERN_ERR "%s: WM8985 N value is not within"
863 " the recommended range: %lu\n", __func__, Ndiv);
864 return -EINVAL;
865 }
866 pll_div->n = Ndiv;
867
868 Nmod = target % source;
869 Kpart = FIXED_PLL_SIZE * (u64)Nmod;
870
871 do_div(Kpart, source);
872
873 K = Kpart & 0xffffffff;
874 if ((K % 10) >= 5)
875 K += 5;
876 K /= 10;
877 pll_div->k = K;
878
879 return 0;
880}
881
882static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
883 int source, unsigned int freq_in,
884 unsigned int freq_out)
885{
886 int ret;
cbc23b74 887 struct snd_soc_component *component;
6d6f8b83
DP		 888 struct pll_div pll_div;
889
cbc23b74 890 component = dai->component;
5f3d25c0
FE		 891 if (!freq_in || !freq_out) {
892 /* disable the PLL */
cbc23b74 893 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
5f3d25c0
FE		 894 WM8985_PLLEN_MASK, 0);
895 } else {
6d6f8b83
DP		 896 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
897 if (ret)
898 return ret;
6d6f8b83 899
5f3d25c0 900 /* set PLLN and PRESCALE */
cbc23b74 901 snd_soc_component_write(component, WM8985_PLL_N,
5f3d25c0
FE		 902 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
903 | pll_div.n);
904 /* set PLLK */
cbc23b74
KM		 905 snd_soc_component_write(component, WM8985_PLL_K_3, pll_div.k & 0x1ff);
906 snd_soc_component_write(component, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
907 snd_soc_component_write(component, WM8985_PLL_K_1, (pll_div.k >> 18));
5f3d25c0 908 /* set the source of the clock to be the PLL */
cbc23b74 909 snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
5f3d25c0
FE		 910 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
911 /* enable the PLL */
cbc23b74 912 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
5f3d25c0
FE		 913 WM8985_PLLEN_MASK, WM8985_PLLEN);
914 }
6d6f8b83
DP		 915 return 0;
916}
917
918static int wm8985_set_sysclk(struct snd_soc_dai *dai,
919 int clk_id, unsigned int freq, int dir)
920{
cbc23b74 921 struct snd_soc_component *component;
6d6f8b83
DP		 922 struct wm8985_priv *wm8985;
923
cbc23b74
KM		 924 component = dai->component;
925 wm8985 = snd_soc_component_get_drvdata(component);
6d6f8b83
DP		 926
927 switch (clk_id) {
928 case WM8985_CLKSRC_MCLK:
cbc23b74 929 snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
6d6f8b83 930 WM8985_CLKSEL_MASK, 0);
cbc23b74 931 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
6d6f8b83
DP		 932 WM8985_PLLEN_MASK, 0);
933 break;
934 case WM8985_CLKSRC_PLL:
cbc23b74 935 snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
6d6f8b83
DP		 936 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
937 break;
938 default:
939 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
940 return -EINVAL;
941 }
942
943 wm8985->sysclk = freq;
944 return 0;
945}
946
cbc23b74 947static int wm8985_set_bias_level(struct snd_soc_component *component,
6d6f8b83
DP		 948 enum snd_soc_bias_level level)
949{
950 int ret;
951 struct wm8985_priv *wm8985;
952
cbc23b74 953 wm8985 = snd_soc_component_get_drvdata(component);
6d6f8b83
DP		 954 switch (level) {
955 case SND_SOC_BIAS_ON:
956 case SND_SOC_BIAS_PREPARE:
957 /* VMID at 75k */
cbc23b74 958 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
6d6f8b83
DP		 959 WM8985_VMIDSEL_MASK,
960 1 << WM8985_VMIDSEL_SHIFT);
961 break;
962 case SND_SOC_BIAS_STANDBY:
cbc23b74 963 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
6d6f8b83
DP		 964 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
965 wm8985->supplies);
966 if (ret) {
cbc23b74 967 dev_err(component->dev,
6d6f8b83
DP		 968 "Failed to enable supplies: %d\n",
969 ret);
970 return ret;
971 }
972
411a3450 973 regcache_sync(wm8985->regmap);
6d6f8b83
DP		 974
975 /* enable anti-pop features */
cbc23b74 976 snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
6d6f8b83
DP		 977 WM8985_POBCTRL_MASK,
978 WM8985_POBCTRL);
979 /* enable thermal shutdown */
cbc23b74 980 snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
6d6f8b83 981 WM8985_TSDEN_MASK, WM8985_TSDEN);
cbc23b74 982 snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
6d6f8b83
DP		 983 WM8985_TSOPCTRL_MASK,
984 WM8985_TSOPCTRL);
985 /* enable BIASEN */
cbc23b74 986 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
6d6f8b83
DP		 987 WM8985_BIASEN_MASK, WM8985_BIASEN);
988 /* VMID at 75k */
cbc23b74 989 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
6d6f8b83
DP		 990 WM8985_VMIDSEL_MASK,
991 1 << WM8985_VMIDSEL_SHIFT);
992 msleep(500);
993 /* disable anti-pop features */
cbc23b74 994 snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
6d6f8b83
DP		 995 WM8985_POBCTRL_MASK, 0);
996 }
997 /* VMID at 300k */
cbc23b74 998 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
6d6f8b83
DP		 999 WM8985_VMIDSEL_MASK,
1000 2 << WM8985_VMIDSEL_SHIFT);
1001 break;
1002 case SND_SOC_BIAS_OFF:
1003 /* disable thermal shutdown */
cbc23b74 1004 snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
6d6f8b83 1005 WM8985_TSOPCTRL_MASK, 0);
cbc23b74 1006 snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
6d6f8b83
DP		 1007 WM8985_TSDEN_MASK, 0);
1008 /* disable VMIDSEL and BIASEN */
cbc23b74 1009 snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
6d6f8b83
DP		 1010 WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
1011 0);
cbc23b74
KM		 1012 snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_1, 0);
1013 snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, 0);
1014 snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, 0);
6d6f8b83 1015
411a3450 1016 regcache_mark_dirty(wm8985->regmap);
6d6f8b83
DP		 1017
1018 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
1019 wm8985->supplies);
1020 break;
1021 }
1022
6d6f8b83
DP		 1023 return 0;
1024}
1025
cbc23b74 1026static int wm8985_probe(struct snd_soc_component *component)
6d6f8b83
DP		 1027{
1028 size_t i;
1029 struct wm8985_priv *wm8985;
1030 int ret;
6d6f8b83 1031
cbc23b74 1032 wm8985 = snd_soc_component_get_drvdata(component);
6d6f8b83
DP		 1033
1034 for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
1035 wm8985->supplies[i].supply = wm8985_supply_names[i];
1036
cbc23b74 1037 ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8985->supplies),
6d6f8b83
DP		 1038 wm8985->supplies);
1039 if (ret) {
cbc23b74 1040 dev_err(component->dev, "Failed to request supplies: %d\n", ret);
6d6f8b83
DP		 1041 return ret;
1042 }
1043
1044 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
1045 wm8985->supplies);
1046 if (ret) {
cbc23b74 1047 dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
a0b148b4 1048 return ret;
6d6f8b83
DP		 1049 }
1050
cbc23b74 1051 ret = wm8985_reset(component);
6d6f8b83 1052 if (ret < 0) {
cbc23b74 1053 dev_err(component->dev, "Failed to issue reset: %d\n", ret);
6d6f8b83
DP		 1054 goto err_reg_enable;
1055 }
1056
6d6f8b83
DP		 1057 /* latch volume update bits */
1058 for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
cbc23b74 1059 snd_soc_component_update_bits(component, volume_update_regs[i],
9f8cbae4 1060 0x100, 0x100);
6d6f8b83 1061 /* enable BIASCUT */
cbc23b74 1062 snd_soc_component_update_bits(component, WM8985_BIAS_CTRL, WM8985_BIASCUT,
9f8cbae4 1063 WM8985_BIASCUT);
6d6f8b83 1064
cbc23b74 1065 wm8985_add_widgets(component);
811e66de 1066
6d6f8b83
DP		 1067 return 0;
1068
1069err_reg_enable:
1070 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
6d6f8b83
DP		 1071 return ret;
1072}
1073
85e7652d 1074static const struct snd_soc_dai_ops wm8985_dai_ops = {
6d6f8b83
DP		 1075 .digital_mute = wm8985_dac_mute,
1076 .hw_params = wm8985_hw_params,
1077 .set_fmt = wm8985_set_fmt,
1078 .set_sysclk = wm8985_set_sysclk,
1079 .set_pll = wm8985_set_pll
1080};
1081
1082#define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1083 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1084
1085static struct snd_soc_dai_driver wm8985_dai = {
1086 .name = "wm8985-hifi",
1087 .playback = {
1088 .stream_name = "Playback",
1089 .channels_min = 2,
1090 .channels_max = 2,
1091 .rates = SNDRV_PCM_RATE_8000_48000,
1092 .formats = WM8985_FORMATS,
1093 },
1094 .capture = {
1095 .stream_name = "Capture",
1096 .channels_min = 2,
1097 .channels_max = 2,
1098 .rates = SNDRV_PCM_RATE_8000_48000,
1099 .formats = WM8985_FORMATS,
1100 },
1101 .ops = &wm8985_dai_ops,
1102 .symmetric_rates = 1
1103};
1104
cbc23b74
KM		 1105static const struct snd_soc_component_driver soc_component_dev_wm8985 = {
1106 .probe = wm8985_probe,
1107 .set_bias_level = wm8985_set_bias_level,
1108 .controls = wm8985_common_snd_controls,
1109 .num_controls = ARRAY_SIZE(wm8985_common_snd_controls),
1110 .dapm_widgets = wm8985_common_dapm_widgets,
1111 .num_dapm_widgets = ARRAY_SIZE(wm8985_common_dapm_widgets),
1112 .dapm_routes = wm8985_common_dapm_routes,
1113 .num_dapm_routes = ARRAY_SIZE(wm8985_common_dapm_routes),
1114 .suspend_bias_off = 1,
1115 .idle_bias_on = 1,
1116 .use_pmdown_time = 1,
1117 .endianness = 1,
1118 .non_legacy_dai_naming = 1,
6d6f8b83
DP		 1119};
1120
411a3450
MB		 1121static const struct regmap_config wm8985_regmap = {
1122 .reg_bits = 7,
1123 .val_bits = 9,
1124
1125 .max_register = WM8985_MAX_REGISTER,
1126 .writeable_reg = wm8985_writeable,
1127
1128 .cache_type = REGCACHE_RBTREE,
1129 .reg_defaults = wm8985_reg_defaults,
1130 .num_reg_defaults = ARRAY_SIZE(wm8985_reg_defaults),
1131};
1132
6d6f8b83 1133#if defined(CONFIG_SPI_MASTER)
7a79e94e 1134static int wm8985_spi_probe(struct spi_device *spi)
6d6f8b83
DP		 1135{
1136 struct wm8985_priv *wm8985;
1137 int ret;
1138
a1fea940 1139 wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
fe3e2e7f
DC		 1140 if (!wm8985)
1141 return -ENOMEM;
6d6f8b83 1142
6d6f8b83
DP		 1143 spi_set_drvdata(spi, wm8985);
1144
811e66de
PK		 1145 wm8985->dev_type = WM8985;
1146
f911fa82 1147 wm8985->regmap = devm_regmap_init_spi(spi, &wm8985_regmap);
411a3450
MB		 1148 if (IS_ERR(wm8985->regmap)) {
1149 ret = PTR_ERR(wm8985->regmap);
1150 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1151 ret);
f911fa82 1152 return ret;
411a3450
MB		 1153 }
1154
cbc23b74
KM		 1155 ret = devm_snd_soc_register_component(&spi->dev,
1156 &soc_component_dev_wm8985, &wm8985_dai, 1);
6d6f8b83
DP		 1157 return ret;
1158}
1159
6d6f8b83
DP		 1160static struct spi_driver wm8985_spi_driver = {
1161 .driver = {
1162 .name = "wm8985",
6d6f8b83
DP		 1163 },
1164 .probe = wm8985_spi_probe,
6d6f8b83
DP		 1165};
1166#endif
1167
50c96973 1168#if IS_ENABLED(CONFIG_I2C)
7a79e94e
BP		 1169static int wm8985_i2c_probe(struct i2c_client *i2c,
1170 const struct i2c_device_id *id)
6d6f8b83
DP		 1171{
1172 struct wm8985_priv *wm8985;
1173 int ret;
1174
a1fea940 1175 wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
fe3e2e7f
DC		 1176 if (!wm8985)
1177 return -ENOMEM;
6d6f8b83 1178
6d6f8b83
DP		 1179 i2c_set_clientdata(i2c, wm8985);
1180
811e66de
PK		 1181 wm8985->dev_type = id->driver_data;
1182
f911fa82 1183 wm8985->regmap = devm_regmap_init_i2c(i2c, &wm8985_regmap);
411a3450
MB		 1184 if (IS_ERR(wm8985->regmap)) {
1185 ret = PTR_ERR(wm8985->regmap);
1186 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1187 ret);
f911fa82 1188 return ret;
411a3450
MB		 1189 }
1190
cbc23b74
KM		 1191 ret = devm_snd_soc_register_component(&i2c->dev,
1192 &soc_component_dev_wm8985, &wm8985_dai, 1);
6d6f8b83
DP		 1193 return ret;
1194}
1195
6d6f8b83 1196static const struct i2c_device_id wm8985_i2c_id[] = {
811e66de
PK		 1197 { "wm8985", WM8985 },
1198 { "wm8758", WM8758 },
6d6f8b83
DP		 1199 { }
1200};
1201MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1202
1203static struct i2c_driver wm8985_i2c_driver = {
1204 .driver = {
1205 .name = "wm8985",
6d6f8b83
DP		 1206 },
1207 .probe = wm8985_i2c_probe,
6d6f8b83
DP		 1208 .id_table = wm8985_i2c_id
1209};
1210#endif
1211
1212static int __init wm8985_modinit(void)
1213{
1214 int ret = 0;
1215
50c96973 1216#if IS_ENABLED(CONFIG_I2C)
6d6f8b83
DP		 1217 ret = i2c_add_driver(&wm8985_i2c_driver);
1218 if (ret) {
1219 printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1220 ret);
1221 }
1222#endif
1223#if defined(CONFIG_SPI_MASTER)
1224 ret = spi_register_driver(&wm8985_spi_driver);
1225 if (ret != 0) {
1226 printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1227 ret);
1228 }
1229#endif
1230 return ret;
1231}
1232module_init(wm8985_modinit);
1233
1234static void __exit wm8985_exit(void)
1235{
50c96973 1236#if IS_ENABLED(CONFIG_I2C)
6d6f8b83
DP		 1237 i2c_del_driver(&wm8985_i2c_driver);
1238#endif
1239#if defined(CONFIG_SPI_MASTER)
1240 spi_unregister_driver(&wm8985_spi_driver);
1241#endif
1242}
1243module_exit(wm8985_exit);
1244
811e66de 1245MODULE_DESCRIPTION("ASoC WM8985 / WM8758 driver");
6d6f8b83
DP		 1246MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1247MODULE_LICENSE("GPL");
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