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ASoC: multi-component - ASoC Multi-Component Support
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8988.c
CommitLineData
5409fb4e
MB		 1/*
2 * wm8988.c -- WM8988 ALSA SoC audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 * Copyright 2005 Openedhand Ltd.
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/spi/spi.h>
21#include <linux/platform_device.h>
5a0e3ad6 22#include <linux/slab.h>
5409fb4e
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/tlv.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30
31#include "wm8988.h"
32
33/*
34 * wm8988 register cache
35 * We can't read the WM8988 register space when we
36 * are using 2 wire for device control, so we cache them instead.
37 */
38static const u16 wm8988_reg[] = {
39 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
40 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
41 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
42 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
43 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
44 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
45 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
46 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
47 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
48 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
49 0x0079, 0x0079, 0x0079, /* 40 */
50};
51
52/* codec private data */
53struct wm8988_priv {
54 unsigned int sysclk;
f0fba2ad
LG		 55 enum snd_soc_control_type control_type;
56 void *control_data;
5409fb4e
MB		 57 struct snd_pcm_hw_constraint_list *sysclk_constraints;
58 u16 reg_cache[WM8988_NUM_REG];
59};
60
61
17a52fd6 62#define wm8988_reset(c) snd_soc_write(c, WM8988_RESET, 0)
5409fb4e
MB		 63
64/*
65 * WM8988 Controls
66 */
67
68static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
69static const struct soc_enum bass_boost =
70 SOC_ENUM_SINGLE(WM8988_BASS, 7, 2, bass_boost_txt);
71
72static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
73static const struct soc_enum bass_filter =
74 SOC_ENUM_SINGLE(WM8988_BASS, 6, 2, bass_filter_txt);
75
76static const char *treble_txt[] = {"8kHz", "4kHz"};
77static const struct soc_enum treble =
78 SOC_ENUM_SINGLE(WM8988_TREBLE, 6, 2, treble_txt);
79
80static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
81static const struct soc_enum stereo_3d_lc =
82 SOC_ENUM_SINGLE(WM8988_3D, 5, 2, stereo_3d_lc_txt);
83
84static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
85static const struct soc_enum stereo_3d_uc =
86 SOC_ENUM_SINGLE(WM8988_3D, 6, 2, stereo_3d_uc_txt);
87
88static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
89static const struct soc_enum stereo_3d_func =
90 SOC_ENUM_SINGLE(WM8988_3D, 7, 2, stereo_3d_func_txt);
91
92static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
93static const struct soc_enum alc_func =
94 SOC_ENUM_SINGLE(WM8988_ALC1, 7, 4, alc_func_txt);
95
96static const char *ng_type_txt[] = {"Constant PGA Gain",
97 "Mute ADC Output"};
98static const struct soc_enum ng_type =
99 SOC_ENUM_SINGLE(WM8988_NGATE, 1, 2, ng_type_txt);
100
101static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
102static const struct soc_enum deemph =
103 SOC_ENUM_SINGLE(WM8988_ADCDAC, 1, 4, deemph_txt);
104
105static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
106 "L + R Invert"};
107static const struct soc_enum adcpol =
108 SOC_ENUM_SINGLE(WM8988_ADCDAC, 5, 4, adcpol_txt);
109
110static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
111static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
112static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
113static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
114static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
115
116static const struct snd_kcontrol_new wm8988_snd_controls[] = {
117
118SOC_ENUM("Bass Boost", bass_boost),
119SOC_ENUM("Bass Filter", bass_filter),
120SOC_SINGLE("Bass Volume", WM8988_BASS, 0, 15, 1),
121
122SOC_SINGLE("Treble Volume", WM8988_TREBLE, 0, 15, 0),
123SOC_ENUM("Treble Cut-off", treble),
124
125SOC_SINGLE("3D Switch", WM8988_3D, 0, 1, 0),
126SOC_SINGLE("3D Volume", WM8988_3D, 1, 15, 0),
127SOC_ENUM("3D Lower Cut-off", stereo_3d_lc),
128SOC_ENUM("3D Upper Cut-off", stereo_3d_uc),
129SOC_ENUM("3D Mode", stereo_3d_func),
130
131SOC_SINGLE("ALC Capture Target Volume", WM8988_ALC1, 0, 7, 0),
132SOC_SINGLE("ALC Capture Max Volume", WM8988_ALC1, 4, 7, 0),
133SOC_ENUM("ALC Capture Function", alc_func),
134SOC_SINGLE("ALC Capture ZC Switch", WM8988_ALC2, 7, 1, 0),
135SOC_SINGLE("ALC Capture Hold Time", WM8988_ALC2, 0, 15, 0),
136SOC_SINGLE("ALC Capture Decay Time", WM8988_ALC3, 4, 15, 0),
137SOC_SINGLE("ALC Capture Attack Time", WM8988_ALC3, 0, 15, 0),
138SOC_SINGLE("ALC Capture NG Threshold", WM8988_NGATE, 3, 31, 0),
139SOC_ENUM("ALC Capture NG Type", ng_type),
140SOC_SINGLE("ALC Capture NG Switch", WM8988_NGATE, 0, 1, 0),
141
142SOC_SINGLE("ZC Timeout Switch", WM8988_ADCTL1, 0, 1, 0),
143
144SOC_DOUBLE_R_TLV("Capture Digital Volume", WM8988_LADC, WM8988_RADC,
145 0, 255, 0, adc_tlv),
146SOC_DOUBLE_R_TLV("Capture Volume", WM8988_LINVOL, WM8988_RINVOL,
147 0, 63, 0, pga_tlv),
148SOC_DOUBLE_R("Capture ZC Switch", WM8988_LINVOL, WM8988_RINVOL, 6, 1, 0),
149SOC_DOUBLE_R("Capture Switch", WM8988_LINVOL, WM8988_RINVOL, 7, 1, 1),
150
151SOC_ENUM("Playback De-emphasis", deemph),
152
153SOC_ENUM("Capture Polarity", adcpol),
154SOC_SINGLE("Playback 6dB Attenuate", WM8988_ADCDAC, 7, 1, 0),
155SOC_SINGLE("Capture 6dB Attenuate", WM8988_ADCDAC, 8, 1, 0),
156
157SOC_DOUBLE_R_TLV("PCM Volume", WM8988_LDAC, WM8988_RDAC, 0, 255, 0, dac_tlv),
158
159SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", WM8988_LOUTM1, 4, 7, 1,
160 bypass_tlv),
161SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", WM8988_LOUTM2, 4, 7, 1,
162 bypass_tlv),
163SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", WM8988_ROUTM1, 4, 7, 1,
164 bypass_tlv),
165SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", WM8988_ROUTM2, 4, 7, 1,
166 bypass_tlv),
167
168SOC_DOUBLE_R("Output 1 Playback ZC Switch", WM8988_LOUT1V,
169 WM8988_ROUT1V, 7, 1, 0),
170SOC_DOUBLE_R_TLV("Output 1 Playback Volume", WM8988_LOUT1V, WM8988_ROUT1V,
171 0, 127, 0, out_tlv),
172
173SOC_DOUBLE_R("Output 2 Playback ZC Switch", WM8988_LOUT2V,
174 WM8988_ROUT2V, 7, 1, 0),
175SOC_DOUBLE_R_TLV("Output 2 Playback Volume", WM8988_LOUT2V, WM8988_ROUT2V,
176 0, 127, 0, out_tlv),
177
178};
179
180/*
181 * DAPM Controls
182 */
183
184static int wm8988_lrc_control(struct snd_soc_dapm_widget *w,
185 struct snd_kcontrol *kcontrol, int event)
186{
187 struct snd_soc_codec *codec = w->codec;
17a52fd6 188 u16 adctl2 = snd_soc_read(codec, WM8988_ADCTL2);
5409fb4e
MB		 189
190 /* Use the DAC to gate LRC if active, otherwise use ADC */
17a52fd6 191 if (snd_soc_read(codec, WM8988_PWR2) & 0x180)
5409fb4e
MB		 192 adctl2 &= ~0x4;
193 else
194 adctl2 |= 0x4;
195
17a52fd6 196 return snd_soc_write(codec, WM8988_ADCTL2, adctl2);
5409fb4e
MB		 197}
198
199static const char *wm8988_line_texts[] = {
200 "Line 1", "Line 2", "PGA", "Differential"};
201
202static const unsigned int wm8988_line_values[] = {
203 0, 1, 3, 4};
204
205static const struct soc_enum wm8988_lline_enum =
206 SOC_VALUE_ENUM_SINGLE(WM8988_LOUTM1, 0, 7,
207 ARRAY_SIZE(wm8988_line_texts),
208 wm8988_line_texts,
209 wm8988_line_values);
210static const struct snd_kcontrol_new wm8988_left_line_controls =
211 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
212
213static const struct soc_enum wm8988_rline_enum =
214 SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7,
215 ARRAY_SIZE(wm8988_line_texts),
216 wm8988_line_texts,
217 wm8988_line_values);
218static const struct snd_kcontrol_new wm8988_right_line_controls =
219 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
220
221/* Left Mixer */
222static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = {
223 SOC_DAPM_SINGLE("Playback Switch", WM8988_LOUTM1, 8, 1, 0),
224 SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_LOUTM1, 7, 1, 0),
225 SOC_DAPM_SINGLE("Right Playback Switch", WM8988_LOUTM2, 8, 1, 0),
226 SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_LOUTM2, 7, 1, 0),
227};
228
229/* Right Mixer */
230static const struct snd_kcontrol_new wm8988_right_mixer_controls[] = {
231 SOC_DAPM_SINGLE("Left Playback Switch", WM8988_ROUTM1, 8, 1, 0),
232 SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_ROUTM1, 7, 1, 0),
233 SOC_DAPM_SINGLE("Playback Switch", WM8988_ROUTM2, 8, 1, 0),
234 SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_ROUTM2, 7, 1, 0),
235};
236
237static const char *wm8988_pga_sel[] = {"Line 1", "Line 2", "Differential"};
238static const unsigned int wm8988_pga_val[] = { 0, 1, 3 };
239
240/* Left PGA Mux */
241static const struct soc_enum wm8988_lpga_enum =
242 SOC_VALUE_ENUM_SINGLE(WM8988_LADCIN, 6, 3,
243 ARRAY_SIZE(wm8988_pga_sel),
244 wm8988_pga_sel,
245 wm8988_pga_val);
246static const struct snd_kcontrol_new wm8988_left_pga_controls =
247 SOC_DAPM_VALUE_ENUM("Route", wm8988_lpga_enum);
248
249/* Right PGA Mux */
250static const struct soc_enum wm8988_rpga_enum =
251 SOC_VALUE_ENUM_SINGLE(WM8988_RADCIN, 6, 3,
252 ARRAY_SIZE(wm8988_pga_sel),
253 wm8988_pga_sel,
254 wm8988_pga_val);
255static const struct snd_kcontrol_new wm8988_right_pga_controls =
256 SOC_DAPM_VALUE_ENUM("Route", wm8988_rpga_enum);
257
258/* Differential Mux */
259static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"};
260static const struct soc_enum diffmux =
261 SOC_ENUM_SINGLE(WM8988_ADCIN, 8, 2, wm8988_diff_sel);
262static const struct snd_kcontrol_new wm8988_diffmux_controls =
263 SOC_DAPM_ENUM("Route", diffmux);
264
265/* Mono ADC Mux */
266static const char *wm8988_mono_mux[] = {"Stereo", "Mono (Left)",
267 "Mono (Right)", "Digital Mono"};
268static const struct soc_enum monomux =
269 SOC_ENUM_SINGLE(WM8988_ADCIN, 6, 4, wm8988_mono_mux);
270static const struct snd_kcontrol_new wm8988_monomux_controls =
271 SOC_DAPM_ENUM("Route", monomux);
272
273static const struct snd_soc_dapm_widget wm8988_dapm_widgets[] = {
274 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8988_PWR1, 1, 0),
275
276 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
277 &wm8988_diffmux_controls),
278 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
279 &wm8988_monomux_controls),
280 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
281 &wm8988_monomux_controls),
282
283 SND_SOC_DAPM_MUX("Left PGA Mux", WM8988_PWR1, 5, 0,
284 &wm8988_left_pga_controls),
285 SND_SOC_DAPM_MUX("Right PGA Mux", WM8988_PWR1, 4, 0,
286 &wm8988_right_pga_controls),
287
288 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
289 &wm8988_left_line_controls),
290 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
291 &wm8988_right_line_controls),
292
293 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8988_PWR1, 2, 0),
294 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8988_PWR1, 3, 0),
295
296 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8988_PWR2, 7, 0),
297 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8988_PWR2, 8, 0),
298
299 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
300 &wm8988_left_mixer_controls[0],
301 ARRAY_SIZE(wm8988_left_mixer_controls)),
302 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
303 &wm8988_right_mixer_controls[0],
304 ARRAY_SIZE(wm8988_right_mixer_controls)),
305
306 SND_SOC_DAPM_PGA("Right Out 2", WM8988_PWR2, 3, 0, NULL, 0),
307 SND_SOC_DAPM_PGA("Left Out 2", WM8988_PWR2, 4, 0, NULL, 0),
308 SND_SOC_DAPM_PGA("Right Out 1", WM8988_PWR2, 5, 0, NULL, 0),
309 SND_SOC_DAPM_PGA("Left Out 1", WM8988_PWR2, 6, 0, NULL, 0),
310
311 SND_SOC_DAPM_POST("LRC control", wm8988_lrc_control),
312
313 SND_SOC_DAPM_OUTPUT("LOUT1"),
314 SND_SOC_DAPM_OUTPUT("ROUT1"),
315 SND_SOC_DAPM_OUTPUT("LOUT2"),
316 SND_SOC_DAPM_OUTPUT("ROUT2"),
317 SND_SOC_DAPM_OUTPUT("VREF"),
318
319 SND_SOC_DAPM_INPUT("LINPUT1"),
320 SND_SOC_DAPM_INPUT("LINPUT2"),
321 SND_SOC_DAPM_INPUT("RINPUT1"),
322 SND_SOC_DAPM_INPUT("RINPUT2"),
323};
324
325static const struct snd_soc_dapm_route audio_map[] = {
326
327 { "Left Line Mux", "Line 1", "LINPUT1" },
328 { "Left Line Mux", "Line 2", "LINPUT2" },
329 { "Left Line Mux", "PGA", "Left PGA Mux" },
330 { "Left Line Mux", "Differential", "Differential Mux" },
331
332 { "Right Line Mux", "Line 1", "RINPUT1" },
333 { "Right Line Mux", "Line 2", "RINPUT2" },
334 { "Right Line Mux", "PGA", "Right PGA Mux" },
335 { "Right Line Mux", "Differential", "Differential Mux" },
336
337 { "Left PGA Mux", "Line 1", "LINPUT1" },
338 { "Left PGA Mux", "Line 2", "LINPUT2" },
339 { "Left PGA Mux", "Differential", "Differential Mux" },
340
341 { "Right PGA Mux", "Line 1", "RINPUT1" },
342 { "Right PGA Mux", "Line 2", "RINPUT2" },
343 { "Right PGA Mux", "Differential", "Differential Mux" },
344
345 { "Differential Mux", "Line 1", "LINPUT1" },
346 { "Differential Mux", "Line 1", "RINPUT1" },
347 { "Differential Mux", "Line 2", "LINPUT2" },
348 { "Differential Mux", "Line 2", "RINPUT2" },
349
350 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
351 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
352 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
353
354 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
355 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
356 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
357
358 { "Left ADC", NULL, "Left ADC Mux" },
359 { "Right ADC", NULL, "Right ADC Mux" },
360
361 { "Left Line Mux", "Line 1", "LINPUT1" },
362 { "Left Line Mux", "Line 2", "LINPUT2" },
363 { "Left Line Mux", "PGA", "Left PGA Mux" },
364 { "Left Line Mux", "Differential", "Differential Mux" },
365
366 { "Right Line Mux", "Line 1", "RINPUT1" },
367 { "Right Line Mux", "Line 2", "RINPUT2" },
368 { "Right Line Mux", "PGA", "Right PGA Mux" },
369 { "Right Line Mux", "Differential", "Differential Mux" },
370
371 { "Left Mixer", "Playback Switch", "Left DAC" },
372 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
373 { "Left Mixer", "Right Playback Switch", "Right DAC" },
374 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
375
376 { "Right Mixer", "Left Playback Switch", "Left DAC" },
377 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
378 { "Right Mixer", "Playback Switch", "Right DAC" },
379 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
380
381 { "Left Out 1", NULL, "Left Mixer" },
382 { "LOUT1", NULL, "Left Out 1" },
383 { "Right Out 1", NULL, "Right Mixer" },
384 { "ROUT1", NULL, "Right Out 1" },
385
386 { "Left Out 2", NULL, "Left Mixer" },
387 { "LOUT2", NULL, "Left Out 2" },
388 { "Right Out 2", NULL, "Right Mixer" },
389 { "ROUT2", NULL, "Right Out 2" },
390};
391
392struct _coeff_div {
393 u32 mclk;
394 u32 rate;
395 u16 fs;
396 u8 sr:5;
397 u8 usb:1;
398};
399
400/* codec hifi mclk clock divider coefficients */
401static const struct _coeff_div coeff_div[] = {
402 /* 8k */
403 {12288000, 8000, 1536, 0x6, 0x0},
404 {11289600, 8000, 1408, 0x16, 0x0},
405 {18432000, 8000, 2304, 0x7, 0x0},
406 {16934400, 8000, 2112, 0x17, 0x0},
407 {12000000, 8000, 1500, 0x6, 0x1},
408
409 /* 11.025k */
410 {11289600, 11025, 1024, 0x18, 0x0},
411 {16934400, 11025, 1536, 0x19, 0x0},
412 {12000000, 11025, 1088, 0x19, 0x1},
413
414 /* 16k */
415 {12288000, 16000, 768, 0xa, 0x0},
416 {18432000, 16000, 1152, 0xb, 0x0},
417 {12000000, 16000, 750, 0xa, 0x1},
418
419 /* 22.05k */
420 {11289600, 22050, 512, 0x1a, 0x0},
421 {16934400, 22050, 768, 0x1b, 0x0},
422 {12000000, 22050, 544, 0x1b, 0x1},
423
424 /* 32k */
425 {12288000, 32000, 384, 0xc, 0x0},
426 {18432000, 32000, 576, 0xd, 0x0},
427 {12000000, 32000, 375, 0xa, 0x1},
428
429 /* 44.1k */
430 {11289600, 44100, 256, 0x10, 0x0},
431 {16934400, 44100, 384, 0x11, 0x0},
432 {12000000, 44100, 272, 0x11, 0x1},
433
434 /* 48k */
435 {12288000, 48000, 256, 0x0, 0x0},
436 {18432000, 48000, 384, 0x1, 0x0},
437 {12000000, 48000, 250, 0x0, 0x1},
438
439 /* 88.2k */
440 {11289600, 88200, 128, 0x1e, 0x0},
441 {16934400, 88200, 192, 0x1f, 0x0},
442 {12000000, 88200, 136, 0x1f, 0x1},
443
444 /* 96k */
445 {12288000, 96000, 128, 0xe, 0x0},
446 {18432000, 96000, 192, 0xf, 0x0},
447 {12000000, 96000, 125, 0xe, 0x1},
448};
449
450static inline int get_coeff(int mclk, int rate)
451{
452 int i;
453
454 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
455 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
456 return i;
457 }
458
459 return -EINVAL;
460}
461
462/* The set of rates we can generate from the above for each SYSCLK */
463
464static unsigned int rates_12288[] = {
465 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
466};
467
468static struct snd_pcm_hw_constraint_list constraints_12288 = {
469 .count = ARRAY_SIZE(rates_12288),
470 .list = rates_12288,
471};
472
473static unsigned int rates_112896[] = {
474 8000, 11025, 22050, 44100,
475};
476
477static struct snd_pcm_hw_constraint_list constraints_112896 = {
478 .count = ARRAY_SIZE(rates_112896),
479 .list = rates_112896,
480};
481
482static unsigned int rates_12[] = {
483 8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
484 48000, 88235, 96000,
485};
486
487static struct snd_pcm_hw_constraint_list constraints_12 = {
488 .count = ARRAY_SIZE(rates_12),
489 .list = rates_12,
490};
491
492/*
493 * Note that this should be called from init rather than from hw_params.
494 */
495static int wm8988_set_dai_sysclk(struct snd_soc_dai *codec_dai,
496 int clk_id, unsigned int freq, int dir)
497{
498 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 499 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
5409fb4e
MB		 500
501 switch (freq) {
502 case 11289600:
503 case 18432000:
504 case 22579200:
505 case 36864000:
506 wm8988->sysclk_constraints = &constraints_112896;
507 wm8988->sysclk = freq;
508 return 0;
509
510 case 12288000:
511 case 16934400:
512 case 24576000:
513 case 33868800:
514 wm8988->sysclk_constraints = &constraints_12288;
515 wm8988->sysclk = freq;
516 return 0;
517
518 case 12000000:
519 case 24000000:
520 wm8988->sysclk_constraints = &constraints_12;
521 wm8988->sysclk = freq;
522 return 0;
523 }
524 return -EINVAL;
525}
526
527static int wm8988_set_dai_fmt(struct snd_soc_dai *codec_dai,
528 unsigned int fmt)
529{
530 struct snd_soc_codec *codec = codec_dai->codec;
531 u16 iface = 0;
532
533 /* set master/slave audio interface */
534 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
535 case SND_SOC_DAIFMT_CBM_CFM:
536 iface = 0x0040;
537 break;
538 case SND_SOC_DAIFMT_CBS_CFS:
539 break;
540 default:
541 return -EINVAL;
542 }
543
544 /* interface format */
545 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
546 case SND_SOC_DAIFMT_I2S:
547 iface |= 0x0002;
548 break;
549 case SND_SOC_DAIFMT_RIGHT_J:
550 break;
551 case SND_SOC_DAIFMT_LEFT_J:
552 iface |= 0x0001;
553 break;
554 case SND_SOC_DAIFMT_DSP_A:
555 iface |= 0x0003;
556 break;
557 case SND_SOC_DAIFMT_DSP_B:
558 iface |= 0x0013;
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 /* clock inversion */
565 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
566 case SND_SOC_DAIFMT_NB_NF:
567 break;
568 case SND_SOC_DAIFMT_IB_IF:
569 iface |= 0x0090;
570 break;
571 case SND_SOC_DAIFMT_IB_NF:
572 iface |= 0x0080;
573 break;
574 case SND_SOC_DAIFMT_NB_IF:
575 iface |= 0x0010;
576 break;
577 default:
578 return -EINVAL;
579 }
580
17a52fd6 581 snd_soc_write(codec, WM8988_IFACE, iface);
5409fb4e
MB		 582 return 0;
583}
584
585static int wm8988_pcm_startup(struct snd_pcm_substream *substream,
586 struct snd_soc_dai *dai)
587{
588 struct snd_soc_codec *codec = dai->codec;
b2c812e2 589 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
5409fb4e
MB		 590
591 /* The set of sample rates that can be supported depends on the
592 * MCLK supplied to the CODEC - enforce this.
593 */
594 if (!wm8988->sysclk) {
595 dev_err(codec->dev,
596 "No MCLK configured, call set_sysclk() on init\n");
597 return -EINVAL;
598 }
599
600 snd_pcm_hw_constraint_list(substream->runtime, 0,
601 SNDRV_PCM_HW_PARAM_RATE,
602 wm8988->sysclk_constraints);
603
604 return 0;
605}
606
607static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
608 struct snd_pcm_hw_params *params,
609 struct snd_soc_dai *dai)
610{
611 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 612 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 613 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
17a52fd6
MB		 614 u16 iface = snd_soc_read(codec, WM8988_IFACE) & 0x1f3;
615 u16 srate = snd_soc_read(codec, WM8988_SRATE) & 0x180;
5409fb4e
MB		 616 int coeff;
617
618 coeff = get_coeff(wm8988->sysclk, params_rate(params));
619 if (coeff < 0) {
620 coeff = get_coeff(wm8988->sysclk / 2, params_rate(params));
621 srate |= 0x40;
622 }
623 if (coeff < 0) {
624 dev_err(codec->dev,
625 "Unable to configure sample rate %dHz with %dHz MCLK\n",
626 params_rate(params), wm8988->sysclk);
627 return coeff;
628 }
629
630 /* bit size */
631 switch (params_format(params)) {
632 case SNDRV_PCM_FORMAT_S16_LE:
633 break;
634 case SNDRV_PCM_FORMAT_S20_3LE:
635 iface |= 0x0004;
636 break;
637 case SNDRV_PCM_FORMAT_S24_LE:
638 iface |= 0x0008;
639 break;
640 case SNDRV_PCM_FORMAT_S32_LE:
641 iface |= 0x000c;
642 break;
643 }
644
645 /* set iface & srate */
17a52fd6 646 snd_soc_write(codec, WM8988_IFACE, iface);
5409fb4e 647 if (coeff >= 0)
17a52fd6 648 snd_soc_write(codec, WM8988_SRATE, srate |
5409fb4e
MB		 649 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
650
651 return 0;
652}
653
654static int wm8988_mute(struct snd_soc_dai *dai, int mute)
655{
656 struct snd_soc_codec *codec = dai->codec;
17a52fd6 657 u16 mute_reg = snd_soc_read(codec, WM8988_ADCDAC) & 0xfff7;
5409fb4e
MB		 658
659 if (mute)
17a52fd6 660 snd_soc_write(codec, WM8988_ADCDAC, mute_reg | 0x8);
5409fb4e 661 else
17a52fd6 662 snd_soc_write(codec, WM8988_ADCDAC, mute_reg);
5409fb4e
MB		 663 return 0;
664}
665
666static int wm8988_set_bias_level(struct snd_soc_codec *codec,
667 enum snd_soc_bias_level level)
668{
17a52fd6 669 u16 pwr_reg = snd_soc_read(codec, WM8988_PWR1) & ~0x1c1;
5409fb4e
MB		 670
671 switch (level) {
672 case SND_SOC_BIAS_ON:
673 break;
674
675 case SND_SOC_BIAS_PREPARE:
676 /* VREF, VMID=2x50k, digital enabled */
17a52fd6 677 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x00c0);
5409fb4e
MB		 678 break;
679
680 case SND_SOC_BIAS_STANDBY:
681 if (codec->bias_level == SND_SOC_BIAS_OFF) {
682 /* VREF, VMID=2x5k */
17a52fd6 683 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1);
5409fb4e
MB		 684
685 /* Charge caps */
686 msleep(100);
687 }
688
689 /* VREF, VMID=2*500k, digital stopped */
17a52fd6 690 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x0141);
5409fb4e
MB		 691 break;
692
693 case SND_SOC_BIAS_OFF:
17a52fd6 694 snd_soc_write(codec, WM8988_PWR1, 0x0000);
5409fb4e
MB		 695 break;
696 }
697 codec->bias_level = level;
698 return 0;
699}
700
701#define WM8988_RATES SNDRV_PCM_RATE_8000_96000
702
703#define WM8988_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
704 SNDRV_PCM_FMTBIT_S24_LE)
705
706static struct snd_soc_dai_ops wm8988_ops = {
707 .startup = wm8988_pcm_startup,
708 .hw_params = wm8988_pcm_hw_params,
709 .set_fmt = wm8988_set_dai_fmt,
710 .set_sysclk = wm8988_set_dai_sysclk,
711 .digital_mute = wm8988_mute,
712};
713
f0fba2ad
LG		 714static struct snd_soc_dai_driver wm8988_dai = {
715 .name = "wm8988-hifi",
5409fb4e
MB		 716 .playback = {
717 .stream_name = "Playback",
718 .channels_min = 1,
719 .channels_max = 2,
720 .rates = WM8988_RATES,
721 .formats = WM8988_FORMATS,
722 },
723 .capture = {
724 .stream_name = "Capture",
725 .channels_min = 1,
726 .channels_max = 2,
727 .rates = WM8988_RATES,
728 .formats = WM8988_FORMATS,
729 },
730 .ops = &wm8988_ops,
731 .symmetric_rates = 1,
732};
5409fb4e 733
f0fba2ad 734static int wm8988_suspend(struct snd_soc_codec *codec, pm_message_t state)
5409fb4e 735{
5409fb4e
MB		 736 wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
737 return 0;
738}
739
f0fba2ad 740static int wm8988_resume(struct snd_soc_codec *codec)
5409fb4e 741{
5409fb4e
MB		 742 int i;
743 u8 data[2];
744 u16 *cache = codec->reg_cache;
745
746 /* Sync reg_cache with the hardware */
747 for (i = 0; i < WM8988_NUM_REG; i++) {
748 if (i == WM8988_RESET)
749 continue;
750 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
751 data[1] = cache[i] & 0x00ff;
752 codec->hw_write(codec->control_data, data, 2);
753 }
754
755 wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
756
757 return 0;
758}
759
f0fba2ad 760static int wm8988_probe(struct snd_soc_codec *codec)
5409fb4e 761{
f0fba2ad 762 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
5409fb4e 763 int ret = 0;
5409fb4e
MB		 764 u16 reg;
765
f0fba2ad
LG		 766 codec->control_data = wm8988->control_data;
767 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8988->control_type);
17a52fd6
MB		 768 if (ret < 0) {
769 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 770 return ret;
17a52fd6
MB		 771 }
772
5409fb4e
MB		 773 ret = wm8988_reset(codec);
774 if (ret < 0) {
775 dev_err(codec->dev, "Failed to issue reset\n");
f0fba2ad 776 return ret;
5409fb4e
MB		 777 }
778
779 /* set the update bits (we always update left then right) */
17a52fd6
MB		 780 reg = snd_soc_read(codec, WM8988_RADC);
781 snd_soc_write(codec, WM8988_RADC, reg | 0x100);
782 reg = snd_soc_read(codec, WM8988_RDAC);
783 snd_soc_write(codec, WM8988_RDAC, reg | 0x0100);
784 reg = snd_soc_read(codec, WM8988_ROUT1V);
785 snd_soc_write(codec, WM8988_ROUT1V, reg | 0x0100);
786 reg = snd_soc_read(codec, WM8988_ROUT2V);
787 snd_soc_write(codec, WM8988_ROUT2V, reg | 0x0100);
788 reg = snd_soc_read(codec, WM8988_RINVOL);
789 snd_soc_write(codec, WM8988_RINVOL, reg | 0x0100);
5409fb4e 790
f0fba2ad 791 wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
5409fb4e 792
f0fba2ad
LG		 793 snd_soc_add_controls(codec, wm8988_snd_controls,
794 ARRAY_SIZE(wm8988_snd_controls));
795 snd_soc_dapm_new_controls(codec, wm8988_dapm_widgets,
796 ARRAY_SIZE(wm8988_dapm_widgets));
797 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
5409fb4e
MB		 798
799 return 0;
5409fb4e
MB		 800}
801
f0fba2ad 802static int wm8988_remove(struct snd_soc_codec *codec)
5409fb4e 803{
f0fba2ad
LG		 804 wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
805 return 0;
5409fb4e
MB		 806}
807
f0fba2ad
LG		 808static struct snd_soc_codec_driver soc_codec_dev_wm8988 = {
809 .probe = wm8988_probe,
810 .remove = wm8988_remove,
811 .suspend = wm8988_suspend,
812 .resume = wm8988_resume,
813 .set_bias_level = wm8988_set_bias_level,
814 .reg_cache_size = sizeof(wm8988_reg),
815 .reg_word_size = sizeof(u16),
816 .reg_cache_default = wm8988_reg,
817};
818
819#if defined(CONFIG_SPI_MASTER)
820static int __devinit wm8988_spi_probe(struct spi_device *spi)
5409fb4e
MB		 821{
822 struct wm8988_priv *wm8988;
f0fba2ad 823 int ret;
5409fb4e
MB		 824
825 wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
826 if (wm8988 == NULL)
827 return -ENOMEM;
828
f0fba2ad
LG		 829 wm8988->control_data = spi;
830 wm8988->control_type = SND_SOC_SPI;
831 spi_set_drvdata(spi, wm8988);
5409fb4e 832
f0fba2ad
LG		 833 ret = snd_soc_register_codec(&spi->dev,
834 &soc_codec_dev_wm8988, &wm8988_dai, 1);
835 if (ret < 0)
836 kfree(wm8988);
837 return ret;
5409fb4e
MB		 838}
839
f0fba2ad 840static int __devexit wm8988_spi_remove(struct spi_device *spi)
5409fb4e 841{
f0fba2ad
LG		 842 snd_soc_unregister_codec(&spi->dev);
843 kfree(spi_get_drvdata(spi));
5409fb4e
MB		 844 return 0;
845}
846
f0fba2ad 847static struct spi_driver wm8988_spi_driver = {
5409fb4e 848 .driver = {
f0fba2ad
LG		 849 .name = "wm8988-codec",
850 .bus = &spi_bus_type,
851 .owner = THIS_MODULE,
5409fb4e 852 },
f0fba2ad
LG		 853 .probe = wm8988_spi_probe,
854 .remove = __devexit_p(wm8988_spi_remove),
5409fb4e 855};
f0fba2ad 856#endif /* CONFIG_SPI_MASTER */
5409fb4e 857
f0fba2ad
LG		 858#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
859static __devinit int wm8988_i2c_probe(struct i2c_client *i2c,
860 const struct i2c_device_id *id)
5409fb4e
MB		 861{
862 struct wm8988_priv *wm8988;
f0fba2ad 863 int ret;
5409fb4e
MB		 864
865 wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
866 if (wm8988 == NULL)
867 return -ENOMEM;
868
f0fba2ad
LG		 869 i2c_set_clientdata(i2c, wm8988);
870 wm8988->control_data = i2c;
871 wm8988->control_type = SND_SOC_I2C;
5409fb4e 872
f0fba2ad
LG		 873 ret = snd_soc_register_codec(&i2c->dev,
874 &soc_codec_dev_wm8988, &wm8988_dai, 1);
875 if (ret < 0)
876 kfree(wm8988);
877 return ret;
5409fb4e
MB		 878}
879
f0fba2ad 880static __devexit int wm8988_i2c_remove(struct i2c_client *client)
5409fb4e 881{
f0fba2ad
LG		 882 snd_soc_unregister_codec(&client->dev);
883 kfree(i2c_get_clientdata(client));
5409fb4e
MB		 884 return 0;
885}
886
f0fba2ad
LG		 887static const struct i2c_device_id wm8988_i2c_id[] = {
888 { "wm8988", 0 },
889 { }
890};
891MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
892
893static struct i2c_driver wm8988_i2c_driver = {
5409fb4e 894 .driver = {
f0fba2ad
LG		 895 .name = "wm8988-codec",
896 .owner = THIS_MODULE,
5409fb4e 897 },
f0fba2ad
LG		 898 .probe = wm8988_i2c_probe,
899 .remove = __devexit_p(wm8988_i2c_remove),
900 .id_table = wm8988_i2c_id,
5409fb4e
MB		 901};
902#endif
903
904static int __init wm8988_modinit(void)
905{
f0fba2ad 906 int ret = 0;
5409fb4e
MB		 907#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
908 ret = i2c_add_driver(&wm8988_i2c_driver);
f0fba2ad
LG		 909 if (ret != 0) {
910 printk(KERN_ERR "Failed to register WM8988 I2C driver: %d\n",
911 ret);
912 }
5409fb4e
MB		 913#endif
914#if defined(CONFIG_SPI_MASTER)
915 ret = spi_register_driver(&wm8988_spi_driver);
f0fba2ad
LG		 916 if (ret != 0) {
917 printk(KERN_ERR "Failed to register WM8988 SPI driver: %d\n",
918 ret);
919 }
5409fb4e
MB		 920#endif
921 return ret;
922}
923module_init(wm8988_modinit);
924
925static void __exit wm8988_exit(void)
926{
927#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
928 i2c_del_driver(&wm8988_i2c_driver);
929#endif
930#if defined(CONFIG_SPI_MASTER)
931 spi_unregister_driver(&wm8988_spi_driver);
932#endif
933}
934module_exit(wm8988_exit);
935
936
937MODULE_DESCRIPTION("ASoC WM8988 driver");
938MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
939MODULE_LICENSE("GPL");
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