]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - sound/soc/codecs/wm8994.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: wm8994: Don't bother updating the jackdet mode needlessly
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
9e6e96a1
MB		 126static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127{
b2c812e2 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
5e5e2bef 169
9e6e96a1
MB		 170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177}
178
179static int configure_clock(struct snd_soc_codec *codec)
180{
b2c812e2 181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 182 int change, new;
9e6e96a1
MB		 183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
9e6e96a1 197 return 0;
b00adf76 198 }
9e6e96a1
MB		 199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
04f45c49
AL		 205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 209
b00adf76
MB		 210 wm8958_micd_set_rate(codec);
211
9e6e96a1
MB		 212 return 0;
213}
214
215static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217{
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228}
229
230static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232};
233
234static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
146fd574
UK		 237static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239};
240
241static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
9e6e96a1
MB		 250static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 255static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 256static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 257
258#define WM8994_DRC_SWITCH(xname, reg, shift) \
259{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286}
287
9e6e96a1
MB		 288static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289{
b2c812e2 290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308}
309
310/* Icky as hell but saves code duplication */
311static int wm8994_get_drc(const char *name)
312{
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320}
321
322static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342}
343
344static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346{
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354}
355
356static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357{
b2c812e2 358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411}
412
413/* Icky as hell but saves code duplication */
414static int wm8994_get_retune_mobile_block(const char *name)
415{
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423}
424
425static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445}
446
447static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457}
458
96b101ef 459static const char *aif_chan_src_text[] = {
f554885f
MB		 460 "Left", "Right"
461};
462
96b101ef
MB		 463static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
f554885f 475static const struct soc_enum aif1dacl_src =
96b101ef 476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 477
478static const struct soc_enum aif1dacr_src =
96b101ef 479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 480
481static const struct soc_enum aif2dacl_src =
96b101ef 482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 483
484static const struct soc_enum aif2dacr_src =
96b101ef 485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 486
154b26aa
MB		 487static const char *osr_text[] = {
488 "Low Power", "High Performance",
489};
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
9e6e96a1
MB		 497static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
96b101ef
MB		 508SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 510SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 512
f554885f
MB		 513SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 515SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 517
9e6e96a1
MB		 518SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
146fd574
UK		 555SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
154b26aa
MB		 564SOC_ENUM("ADC OSR", adc_osr),
565SOC_ENUM("DAC OSR", dac_osr),
566
9e6e96a1
MB		 567SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
458350b3 589SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 590 8, 1, 0),
591SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
458350b3 595SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 596 10, 15, 0, wm8994_3d_tlv),
458350b3 597SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 598 8, 1, 0),
599};
600
601static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634};
635
1ddc07d0
MB		 636static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638};
639
640static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
c4431df0
MB		 652static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 654
655SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
c4431df0
MB		 675};
676
81204c84
MB		 677static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682};
683
af6b6fe4
MB		 684/* We run all mode setting through a function to enforce audio mode */
685static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686{
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
28e33269
MB		 689 if (!wm8994->jackdet || !wm8994->jack_cb)
690 return;
691
af6b6fe4
MB		 692 if (wm8994->active_refcount)
693 mode = WM1811_JACKDET_MODE_AUDIO;
694
695 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
696 WM1811_JACKDET_MODE_MASK, mode);
697
698 if (mode == WM1811_JACKDET_MODE_MIC)
699 msleep(2);
700}
701
702static void active_reference(struct snd_soc_codec *codec)
703{
704 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
705
706 mutex_lock(&wm8994->accdet_lock);
707
708 wm8994->active_refcount++;
709
710 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
711 wm8994->active_refcount);
712
713 if (wm8994->active_refcount == 1) {
714 /* If we're using jack detection go into audio mode */
715 if (wm8994->jackdet && wm8994->jack_cb) {
716 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
717 WM1811_JACKDET_MODE_MASK,
718 WM1811_JACKDET_MODE_AUDIO);
719 msleep(2);
720 }
721 }
722
723 mutex_unlock(&wm8994->accdet_lock);
724}
725
726static void active_dereference(struct snd_soc_codec *codec)
727{
728 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
729 u16 mode;
730
731 mutex_lock(&wm8994->accdet_lock);
732
733 wm8994->active_refcount--;
734
735 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
736 wm8994->active_refcount);
737
738 if (wm8994->active_refcount == 0) {
739 /* Go into appropriate detection only mode */
740 if (wm8994->jackdet && wm8994->jack_cb) {
741 if (wm8994->jack_mic || wm8994->mic_detecting)
742 mode = WM1811_JACKDET_MODE_MIC;
743 else
744 mode = WM1811_JACKDET_MODE_JACK;
745
746 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
747 WM1811_JACKDET_MODE_MASK,
748 mode);
749 }
750 }
751
752 mutex_unlock(&wm8994->accdet_lock);
753}
754
9e6e96a1
MB		 755static int clk_sys_event(struct snd_soc_dapm_widget *w,
756 struct snd_kcontrol *kcontrol, int event)
757{
758 struct snd_soc_codec *codec = w->codec;
759
760 switch (event) {
761 case SND_SOC_DAPM_PRE_PMU:
762 return configure_clock(codec);
763
764 case SND_SOC_DAPM_POST_PMD:
765 configure_clock(codec);
766 break;
767 }
768
769 return 0;
770}
771
4b7ed83a
MB		 772static void vmid_reference(struct snd_soc_codec *codec)
773{
774 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
775
db966f8a
MB		 776 pm_runtime_get_sync(codec->dev);
777
4b7ed83a
MB		 778 wm8994->vmid_refcount++;
779
780 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
781 wm8994->vmid_refcount);
782
783 if (wm8994->vmid_refcount == 1) {
cc6d5a8c
MB		 784 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
785 WM8994_LINEOUT_VMID_BUF_ENA |
786 WM8994_LINEOUT1_DISCH |
787 WM8994_LINEOUT2_DISCH,
788 WM8994_LINEOUT_VMID_BUF_ENA);
789
f7085641
MB		 790 wm_hubs_vmid_ena(codec);
791
4b7ed83a
MB		 792 /* Startup bias, VMID ramp & buffer */
793 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
cc6d5a8c
MB		 794 WM8994_BIAS_SRC |
795 WM8994_VMID_DISCH |
4b7ed83a
MB		 796 WM8994_STARTUP_BIAS_ENA |
797 WM8994_VMID_BUF_ENA |
798 WM8994_VMID_RAMP_MASK,
cc6d5a8c 799 WM8994_BIAS_SRC |
4b7ed83a
MB		 800 WM8994_STARTUP_BIAS_ENA |
801 WM8994_VMID_BUF_ENA |
65f01ef0 802 (0x2 << WM8994_VMID_RAMP_SHIFT));
4b7ed83a
MB		 803
804 /* Main bias enable, VMID=2x40k */
805 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
806 WM8994_BIAS_ENA |
807 WM8994_VMID_SEL_MASK,
808 WM8994_BIAS_ENA | 0x2);
809
cc6d5a8c
MB		 810 msleep(50);
811
812 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
813 WM8994_VMID_RAMP_MASK | WM8994_BIAS_SRC,
814 0);
4b7ed83a
MB		 815 }
816}
817
818static void vmid_dereference(struct snd_soc_codec *codec)
819{
820 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
821
822 wm8994->vmid_refcount--;
823
824 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
825 wm8994->vmid_refcount);
826
827 if (wm8994->vmid_refcount == 0) {
828 /* Switch over to startup biases */
829 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
830 WM8994_BIAS_SRC |
831 WM8994_STARTUP_BIAS_ENA |
832 WM8994_VMID_BUF_ENA |
833 WM8994_VMID_RAMP_MASK,
834 WM8994_BIAS_SRC |
835 WM8994_STARTUP_BIAS_ENA |
836 WM8994_VMID_BUF_ENA |
837 (1 << WM8994_VMID_RAMP_SHIFT));
838
839 /* Disable main biases */
840 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
841 WM8994_BIAS_ENA |
842 WM8994_VMID_SEL_MASK, 0);
843
e85b26ce
MB		 844 /* Discharge VMID */
845 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
846 WM8994_VMID_DISCH, WM8994_VMID_DISCH);
847
4b7ed83a
MB		 848 /* Discharge line */
849 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
850 WM8994_LINEOUT1_DISCH |
851 WM8994_LINEOUT2_DISCH,
852 WM8994_LINEOUT1_DISCH |
853 WM8994_LINEOUT2_DISCH);
854
855 msleep(5);
856
857 /* Switch off startup biases */
858 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
859 WM8994_BIAS_SRC |
860 WM8994_STARTUP_BIAS_ENA |
861 WM8994_VMID_BUF_ENA |
862 WM8994_VMID_RAMP_MASK, 0);
863 }
db966f8a
MB		 864
865 pm_runtime_put(codec->dev);
4b7ed83a
MB		 866}
867
868static int vmid_event(struct snd_soc_dapm_widget *w,
869 struct snd_kcontrol *kcontrol, int event)
870{
871 struct snd_soc_codec *codec = w->codec;
872
873 switch (event) {
874 case SND_SOC_DAPM_PRE_PMU:
875 vmid_reference(codec);
876 break;
877
878 case SND_SOC_DAPM_POST_PMD:
879 vmid_dereference(codec);
880 break;
881 }
882
883 return 0;
884}
885
9e6e96a1
MB		 886static void wm8994_update_class_w(struct snd_soc_codec *codec)
887{
fec6dd83 888 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 889 int enable = 1;
890 int source = 0; /* GCC flow analysis can't track enable */
891 int reg, reg_r;
892
893 /* Only support direct DAC->headphone paths */
894 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
895 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 896 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 897 enable = 0;
898 }
899
900 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
901 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 902 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 903 enable = 0;
904 }
905
906 /* We also need the same setting for L/R and only one path */
907 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
908 switch (reg) {
909 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 910 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 911 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
912 break;
913 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 914 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 915 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
916 break;
917 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 918 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 919 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
920 break;
921 default:
ee839a21 922 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 923 enable = 0;
924 break;
925 }
926
927 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
928 if (reg_r != reg) {
ee839a21 929 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 930 enable = 0;
931 }
932
933 if (enable) {
934 dev_dbg(codec->dev, "Class W enabled\n");
935 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
936 WM8994_CP_DYN_PWR |
937 WM8994_CP_DYN_SRC_SEL_MASK,
938 source | WM8994_CP_DYN_PWR);
fec6dd83 939 wm8994->hubs.class_w = true;
9e6e96a1
MB		 940
941 } else {
942 dev_dbg(codec->dev, "Class W disabled\n");
943 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
944 WM8994_CP_DYN_PWR, 0);
fec6dd83 945 wm8994->hubs.class_w = false;
9e6e96a1
MB		 946 }
947}
948
173efa09
DP		 949static int late_enable_ev(struct snd_soc_dapm_widget *w,
950 struct snd_kcontrol *kcontrol, int event)
951{
952 struct snd_soc_codec *codec = w->codec;
953 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
954
955 switch (event) {
956 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 957 if (wm8994->aif1clk_enable) {
173efa09
DP		 958 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
959 WM8994_AIF1CLK_ENA_MASK,
960 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 961 wm8994->aif1clk_enable = 0;
962 }
963 if (wm8994->aif2clk_enable) {
173efa09
DP		 964 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
965 WM8994_AIF2CLK_ENA_MASK,
966 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 967 wm8994->aif2clk_enable = 0;
968 }
173efa09
DP		 969 break;
970 }
971
c6b7b570
MB		 972 /* We may also have postponed startup of DSP, handle that. */
973 wm8958_aif_ev(w, kcontrol, event);
974
173efa09
DP		 975 return 0;
976}
977
978static int late_disable_ev(struct snd_soc_dapm_widget *w,
979 struct snd_kcontrol *kcontrol, int event)
980{
981 struct snd_soc_codec *codec = w->codec;
982 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
983
984 switch (event) {
985 case SND_SOC_DAPM_POST_PMD:
a3cff81a 986 if (wm8994->aif1clk_disable) {
173efa09
DP		 987 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
988 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 989 wm8994->aif1clk_disable = 0;
173efa09 990 }
a3cff81a 991 if (wm8994->aif2clk_disable) {
173efa09
DP		 992 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
993 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 994 wm8994->aif2clk_disable = 0;
173efa09
DP		 995 }
996 break;
997 }
998
999 return 0;
1000}
1001
1002static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1003 struct snd_kcontrol *kcontrol, int event)
1004{
1005 struct snd_soc_codec *codec = w->codec;
1006 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1007
1008 switch (event) {
1009 case SND_SOC_DAPM_PRE_PMU:
1010 wm8994->aif1clk_enable = 1;
1011 break;
a3cff81a
DP		 1012 case SND_SOC_DAPM_POST_PMD:
1013 wm8994->aif1clk_disable = 1;
1014 break;
173efa09
DP		 1015 }
1016
1017 return 0;
1018}
1019
1020static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1021 struct snd_kcontrol *kcontrol, int event)
1022{
1023 struct snd_soc_codec *codec = w->codec;
1024 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1025
1026 switch (event) {
1027 case SND_SOC_DAPM_PRE_PMU:
1028 wm8994->aif2clk_enable = 1;
1029 break;
a3cff81a
DP		 1030 case SND_SOC_DAPM_POST_PMD:
1031 wm8994->aif2clk_disable = 1;
1032 break;
173efa09
DP		 1033 }
1034
1035 return 0;
1036}
1037
04d28681
DP		 1038static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1039 struct snd_kcontrol *kcontrol, int event)
1040{
1041 late_enable_ev(w, kcontrol, event);
1042 return 0;
1043}
1044
b462c6e6
DP		 1045static int micbias_ev(struct snd_soc_dapm_widget *w,
1046 struct snd_kcontrol *kcontrol, int event)
1047{
1048 late_enable_ev(w, kcontrol, event);
1049 return 0;
1050}
1051
c52fd021
DP		 1052static int dac_ev(struct snd_soc_dapm_widget *w,
1053 struct snd_kcontrol *kcontrol, int event)
1054{
1055 struct snd_soc_codec *codec = w->codec;
1056 unsigned int mask = 1 << w->shift;
1057
1058 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1059 mask, mask);
1060 return 0;
1061}
1062
9e6e96a1
MB		 1063static const char *hp_mux_text[] = {
1064 "Mixer",
1065 "DAC",
1066};
1067
1068#define WM8994_HP_ENUM(xname, xenum) \
1069{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1070 .info = snd_soc_info_enum_double, \
1071 .get = snd_soc_dapm_get_enum_double, \
1072 .put = wm8994_put_hp_enum, \
1073 .private_value = (unsigned long)&xenum }
1074
1075static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1076 struct snd_ctl_elem_value *ucontrol)
1077{
9d03545d
JN		 1078 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1079 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1080 struct snd_soc_codec *codec = w->codec;
1081 int ret;
1082
1083 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1084
1085 wm8994_update_class_w(codec);
1086
1087 return ret;
1088}
1089
1090static const struct soc_enum hpl_enum =
1091 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1092
1093static const struct snd_kcontrol_new hpl_mux =
1094 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1095
1096static const struct soc_enum hpr_enum =
1097 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1098
1099static const struct snd_kcontrol_new hpr_mux =
1100 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1101
1102static const char *adc_mux_text[] = {
1103 "ADC",
1104 "DMIC",
1105};
1106
1107static const struct soc_enum adc_enum =
1108 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1109
1110static const struct snd_kcontrol_new adcl_mux =
1111 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1112
1113static const struct snd_kcontrol_new adcr_mux =
1114 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1115
1116static const struct snd_kcontrol_new left_speaker_mixer[] = {
1117SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1118SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1119SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1120SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1121SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1122};
1123
1124static const struct snd_kcontrol_new right_speaker_mixer[] = {
1125SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1126SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1127SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1128SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1129SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1130};
1131
1132/* Debugging; dump chip status after DAPM transitions */
1133static int post_ev(struct snd_soc_dapm_widget *w,
1134 struct snd_kcontrol *kcontrol, int event)
1135{
1136 struct snd_soc_codec *codec = w->codec;
1137 dev_dbg(codec->dev, "SRC status: %x\n",
1138 snd_soc_read(codec,
1139 WM8994_RATE_STATUS));
1140 return 0;
1141}
1142
1143static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1144SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1145 1, 1, 0),
1146SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1147 0, 1, 0),
1148};
1149
1150static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1151SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1152 1, 1, 0),
1153SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1154 0, 1, 0),
1155};
1156
a3257ba8
MB		 1157static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1158SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1159 1, 1, 0),
1160SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1161 0, 1, 0),
1162};
1163
1164static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1165SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1166 1, 1, 0),
1167SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1168 0, 1, 0),
1169};
1170
9e6e96a1
MB		 1171static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1172SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1173 5, 1, 0),
1174SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1175 4, 1, 0),
1176SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1177 2, 1, 0),
1178SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1179 1, 1, 0),
1180SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1181 0, 1, 0),
1182};
1183
1184static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1185SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1186 5, 1, 0),
1187SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1188 4, 1, 0),
1189SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1190 2, 1, 0),
1191SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1192 1, 1, 0),
1193SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1194 0, 1, 0),
1195};
1196
1197#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1198{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1199 .info = snd_soc_info_volsw, \
1200 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1201 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1202
1203static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1204 struct snd_ctl_elem_value *ucontrol)
1205{
9d03545d
JN		 1206 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1207 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1208 struct snd_soc_codec *codec = w->codec;
1209 int ret;
1210
1211 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1212
1213 wm8994_update_class_w(codec);
1214
1215 return ret;
1216}
1217
1218static const struct snd_kcontrol_new dac1l_mix[] = {
1219WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1220 5, 1, 0),
1221WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1222 4, 1, 0),
1223WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1224 2, 1, 0),
1225WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1226 1, 1, 0),
1227WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1228 0, 1, 0),
1229};
1230
1231static const struct snd_kcontrol_new dac1r_mix[] = {
1232WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1233 5, 1, 0),
1234WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1235 4, 1, 0),
1236WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1237 2, 1, 0),
1238WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1239 1, 1, 0),
1240WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1241 0, 1, 0),
1242};
1243
1244static const char *sidetone_text[] = {
1245 "ADC/DMIC1", "DMIC2",
1246};
1247
1248static const struct soc_enum sidetone1_enum =
1249 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1250
1251static const struct snd_kcontrol_new sidetone1_mux =
1252 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1253
1254static const struct soc_enum sidetone2_enum =
1255 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1256
1257static const struct snd_kcontrol_new sidetone2_mux =
1258 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1259
1260static const char *aif1dac_text[] = {
1261 "AIF1DACDAT", "AIF3DACDAT",
1262};
1263
1264static const struct soc_enum aif1dac_enum =
1265 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1266
1267static const struct snd_kcontrol_new aif1dac_mux =
1268 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1269
1270static const char *aif2dac_text[] = {
1271 "AIF2DACDAT", "AIF3DACDAT",
1272};
1273
1274static const struct soc_enum aif2dac_enum =
1275 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1276
1277static const struct snd_kcontrol_new aif2dac_mux =
1278 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1279
1280static const char *aif2adc_text[] = {
1281 "AIF2ADCDAT", "AIF3DACDAT",
1282};
1283
1284static const struct soc_enum aif2adc_enum =
1285 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1286
1287static const struct snd_kcontrol_new aif2adc_mux =
1288 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1289
1290static const char *aif3adc_text[] = {
c4431df0 1291 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1292};
1293
c4431df0 1294static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1295 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1296
c4431df0
MB		 1297static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1298 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1299
1300static const struct soc_enum wm8958_aif3adc_enum =
1301 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1302
1303static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1304 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1305
1306static const char *mono_pcm_out_text[] = {
1307 "None", "AIF2ADCL", "AIF2ADCR",
1308};
1309
1310static const struct soc_enum mono_pcm_out_enum =
1311 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1312
1313static const struct snd_kcontrol_new mono_pcm_out_mux =
1314 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1315
1316static const char *aif2dac_src_text[] = {
1317 "AIF2", "AIF3",
1318};
1319
1320/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1321static const struct soc_enum aif2dacl_src_enum =
1322 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1323
1324static const struct snd_kcontrol_new aif2dacl_src_mux =
1325 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1326
1327static const struct soc_enum aif2dacr_src_enum =
1328 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1329
1330static const struct snd_kcontrol_new aif2dacr_src_mux =
1331 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1332
173efa09
DP		 1333static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1334SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1335 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1336SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1337 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1338
1339SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1340 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1341SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1342 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1343SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1344 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1345SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1346 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1347SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1348 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1349
1350SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1351 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1352 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1353SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1354 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1355 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1356SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1357 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1358SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1359 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1360
1361SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1362};
1363
1364static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1365SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1366SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1367SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1368SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1369 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1370SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1371 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1372SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1373SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1374};
1375
c52fd021
DP		 1376static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1377SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1378 dac_ev, SND_SOC_DAPM_PRE_PMU),
1379SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1380 dac_ev, SND_SOC_DAPM_PRE_PMU),
1381SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1382 dac_ev, SND_SOC_DAPM_PRE_PMU),
1383SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1384 dac_ev, SND_SOC_DAPM_PRE_PMU),
1385};
1386
1387static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1388SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1389SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1390SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1391SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1392};
1393
04d28681 1394static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1395SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1396 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1397SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1398 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1399};
1400
1401static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1402SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1403SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1404};
1405
9e6e96a1
MB		 1406static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1407SND_SOC_DAPM_INPUT("DMIC1DAT"),
1408SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1409SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1410
b462c6e6
DP		 1411SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1412 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1413SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1414 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1415
9e6e96a1
MB		 1416SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1417 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1418
1419SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1420SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1421SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1422
7f94de48 1423SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1424 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1425SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1426 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1427SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1428 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1429 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1430SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1431 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1432 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1433
7f94de48 1434SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1435 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1436SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1437 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1438SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1439 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1440 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1441SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1442 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1443 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1444
1445SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1446 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1447SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1448 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1449
a3257ba8
MB		 1450SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1451 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1452SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1453 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1454
9e6e96a1
MB		 1455SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1456 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1457SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1458 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1459
1460SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1461SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1462
1463SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1464 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1465SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1466 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1467
1468SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1469 WM8994_POWER_MANAGEMENT_4, 13, 0),
1470SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1471 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1472SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1473 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1474 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1475SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1476 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1477 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1478
5567d8c6
MB		 1479SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1480SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1481SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1482SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1483
1484SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1485SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1486SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1487
5567d8c6
MB		 1488SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1489SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1490
1491SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1492
1493SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1494SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1495SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1496SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1497
1498/* Power is done with the muxes since the ADC power also controls the
1499 * downsampling chain, the chip will automatically manage the analogue
1500 * specific portions.
1501 */
1502SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1503SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1504
9e6e96a1
MB		 1505SND_SOC_DAPM_POST("Debug log", post_ev),
1506};
1507
c4431df0
MB		 1508static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1509SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1510};
9e6e96a1 1511
c4431df0
MB		 1512static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1513SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1514SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1515SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1516SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1517};
1518
1519static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1520 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1521 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1522
1523 { "DSP1CLK", NULL, "CLK_SYS" },
1524 { "DSP2CLK", NULL, "CLK_SYS" },
1525 { "DSPINTCLK", NULL, "CLK_SYS" },
1526
1527 { "AIF1ADC1L", NULL, "AIF1CLK" },
1528 { "AIF1ADC1L", NULL, "DSP1CLK" },
1529 { "AIF1ADC1R", NULL, "AIF1CLK" },
1530 { "AIF1ADC1R", NULL, "DSP1CLK" },
1531 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1532
1533 { "AIF1DAC1L", NULL, "AIF1CLK" },
1534 { "AIF1DAC1L", NULL, "DSP1CLK" },
1535 { "AIF1DAC1R", NULL, "AIF1CLK" },
1536 { "AIF1DAC1R", NULL, "DSP1CLK" },
1537 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1538
1539 { "AIF1ADC2L", NULL, "AIF1CLK" },
1540 { "AIF1ADC2L", NULL, "DSP1CLK" },
1541 { "AIF1ADC2R", NULL, "AIF1CLK" },
1542 { "AIF1ADC2R", NULL, "DSP1CLK" },
1543 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1544
1545 { "AIF1DAC2L", NULL, "AIF1CLK" },
1546 { "AIF1DAC2L", NULL, "DSP1CLK" },
1547 { "AIF1DAC2R", NULL, "AIF1CLK" },
1548 { "AIF1DAC2R", NULL, "DSP1CLK" },
1549 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1550
1551 { "AIF2ADCL", NULL, "AIF2CLK" },
1552 { "AIF2ADCL", NULL, "DSP2CLK" },
1553 { "AIF2ADCR", NULL, "AIF2CLK" },
1554 { "AIF2ADCR", NULL, "DSP2CLK" },
1555 { "AIF2ADCR", NULL, "DSPINTCLK" },
1556
1557 { "AIF2DACL", NULL, "AIF2CLK" },
1558 { "AIF2DACL", NULL, "DSP2CLK" },
1559 { "AIF2DACR", NULL, "AIF2CLK" },
1560 { "AIF2DACR", NULL, "DSP2CLK" },
1561 { "AIF2DACR", NULL, "DSPINTCLK" },
1562
1563 { "DMIC1L", NULL, "DMIC1DAT" },
1564 { "DMIC1L", NULL, "CLK_SYS" },
1565 { "DMIC1R", NULL, "DMIC1DAT" },
1566 { "DMIC1R", NULL, "CLK_SYS" },
1567 { "DMIC2L", NULL, "DMIC2DAT" },
1568 { "DMIC2L", NULL, "CLK_SYS" },
1569 { "DMIC2R", NULL, "DMIC2DAT" },
1570 { "DMIC2R", NULL, "CLK_SYS" },
1571
1572 { "ADCL", NULL, "AIF1CLK" },
1573 { "ADCL", NULL, "DSP1CLK" },
1574 { "ADCL", NULL, "DSPINTCLK" },
1575
1576 { "ADCR", NULL, "AIF1CLK" },
1577 { "ADCR", NULL, "DSP1CLK" },
1578 { "ADCR", NULL, "DSPINTCLK" },
1579
1580 { "ADCL Mux", "ADC", "ADCL" },
1581 { "ADCL Mux", "DMIC", "DMIC1L" },
1582 { "ADCR Mux", "ADC", "ADCR" },
1583 { "ADCR Mux", "DMIC", "DMIC1R" },
1584
1585 { "DAC1L", NULL, "AIF1CLK" },
1586 { "DAC1L", NULL, "DSP1CLK" },
1587 { "DAC1L", NULL, "DSPINTCLK" },
1588
1589 { "DAC1R", NULL, "AIF1CLK" },
1590 { "DAC1R", NULL, "DSP1CLK" },
1591 { "DAC1R", NULL, "DSPINTCLK" },
1592
1593 { "DAC2L", NULL, "AIF2CLK" },
1594 { "DAC2L", NULL, "DSP2CLK" },
1595 { "DAC2L", NULL, "DSPINTCLK" },
1596
1597 { "DAC2R", NULL, "AIF2DACR" },
1598 { "DAC2R", NULL, "AIF2CLK" },
1599 { "DAC2R", NULL, "DSP2CLK" },
1600 { "DAC2R", NULL, "DSPINTCLK" },
1601
1602 { "TOCLK", NULL, "CLK_SYS" },
1603
5567d8c6
MB		 1604 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1605 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1606 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1607
1608 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1609 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1610 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1611
9e6e96a1
MB		 1612 /* AIF1 outputs */
1613 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1614 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1615 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1616
1617 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1618 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1619 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1620
a3257ba8
MB		 1621 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1622 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1623 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1624
1625 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1626 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1627 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1628
9e6e96a1
MB		 1629 /* Pin level routing for AIF3 */
1630 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1631 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1632 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1633 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1634
9e6e96a1
MB		 1635 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1636 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1637 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1638 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1639 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1640 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1641 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1642
1643 /* DAC1 inputs */
9e6e96a1
MB		 1644 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1645 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1646 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1647 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1648 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1649
9e6e96a1
MB		 1650 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1651 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1652 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1653 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1654 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1655
1656 /* DAC2/AIF2 outputs */
1657 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1658 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1659 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1660 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1661 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1662 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1663
1664 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1665 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1666 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1667 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1668 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1669 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1670
7f94de48
MB		 1671 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1672 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1673 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1674 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1675
9e6e96a1
MB		 1676 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1677
1678 /* AIF3 output */
1679 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1680 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1681 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1682 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1683 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1684 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1685 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1686 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1687
1688 /* Sidetone */
1689 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1690 { "Left Sidetone", "DMIC2", "DMIC2L" },
1691 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1692 { "Right Sidetone", "DMIC2", "DMIC2R" },
1693
1694 /* Output stages */
1695 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1696 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1697
1698 { "SPKL", "DAC1 Switch", "DAC1L" },
1699 { "SPKL", "DAC2 Switch", "DAC2L" },
1700
1701 { "SPKR", "DAC1 Switch", "DAC1R" },
1702 { "SPKR", "DAC2 Switch", "DAC2R" },
1703
1704 { "Left Headphone Mux", "DAC", "DAC1L" },
1705 { "Right Headphone Mux", "DAC", "DAC1R" },
1706};
1707
173efa09
DP		 1708static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1709 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1710 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1711 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1712 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1713 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1714 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1715 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1716 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1717};
1718
1719static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1720 { "DAC1L", NULL, "DAC1L Mixer" },
1721 { "DAC1R", NULL, "DAC1R Mixer" },
1722 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1723 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1724};
1725
6ed8f148
MB		 1726static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1727 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1728 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1729 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1730 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1731 { "MICBIAS1", NULL, "CLK_SYS" },
1732 { "MICBIAS1", NULL, "MICBIAS Supply" },
1733 { "MICBIAS2", NULL, "CLK_SYS" },
1734 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1735};
1736
c4431df0
MB		 1737static const struct snd_soc_dapm_route wm8994_intercon[] = {
1738 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1739 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1740 { "MICBIAS1", NULL, "VMID" },
1741 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1742};
1743
1744static const struct snd_soc_dapm_route wm8958_intercon[] = {
1745 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1746 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1747
1748 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1749 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1750 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1751 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1752
1753 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1754 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1755
1756 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1757};
1758
9e6e96a1
MB		 1759/* The size in bits of the FLL divide multiplied by 10
1760 * to allow rounding later */
1761#define FIXED_FLL_SIZE ((1 << 16) * 10)
1762
1763struct fll_div {
1764 u16 outdiv;
1765 u16 n;
1766 u16 k;
1767 u16 clk_ref_div;
1768 u16 fll_fratio;
1769};
1770
1771static int wm8994_get_fll_config(struct fll_div *fll,
1772 int freq_in, int freq_out)
1773{
1774 u64 Kpart;
1775 unsigned int K, Ndiv, Nmod;
1776
1777 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1778
1779 /* Scale the input frequency down to <= 13.5MHz */
1780 fll->clk_ref_div = 0;
1781 while (freq_in > 13500000) {
1782 fll->clk_ref_div++;
1783 freq_in /= 2;
1784
1785 if (fll->clk_ref_div > 3)
1786 return -EINVAL;
1787 }
1788 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1789
1790 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1791 fll->outdiv = 3;
1792 while (freq_out * (fll->outdiv + 1) < 90000000) {
1793 fll->outdiv++;
1794 if (fll->outdiv > 63)
1795 return -EINVAL;
1796 }
1797 freq_out *= fll->outdiv + 1;
1798 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1799
1800 if (freq_in > 1000000) {
1801 fll->fll_fratio = 0;
7d48a6ac
MB		 1802 } else if (freq_in > 256000) {
1803 fll->fll_fratio = 1;
1804 freq_in *= 2;
1805 } else if (freq_in > 128000) {
1806 fll->fll_fratio = 2;
1807 freq_in *= 4;
1808 } else if (freq_in > 64000) {
9e6e96a1
MB		 1809 fll->fll_fratio = 3;
1810 freq_in *= 8;
7d48a6ac
MB		 1811 } else {
1812 fll->fll_fratio = 4;
1813 freq_in *= 16;
9e6e96a1
MB		 1814 }
1815 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1816
1817 /* Now, calculate N.K */
1818 Ndiv = freq_out / freq_in;
1819
1820 fll->n = Ndiv;
1821 Nmod = freq_out % freq_in;
1822 pr_debug("Nmod=%d\n", Nmod);
1823
1824 /* Calculate fractional part - scale up so we can round. */
1825 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1826
1827 do_div(Kpart, freq_in);
1828
1829 K = Kpart & 0xFFFFFFFF;
1830
1831 if ((K % 10) >= 5)
1832 K += 5;
1833
1834 /* Move down to proper range now rounding is done */
1835 fll->k = K / 10;
1836
1837 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1838
1839 return 0;
1840}
1841
f0fba2ad 1842static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1843 unsigned int freq_in, unsigned int freq_out)
1844{
b2c812e2 1845 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1846 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1847 int reg_offset, ret;
1848 struct fll_div fll;
1849 u16 reg, aif1, aif2;
c7ebf932 1850 unsigned long timeout;
4b7ed83a 1851 bool was_enabled;
9e6e96a1
MB		 1852
1853 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1854 & WM8994_AIF1CLK_ENA;
1855
1856 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1857 & WM8994_AIF2CLK_ENA;
1858
1859 switch (id) {
1860 case WM8994_FLL1:
1861 reg_offset = 0;
1862 id = 0;
1863 break;
1864 case WM8994_FLL2:
1865 reg_offset = 0x20;
1866 id = 1;
1867 break;
1868 default:
1869 return -EINVAL;
1870 }
1871
4b7ed83a
MB		 1872 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1873 was_enabled = reg & WM8994_FLL1_ENA;
1874
136ff2a2 1875 switch (src) {
7add84aa
MB		 1876 case 0:
1877 /* Allow no source specification when stopping */
1878 if (freq_out)
1879 return -EINVAL;
4514e899 1880 src = wm8994->fll[id].src;
7add84aa 1881 break;
136ff2a2
MB		 1882 case WM8994_FLL_SRC_MCLK1:
1883 case WM8994_FLL_SRC_MCLK2:
1884 case WM8994_FLL_SRC_LRCLK:
1885 case WM8994_FLL_SRC_BCLK:
1886 break;
1887 default:
1888 return -EINVAL;
1889 }
1890
9e6e96a1
MB		 1891 /* Are we changing anything? */
1892 if (wm8994->fll[id].src == src &&
1893 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1894 return 0;
1895
1896 /* If we're stopping the FLL redo the old config - no
1897 * registers will actually be written but we avoid GCC flow
1898 * analysis bugs spewing warnings.
1899 */
1900 if (freq_out)
1901 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1902 else
1903 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1904 wm8994->fll[id].out);
1905 if (ret < 0)
1906 return ret;
1907
1908 /* Gate the AIF clocks while we reclock */
1909 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1910 WM8994_AIF1CLK_ENA, 0);
1911 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1912 WM8994_AIF2CLK_ENA, 0);
1913
1914 /* We always need to disable the FLL while reconfiguring */
1915 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1916 WM8994_FLL1_ENA, 0);
1917
1918 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1919 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1920 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1921 WM8994_FLL1_OUTDIV_MASK |
1922 WM8994_FLL1_FRATIO_MASK, reg);
1923
b16db745
MB		 1924 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1925 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 1926
1927 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1928 WM8994_FLL1_N_MASK,
1929 fll.n << WM8994_FLL1_N_SHIFT);
1930
1931 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1932 WM8994_FLL1_REFCLK_DIV_MASK |
1933 WM8994_FLL1_REFCLK_SRC_MASK,
1934 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1935 (src - 1));
9e6e96a1 1936
f0f5039c
MB		 1937 /* Clear any pending completion from a previous failure */
1938 try_wait_for_completion(&wm8994->fll_locked[id]);
1939
9e6e96a1
MB		 1940 /* Enable (with fractional mode if required) */
1941 if (freq_out) {
4b7ed83a
MB		 1942 /* Enable VMID if we need it */
1943 if (!was_enabled) {
af6b6fe4
MB		 1944 active_reference(codec);
1945
4b7ed83a
MB		 1946 switch (control->type) {
1947 case WM8994:
1948 vmid_reference(codec);
1949 break;
1950 case WM8958:
1951 if (wm8994->revision < 1)
1952 vmid_reference(codec);
1953 break;
1954 default:
1955 break;
1956 }
1957 }
1958
9e6e96a1
MB		 1959 if (fll.k)
1960 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1961 else
1962 reg = WM8994_FLL1_ENA;
1963 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1964 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1965 reg);
8e9ddf81 1966
c7ebf932
MB		 1967 if (wm8994->fll_locked_irq) {
1968 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1969 msecs_to_jiffies(10));
1970 if (timeout == 0)
1971 dev_warn(codec->dev,
1972 "Timed out waiting for FLL lock\n");
1973 } else {
1974 msleep(5);
1975 }
4b7ed83a
MB		 1976 } else {
1977 if (was_enabled) {
1978 switch (control->type) {
1979 case WM8994:
1980 vmid_dereference(codec);
1981 break;
1982 case WM8958:
1983 if (wm8994->revision < 1)
1984 vmid_dereference(codec);
1985 break;
1986 default:
1987 break;
1988 }
af6b6fe4
MB		 1989
1990 active_dereference(codec);
4b7ed83a 1991 }
9e6e96a1
MB		 1992 }
1993
1994 wm8994->fll[id].in = freq_in;
1995 wm8994->fll[id].out = freq_out;
136ff2a2 1996 wm8994->fll[id].src = src;
9e6e96a1
MB		 1997
1998 /* Enable any gated AIF clocks */
1999 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2000 WM8994_AIF1CLK_ENA, aif1);
2001 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2002 WM8994_AIF2CLK_ENA, aif2);
2003
2004 configure_clock(codec);
2005
2006 return 0;
2007}
2008
c7ebf932
MB		 2009static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2010{
2011 struct completion *completion = data;
2012
2013 complete(completion);
2014
2015 return IRQ_HANDLED;
2016}
f0fba2ad 2017
66b47fdb
MB		 2018static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2019
f0fba2ad
LG		 2020static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2021 unsigned int freq_in, unsigned int freq_out)
2022{
2023 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2024}
2025
9e6e96a1
MB		 2026static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2027 int clk_id, unsigned int freq, int dir)
2028{
2029 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2030 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2031 int i;
9e6e96a1
MB		 2032
2033 switch (dai->id) {
2034 case 1:
2035 case 2:
2036 break;
2037
2038 default:
2039 /* AIF3 shares clocking with AIF1/2 */
2040 return -EINVAL;
2041 }
2042
2043 switch (clk_id) {
2044 case WM8994_SYSCLK_MCLK1:
2045 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2046 wm8994->mclk[0] = freq;
2047 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2048 dai->id, freq);
2049 break;
2050
2051 case WM8994_SYSCLK_MCLK2:
2052 /* TODO: Set GPIO AF */
2053 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2054 wm8994->mclk[1] = freq;
2055 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2056 dai->id, freq);
2057 break;
2058
2059 case WM8994_SYSCLK_FLL1:
2060 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2061 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2062 break;
2063
2064 case WM8994_SYSCLK_FLL2:
2065 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2066 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2067 break;
2068
66b47fdb
MB		 2069 case WM8994_SYSCLK_OPCLK:
2070 /* Special case - a division (times 10) is given and
2071 * no effect on main clocking.
2072 */
2073 if (freq) {
2074 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2075 if (opclk_divs[i] == freq)
2076 break;
2077 if (i == ARRAY_SIZE(opclk_divs))
2078 return -EINVAL;
2079 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2080 WM8994_OPCLK_DIV_MASK, i);
2081 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2082 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2083 } else {
2084 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2085 WM8994_OPCLK_ENA, 0);
2086 }
2087
9e6e96a1
MB		 2088 default:
2089 return -EINVAL;
2090 }
2091
2092 configure_clock(codec);
2093
2094 return 0;
2095}
2096
2097static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2098 enum snd_soc_bias_level level)
2099{
b6b05691 2100 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2101 struct wm8994 *control = wm8994->wm8994;
b6b05691 2102
5f2f3890
MB		 2103 wm_hubs_set_bias_level(codec, level);
2104
9e6e96a1
MB		 2105 switch (level) {
2106 case SND_SOC_BIAS_ON:
2107 break;
2108
2109 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2110 /* MICBIAS into regulating mode */
2111 switch (control->type) {
2112 case WM8958:
2113 case WM1811:
2114 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2115 WM8958_MICB1_MODE, 0);
2116 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2117 WM8958_MICB2_MODE, 0);
2118 break;
2119 default:
2120 break;
2121 }
af6b6fe4
MB		 2122
2123 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2124 active_reference(codec);
9e6e96a1
MB		 2125 break;
2126
2127 case SND_SOC_BIAS_STANDBY:
ce6120cc 2128 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2
MB		 2129 switch (control->type) {
2130 case WM8994:
2131 if (wm8994->revision < 4) {
2132 /* Tweak DC servo and DSP
2133 * configuration for improved
2134 * performance. */
2135 snd_soc_write(codec, 0x102, 0x3);
2136 snd_soc_write(codec, 0x56, 0x3);
2137 snd_soc_write(codec, 0x817, 0);
2138 snd_soc_write(codec, 0x102, 0);
2139 }
2140 break;
2141
2142 case WM8958:
2143 if (wm8994->revision == 0) {
2144 /* Optimise performance for rev A */
2145 snd_soc_write(codec, 0x102, 0x3);
2146 snd_soc_write(codec, 0xcb, 0x81);
2147 snd_soc_write(codec, 0x817, 0);
2148 snd_soc_write(codec, 0x102, 0);
2149
2150 snd_soc_update_bits(codec,
2151 WM8958_CHARGE_PUMP_2,
2152 WM8958_CP_DISCH,
2153 WM8958_CP_DISCH);
2154 }
2155 break;
81204c84
MB		 2156
2157 case WM1811:
2158 if (wm8994->revision < 2) {
2159 snd_soc_write(codec, 0x102, 0x3);
2160 snd_soc_write(codec, 0x5d, 0x7e);
2161 snd_soc_write(codec, 0x5e, 0x0);
2162 snd_soc_write(codec, 0x102, 0x0);
2163 }
2164 break;
b6b05691 2165 }
9e6e96a1
MB		 2166
2167 /* Discharge LINEOUT1 & 2 */
2168 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2169 WM8994_LINEOUT1_DISCH |
2170 WM8994_LINEOUT2_DISCH,
2171 WM8994_LINEOUT1_DISCH |
2172 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2173 }
2174
af6b6fe4
MB		 2175 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2176 active_dereference(codec);
2177
500fa30e
MB		 2178 /* MICBIAS into bypass mode on newer devices */
2179 switch (control->type) {
2180 case WM8958:
2181 case WM1811:
2182 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2183 WM8958_MICB1_MODE,
2184 WM8958_MICB1_MODE);
2185 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2186 WM8958_MICB2_MODE,
2187 WM8958_MICB2_MODE);
2188 break;
2189 default:
2190 break;
2191 }
9e6e96a1
MB		 2192 break;
2193
2194 case SND_SOC_BIAS_OFF:
4105ab84 2195 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2196 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2197 break;
2198 }
5f2f3890 2199
ce6120cc 2200 codec->dapm.bias_level = level;
af6b6fe4 2201
9e6e96a1
MB		 2202 return 0;
2203}
2204
2205static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2206{
2207 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2208 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2209 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2210 int ms_reg;
2211 int aif1_reg;
2212 int ms = 0;
2213 int aif1 = 0;
2214
2215 switch (dai->id) {
2216 case 1:
2217 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2218 aif1_reg = WM8994_AIF1_CONTROL_1;
2219 break;
2220 case 2:
2221 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2222 aif1_reg = WM8994_AIF2_CONTROL_1;
2223 break;
2224 default:
2225 return -EINVAL;
2226 }
2227
2228 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2229 case SND_SOC_DAIFMT_CBS_CFS:
2230 break;
2231 case SND_SOC_DAIFMT_CBM_CFM:
2232 ms = WM8994_AIF1_MSTR;
2233 break;
2234 default:
2235 return -EINVAL;
2236 }
2237
2238 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2239 case SND_SOC_DAIFMT_DSP_B:
2240 aif1 |= WM8994_AIF1_LRCLK_INV;
2241 case SND_SOC_DAIFMT_DSP_A:
2242 aif1 |= 0x18;
2243 break;
2244 case SND_SOC_DAIFMT_I2S:
2245 aif1 |= 0x10;
2246 break;
2247 case SND_SOC_DAIFMT_RIGHT_J:
2248 break;
2249 case SND_SOC_DAIFMT_LEFT_J:
2250 aif1 |= 0x8;
2251 break;
2252 default:
2253 return -EINVAL;
2254 }
2255
2256 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2257 case SND_SOC_DAIFMT_DSP_A:
2258 case SND_SOC_DAIFMT_DSP_B:
2259 /* frame inversion not valid for DSP modes */
2260 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2261 case SND_SOC_DAIFMT_NB_NF:
2262 break;
2263 case SND_SOC_DAIFMT_IB_NF:
2264 aif1 |= WM8994_AIF1_BCLK_INV;
2265 break;
2266 default:
2267 return -EINVAL;
2268 }
2269 break;
2270
2271 case SND_SOC_DAIFMT_I2S:
2272 case SND_SOC_DAIFMT_RIGHT_J:
2273 case SND_SOC_DAIFMT_LEFT_J:
2274 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2275 case SND_SOC_DAIFMT_NB_NF:
2276 break;
2277 case SND_SOC_DAIFMT_IB_IF:
2278 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2279 break;
2280 case SND_SOC_DAIFMT_IB_NF:
2281 aif1 |= WM8994_AIF1_BCLK_INV;
2282 break;
2283 case SND_SOC_DAIFMT_NB_IF:
2284 aif1 |= WM8994_AIF1_LRCLK_INV;
2285 break;
2286 default:
2287 return -EINVAL;
2288 }
2289 break;
2290 default:
2291 return -EINVAL;
2292 }
2293
c4431df0
MB		 2294 /* The AIF2 format configuration needs to be mirrored to AIF3
2295 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2296 switch (control->type) {
2297 case WM1811:
2298 case WM8958:
2299 if (dai->id == 2)
2300 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2301 WM8994_AIF1_LRCLK_INV |
2302 WM8958_AIF3_FMT_MASK, aif1);
2303 break;
2304
2305 default:
2306 break;
2307 }
c4431df0 2308
9e6e96a1
MB		 2309 snd_soc_update_bits(codec, aif1_reg,
2310 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2311 WM8994_AIF1_FMT_MASK,
2312 aif1);
2313 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2314 ms);
2315
2316 return 0;
2317}
2318
2319static struct {
2320 int val, rate;
2321} srs[] = {
2322 { 0, 8000 },
2323 { 1, 11025 },
2324 { 2, 12000 },
2325 { 3, 16000 },
2326 { 4, 22050 },
2327 { 5, 24000 },
2328 { 6, 32000 },
2329 { 7, 44100 },
2330 { 8, 48000 },
2331 { 9, 88200 },
2332 { 10, 96000 },
2333};
2334
2335static int fs_ratios[] = {
2336 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2337};
2338
2339static int bclk_divs[] = {
2340 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2341 640, 880, 960, 1280, 1760, 1920
2342};
2343
2344static int wm8994_hw_params(struct snd_pcm_substream *substream,
2345 struct snd_pcm_hw_params *params,
2346 struct snd_soc_dai *dai)
2347{
2348 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2349 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2350 int aif1_reg;
b1e43d93 2351 int aif2_reg;
9e6e96a1
MB		 2352 int bclk_reg;
2353 int lrclk_reg;
2354 int rate_reg;
2355 int aif1 = 0;
b1e43d93 2356 int aif2 = 0;
9e6e96a1
MB		 2357 int bclk = 0;
2358 int lrclk = 0;
2359 int rate_val = 0;
2360 int id = dai->id - 1;
2361
2362 int i, cur_val, best_val, bclk_rate, best;
2363
2364 switch (dai->id) {
2365 case 1:
2366 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2367 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2368 bclk_reg = WM8994_AIF1_BCLK;
2369 rate_reg = WM8994_AIF1_RATE;
2370 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2371 wm8994->lrclk_shared[0]) {
9e6e96a1 2372 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2373 } else {
9e6e96a1 2374 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2375 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2376 }
9e6e96a1
MB		 2377 break;
2378 case 2:
2379 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2380 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2381 bclk_reg = WM8994_AIF2_BCLK;
2382 rate_reg = WM8994_AIF2_RATE;
2383 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2384 wm8994->lrclk_shared[1]) {
9e6e96a1 2385 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2386 } else {
9e6e96a1 2387 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2388 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2389 }
9e6e96a1
MB		 2390 break;
2391 default:
2392 return -EINVAL;
2393 }
2394
2395 bclk_rate = params_rate(params) * 2;
2396 switch (params_format(params)) {
2397 case SNDRV_PCM_FORMAT_S16_LE:
2398 bclk_rate *= 16;
2399 break;
2400 case SNDRV_PCM_FORMAT_S20_3LE:
2401 bclk_rate *= 20;
2402 aif1 |= 0x20;
2403 break;
2404 case SNDRV_PCM_FORMAT_S24_LE:
2405 bclk_rate *= 24;
2406 aif1 |= 0x40;
2407 break;
2408 case SNDRV_PCM_FORMAT_S32_LE:
2409 bclk_rate *= 32;
2410 aif1 |= 0x60;
2411 break;
2412 default:
2413 return -EINVAL;
2414 }
2415
2416 /* Try to find an appropriate sample rate; look for an exact match. */
2417 for (i = 0; i < ARRAY_SIZE(srs); i++)
2418 if (srs[i].rate == params_rate(params))
2419 break;
2420 if (i == ARRAY_SIZE(srs))
2421 return -EINVAL;
2422 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2423
2424 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2425 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2426 dai->id, wm8994->aifclk[id], bclk_rate);
2427
b1e43d93
MB		 2428 if (params_channels(params) == 1 &&
2429 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2430 aif2 |= WM8994_AIF1_MONO;
2431
9e6e96a1
MB		 2432 if (wm8994->aifclk[id] == 0) {
2433 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2434 return -EINVAL;
2435 }
2436
2437 /* AIFCLK/fs ratio; look for a close match in either direction */
2438 best = 0;
2439 best_val = abs((fs_ratios[0] * params_rate(params))
2440 - wm8994->aifclk[id]);
2441 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2442 cur_val = abs((fs_ratios[i] * params_rate(params))
2443 - wm8994->aifclk[id]);
2444 if (cur_val >= best_val)
2445 continue;
2446 best = i;
2447 best_val = cur_val;
2448 }
2449 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2450 dai->id, fs_ratios[best]);
2451 rate_val |= best;
2452
2453 /* We may not get quite the right frequency if using
2454 * approximate clocks so look for the closest match that is
2455 * higher than the target (we need to ensure that there enough
2456 * BCLKs to clock out the samples).
2457 */
2458 best = 0;
2459 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2460 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2461 if (cur_val < 0) /* BCLK table is sorted */
2462 break;
2463 best = i;
2464 }
07cd8ada 2465 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2466 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2467 bclk_divs[best], bclk_rate);
2468 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2469
2470 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2471 if (!lrclk) {
2472 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2473 bclk_rate);
2474 return -EINVAL;
2475 }
9e6e96a1
MB		 2476 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2477 lrclk, bclk_rate / lrclk);
2478
2479 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2480 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2481 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2482 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2483 lrclk);
2484 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2485 WM8994_AIF1CLK_RATE_MASK, rate_val);
2486
2487 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2488 switch (dai->id) {
2489 case 1:
2490 wm8994->dac_rates[0] = params_rate(params);
2491 wm8994_set_retune_mobile(codec, 0);
2492 wm8994_set_retune_mobile(codec, 1);
2493 break;
2494 case 2:
2495 wm8994->dac_rates[1] = params_rate(params);
2496 wm8994_set_retune_mobile(codec, 2);
2497 break;
2498 }
2499 }
2500
2501 return 0;
2502}
2503
c4431df0
MB		 2504static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2505 struct snd_pcm_hw_params *params,
2506 struct snd_soc_dai *dai)
2507{
2508 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2509 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2510 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2511 int aif1_reg;
2512 int aif1 = 0;
2513
2514 switch (dai->id) {
2515 case 3:
2516 switch (control->type) {
81204c84 2517 case WM1811:
c4431df0
MB		 2518 case WM8958:
2519 aif1_reg = WM8958_AIF3_CONTROL_1;
2520 break;
2521 default:
2522 return 0;
2523 }
2524 default:
2525 return 0;
2526 }
2527
2528 switch (params_format(params)) {
2529 case SNDRV_PCM_FORMAT_S16_LE:
2530 break;
2531 case SNDRV_PCM_FORMAT_S20_3LE:
2532 aif1 |= 0x20;
2533 break;
2534 case SNDRV_PCM_FORMAT_S24_LE:
2535 aif1 |= 0x40;
2536 break;
2537 case SNDRV_PCM_FORMAT_S32_LE:
2538 aif1 |= 0x60;
2539 break;
2540 default:
2541 return -EINVAL;
2542 }
2543
2544 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2545}
2546
7d02173c
MB		 2547static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2548 struct snd_soc_dai *dai)
2549{
2550 struct snd_soc_codec *codec = dai->codec;
2551 int rate_reg = 0;
2552
2553 switch (dai->id) {
2554 case 1:
2555 rate_reg = WM8994_AIF1_RATE;
2556 break;
2557 case 2:
c527e6aa 2558 rate_reg = WM8994_AIF2_RATE;
7d02173c
MB		 2559 break;
2560 default:
2561 break;
2562 }
2563
2564 /* If the DAI is idle then configure the divider tree for the
2565 * lowest output rate to save a little power if the clock is
2566 * still active (eg, because it is system clock).
2567 */
2568 if (rate_reg && !dai->playback_active && !dai->capture_active)
2569 snd_soc_update_bits(codec, rate_reg,
2570 WM8994_AIF1_SR_MASK |
2571 WM8994_AIF1CLK_RATE_MASK, 0x9);
2572}
2573
9e6e96a1
MB		 2574static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2575{
2576 struct snd_soc_codec *codec = codec_dai->codec;
2577 int mute_reg;
2578 int reg;
2579
2580 switch (codec_dai->id) {
2581 case 1:
2582 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2583 break;
2584 case 2:
2585 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2586 break;
2587 default:
2588 return -EINVAL;
2589 }
2590
2591 if (mute)
2592 reg = WM8994_AIF1DAC1_MUTE;
2593 else
2594 reg = 0;
2595
2596 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2597
2598 return 0;
2599}
2600
778a76e2
MB		 2601static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2602{
2603 struct snd_soc_codec *codec = codec_dai->codec;
2604 int reg, val, mask;
2605
2606 switch (codec_dai->id) {
2607 case 1:
2608 reg = WM8994_AIF1_MASTER_SLAVE;
2609 mask = WM8994_AIF1_TRI;
2610 break;
2611 case 2:
2612 reg = WM8994_AIF2_MASTER_SLAVE;
2613 mask = WM8994_AIF2_TRI;
2614 break;
2615 case 3:
2616 reg = WM8994_POWER_MANAGEMENT_6;
2617 mask = WM8994_AIF3_TRI;
2618 break;
2619 default:
2620 return -EINVAL;
2621 }
2622
2623 if (tristate)
2624 val = mask;
2625 else
2626 val = 0;
2627
78b3fb46 2628 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2629}
2630
d09f3ecf
MB		 2631static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2632{
2633 struct snd_soc_codec *codec = dai->codec;
2634
2635 /* Disable the pulls on the AIF if we're using it to save power. */
2636 snd_soc_update_bits(codec, WM8994_GPIO_3,
2637 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2638 snd_soc_update_bits(codec, WM8994_GPIO_4,
2639 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2640 snd_soc_update_bits(codec, WM8994_GPIO_5,
2641 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2642
2643 return 0;
2644}
2645
9e6e96a1
MB		 2646#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2647
2648#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2649 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2650
85e7652d 2651static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2652 .set_sysclk = wm8994_set_dai_sysclk,
2653 .set_fmt = wm8994_set_dai_fmt,
2654 .hw_params = wm8994_hw_params,
7d02173c 2655 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2656 .digital_mute = wm8994_aif_mute,
2657 .set_pll = wm8994_set_fll,
778a76e2 2658 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2659};
2660
85e7652d 2661static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2662 .set_sysclk = wm8994_set_dai_sysclk,
2663 .set_fmt = wm8994_set_dai_fmt,
2664 .hw_params = wm8994_hw_params,
7d02173c 2665 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2666 .digital_mute = wm8994_aif_mute,
2667 .set_pll = wm8994_set_fll,
778a76e2
MB		 2668 .set_tristate = wm8994_set_tristate,
2669};
2670
85e7652d 2671static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2672 .hw_params = wm8994_aif3_hw_params,
778a76e2 2673 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2674};
2675
f0fba2ad 2676static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2677 {
f0fba2ad 2678 .name = "wm8994-aif1",
8c7f78b3 2679 .id = 1,
9e6e96a1
MB		 2680 .playback = {
2681 .stream_name = "AIF1 Playback",
b1e43d93 2682 .channels_min = 1,
9e6e96a1
MB		 2683 .channels_max = 2,
2684 .rates = WM8994_RATES,
2685 .formats = WM8994_FORMATS,
99b0292d 2686 .sig_bits = 24,
9e6e96a1
MB		 2687 },
2688 .capture = {
2689 .stream_name = "AIF1 Capture",
b1e43d93 2690 .channels_min = 1,
9e6e96a1
MB		 2691 .channels_max = 2,
2692 .rates = WM8994_RATES,
2693 .formats = WM8994_FORMATS,
99b0292d 2694 .sig_bits = 24,
9e6e96a1
MB		 2695 },
2696 .ops = &wm8994_aif1_dai_ops,
2697 },
2698 {
f0fba2ad 2699 .name = "wm8994-aif2",
8c7f78b3 2700 .id = 2,
9e6e96a1
MB		 2701 .playback = {
2702 .stream_name = "AIF2 Playback",
b1e43d93 2703 .channels_min = 1,
9e6e96a1
MB		 2704 .channels_max = 2,
2705 .rates = WM8994_RATES,
2706 .formats = WM8994_FORMATS,
99b0292d 2707 .sig_bits = 24,
9e6e96a1
MB		 2708 },
2709 .capture = {
2710 .stream_name = "AIF2 Capture",
b1e43d93 2711 .channels_min = 1,
9e6e96a1
MB		 2712 .channels_max = 2,
2713 .rates = WM8994_RATES,
2714 .formats = WM8994_FORMATS,
99b0292d 2715 .sig_bits = 24,
9e6e96a1 2716 },
d09f3ecf 2717 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2718 .ops = &wm8994_aif2_dai_ops,
2719 },
2720 {
f0fba2ad 2721 .name = "wm8994-aif3",
8c7f78b3 2722 .id = 3,
9e6e96a1
MB		 2723 .playback = {
2724 .stream_name = "AIF3 Playback",
b1e43d93 2725 .channels_min = 1,
9e6e96a1
MB		 2726 .channels_max = 2,
2727 .rates = WM8994_RATES,
2728 .formats = WM8994_FORMATS,
99b0292d 2729 .sig_bits = 24,
9e6e96a1 2730 },
a8462bde 2731 .capture = {
9e6e96a1 2732 .stream_name = "AIF3 Capture",
b1e43d93 2733 .channels_min = 1,
9e6e96a1
MB		 2734 .channels_max = 2,
2735 .rates = WM8994_RATES,
2736 .formats = WM8994_FORMATS,
99b0292d
MB		 2737 .sig_bits = 24,
2738 },
778a76e2 2739 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2740 }
2741};
9e6e96a1
MB		 2742
2743#ifdef CONFIG_PM
84b315ee 2744static int wm8994_suspend(struct snd_soc_codec *codec)
9e6e96a1 2745{
b2c812e2 2746 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2747 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2748 int i, ret;
2749
ca629928
MB		 2750 switch (control->type) {
2751 case WM8994:
2752 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2753 break;
81204c84 2754 case WM1811:
af6b6fe4
MB		 2755 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2756 WM1811_JACKDET_MODE_MASK, 0);
2757 /* Fall through */
ca629928
MB		 2758 case WM8958:
2759 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2760 WM8958_MICD_ENA, 0);
2761 break;
2762 }
2763
9e6e96a1
MB		 2764 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2765 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2766 sizeof(struct wm8994_fll_config));
f0fba2ad 2767 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2768 if (ret < 0)
2769 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2770 i + 1, ret);
2771 }
2772
2773 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2774
2775 return 0;
2776}
2777
f0fba2ad 2778static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2779{
b2c812e2 2780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2781 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2782 int i, ret;
c52fd021
DP		 2783 unsigned int val, mask;
2784
2785 if (wm8994->revision < 4) {
2786 /* force a HW read */
d9a7666f
MB		 2787 ret = regmap_read(control->regmap,
2788 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 2789
2790 /* modify the cache only */
2791 codec->cache_only = 1;
2792 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2793 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2794 val &= mask;
2795 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2796 mask, val);
2797 codec->cache_only = 0;
2798 }
9e6e96a1 2799
9e6e96a1 2800 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2801 if (!wm8994->fll_suspend[i].out)
2802 continue;
2803
f0fba2ad 2804 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2805 wm8994->fll_suspend[i].src,
2806 wm8994->fll_suspend[i].in,
2807 wm8994->fll_suspend[i].out);
2808 if (ret < 0)
2809 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2810 i + 1, ret);
2811 }
2812
ca629928
MB		 2813 switch (control->type) {
2814 case WM8994:
2815 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2816 snd_soc_update_bits(codec, WM8994_MICBIAS,
2817 WM8994_MICD_ENA, WM8994_MICD_ENA);
2818 break;
81204c84 2819 case WM1811:
af6b6fe4
MB		 2820 if (wm8994->jackdet && wm8994->jack_cb) {
2821 /* Restart from idle */
2822 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2823 WM1811_JACKDET_MODE_MASK,
2824 WM1811_JACKDET_MODE_JACK);
2825 break;
2826 }
ca629928
MB		 2827 case WM8958:
2828 if (wm8994->jack_cb)
2829 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2830 WM8958_MICD_ENA, WM8958_MICD_ENA);
2831 break;
2832 }
2833
9e6e96a1
MB		 2834 return 0;
2835}
2836#else
2837#define wm8994_suspend NULL
2838#define wm8994_resume NULL
2839#endif
2840
2841static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2842{
f0fba2ad 2843 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2844 struct wm8994_pdata *pdata = wm8994->pdata;
2845 struct snd_kcontrol_new controls[] = {
2846 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2847 wm8994->retune_mobile_enum,
2848 wm8994_get_retune_mobile_enum,
2849 wm8994_put_retune_mobile_enum),
2850 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2851 wm8994->retune_mobile_enum,
2852 wm8994_get_retune_mobile_enum,
2853 wm8994_put_retune_mobile_enum),
2854 SOC_ENUM_EXT("AIF2 EQ Mode",
2855 wm8994->retune_mobile_enum,
2856 wm8994_get_retune_mobile_enum,
2857 wm8994_put_retune_mobile_enum),
2858 };
2859 int ret, i, j;
2860 const char **t;
2861
2862 /* We need an array of texts for the enum API but the number
2863 * of texts is likely to be less than the number of
2864 * configurations due to the sample rate dependency of the
2865 * configurations. */
2866 wm8994->num_retune_mobile_texts = 0;
2867 wm8994->retune_mobile_texts = NULL;
2868 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2869 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2870 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2871 wm8994->retune_mobile_texts[j]) == 0)
2872 break;
2873 }
2874
2875 if (j != wm8994->num_retune_mobile_texts)
2876 continue;
2877
2878 /* Expand the array... */
2879 t = krealloc(wm8994->retune_mobile_texts,
2880 sizeof(char *) *
2881 (wm8994->num_retune_mobile_texts + 1),
2882 GFP_KERNEL);
2883 if (t == NULL)
2884 continue;
2885
2886 /* ...store the new entry... */
2887 t[wm8994->num_retune_mobile_texts] =
2888 pdata->retune_mobile_cfgs[i].name;
2889
2890 /* ...and remember the new version. */
2891 wm8994->num_retune_mobile_texts++;
2892 wm8994->retune_mobile_texts = t;
2893 }
2894
2895 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2896 wm8994->num_retune_mobile_texts);
2897
2898 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2899 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2900
022658be 2901 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2902 ARRAY_SIZE(controls));
2903 if (ret != 0)
f0fba2ad 2904 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2905 "Failed to add ReTune Mobile controls: %d\n", ret);
2906}
2907
2908static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2909{
f0fba2ad 2910 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2911 struct wm8994_pdata *pdata = wm8994->pdata;
2912 int ret, i;
2913
2914 if (!pdata)
2915 return;
2916
2917 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2918 pdata->lineout2_diff,
2919 pdata->lineout1fb,
2920 pdata->lineout2fb,
2921 pdata->jd_scthr,
2922 pdata->jd_thr,
2923 pdata->micbias1_lvl,
2924 pdata->micbias2_lvl);
2925
2926 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2927
2928 if (pdata->num_drc_cfgs) {
2929 struct snd_kcontrol_new controls[] = {
2930 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2931 wm8994_get_drc_enum, wm8994_put_drc_enum),
2932 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2933 wm8994_get_drc_enum, wm8994_put_drc_enum),
2934 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2935 wm8994_get_drc_enum, wm8994_put_drc_enum),
2936 };
2937
2938 /* We need an array of texts for the enum API */
7270cebe
MB		 2939 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2940 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 2941 if (!wm8994->drc_texts) {
f0fba2ad 2942 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2943 "Failed to allocate %d DRC config texts\n",
2944 pdata->num_drc_cfgs);
2945 return;
2946 }
2947
2948 for (i = 0; i < pdata->num_drc_cfgs; i++)
2949 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2950
2951 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2952 wm8994->drc_enum.texts = wm8994->drc_texts;
2953
022658be 2954 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2955 ARRAY_SIZE(controls));
2956 if (ret != 0)
f0fba2ad 2957 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2958 "Failed to add DRC mode controls: %d\n", ret);
2959
2960 for (i = 0; i < WM8994_NUM_DRC; i++)
2961 wm8994_set_drc(codec, i);
2962 }
2963
2964 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2965 pdata->num_retune_mobile_cfgs);
2966
2967 if (pdata->num_retune_mobile_cfgs)
2968 wm8994_handle_retune_mobile_pdata(wm8994);
2969 else
022658be 2970 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2971 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2972
2973 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2974 if (pdata->micbias[i]) {
2975 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2976 pdata->micbias[i] & 0xffff);
2977 }
2978 }
9e6e96a1
MB		 2979}
2980
88766984
MB		 2981/**
2982 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2983 *
2984 * @codec: WM8994 codec
2985 * @jack: jack to report detection events on
2986 * @micbias: microphone bias to detect on
88766984
MB		 2987 *
2988 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2989 * being used to bring out signals to the processor then only platform
5ab230a7 2990 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2991 * be configured using snd_soc_jack_add_gpios() instead.
2992 *
2993 * Configuration of detection levels is available via the micbias1_lvl
2994 * and micbias2_lvl platform data members.
2995 */
2996int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 2997 int micbias)
88766984 2998{
b2c812e2 2999 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3000 struct wm8994_micdet *micdet;
2a8a856d 3001 struct wm8994 *control = wm8994->wm8994;
87092e3c 3002 int reg, ret;
88766984 3003
87092e3c
MB		 3004 if (control->type != WM8994) {
3005 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3006 return -EINVAL;
87092e3c 3007 }
3a423157 3008
88766984
MB		 3009 switch (micbias) {
3010 case 1:
3011 micdet = &wm8994->micdet[0];
87092e3c
MB		 3012 if (jack)
3013 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3014 "MICBIAS1");
3015 else
3016 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3017 "MICBIAS1");
88766984
MB		 3018 break;
3019 case 2:
3020 micdet = &wm8994->micdet[1];
87092e3c
MB		 3021 if (jack)
3022 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3023 "MICBIAS1");
3024 else
3025 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3026 "MICBIAS1");
88766984
MB		 3027 break;
3028 default:
87092e3c 3029 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3030 return -EINVAL;
87092e3c 3031 }
88766984 3032
87092e3c
MB		 3033 if (ret != 0)
3034 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3035 micbias, ret);
3036
3037 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3038 micbias, jack);
88766984
MB		 3039
3040 /* Store the configuration */
3041 micdet->jack = jack;
87092e3c 3042 micdet->detecting = true;
88766984
MB		 3043
3044 /* If either of the jacks is set up then enable detection */
3045 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3046 reg = WM8994_MICD_ENA;
87092e3c 3047 else
88766984
MB		 3048 reg = 0;
3049
3050 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3051
87092e3c
MB		 3052 snd_soc_dapm_sync(&codec->dapm);
3053
88766984
MB		 3054 return 0;
3055}
3056EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3057
3058static irqreturn_t wm8994_mic_irq(int irq, void *data)
3059{
3060 struct wm8994_priv *priv = data;
f0fba2ad 3061 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3062 int reg;
3063 int report;
3064
7116f452 3065#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3066 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3067#endif
2bbb5d66 3068
88766984
MB		 3069 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3070 if (reg < 0) {
3071 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3072 reg);
3073 return IRQ_HANDLED;
3074 }
3075
3076 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3077
3078 report = 0;
87092e3c
MB		 3079 if (reg & WM8994_MIC1_DET_STS) {
3080 if (priv->micdet[0].detecting)
3081 report = SND_JACK_HEADSET;
3082 }
3083 if (reg & WM8994_MIC1_SHRT_STS) {
3084 if (priv->micdet[0].detecting)
3085 report = SND_JACK_HEADPHONE;
3086 else
3087 report |= SND_JACK_BTN_0;
3088 }
3089 if (report)
3090 priv->micdet[0].detecting = false;
3091 else
3092 priv->micdet[0].detecting = true;
3093
88766984 3094 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3095 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3096
3097 report = 0;
87092e3c
MB		 3098 if (reg & WM8994_MIC2_DET_STS) {
3099 if (priv->micdet[1].detecting)
3100 report = SND_JACK_HEADSET;
3101 }
3102 if (reg & WM8994_MIC2_SHRT_STS) {
3103 if (priv->micdet[1].detecting)
3104 report = SND_JACK_HEADPHONE;
3105 else
3106 report |= SND_JACK_BTN_0;
3107 }
3108 if (report)
3109 priv->micdet[1].detecting = false;
3110 else
3111 priv->micdet[1].detecting = true;
3112
88766984 3113 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3114 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3115
3116 return IRQ_HANDLED;
3117}
3118
821edd2f
MB		 3119/* Default microphone detection handler for WM8958 - the user can
3120 * override this if they wish.
3121 */
3122static void wm8958_default_micdet(u16 status, void *data)
3123{
3124 struct snd_soc_codec *codec = data;
3125 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3126 int report;
821edd2f 3127
a1691343
MB		 3128 dev_dbg(codec->dev, "MICDET %x\n", status);
3129
af6b6fe4 3130 /* Either nothing present or just starting detection */
b00adf76 3131 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3132 if (!wm8994->jackdet) {
3133 /* If nothing present then clear our statuses */
3134 dev_dbg(codec->dev, "Detected open circuit\n");
3135 wm8994->jack_mic = false;
3136 wm8994->mic_detecting = true;
b00adf76 3137
af6b6fe4 3138 wm8958_micd_set_rate(codec);
b00adf76 3139
af6b6fe4
MB		 3140 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3141 wm8994->btn_mask |
3142 SND_JACK_HEADSET);
3143 }
b00adf76
MB		 3144 return;
3145 }
821edd2f 3146
b00adf76
MB		 3147 /* If the measurement is showing a high impedence we've got a
3148 * microphone.
3149 */
157a75e6 3150 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3151 dev_dbg(codec->dev, "Detected microphone\n");
3152
157a75e6 3153 wm8994->mic_detecting = false;
b00adf76
MB		 3154 wm8994->jack_mic = true;
3155
3156 wm8958_micd_set_rate(codec);
3157
3158 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3159 SND_JACK_HEADSET);
3160 }
821edd2f 3161
b00adf76 3162
7c08b51f 3163 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3164 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3165 wm8994->mic_detecting = false;
b00adf76
MB		 3166
3167 wm8958_micd_set_rate(codec);
3168
3169 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3170 SND_JACK_HEADSET);
af6b6fe4
MB		 3171
3172 /* If we have jackdet that will detect removal */
3173 if (wm8994->jackdet) {
3174 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3175 WM8958_MICD_ENA, 0);
3176
07fb9d9e
MB		 3177 if (wm8994->pdata->jd_ext_cap) {
3178 mutex_lock(&codec->mutex);
3179 snd_soc_dapm_disable_pin(&codec->dapm,
3180 "MICBIAS2");
3181 snd_soc_dapm_sync(&codec->dapm);
3182 mutex_unlock(&codec->mutex);
3183 }
b9e67e5e
MB		 3184
3185 wm1811_jackdet_set_mode(codec,
3186 WM1811_JACKDET_MODE_JACK);
af6b6fe4 3187 }
b00adf76
MB		 3188 }
3189
3190 /* Report short circuit as a button */
3191 if (wm8994->jack_mic) {
4585790d 3192 report = 0;
b00adf76 3193 if (status & 0x4)
4585790d
MB		 3194 report |= SND_JACK_BTN_0;
3195
3196 if (status & 0x8)
3197 report |= SND_JACK_BTN_1;
3198
3199 if (status & 0x10)
3200 report |= SND_JACK_BTN_2;
3201
3202 if (status & 0x20)
3203 report |= SND_JACK_BTN_3;
3204
3205 if (status & 0x40)
3206 report |= SND_JACK_BTN_4;
3207
3208 if (status & 0x80)
3209 report |= SND_JACK_BTN_5;
3210
3211 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3212 wm8994->btn_mask);
b00adf76 3213 }
821edd2f
MB		 3214}
3215
af6b6fe4
MB		 3216static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3217{
3218 struct wm8994_priv *wm8994 = data;
3219 struct snd_soc_codec *codec = wm8994->codec;
3220 int reg;
3221
3222 mutex_lock(&wm8994->accdet_lock);
3223
3224 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3225 if (reg < 0) {
3226 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3227 mutex_unlock(&wm8994->accdet_lock);
3228 return IRQ_NONE;
3229 }
3230
3231 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3232
3233 if (reg & WM1811_JACKDET_LVL) {
3234 dev_dbg(codec->dev, "Jack detected\n");
3235
3236 snd_soc_jack_report(wm8994->micdet[0].jack,
3237 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3238
55a27786
MB		 3239 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3240 WM8958_MICB2_DISCH, 0);
3241
378ec0ca
MB		 3242 /* Disable debounce while inserted */
3243 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3244 WM1811_JACKDET_DB, 0);
3245
af6b6fe4
MB		 3246 /*
3247 * Start off measument of microphone impedence to find
3248 * out what's actually there.
3249 */
3250 wm8994->mic_detecting = true;
3251 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
b9e67e5e 3252
af6b6fe4
MB		 3253 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3254 WM8958_MICD_ENA, WM8958_MICD_ENA);
b9e67e5e
MB		 3255
3256 /* If required for an external cap force MICBIAS on */
3257 if (wm8994->pdata->jd_ext_cap) {
3258 mutex_lock(&codec->mutex);
3259 snd_soc_dapm_force_enable_pin(&codec->dapm,
3260 "MICBIAS2");
3261 snd_soc_dapm_sync(&codec->dapm);
3262 mutex_unlock(&codec->mutex);
3263 }
af6b6fe4
MB		 3264 } else {
3265 dev_dbg(codec->dev, "Jack not detected\n");
3266
55a27786
MB		 3267 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3268 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3269
07fb9d9e
MB		 3270 if (wm8994->pdata->jd_ext_cap) {
3271 mutex_lock(&codec->mutex);
3272 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3273 snd_soc_dapm_sync(&codec->dapm);
3274 mutex_unlock(&codec->mutex);
3275 }
3276
af6b6fe4
MB		 3277 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3278 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3279 wm8994->btn_mask);
3280
378ec0ca
MB		 3281 /* Enable debounce while removed */
3282 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3283 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3284
af6b6fe4
MB		 3285 wm8994->mic_detecting = false;
3286 wm8994->jack_mic = false;
3287 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3288 WM8958_MICD_ENA, 0);
3289 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3290 }
3291
3292 mutex_unlock(&wm8994->accdet_lock);
3293
3294 return IRQ_HANDLED;
3295}
3296
821edd2f
MB		 3297/**
3298 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3299 *
3300 * @codec: WM8958 codec
3301 * @jack: jack to report detection events on
3302 *
3303 * Enable microphone detection functionality for the WM8958. By
3304 * default simple detection which supports the detection of up to 6
3305 * buttons plus video and microphone functionality is supported.
3306 *
3307 * The WM8958 has an advanced jack detection facility which is able to
3308 * support complex accessory detection, especially when used in
3309 * conjunction with external circuitry. In order to provide maximum
3310 * flexiblity a callback is provided which allows a completely custom
3311 * detection algorithm.
3312 */
3313int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3314 wm8958_micdet_cb cb, void *cb_data)
3315{
3316 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3317 struct wm8994 *control = wm8994->wm8994;
4585790d 3318 u16 micd_lvl_sel;
821edd2f 3319
81204c84
MB		 3320 switch (control->type) {
3321 case WM1811:
3322 case WM8958:
3323 break;
3324 default:
821edd2f 3325 return -EINVAL;
81204c84 3326 }
821edd2f
MB		 3327
3328 if (jack) {
3329 if (!cb) {
3330 dev_dbg(codec->dev, "Using default micdet callback\n");
3331 cb = wm8958_default_micdet;
3332 cb_data = codec;
3333 }
3334
4cdf5e49 3335 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3336 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3337
821edd2f
MB		 3338 wm8994->micdet[0].jack = jack;
3339 wm8994->jack_cb = cb;
3340 wm8994->jack_cb_data = cb_data;
3341
157a75e6 3342 wm8994->mic_detecting = true;
b00adf76
MB		 3343 wm8994->jack_mic = false;
3344
3345 wm8958_micd_set_rate(codec);
3346
4585790d
MB		 3347 /* Detect microphones and short circuits by default */
3348 if (wm8994->pdata->micd_lvl_sel)
3349 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3350 else
3351 micd_lvl_sel = 0x41;
3352
3353 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3354 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3355 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3356
b00adf76 3357 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3358 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3359
af6b6fe4
MB		 3360 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3361
3362 /*
3363 * If we can use jack detection start off with that,
3364 * otherwise jump straight to microphone detection.
3365 */
3366 if (wm8994->jackdet) {
55a27786
MB		 3367 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3368 WM8958_MICB2_DISCH,
3369 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3370 snd_soc_update_bits(codec, WM8994_LDO_1,
3371 WM8994_LDO1_DISCH, 0);
3372 wm1811_jackdet_set_mode(codec,
3373 WM1811_JACKDET_MODE_JACK);
3374 } else {
3375 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3376 WM8958_MICD_ENA, WM8958_MICD_ENA);
3377 }
3378
821edd2f
MB		 3379 } else {
3380 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3381 WM8958_MICD_ENA, 0);
afaf1591 3382 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3383 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3384 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3385 }
3386
3387 return 0;
3388}
3389EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3390
3391static irqreturn_t wm8958_mic_irq(int irq, void *data)
3392{
3393 struct wm8994_priv *wm8994 = data;
3394 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3395 int reg, count;
821edd2f 3396
af6b6fe4
MB		 3397 mutex_lock(&wm8994->accdet_lock);
3398
3399 /*
3400 * Jack detection may have detected a removal simulataneously
3401 * with an update of the MICDET status; if so it will have
3402 * stopped detection and we can ignore this interrupt.
3403 */
3404 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3405 mutex_unlock(&wm8994->accdet_lock);
3406 return IRQ_HANDLED;
3407 }
3408
19940b3d
MB		 3409 /* We may occasionally read a detection without an impedence
3410 * range being provided - if that happens loop again.
3411 */
3412 count = 10;
3413 do {
3414 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3415 if (reg < 0) {
af6b6fe4 3416 mutex_unlock(&wm8994->accdet_lock);
19940b3d
MB		 3417 dev_err(codec->dev,
3418 "Failed to read mic detect status: %d\n",
3419 reg);
3420 return IRQ_NONE;
3421 }
821edd2f 3422
19940b3d
MB		 3423 if (!(reg & WM8958_MICD_VALID)) {
3424 dev_dbg(codec->dev, "Mic detect data not valid\n");
3425 goto out;
3426 }
3427
3428 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3429 break;
3430
3431 msleep(1);
3432 } while (count--);
3433
3434 if (count == 0)
3435 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3436
7116f452 3437#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3438 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3439#endif
2bbb5d66 3440
821edd2f
MB		 3441 if (wm8994->jack_cb)
3442 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3443 else
3444 dev_warn(codec->dev, "Accessory detection with no callback\n");
3445
3446out:
af6b6fe4
MB		 3447 mutex_unlock(&wm8994->accdet_lock);
3448
821edd2f
MB		 3449 return IRQ_HANDLED;
3450}
3451
3b1af3f8
MB		 3452static irqreturn_t wm8994_fifo_error(int irq, void *data)
3453{
3454 struct snd_soc_codec *codec = data;
3455
3456 dev_err(codec->dev, "FIFO error\n");
3457
3458 return IRQ_HANDLED;
3459}
3460
f0b182b0
MB		 3461static irqreturn_t wm8994_temp_warn(int irq, void *data)
3462{
3463 struct snd_soc_codec *codec = data;
3464
3465 dev_err(codec->dev, "Thermal warning\n");
3466
3467 return IRQ_HANDLED;
3468}
3469
3470static irqreturn_t wm8994_temp_shut(int irq, void *data)
3471{
3472 struct snd_soc_codec *codec = data;
3473
3474 dev_crit(codec->dev, "Thermal shutdown\n");
3475
3476 return IRQ_HANDLED;
3477}
3478
f0fba2ad 3479static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3480{
d9a7666f 3481 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3482 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3483 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3484 unsigned int reg;
ec62dbd7 3485 int ret, i;
9e6e96a1 3486
2bc16ed8 3487 wm8994->codec = codec;
d9a7666f 3488 codec->control_data = control->regmap;
9e6e96a1 3489
d9a7666f 3490 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3491
f0fba2ad 3492 wm8994->codec = codec;
9e6e96a1 3493
af6b6fe4
MB		 3494 mutex_init(&wm8994->accdet_lock);
3495
c7ebf932
MB		 3496 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3497 init_completion(&wm8994->fll_locked[i]);
3498
9b7c525d
MB		 3499 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3500 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3501 else if (wm8994->pdata && wm8994->pdata->irq_base)
3502 wm8994->micdet_irq = wm8994->pdata->irq_base +
3503 WM8994_IRQ_MIC1_DET;
3504
39fb51a1 3505 pm_runtime_enable(codec->dev);
5fab5174 3506 pm_runtime_idle(codec->dev);
39fb51a1 3507
f959dee9
MB		 3508 /* By default use idle_bias_off, will override for WM8994 */
3509 codec->dapm.idle_bias_off = 1;
3510
9e6e96a1 3511 /* Set revision-specific configuration */
b6b05691 3512 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3513 switch (control->type) {
3514 case WM8994:
f959dee9
MB		 3515 /* Single ended line outputs should have VMID on. */
3516 if (!wm8994->pdata->lineout1_diff ||
3517 !wm8994->pdata->lineout2_diff)
3518 codec->dapm.idle_bias_off = 0;
3519
3a423157
MB		 3520 switch (wm8994->revision) {
3521 case 2:
3522 case 3:
4537c4e7
MB		 3523 wm8994->hubs.dcs_codes_l = -5;
3524 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3525 wm8994->hubs.hp_startup_mode = 1;
3526 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3527 wm8994->hubs.series_startup = 1;
3a423157
MB		 3528 break;
3529 default:
79ef0abc 3530 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3531 break;
3532 }
280ec8b7 3533 break;
3a423157
MB		 3534
3535 case WM8958:
8437f700 3536 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3537 wm8994->hubs.hp_startup_mode = 1;
9e6e96a1 3538 break;
3a423157 3539
81204c84
MB		 3540 case WM1811:
3541 wm8994->hubs.dcs_readback_mode = 2;
3542 wm8994->hubs.no_series_update = 1;
29fdc360 3543 wm8994->hubs.hp_startup_mode = 1;
67109cbe 3544 wm8994->hubs.no_cache_class_w = true;
81204c84
MB		 3545
3546 switch (wm8994->revision) {
3547 case 0:
3548 case 1:
fc8e6e86
MB		 3549 case 2:
3550 case 3:
6473a148
MB		 3551 wm8994->hubs.dcs_codes_l = -9;
3552 wm8994->hubs.dcs_codes_r = -5;
81204c84
MB		 3553 break;
3554 default:
3555 break;
3556 }
3557
3558 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3559 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3560 break;
3561
9e6e96a1
MB		 3562 default:
3563 break;
3564 }
9e6e96a1 3565
2a8a856d 3566 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3567 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3568 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3569 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3570 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3571 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3572
2a8a856d 3573 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3574 wm_hubs_dcs_done, "DC servo done",
3575 &wm8994->hubs);
3576 if (ret == 0)
3577 wm8994->hubs.dcs_done_irq = true;
3578
3a423157
MB		 3579 switch (control->type) {
3580 case WM8994:
9b7c525d
MB		 3581 if (wm8994->micdet_irq) {
3582 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3583 wm8994_mic_irq,
3584 IRQF_TRIGGER_RISING,
3585 "Mic1 detect",
3586 wm8994);
3587 if (ret != 0)
3588 dev_warn(codec->dev,
3589 "Failed to request Mic1 detect IRQ: %d\n",
3590 ret);
3591 }
3a423157 3592
2a8a856d 3593 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3594 WM8994_IRQ_MIC1_SHRT,
3595 wm8994_mic_irq, "Mic 1 short",
3596 wm8994);
3597 if (ret != 0)
3598 dev_warn(codec->dev,
3599 "Failed to request Mic1 short IRQ: %d\n",
3600 ret);
3601
2a8a856d 3602 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3603 WM8994_IRQ_MIC2_DET,
3604 wm8994_mic_irq, "Mic 2 detect",
3605 wm8994);
3606 if (ret != 0)
3607 dev_warn(codec->dev,
3608 "Failed to request Mic2 detect IRQ: %d\n",
3609 ret);
3610
2a8a856d 3611 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3612 WM8994_IRQ_MIC2_SHRT,
3613 wm8994_mic_irq, "Mic 2 short",
3614 wm8994);
3615 if (ret != 0)
3616 dev_warn(codec->dev,
3617 "Failed to request Mic2 short IRQ: %d\n",
3618 ret);
3619 break;
821edd2f
MB		 3620
3621 case WM8958:
81204c84 3622 case WM1811:
9b7c525d
MB		 3623 if (wm8994->micdet_irq) {
3624 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3625 wm8958_mic_irq,
3626 IRQF_TRIGGER_RISING,
3627 "Mic detect",
3628 wm8994);
3629 if (ret != 0)
3630 dev_warn(codec->dev,
3631 "Failed to request Mic detect IRQ: %d\n",
3632 ret);
3633 }
3a423157 3634 }
88766984 3635
af6b6fe4
MB		 3636 switch (control->type) {
3637 case WM1811:
3638 if (wm8994->revision > 1) {
3639 ret = wm8994_request_irq(wm8994->wm8994,
3640 WM8994_IRQ_GPIO(6),
3641 wm1811_jackdet_irq, "JACKDET",
3642 wm8994);
3643 if (ret == 0)
3644 wm8994->jackdet = true;
3645 }
3646 break;
3647 default:
3648 break;
3649 }
3650
c7ebf932
MB		 3651 wm8994->fll_locked_irq = true;
3652 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3653 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3654 WM8994_IRQ_FLL1_LOCK + i,
3655 wm8994_fll_locked_irq, "FLL lock",
3656 &wm8994->fll_locked[i]);
3657 if (ret != 0)
3658 wm8994->fll_locked_irq = false;
3659 }
3660
27060b3c
MB		 3661 /* Make sure we can read from the GPIOs if they're inputs */
3662 pm_runtime_get_sync(codec->dev);
3663
9e6e96a1
MB		 3664 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3665 * configured on init - if a system wants to do this dynamically
3666 * at runtime we can deal with that then.
3667 */
d9a7666f 3668 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3669 if (ret < 0) {
3670 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3671 goto err_irq;
9e6e96a1 3672 }
d9a7666f 3673 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3674 wm8994->lrclk_shared[0] = 1;
3675 wm8994_dai[0].symmetric_rates = 1;
3676 } else {
3677 wm8994->lrclk_shared[0] = 0;
3678 }
3679
d9a7666f 3680 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3681 if (ret < 0) {
3682 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3683 goto err_irq;
9e6e96a1 3684 }
d9a7666f 3685 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3686 wm8994->lrclk_shared[1] = 1;
3687 wm8994_dai[1].symmetric_rates = 1;
3688 } else {
3689 wm8994->lrclk_shared[1] = 0;
3690 }
3691
27060b3c
MB		 3692 pm_runtime_put(codec->dev);
3693
9e6e96a1 3694 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3695 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3696 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3697 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3698 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3699 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3700 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3701 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3702 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3703 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3704 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3705 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3706 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3707 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3708 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3709 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3710 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3711 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3712 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3713 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3714 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3715 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3716 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3717 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3718 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3719 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3720 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3721 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3722 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3723 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3724 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3725 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3726 WM8994_DAC2_VU, WM8994_DAC2_VU);
3727
3728 /* Set the low bit of the 3D stereo depth so TLV matches */
3729 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3730 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3731 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3732 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3733 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3734 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3735 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3736 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3737 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3738
5b739670
MB		 3739 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3740 * use this; it only affects behaviour on idle TDM clock
3741 * cycles. */
3742 switch (control->type) {
3743 case WM8994:
3744 case WM8958:
3745 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3746 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3747 break;
3748 default:
3749 break;
3750 }
d1ce6b20 3751
500fa30e
MB		 3752 /* Put MICBIAS into bypass mode by default on newer devices */
3753 switch (control->type) {
3754 case WM8958:
3755 case WM1811:
3756 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3757 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3758 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3759 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3760 break;
3761 default:
3762 break;
3763 }
3764
9e6e96a1
MB		 3765 wm8994_update_class_w(codec);
3766
f0fba2ad 3767 wm8994_handle_pdata(wm8994);
9e6e96a1 3768
f0fba2ad 3769 wm_hubs_add_analogue_controls(codec);
022658be 3770 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 3771 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3772 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3773 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3774
3775 switch (control->type) {
3776 case WM8994:
3777 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3778 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3779 if (wm8994->revision < 4) {
173efa09
DP		 3780 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3781 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3782 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3783 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3784 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3785 ARRAY_SIZE(wm8994_dac_revd_widgets));
3786 } else {
173efa09
DP		 3787 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3788 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3789 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3790 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3791 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3792 ARRAY_SIZE(wm8994_dac_widgets));
3793 }
c4431df0
MB		 3794 break;
3795 case WM8958:
022658be 3796 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 3797 ARRAY_SIZE(wm8958_snd_controls));
3798 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3799 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3800 if (wm8994->revision < 1) {
3801 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3802 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3803 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3804 ARRAY_SIZE(wm8994_adc_revd_widgets));
3805 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3806 ARRAY_SIZE(wm8994_dac_revd_widgets));
3807 } else {
3808 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3809 ARRAY_SIZE(wm8994_lateclk_widgets));
3810 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3811 ARRAY_SIZE(wm8994_adc_widgets));
3812 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3813 ARRAY_SIZE(wm8994_dac_widgets));
3814 }
c4431df0 3815 break;
81204c84
MB		 3816
3817 case WM1811:
022658be 3818 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 3819 ARRAY_SIZE(wm8958_snd_controls));
3820 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3821 ARRAY_SIZE(wm8958_dapm_widgets));
3822 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3823 ARRAY_SIZE(wm8994_lateclk_widgets));
3824 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3825 ARRAY_SIZE(wm8994_adc_widgets));
3826 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3827 ARRAY_SIZE(wm8994_dac_widgets));
3828 break;
c4431df0
MB		 3829 }
3830
3831
f0fba2ad 3832 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3833 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3834
c4431df0
MB		 3835 switch (control->type) {
3836 case WM8994:
3837 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3838 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3839
173efa09 3840 if (wm8994->revision < 4) {
6ed8f148
MB		 3841 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3842 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3843 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3844 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3845 } else {
3846 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3847 ARRAY_SIZE(wm8994_lateclk_intercon));
3848 }
c4431df0
MB		 3849 break;
3850 case WM8958:
780e2806
MB		 3851 if (wm8994->revision < 1) {
3852 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3853 ARRAY_SIZE(wm8994_revd_intercon));
3854 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3855 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3856 } else {
3857 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3858 ARRAY_SIZE(wm8994_lateclk_intercon));
3859 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3860 ARRAY_SIZE(wm8958_intercon));
3861 }
f701a2e5
MB		 3862
3863 wm8958_dsp2_init(codec);
c4431df0 3864 break;
81204c84
MB		 3865 case WM1811:
3866 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3867 ARRAY_SIZE(wm8994_lateclk_intercon));
3868 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3869 ARRAY_SIZE(wm8958_intercon));
3870 break;
c4431df0
MB		 3871 }
3872
9e6e96a1
MB		 3873 return 0;
3874
88766984 3875err_irq:
af6b6fe4
MB		 3876 if (wm8994->jackdet)
3877 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3878 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3879 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3880 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3881 if (wm8994->micdet_irq)
3882 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3883 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3884 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3885 &wm8994->fll_locked[i]);
2a8a856d 3886 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3887 &wm8994->hubs);
2a8a856d
MB		 3888 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3889 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3890 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 3891
9e6e96a1
MB		 3892 return ret;
3893}
3894
f0fba2ad 3895static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3896{
f0fba2ad 3897 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3898 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3899 int i;
9e6e96a1
MB		 3900
3901 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3902
39fb51a1
MB		 3903 pm_runtime_disable(codec->dev);
3904
c7ebf932 3905 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3906 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3907 &wm8994->fll_locked[i]);
3908
2a8a856d 3909 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3910 &wm8994->hubs);
2a8a856d
MB		 3911 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3912 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3913 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3914
af6b6fe4
MB		 3915 if (wm8994->jackdet)
3916 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3917
3a423157
MB		 3918 switch (control->type) {
3919 case WM8994:
9b7c525d
MB		 3920 if (wm8994->micdet_irq)
3921 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3922 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3923 wm8994);
2a8a856d 3924 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3925 wm8994);
2a8a856d 3926 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3927 wm8994);
3928 break;
821edd2f 3929
81204c84 3930 case WM1811:
821edd2f 3931 case WM8958:
9b7c525d
MB		 3932 if (wm8994->micdet_irq)
3933 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3934 break;
3a423157 3935 }
fbbf5920
MB		 3936 if (wm8994->mbc)
3937 release_firmware(wm8994->mbc);
09e10d7f
MB		 3938 if (wm8994->mbc_vss)
3939 release_firmware(wm8994->mbc_vss);
31215871
MB		 3940 if (wm8994->enh_eq)
3941 release_firmware(wm8994->enh_eq);
24fb2b11 3942 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 3943
3944 return 0;
3945}
3946
f0fba2ad
LG		 3947static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3948 .probe = wm8994_codec_probe,
3949 .remove = wm8994_codec_remove,
3950 .suspend = wm8994_suspend,
3951 .resume = wm8994_resume,
f0fba2ad
LG		 3952 .set_bias_level = wm8994_set_bias_level,
3953};
3954
3955static int __devinit wm8994_probe(struct platform_device *pdev)
3956{
2bc16ed8
MB		 3957 struct wm8994_priv *wm8994;
3958
3959 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
3960 GFP_KERNEL);
3961 if (wm8994 == NULL)
3962 return -ENOMEM;
3963 platform_set_drvdata(pdev, wm8994);
3964
3965 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
3966 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
3967
f0fba2ad
LG		 3968 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3969 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3970}
3971
3972static int __devexit wm8994_remove(struct platform_device *pdev)
3973{
3974 snd_soc_unregister_codec(&pdev->dev);
3975 return 0;
3976}
3977
9e6e96a1
MB		 3978static struct platform_driver wm8994_codec_driver = {
3979 .driver = {
3980 .name = "wm8994-codec",
3981 .owner = THIS_MODULE,
3982 },
f0fba2ad
LG		 3983 .probe = wm8994_probe,
3984 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3985};
3986
5bbcc3c0 3987module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 3988
3989MODULE_DESCRIPTION("ASoC WM8994 driver");
3990MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3991MODULE_LICENSE("GPL");
3992MODULE_ALIAS("platform:wm8994-codec");
ubuntu-bionic-kernel mirror