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9e6e96a1 MB |
1 | /* |
2 | * wm8994.c -- WM8994 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/i2c.h> | |
20 | #include <linux/platform_device.h> | |
39fb51a1 | 21 | #include <linux/pm_runtime.h> |
9e6e96a1 | 22 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
9e6e96a1 | 24 | #include <sound/core.h> |
821edd2f | 25 | #include <sound/jack.h> |
9e6e96a1 MB |
26 | #include <sound/pcm.h> |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/soc.h> | |
9e6e96a1 MB |
29 | #include <sound/initval.h> |
30 | #include <sound/tlv.h> | |
2bbb5d66 | 31 | #include <trace/events/asoc.h> |
9e6e96a1 MB |
32 | |
33 | #include <linux/mfd/wm8994/core.h> | |
34 | #include <linux/mfd/wm8994/registers.h> | |
35 | #include <linux/mfd/wm8994/pdata.h> | |
36 | #include <linux/mfd/wm8994/gpio.h> | |
37 | ||
38 | #include "wm8994.h" | |
39 | #include "wm_hubs.h" | |
40 | ||
9e6e96a1 MB |
41 | #define WM8994_NUM_DRC 3 |
42 | #define WM8994_NUM_EQ 3 | |
43 | ||
44 | static int wm8994_drc_base[] = { | |
45 | WM8994_AIF1_DRC1_1, | |
46 | WM8994_AIF1_DRC2_1, | |
47 | WM8994_AIF2_DRC_1, | |
48 | }; | |
49 | ||
50 | static int wm8994_retune_mobile_base[] = { | |
51 | WM8994_AIF1_DAC1_EQ_GAINS_1, | |
52 | WM8994_AIF1_DAC2_EQ_GAINS_1, | |
53 | WM8994_AIF2_EQ_GAINS_1, | |
54 | }; | |
55 | ||
d4754ec9 | 56 | static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg) |
9e6e96a1 | 57 | { |
af9af866 MB |
58 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
59 | struct wm8994 *control = wm8994->control_data; | |
60 | ||
e88ff1e6 MB |
61 | switch (reg) { |
62 | case WM8994_GPIO_1: | |
63 | case WM8994_GPIO_2: | |
64 | case WM8994_GPIO_3: | |
65 | case WM8994_GPIO_4: | |
66 | case WM8994_GPIO_5: | |
67 | case WM8994_GPIO_6: | |
68 | case WM8994_GPIO_7: | |
69 | case WM8994_GPIO_8: | |
70 | case WM8994_GPIO_9: | |
71 | case WM8994_GPIO_10: | |
72 | case WM8994_GPIO_11: | |
73 | case WM8994_INTERRUPT_STATUS_1: | |
74 | case WM8994_INTERRUPT_STATUS_2: | |
75 | case WM8994_INTERRUPT_RAW_STATUS_2: | |
76 | return 1; | |
af9af866 MB |
77 | |
78 | case WM8958_DSP2_PROGRAM: | |
79 | case WM8958_DSP2_CONFIG: | |
80 | case WM8958_DSP2_EXECCONTROL: | |
81 | if (control->type == WM8958) | |
82 | return 1; | |
83 | else | |
84 | return 0; | |
85 | ||
e88ff1e6 MB |
86 | default: |
87 | break; | |
88 | } | |
89 | ||
7b306dae | 90 | if (reg >= WM8994_CACHE_SIZE) |
9e6e96a1 | 91 | return 0; |
7b306dae | 92 | return wm8994_access_masks[reg].readable != 0; |
9e6e96a1 MB |
93 | } |
94 | ||
d4754ec9 | 95 | static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg) |
9e6e96a1 | 96 | { |
ca9aef50 | 97 | if (reg >= WM8994_CACHE_SIZE) |
9e6e96a1 MB |
98 | return 1; |
99 | ||
100 | switch (reg) { | |
101 | case WM8994_SOFTWARE_RESET: | |
102 | case WM8994_CHIP_REVISION: | |
103 | case WM8994_DC_SERVO_1: | |
104 | case WM8994_DC_SERVO_READBACK: | |
105 | case WM8994_RATE_STATUS: | |
106 | case WM8994_LDO_1: | |
107 | case WM8994_LDO_2: | |
d6addcc9 | 108 | case WM8958_DSP2_EXECCONTROL: |
821edd2f | 109 | case WM8958_MIC_DETECT_3: |
79ef0abc | 110 | case WM8994_DC_SERVO_4E: |
9e6e96a1 MB |
111 | return 1; |
112 | default: | |
113 | return 0; | |
114 | } | |
115 | } | |
116 | ||
117 | static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, | |
118 | unsigned int value) | |
119 | { | |
ca9aef50 | 120 | int ret; |
9e6e96a1 MB |
121 | |
122 | BUG_ON(reg > WM8994_MAX_REGISTER); | |
123 | ||
d4754ec9 | 124 | if (!wm8994_volatile(codec, reg)) { |
ca9aef50 MB |
125 | ret = snd_soc_cache_write(codec, reg, value); |
126 | if (ret != 0) | |
127 | dev_err(codec->dev, "Cache write to %x failed: %d\n", | |
128 | reg, ret); | |
129 | } | |
9e6e96a1 MB |
130 | |
131 | return wm8994_reg_write(codec->control_data, reg, value); | |
132 | } | |
133 | ||
134 | static unsigned int wm8994_read(struct snd_soc_codec *codec, | |
135 | unsigned int reg) | |
136 | { | |
ca9aef50 MB |
137 | unsigned int val; |
138 | int ret; | |
9e6e96a1 MB |
139 | |
140 | BUG_ON(reg > WM8994_MAX_REGISTER); | |
141 | ||
d4754ec9 | 142 | if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) && |
ca9aef50 MB |
143 | reg < codec->driver->reg_cache_size) { |
144 | ret = snd_soc_cache_read(codec, reg, &val); | |
145 | if (ret >= 0) | |
146 | return val; | |
147 | else | |
148 | dev_err(codec->dev, "Cache read from %x failed: %d\n", | |
149 | reg, ret); | |
150 | } | |
151 | ||
152 | return wm8994_reg_read(codec->control_data, reg); | |
9e6e96a1 MB |
153 | } |
154 | ||
155 | static int configure_aif_clock(struct snd_soc_codec *codec, int aif) | |
156 | { | |
b2c812e2 | 157 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
158 | int rate; |
159 | int reg1 = 0; | |
160 | int offset; | |
161 | ||
162 | if (aif) | |
163 | offset = 4; | |
164 | else | |
165 | offset = 0; | |
166 | ||
167 | switch (wm8994->sysclk[aif]) { | |
168 | case WM8994_SYSCLK_MCLK1: | |
169 | rate = wm8994->mclk[0]; | |
170 | break; | |
171 | ||
172 | case WM8994_SYSCLK_MCLK2: | |
173 | reg1 |= 0x8; | |
174 | rate = wm8994->mclk[1]; | |
175 | break; | |
176 | ||
177 | case WM8994_SYSCLK_FLL1: | |
178 | reg1 |= 0x10; | |
179 | rate = wm8994->fll[0].out; | |
180 | break; | |
181 | ||
182 | case WM8994_SYSCLK_FLL2: | |
183 | reg1 |= 0x18; | |
184 | rate = wm8994->fll[1].out; | |
185 | break; | |
186 | ||
187 | default: | |
188 | return -EINVAL; | |
189 | } | |
190 | ||
191 | if (rate >= 13500000) { | |
192 | rate /= 2; | |
193 | reg1 |= WM8994_AIF1CLK_DIV; | |
194 | ||
195 | dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", | |
196 | aif + 1, rate); | |
197 | } | |
5e5e2bef | 198 | |
9e6e96a1 MB |
199 | wm8994->aifclk[aif] = rate; |
200 | ||
201 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, | |
202 | WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, | |
203 | reg1); | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | static int configure_clock(struct snd_soc_codec *codec) | |
209 | { | |
b2c812e2 | 210 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
211 | int old, new; |
212 | ||
213 | /* Bring up the AIF clocks first */ | |
214 | configure_aif_clock(codec, 0); | |
215 | configure_aif_clock(codec, 1); | |
216 | ||
217 | /* Then switch CLK_SYS over to the higher of them; a change | |
218 | * can only happen as a result of a clocking change which can | |
219 | * only be made outside of DAPM so we can safely redo the | |
220 | * clocking. | |
221 | */ | |
222 | ||
223 | /* If they're equal it doesn't matter which is used */ | |
224 | if (wm8994->aifclk[0] == wm8994->aifclk[1]) | |
225 | return 0; | |
226 | ||
227 | if (wm8994->aifclk[0] < wm8994->aifclk[1]) | |
228 | new = WM8994_SYSCLK_SRC; | |
229 | else | |
230 | new = 0; | |
231 | ||
232 | old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC; | |
233 | ||
234 | /* If there's no change then we're done. */ | |
235 | if (old == new) | |
236 | return 0; | |
237 | ||
238 | snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); | |
239 | ||
ce6120cc | 240 | snd_soc_dapm_sync(&codec->dapm); |
9e6e96a1 MB |
241 | |
242 | return 0; | |
243 | } | |
244 | ||
245 | static int check_clk_sys(struct snd_soc_dapm_widget *source, | |
246 | struct snd_soc_dapm_widget *sink) | |
247 | { | |
248 | int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); | |
249 | const char *clk; | |
250 | ||
251 | /* Check what we're currently using for CLK_SYS */ | |
252 | if (reg & WM8994_SYSCLK_SRC) | |
253 | clk = "AIF2CLK"; | |
254 | else | |
255 | clk = "AIF1CLK"; | |
256 | ||
257 | return strcmp(source->name, clk) == 0; | |
258 | } | |
259 | ||
260 | static const char *sidetone_hpf_text[] = { | |
261 | "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" | |
262 | }; | |
263 | ||
264 | static const struct soc_enum sidetone_hpf = | |
265 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); | |
266 | ||
146fd574 UK |
267 | static const char *adc_hpf_text[] = { |
268 | "HiFi", "Voice 1", "Voice 2", "Voice 3" | |
269 | }; | |
270 | ||
271 | static const struct soc_enum aif1adc1_hpf = | |
272 | SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); | |
273 | ||
274 | static const struct soc_enum aif1adc2_hpf = | |
275 | SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); | |
276 | ||
277 | static const struct soc_enum aif2adc_hpf = | |
278 | SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); | |
279 | ||
9e6e96a1 MB |
280 | static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); |
281 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
282 | static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); | |
283 | static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); | |
284 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
285 | ||
286 | #define WM8994_DRC_SWITCH(xname, reg, shift) \ | |
287 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
288 | .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ | |
289 | .put = wm8994_put_drc_sw, \ | |
290 | .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } | |
291 | ||
292 | static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, | |
293 | struct snd_ctl_elem_value *ucontrol) | |
294 | { | |
295 | struct soc_mixer_control *mc = | |
296 | (struct soc_mixer_control *)kcontrol->private_value; | |
297 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
298 | int mask, ret; | |
299 | ||
300 | /* Can't enable both ADC and DAC paths simultaneously */ | |
301 | if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) | |
302 | mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | | |
303 | WM8994_AIF1ADC1R_DRC_ENA_MASK; | |
304 | else | |
305 | mask = WM8994_AIF1DAC1_DRC_ENA_MASK; | |
306 | ||
307 | ret = snd_soc_read(codec, mc->reg); | |
308 | if (ret < 0) | |
309 | return ret; | |
310 | if (ret & mask) | |
311 | return -EINVAL; | |
312 | ||
313 | return snd_soc_put_volsw(kcontrol, ucontrol); | |
314 | } | |
315 | ||
9e6e96a1 MB |
316 | static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) |
317 | { | |
b2c812e2 | 318 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
319 | struct wm8994_pdata *pdata = wm8994->pdata; |
320 | int base = wm8994_drc_base[drc]; | |
321 | int cfg = wm8994->drc_cfg[drc]; | |
322 | int save, i; | |
323 | ||
324 | /* Save any enables; the configuration should clear them. */ | |
325 | save = snd_soc_read(codec, base); | |
326 | save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | | |
327 | WM8994_AIF1ADC1R_DRC_ENA; | |
328 | ||
329 | for (i = 0; i < WM8994_DRC_REGS; i++) | |
330 | snd_soc_update_bits(codec, base + i, 0xffff, | |
331 | pdata->drc_cfgs[cfg].regs[i]); | |
332 | ||
333 | snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | | |
334 | WM8994_AIF1ADC1L_DRC_ENA | | |
335 | WM8994_AIF1ADC1R_DRC_ENA, save); | |
336 | } | |
337 | ||
338 | /* Icky as hell but saves code duplication */ | |
339 | static int wm8994_get_drc(const char *name) | |
340 | { | |
341 | if (strcmp(name, "AIF1DRC1 Mode") == 0) | |
342 | return 0; | |
343 | if (strcmp(name, "AIF1DRC2 Mode") == 0) | |
344 | return 1; | |
345 | if (strcmp(name, "AIF2DRC Mode") == 0) | |
346 | return 2; | |
347 | return -EINVAL; | |
348 | } | |
349 | ||
350 | static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, | |
351 | struct snd_ctl_elem_value *ucontrol) | |
352 | { | |
353 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 354 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
355 | struct wm8994_pdata *pdata = wm8994->pdata; |
356 | int drc = wm8994_get_drc(kcontrol->id.name); | |
357 | int value = ucontrol->value.integer.value[0]; | |
358 | ||
359 | if (drc < 0) | |
360 | return drc; | |
361 | ||
362 | if (value >= pdata->num_drc_cfgs) | |
363 | return -EINVAL; | |
364 | ||
365 | wm8994->drc_cfg[drc] = value; | |
366 | ||
367 | wm8994_set_drc(codec, drc); | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, | |
373 | struct snd_ctl_elem_value *ucontrol) | |
374 | { | |
375 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 376 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
377 | int drc = wm8994_get_drc(kcontrol->id.name); |
378 | ||
379 | ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
384 | static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) | |
385 | { | |
b2c812e2 | 386 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
387 | struct wm8994_pdata *pdata = wm8994->pdata; |
388 | int base = wm8994_retune_mobile_base[block]; | |
389 | int iface, best, best_val, save, i, cfg; | |
390 | ||
391 | if (!pdata || !wm8994->num_retune_mobile_texts) | |
392 | return; | |
393 | ||
394 | switch (block) { | |
395 | case 0: | |
396 | case 1: | |
397 | iface = 0; | |
398 | break; | |
399 | case 2: | |
400 | iface = 1; | |
401 | break; | |
402 | default: | |
403 | return; | |
404 | } | |
405 | ||
406 | /* Find the version of the currently selected configuration | |
407 | * with the nearest sample rate. */ | |
408 | cfg = wm8994->retune_mobile_cfg[block]; | |
409 | best = 0; | |
410 | best_val = INT_MAX; | |
411 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
412 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
413 | wm8994->retune_mobile_texts[cfg]) == 0 && | |
414 | abs(pdata->retune_mobile_cfgs[i].rate | |
415 | - wm8994->dac_rates[iface]) < best_val) { | |
416 | best = i; | |
417 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
418 | - wm8994->dac_rates[iface]); | |
419 | } | |
420 | } | |
421 | ||
422 | dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", | |
423 | block, | |
424 | pdata->retune_mobile_cfgs[best].name, | |
425 | pdata->retune_mobile_cfgs[best].rate, | |
426 | wm8994->dac_rates[iface]); | |
427 | ||
428 | /* The EQ will be disabled while reconfiguring it, remember the | |
429 | * current configuration. | |
430 | */ | |
431 | save = snd_soc_read(codec, base); | |
432 | save &= WM8994_AIF1DAC1_EQ_ENA; | |
433 | ||
434 | for (i = 0; i < WM8994_EQ_REGS; i++) | |
435 | snd_soc_update_bits(codec, base + i, 0xffff, | |
436 | pdata->retune_mobile_cfgs[best].regs[i]); | |
437 | ||
438 | snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); | |
439 | } | |
440 | ||
441 | /* Icky as hell but saves code duplication */ | |
442 | static int wm8994_get_retune_mobile_block(const char *name) | |
443 | { | |
444 | if (strcmp(name, "AIF1.1 EQ Mode") == 0) | |
445 | return 0; | |
446 | if (strcmp(name, "AIF1.2 EQ Mode") == 0) | |
447 | return 1; | |
448 | if (strcmp(name, "AIF2 EQ Mode") == 0) | |
449 | return 2; | |
450 | return -EINVAL; | |
451 | } | |
452 | ||
453 | static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
454 | struct snd_ctl_elem_value *ucontrol) | |
455 | { | |
456 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 457 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
458 | struct wm8994_pdata *pdata = wm8994->pdata; |
459 | int block = wm8994_get_retune_mobile_block(kcontrol->id.name); | |
460 | int value = ucontrol->value.integer.value[0]; | |
461 | ||
462 | if (block < 0) | |
463 | return block; | |
464 | ||
465 | if (value >= pdata->num_retune_mobile_cfgs) | |
466 | return -EINVAL; | |
467 | ||
468 | wm8994->retune_mobile_cfg[block] = value; | |
469 | ||
470 | wm8994_set_retune_mobile(codec, block); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
476 | struct snd_ctl_elem_value *ucontrol) | |
477 | { | |
478 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
4a8d929d | 479 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
480 | int block = wm8994_get_retune_mobile_block(kcontrol->id.name); |
481 | ||
482 | ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
96b101ef | 487 | static const char *aif_chan_src_text[] = { |
f554885f MB |
488 | "Left", "Right" |
489 | }; | |
490 | ||
96b101ef MB |
491 | static const struct soc_enum aif1adcl_src = |
492 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); | |
493 | ||
494 | static const struct soc_enum aif1adcr_src = | |
495 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); | |
496 | ||
497 | static const struct soc_enum aif2adcl_src = | |
498 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); | |
499 | ||
500 | static const struct soc_enum aif2adcr_src = | |
501 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); | |
502 | ||
f554885f | 503 | static const struct soc_enum aif1dacl_src = |
96b101ef | 504 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); |
f554885f MB |
505 | |
506 | static const struct soc_enum aif1dacr_src = | |
96b101ef | 507 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); |
f554885f MB |
508 | |
509 | static const struct soc_enum aif2dacl_src = | |
96b101ef | 510 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); |
f554885f MB |
511 | |
512 | static const struct soc_enum aif2dacr_src = | |
96b101ef | 513 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); |
f554885f | 514 | |
154b26aa MB |
515 | static const char *osr_text[] = { |
516 | "Low Power", "High Performance", | |
517 | }; | |
518 | ||
519 | static const struct soc_enum dac_osr = | |
520 | SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); | |
521 | ||
522 | static const struct soc_enum adc_osr = | |
523 | SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); | |
524 | ||
9e6e96a1 MB |
525 | static const struct snd_kcontrol_new wm8994_snd_controls[] = { |
526 | SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, | |
527 | WM8994_AIF1_ADC1_RIGHT_VOLUME, | |
528 | 1, 119, 0, digital_tlv), | |
529 | SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, | |
530 | WM8994_AIF1_ADC2_RIGHT_VOLUME, | |
531 | 1, 119, 0, digital_tlv), | |
532 | SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, | |
533 | WM8994_AIF2_ADC_RIGHT_VOLUME, | |
534 | 1, 119, 0, digital_tlv), | |
535 | ||
96b101ef MB |
536 | SOC_ENUM("AIF1ADCL Source", aif1adcl_src), |
537 | SOC_ENUM("AIF1ADCR Source", aif1adcr_src), | |
49db7e7b MB |
538 | SOC_ENUM("AIF2ADCL Source", aif2adcl_src), |
539 | SOC_ENUM("AIF2ADCR Source", aif2adcr_src), | |
96b101ef | 540 | |
f554885f MB |
541 | SOC_ENUM("AIF1DACL Source", aif1dacl_src), |
542 | SOC_ENUM("AIF1DACR Source", aif1dacr_src), | |
49db7e7b MB |
543 | SOC_ENUM("AIF2DACL Source", aif2dacl_src), |
544 | SOC_ENUM("AIF2DACR Source", aif2dacr_src), | |
f554885f | 545 | |
9e6e96a1 MB |
546 | SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, |
547 | WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
548 | SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, | |
549 | WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
550 | SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, | |
551 | WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
552 | ||
553 | SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), | |
554 | SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), | |
555 | ||
556 | SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), | |
557 | SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), | |
558 | SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), | |
559 | ||
560 | WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), | |
561 | WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), | |
562 | WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), | |
563 | ||
564 | WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), | |
565 | WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), | |
566 | WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), | |
567 | ||
568 | WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), | |
569 | WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), | |
570 | WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), | |
571 | ||
572 | SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, | |
573 | 5, 12, 0, st_tlv), | |
574 | SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, | |
575 | 0, 12, 0, st_tlv), | |
576 | SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, | |
577 | 5, 12, 0, st_tlv), | |
578 | SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, | |
579 | 0, 12, 0, st_tlv), | |
580 | SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), | |
581 | SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), | |
582 | ||
146fd574 UK |
583 | SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), |
584 | SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), | |
585 | ||
586 | SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), | |
587 | SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), | |
588 | ||
589 | SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), | |
590 | SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), | |
591 | ||
154b26aa MB |
592 | SOC_ENUM("ADC OSR", adc_osr), |
593 | SOC_ENUM("DAC OSR", dac_osr), | |
594 | ||
9e6e96a1 MB |
595 | SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, |
596 | WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
597 | SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, | |
598 | WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), | |
599 | ||
600 | SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, | |
601 | WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
602 | SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, | |
603 | WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), | |
604 | ||
605 | SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, | |
606 | 6, 1, 1, wm_hubs_spkmix_tlv), | |
607 | SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, | |
608 | 2, 1, 1, wm_hubs_spkmix_tlv), | |
609 | ||
610 | SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, | |
611 | 6, 1, 1, wm_hubs_spkmix_tlv), | |
612 | SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, | |
613 | 2, 1, 1, wm_hubs_spkmix_tlv), | |
614 | ||
615 | SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, | |
616 | 10, 15, 0, wm8994_3d_tlv), | |
458350b3 | 617 | SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, |
9e6e96a1 MB |
618 | 8, 1, 0), |
619 | SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, | |
620 | 10, 15, 0, wm8994_3d_tlv), | |
621 | SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, | |
622 | 8, 1, 0), | |
458350b3 | 623 | SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, |
9e6e96a1 | 624 | 10, 15, 0, wm8994_3d_tlv), |
458350b3 | 625 | SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, |
9e6e96a1 MB |
626 | 8, 1, 0), |
627 | }; | |
628 | ||
629 | static const struct snd_kcontrol_new wm8994_eq_controls[] = { | |
630 | SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, | |
631 | eq_tlv), | |
632 | SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, | |
633 | eq_tlv), | |
634 | SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, | |
635 | eq_tlv), | |
636 | SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, | |
637 | eq_tlv), | |
638 | SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, | |
639 | eq_tlv), | |
640 | ||
641 | SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, | |
642 | eq_tlv), | |
643 | SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, | |
644 | eq_tlv), | |
645 | SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, | |
646 | eq_tlv), | |
647 | SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, | |
648 | eq_tlv), | |
649 | SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, | |
650 | eq_tlv), | |
651 | ||
652 | SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, | |
653 | eq_tlv), | |
654 | SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, | |
655 | eq_tlv), | |
656 | SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, | |
657 | eq_tlv), | |
658 | SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, | |
659 | eq_tlv), | |
660 | SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, | |
661 | eq_tlv), | |
662 | }; | |
663 | ||
c4431df0 MB |
664 | static const struct snd_kcontrol_new wm8958_snd_controls[] = { |
665 | SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), | |
666 | }; | |
667 | ||
9e6e96a1 MB |
668 | static int clk_sys_event(struct snd_soc_dapm_widget *w, |
669 | struct snd_kcontrol *kcontrol, int event) | |
670 | { | |
671 | struct snd_soc_codec *codec = w->codec; | |
672 | ||
673 | switch (event) { | |
674 | case SND_SOC_DAPM_PRE_PMU: | |
675 | return configure_clock(codec); | |
676 | ||
677 | case SND_SOC_DAPM_POST_PMD: | |
678 | configure_clock(codec); | |
679 | break; | |
680 | } | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
4b7ed83a MB |
685 | static void vmid_reference(struct snd_soc_codec *codec) |
686 | { | |
687 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
688 | ||
689 | wm8994->vmid_refcount++; | |
690 | ||
691 | dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n", | |
692 | wm8994->vmid_refcount); | |
693 | ||
694 | if (wm8994->vmid_refcount == 1) { | |
695 | /* Startup bias, VMID ramp & buffer */ | |
696 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
697 | WM8994_STARTUP_BIAS_ENA | | |
698 | WM8994_VMID_BUF_ENA | | |
699 | WM8994_VMID_RAMP_MASK, | |
700 | WM8994_STARTUP_BIAS_ENA | | |
701 | WM8994_VMID_BUF_ENA | | |
702 | (0x11 << WM8994_VMID_RAMP_SHIFT)); | |
703 | ||
704 | /* Main bias enable, VMID=2x40k */ | |
705 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
706 | WM8994_BIAS_ENA | | |
707 | WM8994_VMID_SEL_MASK, | |
708 | WM8994_BIAS_ENA | 0x2); | |
709 | ||
710 | msleep(20); | |
711 | } | |
712 | } | |
713 | ||
714 | static void vmid_dereference(struct snd_soc_codec *codec) | |
715 | { | |
716 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
717 | ||
718 | wm8994->vmid_refcount--; | |
719 | ||
720 | dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n", | |
721 | wm8994->vmid_refcount); | |
722 | ||
723 | if (wm8994->vmid_refcount == 0) { | |
724 | /* Switch over to startup biases */ | |
725 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
726 | WM8994_BIAS_SRC | | |
727 | WM8994_STARTUP_BIAS_ENA | | |
728 | WM8994_VMID_BUF_ENA | | |
729 | WM8994_VMID_RAMP_MASK, | |
730 | WM8994_BIAS_SRC | | |
731 | WM8994_STARTUP_BIAS_ENA | | |
732 | WM8994_VMID_BUF_ENA | | |
733 | (1 << WM8994_VMID_RAMP_SHIFT)); | |
734 | ||
735 | /* Disable main biases */ | |
736 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
737 | WM8994_BIAS_ENA | | |
738 | WM8994_VMID_SEL_MASK, 0); | |
739 | ||
740 | /* Discharge line */ | |
741 | snd_soc_update_bits(codec, WM8994_ANTIPOP_1, | |
742 | WM8994_LINEOUT1_DISCH | | |
743 | WM8994_LINEOUT2_DISCH, | |
744 | WM8994_LINEOUT1_DISCH | | |
745 | WM8994_LINEOUT2_DISCH); | |
746 | ||
747 | msleep(5); | |
748 | ||
749 | /* Switch off startup biases */ | |
750 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
751 | WM8994_BIAS_SRC | | |
752 | WM8994_STARTUP_BIAS_ENA | | |
753 | WM8994_VMID_BUF_ENA | | |
754 | WM8994_VMID_RAMP_MASK, 0); | |
755 | } | |
756 | } | |
757 | ||
758 | static int vmid_event(struct snd_soc_dapm_widget *w, | |
759 | struct snd_kcontrol *kcontrol, int event) | |
760 | { | |
761 | struct snd_soc_codec *codec = w->codec; | |
762 | ||
763 | switch (event) { | |
764 | case SND_SOC_DAPM_PRE_PMU: | |
765 | vmid_reference(codec); | |
766 | break; | |
767 | ||
768 | case SND_SOC_DAPM_POST_PMD: | |
769 | vmid_dereference(codec); | |
770 | break; | |
771 | } | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
9e6e96a1 MB |
776 | static void wm8994_update_class_w(struct snd_soc_codec *codec) |
777 | { | |
fec6dd83 | 778 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
779 | int enable = 1; |
780 | int source = 0; /* GCC flow analysis can't track enable */ | |
781 | int reg, reg_r; | |
782 | ||
783 | /* Only support direct DAC->headphone paths */ | |
784 | reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1); | |
785 | if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) { | |
ee839a21 | 786 | dev_vdbg(codec->dev, "HPL connected to output mixer\n"); |
9e6e96a1 MB |
787 | enable = 0; |
788 | } | |
789 | ||
790 | reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2); | |
791 | if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) { | |
ee839a21 | 792 | dev_vdbg(codec->dev, "HPR connected to output mixer\n"); |
9e6e96a1 MB |
793 | enable = 0; |
794 | } | |
795 | ||
796 | /* We also need the same setting for L/R and only one path */ | |
797 | reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); | |
798 | switch (reg) { | |
799 | case WM8994_AIF2DACL_TO_DAC1L: | |
ee839a21 | 800 | dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); |
9e6e96a1 MB |
801 | source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
802 | break; | |
803 | case WM8994_AIF1DAC2L_TO_DAC1L: | |
ee839a21 | 804 | dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); |
9e6e96a1 MB |
805 | source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
806 | break; | |
807 | case WM8994_AIF1DAC1L_TO_DAC1L: | |
ee839a21 | 808 | dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); |
9e6e96a1 MB |
809 | source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
810 | break; | |
811 | default: | |
ee839a21 | 812 | dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); |
9e6e96a1 MB |
813 | enable = 0; |
814 | break; | |
815 | } | |
816 | ||
817 | reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); | |
818 | if (reg_r != reg) { | |
ee839a21 | 819 | dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); |
9e6e96a1 MB |
820 | enable = 0; |
821 | } | |
822 | ||
823 | if (enable) { | |
824 | dev_dbg(codec->dev, "Class W enabled\n"); | |
825 | snd_soc_update_bits(codec, WM8994_CLASS_W_1, | |
826 | WM8994_CP_DYN_PWR | | |
827 | WM8994_CP_DYN_SRC_SEL_MASK, | |
828 | source | WM8994_CP_DYN_PWR); | |
fec6dd83 | 829 | wm8994->hubs.class_w = true; |
9e6e96a1 MB |
830 | |
831 | } else { | |
832 | dev_dbg(codec->dev, "Class W disabled\n"); | |
833 | snd_soc_update_bits(codec, WM8994_CLASS_W_1, | |
834 | WM8994_CP_DYN_PWR, 0); | |
fec6dd83 | 835 | wm8994->hubs.class_w = false; |
9e6e96a1 MB |
836 | } |
837 | } | |
838 | ||
173efa09 DP |
839 | static int late_enable_ev(struct snd_soc_dapm_widget *w, |
840 | struct snd_kcontrol *kcontrol, int event) | |
841 | { | |
842 | struct snd_soc_codec *codec = w->codec; | |
843 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
844 | ||
845 | switch (event) { | |
846 | case SND_SOC_DAPM_PRE_PMU: | |
a3cff81a | 847 | if (wm8994->aif1clk_enable) { |
173efa09 DP |
848 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, |
849 | WM8994_AIF1CLK_ENA_MASK, | |
850 | WM8994_AIF1CLK_ENA); | |
a3cff81a DP |
851 | wm8994->aif1clk_enable = 0; |
852 | } | |
853 | if (wm8994->aif2clk_enable) { | |
173efa09 DP |
854 | snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, |
855 | WM8994_AIF2CLK_ENA_MASK, | |
856 | WM8994_AIF2CLK_ENA); | |
a3cff81a DP |
857 | wm8994->aif2clk_enable = 0; |
858 | } | |
173efa09 DP |
859 | break; |
860 | } | |
861 | ||
c6b7b570 MB |
862 | /* We may also have postponed startup of DSP, handle that. */ |
863 | wm8958_aif_ev(w, kcontrol, event); | |
864 | ||
173efa09 DP |
865 | return 0; |
866 | } | |
867 | ||
868 | static int late_disable_ev(struct snd_soc_dapm_widget *w, | |
869 | struct snd_kcontrol *kcontrol, int event) | |
870 | { | |
871 | struct snd_soc_codec *codec = w->codec; | |
872 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
873 | ||
874 | switch (event) { | |
875 | case SND_SOC_DAPM_POST_PMD: | |
a3cff81a | 876 | if (wm8994->aif1clk_disable) { |
173efa09 DP |
877 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, |
878 | WM8994_AIF1CLK_ENA_MASK, 0); | |
a3cff81a | 879 | wm8994->aif1clk_disable = 0; |
173efa09 | 880 | } |
a3cff81a | 881 | if (wm8994->aif2clk_disable) { |
173efa09 DP |
882 | snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, |
883 | WM8994_AIF2CLK_ENA_MASK, 0); | |
a3cff81a | 884 | wm8994->aif2clk_disable = 0; |
173efa09 DP |
885 | } |
886 | break; | |
887 | } | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | static int aif1clk_ev(struct snd_soc_dapm_widget *w, | |
893 | struct snd_kcontrol *kcontrol, int event) | |
894 | { | |
895 | struct snd_soc_codec *codec = w->codec; | |
896 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
897 | ||
898 | switch (event) { | |
899 | case SND_SOC_DAPM_PRE_PMU: | |
900 | wm8994->aif1clk_enable = 1; | |
901 | break; | |
a3cff81a DP |
902 | case SND_SOC_DAPM_POST_PMD: |
903 | wm8994->aif1clk_disable = 1; | |
904 | break; | |
173efa09 DP |
905 | } |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
910 | static int aif2clk_ev(struct snd_soc_dapm_widget *w, | |
911 | struct snd_kcontrol *kcontrol, int event) | |
912 | { | |
913 | struct snd_soc_codec *codec = w->codec; | |
914 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
915 | ||
916 | switch (event) { | |
917 | case SND_SOC_DAPM_PRE_PMU: | |
918 | wm8994->aif2clk_enable = 1; | |
919 | break; | |
a3cff81a DP |
920 | case SND_SOC_DAPM_POST_PMD: |
921 | wm8994->aif2clk_disable = 1; | |
922 | break; | |
173efa09 DP |
923 | } |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
04d28681 DP |
928 | static int adc_mux_ev(struct snd_soc_dapm_widget *w, |
929 | struct snd_kcontrol *kcontrol, int event) | |
930 | { | |
931 | late_enable_ev(w, kcontrol, event); | |
932 | return 0; | |
933 | } | |
934 | ||
b462c6e6 DP |
935 | static int micbias_ev(struct snd_soc_dapm_widget *w, |
936 | struct snd_kcontrol *kcontrol, int event) | |
937 | { | |
938 | late_enable_ev(w, kcontrol, event); | |
939 | return 0; | |
940 | } | |
941 | ||
c52fd021 DP |
942 | static int dac_ev(struct snd_soc_dapm_widget *w, |
943 | struct snd_kcontrol *kcontrol, int event) | |
944 | { | |
945 | struct snd_soc_codec *codec = w->codec; | |
946 | unsigned int mask = 1 << w->shift; | |
947 | ||
948 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, | |
949 | mask, mask); | |
950 | return 0; | |
951 | } | |
952 | ||
9e6e96a1 MB |
953 | static const char *hp_mux_text[] = { |
954 | "Mixer", | |
955 | "DAC", | |
956 | }; | |
957 | ||
958 | #define WM8994_HP_ENUM(xname, xenum) \ | |
959 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
960 | .info = snd_soc_info_enum_double, \ | |
961 | .get = snd_soc_dapm_get_enum_double, \ | |
962 | .put = wm8994_put_hp_enum, \ | |
963 | .private_value = (unsigned long)&xenum } | |
964 | ||
965 | static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol, | |
966 | struct snd_ctl_elem_value *ucontrol) | |
967 | { | |
9d03545d JN |
968 | struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); |
969 | struct snd_soc_dapm_widget *w = wlist->widgets[0]; | |
9e6e96a1 MB |
970 | struct snd_soc_codec *codec = w->codec; |
971 | int ret; | |
972 | ||
973 | ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); | |
974 | ||
975 | wm8994_update_class_w(codec); | |
976 | ||
977 | return ret; | |
978 | } | |
979 | ||
980 | static const struct soc_enum hpl_enum = | |
981 | SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text); | |
982 | ||
983 | static const struct snd_kcontrol_new hpl_mux = | |
984 | WM8994_HP_ENUM("Left Headphone Mux", hpl_enum); | |
985 | ||
986 | static const struct soc_enum hpr_enum = | |
987 | SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text); | |
988 | ||
989 | static const struct snd_kcontrol_new hpr_mux = | |
990 | WM8994_HP_ENUM("Right Headphone Mux", hpr_enum); | |
991 | ||
992 | static const char *adc_mux_text[] = { | |
993 | "ADC", | |
994 | "DMIC", | |
995 | }; | |
996 | ||
997 | static const struct soc_enum adc_enum = | |
998 | SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); | |
999 | ||
1000 | static const struct snd_kcontrol_new adcl_mux = | |
1001 | SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); | |
1002 | ||
1003 | static const struct snd_kcontrol_new adcr_mux = | |
1004 | SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); | |
1005 | ||
1006 | static const struct snd_kcontrol_new left_speaker_mixer[] = { | |
1007 | SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), | |
1008 | SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), | |
1009 | SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), | |
1010 | SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), | |
1011 | SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), | |
1012 | }; | |
1013 | ||
1014 | static const struct snd_kcontrol_new right_speaker_mixer[] = { | |
1015 | SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), | |
1016 | SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), | |
1017 | SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), | |
1018 | SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), | |
1019 | SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), | |
1020 | }; | |
1021 | ||
1022 | /* Debugging; dump chip status after DAPM transitions */ | |
1023 | static int post_ev(struct snd_soc_dapm_widget *w, | |
1024 | struct snd_kcontrol *kcontrol, int event) | |
1025 | { | |
1026 | struct snd_soc_codec *codec = w->codec; | |
1027 | dev_dbg(codec->dev, "SRC status: %x\n", | |
1028 | snd_soc_read(codec, | |
1029 | WM8994_RATE_STATUS)); | |
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | static const struct snd_kcontrol_new aif1adc1l_mix[] = { | |
1034 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
1035 | 1, 1, 0), | |
1036 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
1037 | 0, 1, 0), | |
1038 | }; | |
1039 | ||
1040 | static const struct snd_kcontrol_new aif1adc1r_mix[] = { | |
1041 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
1042 | 1, 1, 0), | |
1043 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
1044 | 0, 1, 0), | |
1045 | }; | |
1046 | ||
a3257ba8 MB |
1047 | static const struct snd_kcontrol_new aif1adc2l_mix[] = { |
1048 | SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
1049 | 1, 1, 0), | |
1050 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
1051 | 0, 1, 0), | |
1052 | }; | |
1053 | ||
1054 | static const struct snd_kcontrol_new aif1adc2r_mix[] = { | |
1055 | SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
1056 | 1, 1, 0), | |
1057 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
1058 | 0, 1, 0), | |
1059 | }; | |
1060 | ||
9e6e96a1 MB |
1061 | static const struct snd_kcontrol_new aif2dac2l_mix[] = { |
1062 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1063 | 5, 1, 0), | |
1064 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1065 | 4, 1, 0), | |
1066 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1067 | 2, 1, 0), | |
1068 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1069 | 1, 1, 0), | |
1070 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1071 | 0, 1, 0), | |
1072 | }; | |
1073 | ||
1074 | static const struct snd_kcontrol_new aif2dac2r_mix[] = { | |
1075 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1076 | 5, 1, 0), | |
1077 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1078 | 4, 1, 0), | |
1079 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1080 | 2, 1, 0), | |
1081 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1082 | 1, 1, 0), | |
1083 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1084 | 0, 1, 0), | |
1085 | }; | |
1086 | ||
1087 | #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ | |
1088 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1089 | .info = snd_soc_info_volsw, \ | |
1090 | .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ | |
1091 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } | |
1092 | ||
1093 | static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, | |
1094 | struct snd_ctl_elem_value *ucontrol) | |
1095 | { | |
9d03545d JN |
1096 | struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); |
1097 | struct snd_soc_dapm_widget *w = wlist->widgets[0]; | |
9e6e96a1 MB |
1098 | struct snd_soc_codec *codec = w->codec; |
1099 | int ret; | |
1100 | ||
1101 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); | |
1102 | ||
1103 | wm8994_update_class_w(codec); | |
1104 | ||
1105 | return ret; | |
1106 | } | |
1107 | ||
1108 | static const struct snd_kcontrol_new dac1l_mix[] = { | |
1109 | WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1110 | 5, 1, 0), | |
1111 | WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1112 | 4, 1, 0), | |
1113 | WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1114 | 2, 1, 0), | |
1115 | WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1116 | 1, 1, 0), | |
1117 | WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1118 | 0, 1, 0), | |
1119 | }; | |
1120 | ||
1121 | static const struct snd_kcontrol_new dac1r_mix[] = { | |
1122 | WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1123 | 5, 1, 0), | |
1124 | WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1125 | 4, 1, 0), | |
1126 | WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1127 | 2, 1, 0), | |
1128 | WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1129 | 1, 1, 0), | |
1130 | WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1131 | 0, 1, 0), | |
1132 | }; | |
1133 | ||
1134 | static const char *sidetone_text[] = { | |
1135 | "ADC/DMIC1", "DMIC2", | |
1136 | }; | |
1137 | ||
1138 | static const struct soc_enum sidetone1_enum = | |
1139 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); | |
1140 | ||
1141 | static const struct snd_kcontrol_new sidetone1_mux = | |
1142 | SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); | |
1143 | ||
1144 | static const struct soc_enum sidetone2_enum = | |
1145 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); | |
1146 | ||
1147 | static const struct snd_kcontrol_new sidetone2_mux = | |
1148 | SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); | |
1149 | ||
1150 | static const char *aif1dac_text[] = { | |
1151 | "AIF1DACDAT", "AIF3DACDAT", | |
1152 | }; | |
1153 | ||
1154 | static const struct soc_enum aif1dac_enum = | |
1155 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); | |
1156 | ||
1157 | static const struct snd_kcontrol_new aif1dac_mux = | |
1158 | SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); | |
1159 | ||
1160 | static const char *aif2dac_text[] = { | |
1161 | "AIF2DACDAT", "AIF3DACDAT", | |
1162 | }; | |
1163 | ||
1164 | static const struct soc_enum aif2dac_enum = | |
1165 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); | |
1166 | ||
1167 | static const struct snd_kcontrol_new aif2dac_mux = | |
1168 | SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); | |
1169 | ||
1170 | static const char *aif2adc_text[] = { | |
1171 | "AIF2ADCDAT", "AIF3DACDAT", | |
1172 | }; | |
1173 | ||
1174 | static const struct soc_enum aif2adc_enum = | |
1175 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); | |
1176 | ||
1177 | static const struct snd_kcontrol_new aif2adc_mux = | |
1178 | SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); | |
1179 | ||
1180 | static const char *aif3adc_text[] = { | |
c4431df0 | 1181 | "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", |
9e6e96a1 MB |
1182 | }; |
1183 | ||
c4431df0 | 1184 | static const struct soc_enum wm8994_aif3adc_enum = |
9e6e96a1 MB |
1185 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); |
1186 | ||
c4431df0 MB |
1187 | static const struct snd_kcontrol_new wm8994_aif3adc_mux = |
1188 | SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); | |
1189 | ||
1190 | static const struct soc_enum wm8958_aif3adc_enum = | |
1191 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); | |
1192 | ||
1193 | static const struct snd_kcontrol_new wm8958_aif3adc_mux = | |
1194 | SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); | |
1195 | ||
1196 | static const char *mono_pcm_out_text[] = { | |
1197 | "None", "AIF2ADCL", "AIF2ADCR", | |
1198 | }; | |
1199 | ||
1200 | static const struct soc_enum mono_pcm_out_enum = | |
1201 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); | |
1202 | ||
1203 | static const struct snd_kcontrol_new mono_pcm_out_mux = | |
1204 | SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); | |
1205 | ||
1206 | static const char *aif2dac_src_text[] = { | |
1207 | "AIF2", "AIF3", | |
1208 | }; | |
1209 | ||
1210 | /* Note that these two control shouldn't be simultaneously switched to AIF3 */ | |
1211 | static const struct soc_enum aif2dacl_src_enum = | |
1212 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); | |
1213 | ||
1214 | static const struct snd_kcontrol_new aif2dacl_src_mux = | |
1215 | SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); | |
1216 | ||
1217 | static const struct soc_enum aif2dacr_src_enum = | |
1218 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); | |
1219 | ||
1220 | static const struct snd_kcontrol_new aif2dacr_src_mux = | |
1221 | SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); | |
9e6e96a1 | 1222 | |
173efa09 DP |
1223 | static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { |
1224 | SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev, | |
1225 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
1226 | SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev, | |
1227 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
1228 | ||
1229 | SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
1230 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1231 | SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
1232 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1233 | SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
1234 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1235 | SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
1236 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
b70a51ba MB |
1237 | SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, |
1238 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1239 | ||
1240 | SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, | |
1241 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), | |
1242 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1243 | SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, | |
1244 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), | |
1245 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1246 | SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux, | |
1247 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1248 | SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux, | |
1249 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
173efa09 DP |
1250 | |
1251 | SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) | |
1252 | }; | |
1253 | ||
1254 | static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { | |
1255 | SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0), | |
b70a51ba MB |
1256 | SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0), |
1257 | SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1258 | SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, | |
1259 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), | |
1260 | SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, | |
1261 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), | |
1262 | SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), | |
1263 | SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), | |
173efa09 DP |
1264 | }; |
1265 | ||
c52fd021 DP |
1266 | static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { |
1267 | SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, | |
1268 | dac_ev, SND_SOC_DAPM_PRE_PMU), | |
1269 | SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, | |
1270 | dac_ev, SND_SOC_DAPM_PRE_PMU), | |
1271 | SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, | |
1272 | dac_ev, SND_SOC_DAPM_PRE_PMU), | |
1273 | SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, | |
1274 | dac_ev, SND_SOC_DAPM_PRE_PMU), | |
1275 | }; | |
1276 | ||
1277 | static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { | |
1278 | SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), | |
0627bd25 | 1279 | SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), |
c52fd021 DP |
1280 | SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), |
1281 | SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), | |
1282 | }; | |
1283 | ||
04d28681 DP |
1284 | static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { |
1285 | SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, | |
1286 | adc_mux_ev, SND_SOC_DAPM_PRE_PMU), | |
1287 | SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, | |
1288 | adc_mux_ev, SND_SOC_DAPM_PRE_PMU), | |
1289 | }; | |
1290 | ||
1291 | static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { | |
1292 | SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), | |
1293 | SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), | |
1294 | }; | |
1295 | ||
9e6e96a1 MB |
1296 | static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { |
1297 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
1298 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
66b47fdb | 1299 | SND_SOC_DAPM_INPUT("Clock"), |
9e6e96a1 | 1300 | |
b462c6e6 DP |
1301 | SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, |
1302 | SND_SOC_DAPM_PRE_PMU), | |
4b7ed83a MB |
1303 | SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, |
1304 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
b462c6e6 | 1305 | |
9e6e96a1 MB |
1306 | SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, |
1307 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
1308 | ||
1309 | SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0), | |
1310 | SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0), | |
1311 | SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0), | |
1312 | ||
7f94de48 | 1313 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, |
9e6e96a1 | 1314 | 0, WM8994_POWER_MANAGEMENT_4, 9, 0), |
7f94de48 | 1315 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, |
9e6e96a1 | 1316 | 0, WM8994_POWER_MANAGEMENT_4, 8, 0), |
d6addcc9 MB |
1317 | SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, |
1318 | WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev, | |
b2822a8c | 1319 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
d6addcc9 MB |
1320 | SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, |
1321 | WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev, | |
b2822a8c | 1322 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
9e6e96a1 | 1323 | |
7f94de48 | 1324 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, |
9e6e96a1 | 1325 | 0, WM8994_POWER_MANAGEMENT_4, 11, 0), |
7f94de48 | 1326 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, |
9e6e96a1 | 1327 | 0, WM8994_POWER_MANAGEMENT_4, 10, 0), |
d6addcc9 MB |
1328 | SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, |
1329 | WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev, | |
b2822a8c | 1330 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
d6addcc9 MB |
1331 | SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, |
1332 | WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev, | |
b2822a8c | 1333 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
9e6e96a1 MB |
1334 | |
1335 | SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, | |
1336 | aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), | |
1337 | SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, | |
1338 | aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), | |
1339 | ||
a3257ba8 MB |
1340 | SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, |
1341 | aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), | |
1342 | SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, | |
1343 | aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), | |
1344 | ||
9e6e96a1 MB |
1345 | SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, |
1346 | aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), | |
1347 | SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, | |
1348 | aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), | |
1349 | ||
1350 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), | |
1351 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), | |
1352 | ||
1353 | SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, | |
1354 | dac1l_mix, ARRAY_SIZE(dac1l_mix)), | |
1355 | SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, | |
1356 | dac1r_mix, ARRAY_SIZE(dac1r_mix)), | |
1357 | ||
1358 | SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, | |
1359 | WM8994_POWER_MANAGEMENT_4, 13, 0), | |
1360 | SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, | |
1361 | WM8994_POWER_MANAGEMENT_4, 12, 0), | |
d6addcc9 MB |
1362 | SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, |
1363 | WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev, | |
1364 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
1365 | SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, | |
1366 | WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev, | |
1367 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
9e6e96a1 MB |
1368 | |
1369 | SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
1370 | SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
7f94de48 | 1371 | SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), |
9e6e96a1 MB |
1372 | SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), |
1373 | ||
1374 | SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), | |
1375 | SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), | |
1376 | SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), | |
9e6e96a1 MB |
1377 | |
1378 | SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), | |
1379 | SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), | |
1380 | ||
1381 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), | |
1382 | ||
1383 | SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), | |
1384 | SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), | |
1385 | SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), | |
1386 | SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), | |
1387 | ||
1388 | /* Power is done with the muxes since the ADC power also controls the | |
1389 | * downsampling chain, the chip will automatically manage the analogue | |
1390 | * specific portions. | |
1391 | */ | |
1392 | SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), | |
1393 | SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), | |
1394 | ||
9e6e96a1 MB |
1395 | SND_SOC_DAPM_POST("Debug log", post_ev), |
1396 | }; | |
1397 | ||
c4431df0 MB |
1398 | static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { |
1399 | SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), | |
1400 | }; | |
9e6e96a1 | 1401 | |
c4431df0 MB |
1402 | static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { |
1403 | SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), | |
1404 | SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), | |
1405 | SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), | |
1406 | SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), | |
1407 | }; | |
1408 | ||
1409 | static const struct snd_soc_dapm_route intercon[] = { | |
9e6e96a1 MB |
1410 | { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, |
1411 | { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, | |
1412 | ||
1413 | { "DSP1CLK", NULL, "CLK_SYS" }, | |
1414 | { "DSP2CLK", NULL, "CLK_SYS" }, | |
1415 | { "DSPINTCLK", NULL, "CLK_SYS" }, | |
1416 | ||
1417 | { "AIF1ADC1L", NULL, "AIF1CLK" }, | |
1418 | { "AIF1ADC1L", NULL, "DSP1CLK" }, | |
1419 | { "AIF1ADC1R", NULL, "AIF1CLK" }, | |
1420 | { "AIF1ADC1R", NULL, "DSP1CLK" }, | |
1421 | { "AIF1ADC1R", NULL, "DSPINTCLK" }, | |
1422 | ||
1423 | { "AIF1DAC1L", NULL, "AIF1CLK" }, | |
1424 | { "AIF1DAC1L", NULL, "DSP1CLK" }, | |
1425 | { "AIF1DAC1R", NULL, "AIF1CLK" }, | |
1426 | { "AIF1DAC1R", NULL, "DSP1CLK" }, | |
1427 | { "AIF1DAC1R", NULL, "DSPINTCLK" }, | |
1428 | ||
1429 | { "AIF1ADC2L", NULL, "AIF1CLK" }, | |
1430 | { "AIF1ADC2L", NULL, "DSP1CLK" }, | |
1431 | { "AIF1ADC2R", NULL, "AIF1CLK" }, | |
1432 | { "AIF1ADC2R", NULL, "DSP1CLK" }, | |
1433 | { "AIF1ADC2R", NULL, "DSPINTCLK" }, | |
1434 | ||
1435 | { "AIF1DAC2L", NULL, "AIF1CLK" }, | |
1436 | { "AIF1DAC2L", NULL, "DSP1CLK" }, | |
1437 | { "AIF1DAC2R", NULL, "AIF1CLK" }, | |
1438 | { "AIF1DAC2R", NULL, "DSP1CLK" }, | |
1439 | { "AIF1DAC2R", NULL, "DSPINTCLK" }, | |
1440 | ||
1441 | { "AIF2ADCL", NULL, "AIF2CLK" }, | |
1442 | { "AIF2ADCL", NULL, "DSP2CLK" }, | |
1443 | { "AIF2ADCR", NULL, "AIF2CLK" }, | |
1444 | { "AIF2ADCR", NULL, "DSP2CLK" }, | |
1445 | { "AIF2ADCR", NULL, "DSPINTCLK" }, | |
1446 | ||
1447 | { "AIF2DACL", NULL, "AIF2CLK" }, | |
1448 | { "AIF2DACL", NULL, "DSP2CLK" }, | |
1449 | { "AIF2DACR", NULL, "AIF2CLK" }, | |
1450 | { "AIF2DACR", NULL, "DSP2CLK" }, | |
1451 | { "AIF2DACR", NULL, "DSPINTCLK" }, | |
1452 | ||
1453 | { "DMIC1L", NULL, "DMIC1DAT" }, | |
1454 | { "DMIC1L", NULL, "CLK_SYS" }, | |
1455 | { "DMIC1R", NULL, "DMIC1DAT" }, | |
1456 | { "DMIC1R", NULL, "CLK_SYS" }, | |
1457 | { "DMIC2L", NULL, "DMIC2DAT" }, | |
1458 | { "DMIC2L", NULL, "CLK_SYS" }, | |
1459 | { "DMIC2R", NULL, "DMIC2DAT" }, | |
1460 | { "DMIC2R", NULL, "CLK_SYS" }, | |
1461 | ||
1462 | { "ADCL", NULL, "AIF1CLK" }, | |
1463 | { "ADCL", NULL, "DSP1CLK" }, | |
1464 | { "ADCL", NULL, "DSPINTCLK" }, | |
1465 | ||
1466 | { "ADCR", NULL, "AIF1CLK" }, | |
1467 | { "ADCR", NULL, "DSP1CLK" }, | |
1468 | { "ADCR", NULL, "DSPINTCLK" }, | |
1469 | ||
1470 | { "ADCL Mux", "ADC", "ADCL" }, | |
1471 | { "ADCL Mux", "DMIC", "DMIC1L" }, | |
1472 | { "ADCR Mux", "ADC", "ADCR" }, | |
1473 | { "ADCR Mux", "DMIC", "DMIC1R" }, | |
1474 | ||
1475 | { "DAC1L", NULL, "AIF1CLK" }, | |
1476 | { "DAC1L", NULL, "DSP1CLK" }, | |
1477 | { "DAC1L", NULL, "DSPINTCLK" }, | |
1478 | ||
1479 | { "DAC1R", NULL, "AIF1CLK" }, | |
1480 | { "DAC1R", NULL, "DSP1CLK" }, | |
1481 | { "DAC1R", NULL, "DSPINTCLK" }, | |
1482 | ||
1483 | { "DAC2L", NULL, "AIF2CLK" }, | |
1484 | { "DAC2L", NULL, "DSP2CLK" }, | |
1485 | { "DAC2L", NULL, "DSPINTCLK" }, | |
1486 | ||
1487 | { "DAC2R", NULL, "AIF2DACR" }, | |
1488 | { "DAC2R", NULL, "AIF2CLK" }, | |
1489 | { "DAC2R", NULL, "DSP2CLK" }, | |
1490 | { "DAC2R", NULL, "DSPINTCLK" }, | |
1491 | ||
1492 | { "TOCLK", NULL, "CLK_SYS" }, | |
1493 | ||
1494 | /* AIF1 outputs */ | |
1495 | { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, | |
1496 | { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, | |
1497 | { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, | |
1498 | ||
1499 | { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, | |
1500 | { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, | |
1501 | { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, | |
1502 | ||
a3257ba8 MB |
1503 | { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, |
1504 | { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, | |
1505 | { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, | |
1506 | ||
1507 | { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, | |
1508 | { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, | |
1509 | { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, | |
1510 | ||
9e6e96a1 MB |
1511 | /* Pin level routing for AIF3 */ |
1512 | { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, | |
1513 | { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, | |
1514 | { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, | |
1515 | { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, | |
1516 | ||
9e6e96a1 MB |
1517 | { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, |
1518 | { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, | |
1519 | { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, | |
1520 | { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, | |
1521 | { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, | |
1522 | { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, | |
1523 | { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, | |
1524 | ||
1525 | /* DAC1 inputs */ | |
9e6e96a1 MB |
1526 | { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, |
1527 | { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
1528 | { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
1529 | { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1530 | { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1531 | ||
9e6e96a1 MB |
1532 | { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, |
1533 | { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
1534 | { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
1535 | { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1536 | { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1537 | ||
1538 | /* DAC2/AIF2 outputs */ | |
1539 | { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, | |
9e6e96a1 MB |
1540 | { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, |
1541 | { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
1542 | { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
1543 | { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1544 | { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1545 | ||
1546 | { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, | |
9e6e96a1 MB |
1547 | { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, |
1548 | { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
1549 | { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
1550 | { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1551 | { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1552 | ||
7f94de48 MB |
1553 | { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, |
1554 | { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, | |
1555 | { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, | |
1556 | { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, | |
1557 | ||
9e6e96a1 MB |
1558 | { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, |
1559 | ||
1560 | /* AIF3 output */ | |
1561 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, | |
1562 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, | |
1563 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, | |
1564 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, | |
1565 | { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, | |
1566 | { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, | |
1567 | { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, | |
1568 | { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, | |
1569 | ||
1570 | /* Sidetone */ | |
1571 | { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, | |
1572 | { "Left Sidetone", "DMIC2", "DMIC2L" }, | |
1573 | { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, | |
1574 | { "Right Sidetone", "DMIC2", "DMIC2R" }, | |
1575 | ||
1576 | /* Output stages */ | |
1577 | { "Left Output Mixer", "DAC Switch", "DAC1L" }, | |
1578 | { "Right Output Mixer", "DAC Switch", "DAC1R" }, | |
1579 | ||
1580 | { "SPKL", "DAC1 Switch", "DAC1L" }, | |
1581 | { "SPKL", "DAC2 Switch", "DAC2L" }, | |
1582 | ||
1583 | { "SPKR", "DAC1 Switch", "DAC1R" }, | |
1584 | { "SPKR", "DAC2 Switch", "DAC2R" }, | |
1585 | ||
1586 | { "Left Headphone Mux", "DAC", "DAC1L" }, | |
1587 | { "Right Headphone Mux", "DAC", "DAC1R" }, | |
1588 | }; | |
1589 | ||
173efa09 DP |
1590 | static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { |
1591 | { "DAC1L", NULL, "Late DAC1L Enable PGA" }, | |
1592 | { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, | |
1593 | { "DAC1R", NULL, "Late DAC1R Enable PGA" }, | |
1594 | { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, | |
1595 | { "DAC2L", NULL, "Late DAC2L Enable PGA" }, | |
1596 | { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, | |
1597 | { "DAC2R", NULL, "Late DAC2R Enable PGA" }, | |
1598 | { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } | |
1599 | }; | |
1600 | ||
1601 | static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { | |
1602 | { "DAC1L", NULL, "DAC1L Mixer" }, | |
1603 | { "DAC1R", NULL, "DAC1R Mixer" }, | |
1604 | { "DAC2L", NULL, "AIF2DAC2L Mixer" }, | |
1605 | { "DAC2R", NULL, "AIF2DAC2R Mixer" }, | |
1606 | }; | |
1607 | ||
6ed8f148 MB |
1608 | static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { |
1609 | { "AIF1DACDAT", NULL, "AIF2DACDAT" }, | |
1610 | { "AIF2DACDAT", NULL, "AIF1DACDAT" }, | |
1611 | { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, | |
1612 | { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, | |
b793eb60 MB |
1613 | { "MICBIAS1", NULL, "CLK_SYS" }, |
1614 | { "MICBIAS1", NULL, "MICBIAS Supply" }, | |
1615 | { "MICBIAS2", NULL, "CLK_SYS" }, | |
1616 | { "MICBIAS2", NULL, "MICBIAS Supply" }, | |
6ed8f148 MB |
1617 | }; |
1618 | ||
c4431df0 MB |
1619 | static const struct snd_soc_dapm_route wm8994_intercon[] = { |
1620 | { "AIF2DACL", NULL, "AIF2DAC Mux" }, | |
1621 | { "AIF2DACR", NULL, "AIF2DAC Mux" }, | |
4e04adaf MB |
1622 | { "MICBIAS1", NULL, "VMID" }, |
1623 | { "MICBIAS2", NULL, "VMID" }, | |
c4431df0 MB |
1624 | }; |
1625 | ||
1626 | static const struct snd_soc_dapm_route wm8958_intercon[] = { | |
1627 | { "AIF2DACL", NULL, "AIF2DACL Mux" }, | |
1628 | { "AIF2DACR", NULL, "AIF2DACR Mux" }, | |
1629 | ||
1630 | { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, | |
1631 | { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, | |
1632 | { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, | |
1633 | { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, | |
1634 | ||
1635 | { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, | |
1636 | { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, | |
1637 | ||
1638 | { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, | |
1639 | }; | |
1640 | ||
9e6e96a1 MB |
1641 | /* The size in bits of the FLL divide multiplied by 10 |
1642 | * to allow rounding later */ | |
1643 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1644 | ||
1645 | struct fll_div { | |
1646 | u16 outdiv; | |
1647 | u16 n; | |
1648 | u16 k; | |
1649 | u16 clk_ref_div; | |
1650 | u16 fll_fratio; | |
1651 | }; | |
1652 | ||
1653 | static int wm8994_get_fll_config(struct fll_div *fll, | |
1654 | int freq_in, int freq_out) | |
1655 | { | |
1656 | u64 Kpart; | |
1657 | unsigned int K, Ndiv, Nmod; | |
1658 | ||
1659 | pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); | |
1660 | ||
1661 | /* Scale the input frequency down to <= 13.5MHz */ | |
1662 | fll->clk_ref_div = 0; | |
1663 | while (freq_in > 13500000) { | |
1664 | fll->clk_ref_div++; | |
1665 | freq_in /= 2; | |
1666 | ||
1667 | if (fll->clk_ref_div > 3) | |
1668 | return -EINVAL; | |
1669 | } | |
1670 | pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); | |
1671 | ||
1672 | /* Scale the output to give 90MHz<=Fvco<=100MHz */ | |
1673 | fll->outdiv = 3; | |
1674 | while (freq_out * (fll->outdiv + 1) < 90000000) { | |
1675 | fll->outdiv++; | |
1676 | if (fll->outdiv > 63) | |
1677 | return -EINVAL; | |
1678 | } | |
1679 | freq_out *= fll->outdiv + 1; | |
1680 | pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); | |
1681 | ||
1682 | if (freq_in > 1000000) { | |
1683 | fll->fll_fratio = 0; | |
7d48a6ac MB |
1684 | } else if (freq_in > 256000) { |
1685 | fll->fll_fratio = 1; | |
1686 | freq_in *= 2; | |
1687 | } else if (freq_in > 128000) { | |
1688 | fll->fll_fratio = 2; | |
1689 | freq_in *= 4; | |
1690 | } else if (freq_in > 64000) { | |
9e6e96a1 MB |
1691 | fll->fll_fratio = 3; |
1692 | freq_in *= 8; | |
7d48a6ac MB |
1693 | } else { |
1694 | fll->fll_fratio = 4; | |
1695 | freq_in *= 16; | |
9e6e96a1 MB |
1696 | } |
1697 | pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); | |
1698 | ||
1699 | /* Now, calculate N.K */ | |
1700 | Ndiv = freq_out / freq_in; | |
1701 | ||
1702 | fll->n = Ndiv; | |
1703 | Nmod = freq_out % freq_in; | |
1704 | pr_debug("Nmod=%d\n", Nmod); | |
1705 | ||
1706 | /* Calculate fractional part - scale up so we can round. */ | |
1707 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1708 | ||
1709 | do_div(Kpart, freq_in); | |
1710 | ||
1711 | K = Kpart & 0xFFFFFFFF; | |
1712 | ||
1713 | if ((K % 10) >= 5) | |
1714 | K += 5; | |
1715 | ||
1716 | /* Move down to proper range now rounding is done */ | |
1717 | fll->k = K / 10; | |
1718 | ||
1719 | pr_debug("N=%x K=%x\n", fll->n, fll->k); | |
1720 | ||
1721 | return 0; | |
1722 | } | |
1723 | ||
f0fba2ad | 1724 | static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, |
9e6e96a1 MB |
1725 | unsigned int freq_in, unsigned int freq_out) |
1726 | { | |
b2c812e2 | 1727 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
4b7ed83a | 1728 | struct wm8994 *control = codec->control_data; |
9e6e96a1 MB |
1729 | int reg_offset, ret; |
1730 | struct fll_div fll; | |
1731 | u16 reg, aif1, aif2; | |
c7ebf932 | 1732 | unsigned long timeout; |
4b7ed83a | 1733 | bool was_enabled; |
9e6e96a1 MB |
1734 | |
1735 | aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1) | |
1736 | & WM8994_AIF1CLK_ENA; | |
1737 | ||
1738 | aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1) | |
1739 | & WM8994_AIF2CLK_ENA; | |
1740 | ||
1741 | switch (id) { | |
1742 | case WM8994_FLL1: | |
1743 | reg_offset = 0; | |
1744 | id = 0; | |
1745 | break; | |
1746 | case WM8994_FLL2: | |
1747 | reg_offset = 0x20; | |
1748 | id = 1; | |
1749 | break; | |
1750 | default: | |
1751 | return -EINVAL; | |
1752 | } | |
1753 | ||
4b7ed83a MB |
1754 | reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset); |
1755 | was_enabled = reg & WM8994_FLL1_ENA; | |
1756 | ||
136ff2a2 | 1757 | switch (src) { |
7add84aa MB |
1758 | case 0: |
1759 | /* Allow no source specification when stopping */ | |
1760 | if (freq_out) | |
1761 | return -EINVAL; | |
4514e899 | 1762 | src = wm8994->fll[id].src; |
7add84aa | 1763 | break; |
136ff2a2 MB |
1764 | case WM8994_FLL_SRC_MCLK1: |
1765 | case WM8994_FLL_SRC_MCLK2: | |
1766 | case WM8994_FLL_SRC_LRCLK: | |
1767 | case WM8994_FLL_SRC_BCLK: | |
1768 | break; | |
1769 | default: | |
1770 | return -EINVAL; | |
1771 | } | |
1772 | ||
9e6e96a1 MB |
1773 | /* Are we changing anything? */ |
1774 | if (wm8994->fll[id].src == src && | |
1775 | wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) | |
1776 | return 0; | |
1777 | ||
1778 | /* If we're stopping the FLL redo the old config - no | |
1779 | * registers will actually be written but we avoid GCC flow | |
1780 | * analysis bugs spewing warnings. | |
1781 | */ | |
1782 | if (freq_out) | |
1783 | ret = wm8994_get_fll_config(&fll, freq_in, freq_out); | |
1784 | else | |
1785 | ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, | |
1786 | wm8994->fll[id].out); | |
1787 | if (ret < 0) | |
1788 | return ret; | |
1789 | ||
1790 | /* Gate the AIF clocks while we reclock */ | |
1791 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, | |
1792 | WM8994_AIF1CLK_ENA, 0); | |
1793 | snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, | |
1794 | WM8994_AIF2CLK_ENA, 0); | |
1795 | ||
1796 | /* We always need to disable the FLL while reconfiguring */ | |
1797 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, | |
1798 | WM8994_FLL1_ENA, 0); | |
1799 | ||
1800 | reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | | |
1801 | (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); | |
1802 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, | |
1803 | WM8994_FLL1_OUTDIV_MASK | | |
1804 | WM8994_FLL1_FRATIO_MASK, reg); | |
1805 | ||
1806 | snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k); | |
1807 | ||
1808 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, | |
1809 | WM8994_FLL1_N_MASK, | |
1810 | fll.n << WM8994_FLL1_N_SHIFT); | |
1811 | ||
1812 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, | |
136ff2a2 MB |
1813 | WM8994_FLL1_REFCLK_DIV_MASK | |
1814 | WM8994_FLL1_REFCLK_SRC_MASK, | |
1815 | (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | | |
1816 | (src - 1)); | |
9e6e96a1 | 1817 | |
f0f5039c MB |
1818 | /* Clear any pending completion from a previous failure */ |
1819 | try_wait_for_completion(&wm8994->fll_locked[id]); | |
1820 | ||
9e6e96a1 MB |
1821 | /* Enable (with fractional mode if required) */ |
1822 | if (freq_out) { | |
4b7ed83a MB |
1823 | /* Enable VMID if we need it */ |
1824 | if (!was_enabled) { | |
1825 | switch (control->type) { | |
1826 | case WM8994: | |
1827 | vmid_reference(codec); | |
1828 | break; | |
1829 | case WM8958: | |
1830 | if (wm8994->revision < 1) | |
1831 | vmid_reference(codec); | |
1832 | break; | |
1833 | default: | |
1834 | break; | |
1835 | } | |
1836 | } | |
1837 | ||
9e6e96a1 MB |
1838 | if (fll.k) |
1839 | reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC; | |
1840 | else | |
1841 | reg = WM8994_FLL1_ENA; | |
1842 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, | |
1843 | WM8994_FLL1_ENA | WM8994_FLL1_FRAC, | |
1844 | reg); | |
8e9ddf81 | 1845 | |
c7ebf932 MB |
1846 | if (wm8994->fll_locked_irq) { |
1847 | timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], | |
1848 | msecs_to_jiffies(10)); | |
1849 | if (timeout == 0) | |
1850 | dev_warn(codec->dev, | |
1851 | "Timed out waiting for FLL lock\n"); | |
1852 | } else { | |
1853 | msleep(5); | |
1854 | } | |
4b7ed83a MB |
1855 | } else { |
1856 | if (was_enabled) { | |
1857 | switch (control->type) { | |
1858 | case WM8994: | |
1859 | vmid_dereference(codec); | |
1860 | break; | |
1861 | case WM8958: | |
1862 | if (wm8994->revision < 1) | |
1863 | vmid_dereference(codec); | |
1864 | break; | |
1865 | default: | |
1866 | break; | |
1867 | } | |
1868 | } | |
9e6e96a1 MB |
1869 | } |
1870 | ||
1871 | wm8994->fll[id].in = freq_in; | |
1872 | wm8994->fll[id].out = freq_out; | |
136ff2a2 | 1873 | wm8994->fll[id].src = src; |
9e6e96a1 MB |
1874 | |
1875 | /* Enable any gated AIF clocks */ | |
1876 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, | |
1877 | WM8994_AIF1CLK_ENA, aif1); | |
1878 | snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, | |
1879 | WM8994_AIF2CLK_ENA, aif2); | |
1880 | ||
1881 | configure_clock(codec); | |
1882 | ||
1883 | return 0; | |
1884 | } | |
1885 | ||
c7ebf932 MB |
1886 | static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) |
1887 | { | |
1888 | struct completion *completion = data; | |
1889 | ||
1890 | complete(completion); | |
1891 | ||
1892 | return IRQ_HANDLED; | |
1893 | } | |
f0fba2ad | 1894 | |
66b47fdb MB |
1895 | static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; |
1896 | ||
f0fba2ad LG |
1897 | static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, |
1898 | unsigned int freq_in, unsigned int freq_out) | |
1899 | { | |
1900 | return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); | |
1901 | } | |
1902 | ||
9e6e96a1 MB |
1903 | static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, |
1904 | int clk_id, unsigned int freq, int dir) | |
1905 | { | |
1906 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1907 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
66b47fdb | 1908 | int i; |
9e6e96a1 MB |
1909 | |
1910 | switch (dai->id) { | |
1911 | case 1: | |
1912 | case 2: | |
1913 | break; | |
1914 | ||
1915 | default: | |
1916 | /* AIF3 shares clocking with AIF1/2 */ | |
1917 | return -EINVAL; | |
1918 | } | |
1919 | ||
1920 | switch (clk_id) { | |
1921 | case WM8994_SYSCLK_MCLK1: | |
1922 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; | |
1923 | wm8994->mclk[0] = freq; | |
1924 | dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", | |
1925 | dai->id, freq); | |
1926 | break; | |
1927 | ||
1928 | case WM8994_SYSCLK_MCLK2: | |
1929 | /* TODO: Set GPIO AF */ | |
1930 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; | |
1931 | wm8994->mclk[1] = freq; | |
1932 | dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", | |
1933 | dai->id, freq); | |
1934 | break; | |
1935 | ||
1936 | case WM8994_SYSCLK_FLL1: | |
1937 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; | |
1938 | dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); | |
1939 | break; | |
1940 | ||
1941 | case WM8994_SYSCLK_FLL2: | |
1942 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; | |
1943 | dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); | |
1944 | break; | |
1945 | ||
66b47fdb MB |
1946 | case WM8994_SYSCLK_OPCLK: |
1947 | /* Special case - a division (times 10) is given and | |
1948 | * no effect on main clocking. | |
1949 | */ | |
1950 | if (freq) { | |
1951 | for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) | |
1952 | if (opclk_divs[i] == freq) | |
1953 | break; | |
1954 | if (i == ARRAY_SIZE(opclk_divs)) | |
1955 | return -EINVAL; | |
1956 | snd_soc_update_bits(codec, WM8994_CLOCKING_2, | |
1957 | WM8994_OPCLK_DIV_MASK, i); | |
1958 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, | |
1959 | WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); | |
1960 | } else { | |
1961 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, | |
1962 | WM8994_OPCLK_ENA, 0); | |
1963 | } | |
1964 | ||
9e6e96a1 MB |
1965 | default: |
1966 | return -EINVAL; | |
1967 | } | |
1968 | ||
1969 | configure_clock(codec); | |
1970 | ||
1971 | return 0; | |
1972 | } | |
1973 | ||
1974 | static int wm8994_set_bias_level(struct snd_soc_codec *codec, | |
1975 | enum snd_soc_bias_level level) | |
1976 | { | |
3a423157 | 1977 | struct wm8994 *control = codec->control_data; |
b6b05691 MB |
1978 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
1979 | ||
9e6e96a1 MB |
1980 | switch (level) { |
1981 | case SND_SOC_BIAS_ON: | |
1982 | break; | |
1983 | ||
1984 | case SND_SOC_BIAS_PREPARE: | |
9e6e96a1 MB |
1985 | break; |
1986 | ||
1987 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 1988 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
39fb51a1 MB |
1989 | pm_runtime_get_sync(codec->dev); |
1990 | ||
8bc3c2c2 MB |
1991 | switch (control->type) { |
1992 | case WM8994: | |
1993 | if (wm8994->revision < 4) { | |
1994 | /* Tweak DC servo and DSP | |
1995 | * configuration for improved | |
1996 | * performance. */ | |
1997 | snd_soc_write(codec, 0x102, 0x3); | |
1998 | snd_soc_write(codec, 0x56, 0x3); | |
1999 | snd_soc_write(codec, 0x817, 0); | |
2000 | snd_soc_write(codec, 0x102, 0); | |
2001 | } | |
2002 | break; | |
2003 | ||
2004 | case WM8958: | |
2005 | if (wm8994->revision == 0) { | |
2006 | /* Optimise performance for rev A */ | |
2007 | snd_soc_write(codec, 0x102, 0x3); | |
2008 | snd_soc_write(codec, 0xcb, 0x81); | |
2009 | snd_soc_write(codec, 0x817, 0); | |
2010 | snd_soc_write(codec, 0x102, 0); | |
2011 | ||
2012 | snd_soc_update_bits(codec, | |
2013 | WM8958_CHARGE_PUMP_2, | |
2014 | WM8958_CP_DISCH, | |
2015 | WM8958_CP_DISCH); | |
2016 | } | |
2017 | break; | |
b6b05691 | 2018 | } |
9e6e96a1 MB |
2019 | |
2020 | /* Discharge LINEOUT1 & 2 */ | |
2021 | snd_soc_update_bits(codec, WM8994_ANTIPOP_1, | |
2022 | WM8994_LINEOUT1_DISCH | | |
2023 | WM8994_LINEOUT2_DISCH, | |
2024 | WM8994_LINEOUT1_DISCH | | |
2025 | WM8994_LINEOUT2_DISCH); | |
9e6e96a1 MB |
2026 | } |
2027 | ||
9e6e96a1 MB |
2028 | |
2029 | break; | |
2030 | ||
2031 | case SND_SOC_BIAS_OFF: | |
ce6120cc | 2032 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { |
fbbf5920 MB |
2033 | wm8994->cur_fw = NULL; |
2034 | ||
39fb51a1 | 2035 | pm_runtime_put(codec->dev); |
d522ffbf | 2036 | } |
9e6e96a1 MB |
2037 | break; |
2038 | } | |
ce6120cc | 2039 | codec->dapm.bias_level = level; |
9e6e96a1 MB |
2040 | return 0; |
2041 | } | |
2042 | ||
2043 | static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
2044 | { | |
2045 | struct snd_soc_codec *codec = dai->codec; | |
c4431df0 | 2046 | struct wm8994 *control = codec->control_data; |
9e6e96a1 MB |
2047 | int ms_reg; |
2048 | int aif1_reg; | |
2049 | int ms = 0; | |
2050 | int aif1 = 0; | |
2051 | ||
2052 | switch (dai->id) { | |
2053 | case 1: | |
2054 | ms_reg = WM8994_AIF1_MASTER_SLAVE; | |
2055 | aif1_reg = WM8994_AIF1_CONTROL_1; | |
2056 | break; | |
2057 | case 2: | |
2058 | ms_reg = WM8994_AIF2_MASTER_SLAVE; | |
2059 | aif1_reg = WM8994_AIF2_CONTROL_1; | |
2060 | break; | |
2061 | default: | |
2062 | return -EINVAL; | |
2063 | } | |
2064 | ||
2065 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
2066 | case SND_SOC_DAIFMT_CBS_CFS: | |
2067 | break; | |
2068 | case SND_SOC_DAIFMT_CBM_CFM: | |
2069 | ms = WM8994_AIF1_MSTR; | |
2070 | break; | |
2071 | default: | |
2072 | return -EINVAL; | |
2073 | } | |
2074 | ||
2075 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
2076 | case SND_SOC_DAIFMT_DSP_B: | |
2077 | aif1 |= WM8994_AIF1_LRCLK_INV; | |
2078 | case SND_SOC_DAIFMT_DSP_A: | |
2079 | aif1 |= 0x18; | |
2080 | break; | |
2081 | case SND_SOC_DAIFMT_I2S: | |
2082 | aif1 |= 0x10; | |
2083 | break; | |
2084 | case SND_SOC_DAIFMT_RIGHT_J: | |
2085 | break; | |
2086 | case SND_SOC_DAIFMT_LEFT_J: | |
2087 | aif1 |= 0x8; | |
2088 | break; | |
2089 | default: | |
2090 | return -EINVAL; | |
2091 | } | |
2092 | ||
2093 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
2094 | case SND_SOC_DAIFMT_DSP_A: | |
2095 | case SND_SOC_DAIFMT_DSP_B: | |
2096 | /* frame inversion not valid for DSP modes */ | |
2097 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2098 | case SND_SOC_DAIFMT_NB_NF: | |
2099 | break; | |
2100 | case SND_SOC_DAIFMT_IB_NF: | |
2101 | aif1 |= WM8994_AIF1_BCLK_INV; | |
2102 | break; | |
2103 | default: | |
2104 | return -EINVAL; | |
2105 | } | |
2106 | break; | |
2107 | ||
2108 | case SND_SOC_DAIFMT_I2S: | |
2109 | case SND_SOC_DAIFMT_RIGHT_J: | |
2110 | case SND_SOC_DAIFMT_LEFT_J: | |
2111 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2112 | case SND_SOC_DAIFMT_NB_NF: | |
2113 | break; | |
2114 | case SND_SOC_DAIFMT_IB_IF: | |
2115 | aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; | |
2116 | break; | |
2117 | case SND_SOC_DAIFMT_IB_NF: | |
2118 | aif1 |= WM8994_AIF1_BCLK_INV; | |
2119 | break; | |
2120 | case SND_SOC_DAIFMT_NB_IF: | |
2121 | aif1 |= WM8994_AIF1_LRCLK_INV; | |
2122 | break; | |
2123 | default: | |
2124 | return -EINVAL; | |
2125 | } | |
2126 | break; | |
2127 | default: | |
2128 | return -EINVAL; | |
2129 | } | |
2130 | ||
c4431df0 MB |
2131 | /* The AIF2 format configuration needs to be mirrored to AIF3 |
2132 | * on WM8958 if it's in use so just do it all the time. */ | |
2133 | if (control->type == WM8958 && dai->id == 2) | |
2134 | snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, | |
2135 | WM8994_AIF1_LRCLK_INV | | |
2136 | WM8958_AIF3_FMT_MASK, aif1); | |
2137 | ||
9e6e96a1 MB |
2138 | snd_soc_update_bits(codec, aif1_reg, |
2139 | WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | | |
2140 | WM8994_AIF1_FMT_MASK, | |
2141 | aif1); | |
2142 | snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, | |
2143 | ms); | |
2144 | ||
2145 | return 0; | |
2146 | } | |
2147 | ||
2148 | static struct { | |
2149 | int val, rate; | |
2150 | } srs[] = { | |
2151 | { 0, 8000 }, | |
2152 | { 1, 11025 }, | |
2153 | { 2, 12000 }, | |
2154 | { 3, 16000 }, | |
2155 | { 4, 22050 }, | |
2156 | { 5, 24000 }, | |
2157 | { 6, 32000 }, | |
2158 | { 7, 44100 }, | |
2159 | { 8, 48000 }, | |
2160 | { 9, 88200 }, | |
2161 | { 10, 96000 }, | |
2162 | }; | |
2163 | ||
2164 | static int fs_ratios[] = { | |
2165 | 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 | |
2166 | }; | |
2167 | ||
2168 | static int bclk_divs[] = { | |
2169 | 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, | |
2170 | 640, 880, 960, 1280, 1760, 1920 | |
2171 | }; | |
2172 | ||
2173 | static int wm8994_hw_params(struct snd_pcm_substream *substream, | |
2174 | struct snd_pcm_hw_params *params, | |
2175 | struct snd_soc_dai *dai) | |
2176 | { | |
2177 | struct snd_soc_codec *codec = dai->codec; | |
c4431df0 | 2178 | struct wm8994 *control = codec->control_data; |
b2c812e2 | 2179 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 | 2180 | int aif1_reg; |
b1e43d93 | 2181 | int aif2_reg; |
9e6e96a1 MB |
2182 | int bclk_reg; |
2183 | int lrclk_reg; | |
2184 | int rate_reg; | |
2185 | int aif1 = 0; | |
b1e43d93 | 2186 | int aif2 = 0; |
9e6e96a1 MB |
2187 | int bclk = 0; |
2188 | int lrclk = 0; | |
2189 | int rate_val = 0; | |
2190 | int id = dai->id - 1; | |
2191 | ||
2192 | int i, cur_val, best_val, bclk_rate, best; | |
2193 | ||
2194 | switch (dai->id) { | |
2195 | case 1: | |
2196 | aif1_reg = WM8994_AIF1_CONTROL_1; | |
b1e43d93 | 2197 | aif2_reg = WM8994_AIF1_CONTROL_2; |
9e6e96a1 MB |
2198 | bclk_reg = WM8994_AIF1_BCLK; |
2199 | rate_reg = WM8994_AIF1_RATE; | |
2200 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
7d83d213 | 2201 | wm8994->lrclk_shared[0]) { |
9e6e96a1 | 2202 | lrclk_reg = WM8994_AIF1DAC_LRCLK; |
7d83d213 | 2203 | } else { |
9e6e96a1 | 2204 | lrclk_reg = WM8994_AIF1ADC_LRCLK; |
7d83d213 MB |
2205 | dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); |
2206 | } | |
9e6e96a1 MB |
2207 | break; |
2208 | case 2: | |
2209 | aif1_reg = WM8994_AIF2_CONTROL_1; | |
b1e43d93 | 2210 | aif2_reg = WM8994_AIF2_CONTROL_2; |
9e6e96a1 MB |
2211 | bclk_reg = WM8994_AIF2_BCLK; |
2212 | rate_reg = WM8994_AIF2_RATE; | |
2213 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
7d83d213 | 2214 | wm8994->lrclk_shared[1]) { |
9e6e96a1 | 2215 | lrclk_reg = WM8994_AIF2DAC_LRCLK; |
7d83d213 | 2216 | } else { |
9e6e96a1 | 2217 | lrclk_reg = WM8994_AIF2ADC_LRCLK; |
7d83d213 MB |
2218 | dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); |
2219 | } | |
9e6e96a1 | 2220 | break; |
c4431df0 MB |
2221 | case 3: |
2222 | switch (control->type) { | |
2223 | case WM8958: | |
2224 | aif1_reg = WM8958_AIF3_CONTROL_1; | |
2225 | break; | |
2226 | default: | |
2227 | return 0; | |
2228 | } | |
9e6e96a1 MB |
2229 | default: |
2230 | return -EINVAL; | |
2231 | } | |
2232 | ||
2233 | bclk_rate = params_rate(params) * 2; | |
2234 | switch (params_format(params)) { | |
2235 | case SNDRV_PCM_FORMAT_S16_LE: | |
2236 | bclk_rate *= 16; | |
2237 | break; | |
2238 | case SNDRV_PCM_FORMAT_S20_3LE: | |
2239 | bclk_rate *= 20; | |
2240 | aif1 |= 0x20; | |
2241 | break; | |
2242 | case SNDRV_PCM_FORMAT_S24_LE: | |
2243 | bclk_rate *= 24; | |
2244 | aif1 |= 0x40; | |
2245 | break; | |
2246 | case SNDRV_PCM_FORMAT_S32_LE: | |
2247 | bclk_rate *= 32; | |
2248 | aif1 |= 0x60; | |
2249 | break; | |
2250 | default: | |
2251 | return -EINVAL; | |
2252 | } | |
2253 | ||
2254 | /* Try to find an appropriate sample rate; look for an exact match. */ | |
2255 | for (i = 0; i < ARRAY_SIZE(srs); i++) | |
2256 | if (srs[i].rate == params_rate(params)) | |
2257 | break; | |
2258 | if (i == ARRAY_SIZE(srs)) | |
2259 | return -EINVAL; | |
2260 | rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; | |
2261 | ||
2262 | dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); | |
2263 | dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", | |
2264 | dai->id, wm8994->aifclk[id], bclk_rate); | |
2265 | ||
b1e43d93 MB |
2266 | if (params_channels(params) == 1 && |
2267 | (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) | |
2268 | aif2 |= WM8994_AIF1_MONO; | |
2269 | ||
9e6e96a1 MB |
2270 | if (wm8994->aifclk[id] == 0) { |
2271 | dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); | |
2272 | return -EINVAL; | |
2273 | } | |
2274 | ||
2275 | /* AIFCLK/fs ratio; look for a close match in either direction */ | |
2276 | best = 0; | |
2277 | best_val = abs((fs_ratios[0] * params_rate(params)) | |
2278 | - wm8994->aifclk[id]); | |
2279 | for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { | |
2280 | cur_val = abs((fs_ratios[i] * params_rate(params)) | |
2281 | - wm8994->aifclk[id]); | |
2282 | if (cur_val >= best_val) | |
2283 | continue; | |
2284 | best = i; | |
2285 | best_val = cur_val; | |
2286 | } | |
2287 | dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", | |
2288 | dai->id, fs_ratios[best]); | |
2289 | rate_val |= best; | |
2290 | ||
2291 | /* We may not get quite the right frequency if using | |
2292 | * approximate clocks so look for the closest match that is | |
2293 | * higher than the target (we need to ensure that there enough | |
2294 | * BCLKs to clock out the samples). | |
2295 | */ | |
2296 | best = 0; | |
2297 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
07cd8ada | 2298 | cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; |
9e6e96a1 MB |
2299 | if (cur_val < 0) /* BCLK table is sorted */ |
2300 | break; | |
2301 | best = i; | |
2302 | } | |
07cd8ada | 2303 | bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; |
9e6e96a1 MB |
2304 | dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", |
2305 | bclk_divs[best], bclk_rate); | |
2306 | bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; | |
2307 | ||
2308 | lrclk = bclk_rate / params_rate(params); | |
2309 | dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", | |
2310 | lrclk, bclk_rate / lrclk); | |
2311 | ||
2312 | snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); | |
b1e43d93 | 2313 | snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); |
9e6e96a1 MB |
2314 | snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); |
2315 | snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, | |
2316 | lrclk); | |
2317 | snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | | |
2318 | WM8994_AIF1CLK_RATE_MASK, rate_val); | |
2319 | ||
2320 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
2321 | switch (dai->id) { | |
2322 | case 1: | |
2323 | wm8994->dac_rates[0] = params_rate(params); | |
2324 | wm8994_set_retune_mobile(codec, 0); | |
2325 | wm8994_set_retune_mobile(codec, 1); | |
2326 | break; | |
2327 | case 2: | |
2328 | wm8994->dac_rates[1] = params_rate(params); | |
2329 | wm8994_set_retune_mobile(codec, 2); | |
2330 | break; | |
2331 | } | |
2332 | } | |
2333 | ||
2334 | return 0; | |
2335 | } | |
2336 | ||
c4431df0 MB |
2337 | static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, |
2338 | struct snd_pcm_hw_params *params, | |
2339 | struct snd_soc_dai *dai) | |
2340 | { | |
2341 | struct snd_soc_codec *codec = dai->codec; | |
2342 | struct wm8994 *control = codec->control_data; | |
2343 | int aif1_reg; | |
2344 | int aif1 = 0; | |
2345 | ||
2346 | switch (dai->id) { | |
2347 | case 3: | |
2348 | switch (control->type) { | |
2349 | case WM8958: | |
2350 | aif1_reg = WM8958_AIF3_CONTROL_1; | |
2351 | break; | |
2352 | default: | |
2353 | return 0; | |
2354 | } | |
2355 | default: | |
2356 | return 0; | |
2357 | } | |
2358 | ||
2359 | switch (params_format(params)) { | |
2360 | case SNDRV_PCM_FORMAT_S16_LE: | |
2361 | break; | |
2362 | case SNDRV_PCM_FORMAT_S20_3LE: | |
2363 | aif1 |= 0x20; | |
2364 | break; | |
2365 | case SNDRV_PCM_FORMAT_S24_LE: | |
2366 | aif1 |= 0x40; | |
2367 | break; | |
2368 | case SNDRV_PCM_FORMAT_S32_LE: | |
2369 | aif1 |= 0x60; | |
2370 | break; | |
2371 | default: | |
2372 | return -EINVAL; | |
2373 | } | |
2374 | ||
2375 | return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); | |
2376 | } | |
2377 | ||
7d02173c MB |
2378 | static void wm8994_aif_shutdown(struct snd_pcm_substream *substream, |
2379 | struct snd_soc_dai *dai) | |
2380 | { | |
2381 | struct snd_soc_codec *codec = dai->codec; | |
2382 | int rate_reg = 0; | |
2383 | ||
2384 | switch (dai->id) { | |
2385 | case 1: | |
2386 | rate_reg = WM8994_AIF1_RATE; | |
2387 | break; | |
2388 | case 2: | |
2389 | rate_reg = WM8994_AIF1_RATE; | |
2390 | break; | |
2391 | default: | |
2392 | break; | |
2393 | } | |
2394 | ||
2395 | /* If the DAI is idle then configure the divider tree for the | |
2396 | * lowest output rate to save a little power if the clock is | |
2397 | * still active (eg, because it is system clock). | |
2398 | */ | |
2399 | if (rate_reg && !dai->playback_active && !dai->capture_active) | |
2400 | snd_soc_update_bits(codec, rate_reg, | |
2401 | WM8994_AIF1_SR_MASK | | |
2402 | WM8994_AIF1CLK_RATE_MASK, 0x9); | |
2403 | } | |
2404 | ||
9e6e96a1 MB |
2405 | static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) |
2406 | { | |
2407 | struct snd_soc_codec *codec = codec_dai->codec; | |
2408 | int mute_reg; | |
2409 | int reg; | |
2410 | ||
2411 | switch (codec_dai->id) { | |
2412 | case 1: | |
2413 | mute_reg = WM8994_AIF1_DAC1_FILTERS_1; | |
2414 | break; | |
2415 | case 2: | |
2416 | mute_reg = WM8994_AIF2_DAC_FILTERS_1; | |
2417 | break; | |
2418 | default: | |
2419 | return -EINVAL; | |
2420 | } | |
2421 | ||
2422 | if (mute) | |
2423 | reg = WM8994_AIF1DAC1_MUTE; | |
2424 | else | |
2425 | reg = 0; | |
2426 | ||
2427 | snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); | |
2428 | ||
2429 | return 0; | |
2430 | } | |
2431 | ||
778a76e2 MB |
2432 | static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) |
2433 | { | |
2434 | struct snd_soc_codec *codec = codec_dai->codec; | |
2435 | int reg, val, mask; | |
2436 | ||
2437 | switch (codec_dai->id) { | |
2438 | case 1: | |
2439 | reg = WM8994_AIF1_MASTER_SLAVE; | |
2440 | mask = WM8994_AIF1_TRI; | |
2441 | break; | |
2442 | case 2: | |
2443 | reg = WM8994_AIF2_MASTER_SLAVE; | |
2444 | mask = WM8994_AIF2_TRI; | |
2445 | break; | |
2446 | case 3: | |
2447 | reg = WM8994_POWER_MANAGEMENT_6; | |
2448 | mask = WM8994_AIF3_TRI; | |
2449 | break; | |
2450 | default: | |
2451 | return -EINVAL; | |
2452 | } | |
2453 | ||
2454 | if (tristate) | |
2455 | val = mask; | |
2456 | else | |
2457 | val = 0; | |
2458 | ||
78b3fb46 | 2459 | return snd_soc_update_bits(codec, reg, mask, val); |
778a76e2 MB |
2460 | } |
2461 | ||
9e6e96a1 MB |
2462 | #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 |
2463 | ||
2464 | #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
3079aed5 | 2465 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
9e6e96a1 MB |
2466 | |
2467 | static struct snd_soc_dai_ops wm8994_aif1_dai_ops = { | |
2468 | .set_sysclk = wm8994_set_dai_sysclk, | |
2469 | .set_fmt = wm8994_set_dai_fmt, | |
2470 | .hw_params = wm8994_hw_params, | |
7d02173c | 2471 | .shutdown = wm8994_aif_shutdown, |
9e6e96a1 MB |
2472 | .digital_mute = wm8994_aif_mute, |
2473 | .set_pll = wm8994_set_fll, | |
778a76e2 | 2474 | .set_tristate = wm8994_set_tristate, |
9e6e96a1 MB |
2475 | }; |
2476 | ||
2477 | static struct snd_soc_dai_ops wm8994_aif2_dai_ops = { | |
2478 | .set_sysclk = wm8994_set_dai_sysclk, | |
2479 | .set_fmt = wm8994_set_dai_fmt, | |
2480 | .hw_params = wm8994_hw_params, | |
7d02173c | 2481 | .shutdown = wm8994_aif_shutdown, |
9e6e96a1 MB |
2482 | .digital_mute = wm8994_aif_mute, |
2483 | .set_pll = wm8994_set_fll, | |
778a76e2 MB |
2484 | .set_tristate = wm8994_set_tristate, |
2485 | }; | |
2486 | ||
2487 | static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { | |
c4431df0 | 2488 | .hw_params = wm8994_aif3_hw_params, |
778a76e2 | 2489 | .set_tristate = wm8994_set_tristate, |
9e6e96a1 MB |
2490 | }; |
2491 | ||
f0fba2ad | 2492 | static struct snd_soc_dai_driver wm8994_dai[] = { |
9e6e96a1 | 2493 | { |
f0fba2ad | 2494 | .name = "wm8994-aif1", |
8c7f78b3 | 2495 | .id = 1, |
9e6e96a1 MB |
2496 | .playback = { |
2497 | .stream_name = "AIF1 Playback", | |
b1e43d93 | 2498 | .channels_min = 1, |
9e6e96a1 MB |
2499 | .channels_max = 2, |
2500 | .rates = WM8994_RATES, | |
2501 | .formats = WM8994_FORMATS, | |
2502 | }, | |
2503 | .capture = { | |
2504 | .stream_name = "AIF1 Capture", | |
b1e43d93 | 2505 | .channels_min = 1, |
9e6e96a1 MB |
2506 | .channels_max = 2, |
2507 | .rates = WM8994_RATES, | |
2508 | .formats = WM8994_FORMATS, | |
2509 | }, | |
2510 | .ops = &wm8994_aif1_dai_ops, | |
2511 | }, | |
2512 | { | |
f0fba2ad | 2513 | .name = "wm8994-aif2", |
8c7f78b3 | 2514 | .id = 2, |
9e6e96a1 MB |
2515 | .playback = { |
2516 | .stream_name = "AIF2 Playback", | |
b1e43d93 | 2517 | .channels_min = 1, |
9e6e96a1 MB |
2518 | .channels_max = 2, |
2519 | .rates = WM8994_RATES, | |
2520 | .formats = WM8994_FORMATS, | |
2521 | }, | |
2522 | .capture = { | |
2523 | .stream_name = "AIF2 Capture", | |
b1e43d93 | 2524 | .channels_min = 1, |
9e6e96a1 MB |
2525 | .channels_max = 2, |
2526 | .rates = WM8994_RATES, | |
2527 | .formats = WM8994_FORMATS, | |
2528 | }, | |
2529 | .ops = &wm8994_aif2_dai_ops, | |
2530 | }, | |
2531 | { | |
f0fba2ad | 2532 | .name = "wm8994-aif3", |
8c7f78b3 | 2533 | .id = 3, |
9e6e96a1 MB |
2534 | .playback = { |
2535 | .stream_name = "AIF3 Playback", | |
b1e43d93 | 2536 | .channels_min = 1, |
9e6e96a1 MB |
2537 | .channels_max = 2, |
2538 | .rates = WM8994_RATES, | |
2539 | .formats = WM8994_FORMATS, | |
2540 | }, | |
a8462bde | 2541 | .capture = { |
9e6e96a1 | 2542 | .stream_name = "AIF3 Capture", |
b1e43d93 | 2543 | .channels_min = 1, |
9e6e96a1 MB |
2544 | .channels_max = 2, |
2545 | .rates = WM8994_RATES, | |
2546 | .formats = WM8994_FORMATS, | |
2547 | }, | |
778a76e2 | 2548 | .ops = &wm8994_aif3_dai_ops, |
9e6e96a1 MB |
2549 | } |
2550 | }; | |
9e6e96a1 MB |
2551 | |
2552 | #ifdef CONFIG_PM | |
f0fba2ad | 2553 | static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state) |
9e6e96a1 | 2554 | { |
b2c812e2 | 2555 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
ca629928 | 2556 | struct wm8994 *control = codec->control_data; |
9e6e96a1 MB |
2557 | int i, ret; |
2558 | ||
ca629928 MB |
2559 | switch (control->type) { |
2560 | case WM8994: | |
2561 | snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0); | |
2562 | break; | |
2563 | case WM8958: | |
2564 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, | |
2565 | WM8958_MICD_ENA, 0); | |
2566 | break; | |
2567 | } | |
2568 | ||
9e6e96a1 MB |
2569 | for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { |
2570 | memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], | |
f701a2e5 | 2571 | sizeof(struct wm8994_fll_config)); |
f0fba2ad | 2572 | ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); |
9e6e96a1 MB |
2573 | if (ret < 0) |
2574 | dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", | |
2575 | i + 1, ret); | |
2576 | } | |
2577 | ||
2578 | wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2579 | ||
2580 | return 0; | |
2581 | } | |
2582 | ||
f0fba2ad | 2583 | static int wm8994_resume(struct snd_soc_codec *codec) |
9e6e96a1 | 2584 | { |
b2c812e2 | 2585 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
ca629928 | 2586 | struct wm8994 *control = codec->control_data; |
9e6e96a1 | 2587 | int i, ret; |
c52fd021 DP |
2588 | unsigned int val, mask; |
2589 | ||
2590 | if (wm8994->revision < 4) { | |
2591 | /* force a HW read */ | |
2592 | val = wm8994_reg_read(codec->control_data, | |
2593 | WM8994_POWER_MANAGEMENT_5); | |
2594 | ||
2595 | /* modify the cache only */ | |
2596 | codec->cache_only = 1; | |
2597 | mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA | | |
2598 | WM8994_DAC2R_ENA | WM8994_DAC2L_ENA; | |
2599 | val &= mask; | |
2600 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, | |
2601 | mask, val); | |
2602 | codec->cache_only = 0; | |
2603 | } | |
9e6e96a1 MB |
2604 | |
2605 | /* Restore the registers */ | |
ca9aef50 MB |
2606 | ret = snd_soc_cache_sync(codec); |
2607 | if (ret != 0) | |
2608 | dev_err(codec->dev, "Failed to sync cache: %d\n", ret); | |
9e6e96a1 MB |
2609 | |
2610 | wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2611 | ||
2612 | for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { | |
6a2f1ee1 MB |
2613 | if (!wm8994->fll_suspend[i].out) |
2614 | continue; | |
2615 | ||
f0fba2ad | 2616 | ret = _wm8994_set_fll(codec, i + 1, |
9e6e96a1 MB |
2617 | wm8994->fll_suspend[i].src, |
2618 | wm8994->fll_suspend[i].in, | |
2619 | wm8994->fll_suspend[i].out); | |
2620 | if (ret < 0) | |
2621 | dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", | |
2622 | i + 1, ret); | |
2623 | } | |
2624 | ||
ca629928 MB |
2625 | switch (control->type) { |
2626 | case WM8994: | |
2627 | if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) | |
2628 | snd_soc_update_bits(codec, WM8994_MICBIAS, | |
2629 | WM8994_MICD_ENA, WM8994_MICD_ENA); | |
2630 | break; | |
2631 | case WM8958: | |
2632 | if (wm8994->jack_cb) | |
2633 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, | |
2634 | WM8958_MICD_ENA, WM8958_MICD_ENA); | |
2635 | break; | |
2636 | } | |
2637 | ||
9e6e96a1 MB |
2638 | return 0; |
2639 | } | |
2640 | #else | |
2641 | #define wm8994_suspend NULL | |
2642 | #define wm8994_resume NULL | |
2643 | #endif | |
2644 | ||
2645 | static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) | |
2646 | { | |
f0fba2ad | 2647 | struct snd_soc_codec *codec = wm8994->codec; |
9e6e96a1 MB |
2648 | struct wm8994_pdata *pdata = wm8994->pdata; |
2649 | struct snd_kcontrol_new controls[] = { | |
2650 | SOC_ENUM_EXT("AIF1.1 EQ Mode", | |
2651 | wm8994->retune_mobile_enum, | |
2652 | wm8994_get_retune_mobile_enum, | |
2653 | wm8994_put_retune_mobile_enum), | |
2654 | SOC_ENUM_EXT("AIF1.2 EQ Mode", | |
2655 | wm8994->retune_mobile_enum, | |
2656 | wm8994_get_retune_mobile_enum, | |
2657 | wm8994_put_retune_mobile_enum), | |
2658 | SOC_ENUM_EXT("AIF2 EQ Mode", | |
2659 | wm8994->retune_mobile_enum, | |
2660 | wm8994_get_retune_mobile_enum, | |
2661 | wm8994_put_retune_mobile_enum), | |
2662 | }; | |
2663 | int ret, i, j; | |
2664 | const char **t; | |
2665 | ||
2666 | /* We need an array of texts for the enum API but the number | |
2667 | * of texts is likely to be less than the number of | |
2668 | * configurations due to the sample rate dependency of the | |
2669 | * configurations. */ | |
2670 | wm8994->num_retune_mobile_texts = 0; | |
2671 | wm8994->retune_mobile_texts = NULL; | |
2672 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
2673 | for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { | |
2674 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
2675 | wm8994->retune_mobile_texts[j]) == 0) | |
2676 | break; | |
2677 | } | |
2678 | ||
2679 | if (j != wm8994->num_retune_mobile_texts) | |
2680 | continue; | |
2681 | ||
2682 | /* Expand the array... */ | |
2683 | t = krealloc(wm8994->retune_mobile_texts, | |
2684 | sizeof(char *) * | |
2685 | (wm8994->num_retune_mobile_texts + 1), | |
2686 | GFP_KERNEL); | |
2687 | if (t == NULL) | |
2688 | continue; | |
2689 | ||
2690 | /* ...store the new entry... */ | |
2691 | t[wm8994->num_retune_mobile_texts] = | |
2692 | pdata->retune_mobile_cfgs[i].name; | |
2693 | ||
2694 | /* ...and remember the new version. */ | |
2695 | wm8994->num_retune_mobile_texts++; | |
2696 | wm8994->retune_mobile_texts = t; | |
2697 | } | |
2698 | ||
2699 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
2700 | wm8994->num_retune_mobile_texts); | |
2701 | ||
2702 | wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; | |
2703 | wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; | |
2704 | ||
f0fba2ad | 2705 | ret = snd_soc_add_controls(wm8994->codec, controls, |
9e6e96a1 MB |
2706 | ARRAY_SIZE(controls)); |
2707 | if (ret != 0) | |
f0fba2ad | 2708 | dev_err(wm8994->codec->dev, |
9e6e96a1 MB |
2709 | "Failed to add ReTune Mobile controls: %d\n", ret); |
2710 | } | |
2711 | ||
2712 | static void wm8994_handle_pdata(struct wm8994_priv *wm8994) | |
2713 | { | |
f0fba2ad | 2714 | struct snd_soc_codec *codec = wm8994->codec; |
9e6e96a1 MB |
2715 | struct wm8994_pdata *pdata = wm8994->pdata; |
2716 | int ret, i; | |
2717 | ||
2718 | if (!pdata) | |
2719 | return; | |
2720 | ||
2721 | wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, | |
2722 | pdata->lineout2_diff, | |
2723 | pdata->lineout1fb, | |
2724 | pdata->lineout2fb, | |
2725 | pdata->jd_scthr, | |
2726 | pdata->jd_thr, | |
2727 | pdata->micbias1_lvl, | |
2728 | pdata->micbias2_lvl); | |
2729 | ||
2730 | dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); | |
2731 | ||
2732 | if (pdata->num_drc_cfgs) { | |
2733 | struct snd_kcontrol_new controls[] = { | |
2734 | SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, | |
2735 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
2736 | SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, | |
2737 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
2738 | SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, | |
2739 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
2740 | }; | |
2741 | ||
2742 | /* We need an array of texts for the enum API */ | |
2743 | wm8994->drc_texts = kmalloc(sizeof(char *) | |
2744 | * pdata->num_drc_cfgs, GFP_KERNEL); | |
2745 | if (!wm8994->drc_texts) { | |
f0fba2ad | 2746 | dev_err(wm8994->codec->dev, |
9e6e96a1 MB |
2747 | "Failed to allocate %d DRC config texts\n", |
2748 | pdata->num_drc_cfgs); | |
2749 | return; | |
2750 | } | |
2751 | ||
2752 | for (i = 0; i < pdata->num_drc_cfgs; i++) | |
2753 | wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; | |
2754 | ||
2755 | wm8994->drc_enum.max = pdata->num_drc_cfgs; | |
2756 | wm8994->drc_enum.texts = wm8994->drc_texts; | |
2757 | ||
f0fba2ad | 2758 | ret = snd_soc_add_controls(wm8994->codec, controls, |
9e6e96a1 MB |
2759 | ARRAY_SIZE(controls)); |
2760 | if (ret != 0) | |
f0fba2ad | 2761 | dev_err(wm8994->codec->dev, |
9e6e96a1 MB |
2762 | "Failed to add DRC mode controls: %d\n", ret); |
2763 | ||
2764 | for (i = 0; i < WM8994_NUM_DRC; i++) | |
2765 | wm8994_set_drc(codec, i); | |
2766 | } | |
2767 | ||
2768 | dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", | |
2769 | pdata->num_retune_mobile_cfgs); | |
2770 | ||
2771 | if (pdata->num_retune_mobile_cfgs) | |
2772 | wm8994_handle_retune_mobile_pdata(wm8994); | |
2773 | else | |
f0fba2ad | 2774 | snd_soc_add_controls(wm8994->codec, wm8994_eq_controls, |
9e6e96a1 | 2775 | ARRAY_SIZE(wm8994_eq_controls)); |
48e028ec MB |
2776 | |
2777 | for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { | |
2778 | if (pdata->micbias[i]) { | |
2779 | snd_soc_write(codec, WM8958_MICBIAS1 + i, | |
2780 | pdata->micbias[i] & 0xffff); | |
2781 | } | |
2782 | } | |
9e6e96a1 MB |
2783 | } |
2784 | ||
88766984 MB |
2785 | /** |
2786 | * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ | |
2787 | * | |
2788 | * @codec: WM8994 codec | |
2789 | * @jack: jack to report detection events on | |
2790 | * @micbias: microphone bias to detect on | |
2791 | * @det: value to report for presence detection | |
2792 | * @shrt: value to report for short detection | |
2793 | * | |
2794 | * Enable microphone detection via IRQ on the WM8994. If GPIOs are | |
2795 | * being used to bring out signals to the processor then only platform | |
5ab230a7 | 2796 | * data configuration is needed for WM8994 and processor GPIOs should |
88766984 MB |
2797 | * be configured using snd_soc_jack_add_gpios() instead. |
2798 | * | |
2799 | * Configuration of detection levels is available via the micbias1_lvl | |
2800 | * and micbias2_lvl platform data members. | |
2801 | */ | |
2802 | int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
2803 | int micbias, int det, int shrt) | |
2804 | { | |
b2c812e2 | 2805 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
88766984 | 2806 | struct wm8994_micdet *micdet; |
3a423157 | 2807 | struct wm8994 *control = codec->control_data; |
88766984 MB |
2808 | int reg; |
2809 | ||
3a423157 MB |
2810 | if (control->type != WM8994) |
2811 | return -EINVAL; | |
2812 | ||
88766984 MB |
2813 | switch (micbias) { |
2814 | case 1: | |
2815 | micdet = &wm8994->micdet[0]; | |
2816 | break; | |
2817 | case 2: | |
2818 | micdet = &wm8994->micdet[1]; | |
2819 | break; | |
2820 | default: | |
2821 | return -EINVAL; | |
2822 | } | |
2823 | ||
2824 | dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n", | |
2825 | micbias, det, shrt); | |
2826 | ||
2827 | /* Store the configuration */ | |
2828 | micdet->jack = jack; | |
2829 | micdet->det = det; | |
2830 | micdet->shrt = shrt; | |
2831 | ||
2832 | /* If either of the jacks is set up then enable detection */ | |
2833 | if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) | |
2834 | reg = WM8994_MICD_ENA; | |
2835 | else | |
2836 | reg = 0; | |
2837 | ||
2838 | snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); | |
2839 | ||
2840 | return 0; | |
2841 | } | |
2842 | EXPORT_SYMBOL_GPL(wm8994_mic_detect); | |
2843 | ||
2844 | static irqreturn_t wm8994_mic_irq(int irq, void *data) | |
2845 | { | |
2846 | struct wm8994_priv *priv = data; | |
f0fba2ad | 2847 | struct snd_soc_codec *codec = priv->codec; |
88766984 MB |
2848 | int reg; |
2849 | int report; | |
2850 | ||
7116f452 | 2851 | #ifndef CONFIG_SND_SOC_WM8994_MODULE |
2bbb5d66 | 2852 | trace_snd_soc_jack_irq(dev_name(codec->dev)); |
7116f452 | 2853 | #endif |
2bbb5d66 | 2854 | |
88766984 MB |
2855 | reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); |
2856 | if (reg < 0) { | |
2857 | dev_err(codec->dev, "Failed to read microphone status: %d\n", | |
2858 | reg); | |
2859 | return IRQ_HANDLED; | |
2860 | } | |
2861 | ||
2862 | dev_dbg(codec->dev, "Microphone status: %x\n", reg); | |
2863 | ||
2864 | report = 0; | |
2865 | if (reg & WM8994_MIC1_DET_STS) | |
2866 | report |= priv->micdet[0].det; | |
2867 | if (reg & WM8994_MIC1_SHRT_STS) | |
2868 | report |= priv->micdet[0].shrt; | |
2869 | snd_soc_jack_report(priv->micdet[0].jack, report, | |
2870 | priv->micdet[0].det | priv->micdet[0].shrt); | |
2871 | ||
2872 | report = 0; | |
2873 | if (reg & WM8994_MIC2_DET_STS) | |
2874 | report |= priv->micdet[1].det; | |
2875 | if (reg & WM8994_MIC2_SHRT_STS) | |
2876 | report |= priv->micdet[1].shrt; | |
2877 | snd_soc_jack_report(priv->micdet[1].jack, report, | |
2878 | priv->micdet[1].det | priv->micdet[1].shrt); | |
2879 | ||
2880 | return IRQ_HANDLED; | |
2881 | } | |
2882 | ||
821edd2f MB |
2883 | /* Default microphone detection handler for WM8958 - the user can |
2884 | * override this if they wish. | |
2885 | */ | |
2886 | static void wm8958_default_micdet(u16 status, void *data) | |
2887 | { | |
2888 | struct snd_soc_codec *codec = data; | |
2889 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
2890 | int report = 0; | |
2891 | ||
2892 | /* If nothing present then clear our statuses */ | |
864c4bd2 | 2893 | if (!(status & WM8958_MICD_STS)) |
821edd2f | 2894 | goto done; |
821edd2f | 2895 | |
864c4bd2 | 2896 | report = SND_JACK_MICROPHONE; |
821edd2f MB |
2897 | |
2898 | /* Everything else is buttons; just assign slots */ | |
b35e160a | 2899 | if (status & 0x1c) |
821edd2f | 2900 | report |= SND_JACK_BTN_0; |
821edd2f MB |
2901 | |
2902 | done: | |
406e56c9 | 2903 | snd_soc_jack_report(wm8994->micdet[0].jack, report, |
864c4bd2 | 2904 | SND_JACK_BTN_0 | SND_JACK_MICROPHONE); |
821edd2f MB |
2905 | } |
2906 | ||
2907 | /** | |
2908 | * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ | |
2909 | * | |
2910 | * @codec: WM8958 codec | |
2911 | * @jack: jack to report detection events on | |
2912 | * | |
2913 | * Enable microphone detection functionality for the WM8958. By | |
2914 | * default simple detection which supports the detection of up to 6 | |
2915 | * buttons plus video and microphone functionality is supported. | |
2916 | * | |
2917 | * The WM8958 has an advanced jack detection facility which is able to | |
2918 | * support complex accessory detection, especially when used in | |
2919 | * conjunction with external circuitry. In order to provide maximum | |
2920 | * flexiblity a callback is provided which allows a completely custom | |
2921 | * detection algorithm. | |
2922 | */ | |
2923 | int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
2924 | wm8958_micdet_cb cb, void *cb_data) | |
2925 | { | |
2926 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
2927 | struct wm8994 *control = codec->control_data; | |
2928 | ||
2929 | if (control->type != WM8958) | |
2930 | return -EINVAL; | |
2931 | ||
2932 | if (jack) { | |
2933 | if (!cb) { | |
2934 | dev_dbg(codec->dev, "Using default micdet callback\n"); | |
2935 | cb = wm8958_default_micdet; | |
2936 | cb_data = codec; | |
2937 | } | |
2938 | ||
2939 | wm8994->micdet[0].jack = jack; | |
2940 | wm8994->jack_cb = cb; | |
2941 | wm8994->jack_cb_data = cb_data; | |
2942 | ||
2943 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, | |
2944 | WM8958_MICD_ENA, WM8958_MICD_ENA); | |
2945 | } else { | |
2946 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, | |
2947 | WM8958_MICD_ENA, 0); | |
2948 | } | |
2949 | ||
2950 | return 0; | |
2951 | } | |
2952 | EXPORT_SYMBOL_GPL(wm8958_mic_detect); | |
2953 | ||
2954 | static irqreturn_t wm8958_mic_irq(int irq, void *data) | |
2955 | { | |
2956 | struct wm8994_priv *wm8994 = data; | |
2957 | struct snd_soc_codec *codec = wm8994->codec; | |
2958 | int reg; | |
2959 | ||
2960 | reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); | |
2961 | if (reg < 0) { | |
2962 | dev_err(codec->dev, "Failed to read mic detect status: %d\n", | |
2963 | reg); | |
2964 | return IRQ_NONE; | |
2965 | } | |
2966 | ||
2967 | if (!(reg & WM8958_MICD_VALID)) { | |
2968 | dev_dbg(codec->dev, "Mic detect data not valid\n"); | |
2969 | goto out; | |
2970 | } | |
2971 | ||
7116f452 | 2972 | #ifndef CONFIG_SND_SOC_WM8994_MODULE |
2bbb5d66 | 2973 | trace_snd_soc_jack_irq(dev_name(codec->dev)); |
7116f452 | 2974 | #endif |
2bbb5d66 | 2975 | |
821edd2f MB |
2976 | if (wm8994->jack_cb) |
2977 | wm8994->jack_cb(reg, wm8994->jack_cb_data); | |
2978 | else | |
2979 | dev_warn(codec->dev, "Accessory detection with no callback\n"); | |
2980 | ||
2981 | out: | |
2982 | return IRQ_HANDLED; | |
2983 | } | |
2984 | ||
3b1af3f8 MB |
2985 | static irqreturn_t wm8994_fifo_error(int irq, void *data) |
2986 | { | |
2987 | struct snd_soc_codec *codec = data; | |
2988 | ||
2989 | dev_err(codec->dev, "FIFO error\n"); | |
2990 | ||
2991 | return IRQ_HANDLED; | |
2992 | } | |
2993 | ||
f0fba2ad | 2994 | static int wm8994_codec_probe(struct snd_soc_codec *codec) |
9e6e96a1 | 2995 | { |
3a423157 | 2996 | struct wm8994 *control; |
9e6e96a1 | 2997 | struct wm8994_priv *wm8994; |
ce6120cc | 2998 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
ec62dbd7 | 2999 | int ret, i; |
9e6e96a1 | 3000 | |
f0fba2ad | 3001 | codec->control_data = dev_get_drvdata(codec->dev->parent); |
3a423157 | 3002 | control = codec->control_data; |
9e6e96a1 MB |
3003 | |
3004 | wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); | |
f0fba2ad | 3005 | if (wm8994 == NULL) |
9e6e96a1 | 3006 | return -ENOMEM; |
b2c812e2 | 3007 | snd_soc_codec_set_drvdata(codec, wm8994); |
f0fba2ad LG |
3008 | |
3009 | wm8994->pdata = dev_get_platdata(codec->dev->parent); | |
3010 | wm8994->codec = codec; | |
9e6e96a1 | 3011 | |
c7ebf932 MB |
3012 | for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) |
3013 | init_completion(&wm8994->fll_locked[i]); | |
3014 | ||
9b7c525d MB |
3015 | if (wm8994->pdata && wm8994->pdata->micdet_irq) |
3016 | wm8994->micdet_irq = wm8994->pdata->micdet_irq; | |
3017 | else if (wm8994->pdata && wm8994->pdata->irq_base) | |
3018 | wm8994->micdet_irq = wm8994->pdata->irq_base + | |
3019 | WM8994_IRQ_MIC1_DET; | |
3020 | ||
39fb51a1 MB |
3021 | pm_runtime_enable(codec->dev); |
3022 | pm_runtime_resume(codec->dev); | |
3023 | ||
ca9aef50 MB |
3024 | /* Read our current status back from the chip - we don't want to |
3025 | * reset as this may interfere with the GPIO or LDO operation. */ | |
3026 | for (i = 0; i < WM8994_CACHE_SIZE; i++) { | |
d4754ec9 | 3027 | if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i)) |
ca9aef50 | 3028 | continue; |
9e6e96a1 | 3029 | |
ca9aef50 MB |
3030 | ret = wm8994_reg_read(codec->control_data, i); |
3031 | if (ret <= 0) | |
3032 | continue; | |
3033 | ||
3034 | ret = snd_soc_cache_write(codec, i, ret); | |
3035 | if (ret != 0) { | |
3036 | dev_err(codec->dev, | |
3037 | "Failed to initialise cache for 0x%x: %d\n", | |
3038 | i, ret); | |
3039 | goto err; | |
3040 | } | |
3041 | } | |
9e6e96a1 MB |
3042 | |
3043 | /* Set revision-specific configuration */ | |
b6b05691 | 3044 | wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); |
3a423157 MB |
3045 | switch (control->type) { |
3046 | case WM8994: | |
3047 | switch (wm8994->revision) { | |
3048 | case 2: | |
3049 | case 3: | |
4537c4e7 MB |
3050 | wm8994->hubs.dcs_codes_l = -5; |
3051 | wm8994->hubs.dcs_codes_r = -5; | |
3a423157 MB |
3052 | wm8994->hubs.hp_startup_mode = 1; |
3053 | wm8994->hubs.dcs_readback_mode = 1; | |
f9acf9fe | 3054 | wm8994->hubs.series_startup = 1; |
3a423157 MB |
3055 | break; |
3056 | default: | |
79ef0abc | 3057 | wm8994->hubs.dcs_readback_mode = 2; |
3a423157 MB |
3058 | break; |
3059 | } | |
280ec8b7 | 3060 | break; |
3a423157 MB |
3061 | |
3062 | case WM8958: | |
8437f700 | 3063 | wm8994->hubs.dcs_readback_mode = 1; |
9e6e96a1 | 3064 | break; |
3a423157 | 3065 | |
9e6e96a1 MB |
3066 | default: |
3067 | break; | |
3068 | } | |
9e6e96a1 | 3069 | |
3b1af3f8 MB |
3070 | wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, |
3071 | wm8994_fifo_error, "FIFO error", codec); | |
3072 | ||
b30ead5f MB |
3073 | ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE, |
3074 | wm_hubs_dcs_done, "DC servo done", | |
3075 | &wm8994->hubs); | |
3076 | if (ret == 0) | |
3077 | wm8994->hubs.dcs_done_irq = true; | |
3078 | ||
3a423157 MB |
3079 | switch (control->type) { |
3080 | case WM8994: | |
9b7c525d MB |
3081 | if (wm8994->micdet_irq) { |
3082 | ret = request_threaded_irq(wm8994->micdet_irq, NULL, | |
3083 | wm8994_mic_irq, | |
3084 | IRQF_TRIGGER_RISING, | |
3085 | "Mic1 detect", | |
3086 | wm8994); | |
3087 | if (ret != 0) | |
3088 | dev_warn(codec->dev, | |
3089 | "Failed to request Mic1 detect IRQ: %d\n", | |
3090 | ret); | |
3091 | } | |
3a423157 MB |
3092 | |
3093 | ret = wm8994_request_irq(codec->control_data, | |
3094 | WM8994_IRQ_MIC1_SHRT, | |
3095 | wm8994_mic_irq, "Mic 1 short", | |
3096 | wm8994); | |
3097 | if (ret != 0) | |
3098 | dev_warn(codec->dev, | |
3099 | "Failed to request Mic1 short IRQ: %d\n", | |
3100 | ret); | |
3101 | ||
3102 | ret = wm8994_request_irq(codec->control_data, | |
3103 | WM8994_IRQ_MIC2_DET, | |
3104 | wm8994_mic_irq, "Mic 2 detect", | |
3105 | wm8994); | |
3106 | if (ret != 0) | |
3107 | dev_warn(codec->dev, | |
3108 | "Failed to request Mic2 detect IRQ: %d\n", | |
3109 | ret); | |
3110 | ||
3111 | ret = wm8994_request_irq(codec->control_data, | |
3112 | WM8994_IRQ_MIC2_SHRT, | |
3113 | wm8994_mic_irq, "Mic 2 short", | |
3114 | wm8994); | |
3115 | if (ret != 0) | |
3116 | dev_warn(codec->dev, | |
3117 | "Failed to request Mic2 short IRQ: %d\n", | |
3118 | ret); | |
3119 | break; | |
821edd2f MB |
3120 | |
3121 | case WM8958: | |
9b7c525d MB |
3122 | if (wm8994->micdet_irq) { |
3123 | ret = request_threaded_irq(wm8994->micdet_irq, NULL, | |
3124 | wm8958_mic_irq, | |
3125 | IRQF_TRIGGER_RISING, | |
3126 | "Mic detect", | |
3127 | wm8994); | |
3128 | if (ret != 0) | |
3129 | dev_warn(codec->dev, | |
3130 | "Failed to request Mic detect IRQ: %d\n", | |
3131 | ret); | |
3132 | } | |
3a423157 | 3133 | } |
88766984 | 3134 | |
c7ebf932 MB |
3135 | wm8994->fll_locked_irq = true; |
3136 | for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { | |
3137 | ret = wm8994_request_irq(codec->control_data, | |
3138 | WM8994_IRQ_FLL1_LOCK + i, | |
3139 | wm8994_fll_locked_irq, "FLL lock", | |
3140 | &wm8994->fll_locked[i]); | |
3141 | if (ret != 0) | |
3142 | wm8994->fll_locked_irq = false; | |
3143 | } | |
3144 | ||
9e6e96a1 MB |
3145 | /* Remember if AIFnLRCLK is configured as a GPIO. This should be |
3146 | * configured on init - if a system wants to do this dynamically | |
3147 | * at runtime we can deal with that then. | |
3148 | */ | |
3149 | ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1); | |
3150 | if (ret < 0) { | |
3151 | dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); | |
88766984 | 3152 | goto err_irq; |
9e6e96a1 MB |
3153 | } |
3154 | if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { | |
3155 | wm8994->lrclk_shared[0] = 1; | |
3156 | wm8994_dai[0].symmetric_rates = 1; | |
3157 | } else { | |
3158 | wm8994->lrclk_shared[0] = 0; | |
3159 | } | |
3160 | ||
3161 | ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6); | |
3162 | if (ret < 0) { | |
3163 | dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); | |
88766984 | 3164 | goto err_irq; |
9e6e96a1 MB |
3165 | } |
3166 | if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { | |
3167 | wm8994->lrclk_shared[1] = 1; | |
3168 | wm8994_dai[1].symmetric_rates = 1; | |
3169 | } else { | |
3170 | wm8994->lrclk_shared[1] = 0; | |
3171 | } | |
3172 | ||
9e6e96a1 MB |
3173 | wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
3174 | ||
9e6e96a1 | 3175 | /* Latch volume updates (right only; we always do left then right). */ |
baa81603 MB |
3176 | snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME, |
3177 | WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); | |
9e6e96a1 MB |
3178 | snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME, |
3179 | WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); | |
baa81603 MB |
3180 | snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME, |
3181 | WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); | |
9e6e96a1 MB |
3182 | snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME, |
3183 | WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); | |
baa81603 MB |
3184 | snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME, |
3185 | WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); | |
9e6e96a1 MB |
3186 | snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME, |
3187 | WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); | |
baa81603 MB |
3188 | snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME, |
3189 | WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); | |
9e6e96a1 MB |
3190 | snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME, |
3191 | WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); | |
baa81603 MB |
3192 | snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME, |
3193 | WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); | |
9e6e96a1 MB |
3194 | snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME, |
3195 | WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); | |
baa81603 MB |
3196 | snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME, |
3197 | WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); | |
9e6e96a1 MB |
3198 | snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME, |
3199 | WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); | |
baa81603 MB |
3200 | snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME, |
3201 | WM8994_DAC1_VU, WM8994_DAC1_VU); | |
9e6e96a1 MB |
3202 | snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME, |
3203 | WM8994_DAC1_VU, WM8994_DAC1_VU); | |
baa81603 MB |
3204 | snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME, |
3205 | WM8994_DAC2_VU, WM8994_DAC2_VU); | |
9e6e96a1 MB |
3206 | snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME, |
3207 | WM8994_DAC2_VU, WM8994_DAC2_VU); | |
3208 | ||
3209 | /* Set the low bit of the 3D stereo depth so TLV matches */ | |
3210 | snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, | |
3211 | 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, | |
3212 | 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); | |
3213 | snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, | |
3214 | 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, | |
3215 | 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); | |
3216 | snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, | |
3217 | 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, | |
3218 | 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); | |
3219 | ||
5b739670 MB |
3220 | /* Unconditionally enable AIF1 ADC TDM mode on chips which can |
3221 | * use this; it only affects behaviour on idle TDM clock | |
3222 | * cycles. */ | |
3223 | switch (control->type) { | |
3224 | case WM8994: | |
3225 | case WM8958: | |
3226 | snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, | |
3227 | WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); | |
3228 | break; | |
3229 | default: | |
3230 | break; | |
3231 | } | |
d1ce6b20 | 3232 | |
9e6e96a1 MB |
3233 | wm8994_update_class_w(codec); |
3234 | ||
f0fba2ad | 3235 | wm8994_handle_pdata(wm8994); |
9e6e96a1 | 3236 | |
f0fba2ad LG |
3237 | wm_hubs_add_analogue_controls(codec); |
3238 | snd_soc_add_controls(codec, wm8994_snd_controls, | |
3239 | ARRAY_SIZE(wm8994_snd_controls)); | |
ce6120cc | 3240 | snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, |
f0fba2ad | 3241 | ARRAY_SIZE(wm8994_dapm_widgets)); |
c4431df0 MB |
3242 | |
3243 | switch (control->type) { | |
3244 | case WM8994: | |
3245 | snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, | |
3246 | ARRAY_SIZE(wm8994_specific_dapm_widgets)); | |
c52fd021 | 3247 | if (wm8994->revision < 4) { |
173efa09 DP |
3248 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, |
3249 | ARRAY_SIZE(wm8994_lateclk_revd_widgets)); | |
04d28681 DP |
3250 | snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, |
3251 | ARRAY_SIZE(wm8994_adc_revd_widgets)); | |
c52fd021 DP |
3252 | snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, |
3253 | ARRAY_SIZE(wm8994_dac_revd_widgets)); | |
3254 | } else { | |
173efa09 DP |
3255 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, |
3256 | ARRAY_SIZE(wm8994_lateclk_widgets)); | |
04d28681 DP |
3257 | snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, |
3258 | ARRAY_SIZE(wm8994_adc_widgets)); | |
c52fd021 DP |
3259 | snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, |
3260 | ARRAY_SIZE(wm8994_dac_widgets)); | |
3261 | } | |
c4431df0 MB |
3262 | break; |
3263 | case WM8958: | |
3264 | snd_soc_add_controls(codec, wm8958_snd_controls, | |
3265 | ARRAY_SIZE(wm8958_snd_controls)); | |
3266 | snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, | |
3267 | ARRAY_SIZE(wm8958_dapm_widgets)); | |
780e2806 MB |
3268 | if (wm8994->revision < 1) { |
3269 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, | |
3270 | ARRAY_SIZE(wm8994_lateclk_revd_widgets)); | |
3271 | snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, | |
3272 | ARRAY_SIZE(wm8994_adc_revd_widgets)); | |
3273 | snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, | |
3274 | ARRAY_SIZE(wm8994_dac_revd_widgets)); | |
3275 | } else { | |
3276 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, | |
3277 | ARRAY_SIZE(wm8994_lateclk_widgets)); | |
3278 | snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, | |
3279 | ARRAY_SIZE(wm8994_adc_widgets)); | |
3280 | snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, | |
3281 | ARRAY_SIZE(wm8994_dac_widgets)); | |
3282 | } | |
c4431df0 MB |
3283 | break; |
3284 | } | |
3285 | ||
3286 | ||
f0fba2ad | 3287 | wm_hubs_add_analogue_routes(codec, 0, 0); |
ce6120cc | 3288 | snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); |
9e6e96a1 | 3289 | |
c4431df0 MB |
3290 | switch (control->type) { |
3291 | case WM8994: | |
3292 | snd_soc_dapm_add_routes(dapm, wm8994_intercon, | |
3293 | ARRAY_SIZE(wm8994_intercon)); | |
6ed8f148 | 3294 | |
173efa09 | 3295 | if (wm8994->revision < 4) { |
6ed8f148 MB |
3296 | snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, |
3297 | ARRAY_SIZE(wm8994_revd_intercon)); | |
173efa09 DP |
3298 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, |
3299 | ARRAY_SIZE(wm8994_lateclk_revd_intercon)); | |
3300 | } else { | |
3301 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, | |
3302 | ARRAY_SIZE(wm8994_lateclk_intercon)); | |
3303 | } | |
c4431df0 MB |
3304 | break; |
3305 | case WM8958: | |
780e2806 MB |
3306 | if (wm8994->revision < 1) { |
3307 | snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, | |
3308 | ARRAY_SIZE(wm8994_revd_intercon)); | |
3309 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, | |
3310 | ARRAY_SIZE(wm8994_lateclk_revd_intercon)); | |
3311 | } else { | |
3312 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, | |
3313 | ARRAY_SIZE(wm8994_lateclk_intercon)); | |
3314 | snd_soc_dapm_add_routes(dapm, wm8958_intercon, | |
3315 | ARRAY_SIZE(wm8958_intercon)); | |
3316 | } | |
f701a2e5 MB |
3317 | |
3318 | wm8958_dsp2_init(codec); | |
c4431df0 MB |
3319 | break; |
3320 | } | |
3321 | ||
9e6e96a1 MB |
3322 | return 0; |
3323 | ||
88766984 MB |
3324 | err_irq: |
3325 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); | |
3326 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); | |
3327 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); | |
9b7c525d MB |
3328 | if (wm8994->micdet_irq) |
3329 | free_irq(wm8994->micdet_irq, wm8994); | |
c7ebf932 MB |
3330 | for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) |
3331 | wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i, | |
3332 | &wm8994->fll_locked[i]); | |
b30ead5f MB |
3333 | wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE, |
3334 | &wm8994->hubs); | |
3b1af3f8 | 3335 | wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec); |
9e6e96a1 MB |
3336 | err: |
3337 | kfree(wm8994); | |
3338 | return ret; | |
3339 | } | |
3340 | ||
f0fba2ad | 3341 | static int wm8994_codec_remove(struct snd_soc_codec *codec) |
9e6e96a1 | 3342 | { |
f0fba2ad | 3343 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
3a423157 | 3344 | struct wm8994 *control = codec->control_data; |
c7ebf932 | 3345 | int i; |
9e6e96a1 MB |
3346 | |
3347 | wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
f0fba2ad | 3348 | |
39fb51a1 MB |
3349 | pm_runtime_disable(codec->dev); |
3350 | ||
c7ebf932 MB |
3351 | for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) |
3352 | wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i, | |
3353 | &wm8994->fll_locked[i]); | |
3354 | ||
b30ead5f MB |
3355 | wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE, |
3356 | &wm8994->hubs); | |
3b1af3f8 | 3357 | wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec); |
b30ead5f | 3358 | |
3a423157 MB |
3359 | switch (control->type) { |
3360 | case WM8994: | |
9b7c525d MB |
3361 | if (wm8994->micdet_irq) |
3362 | free_irq(wm8994->micdet_irq, wm8994); | |
3a423157 MB |
3363 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, |
3364 | wm8994); | |
3365 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, | |
3366 | wm8994); | |
3367 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, | |
3368 | wm8994); | |
3369 | break; | |
821edd2f MB |
3370 | |
3371 | case WM8958: | |
9b7c525d MB |
3372 | if (wm8994->micdet_irq) |
3373 | free_irq(wm8994->micdet_irq, wm8994); | |
821edd2f | 3374 | break; |
3a423157 | 3375 | } |
fbbf5920 MB |
3376 | if (wm8994->mbc) |
3377 | release_firmware(wm8994->mbc); | |
09e10d7f MB |
3378 | if (wm8994->mbc_vss) |
3379 | release_firmware(wm8994->mbc_vss); | |
31215871 MB |
3380 | if (wm8994->enh_eq) |
3381 | release_firmware(wm8994->enh_eq); | |
24fb2b11 AL |
3382 | kfree(wm8994->retune_mobile_texts); |
3383 | kfree(wm8994->drc_texts); | |
9e6e96a1 | 3384 | kfree(wm8994); |
9e6e96a1 MB |
3385 | |
3386 | return 0; | |
3387 | } | |
3388 | ||
f0fba2ad LG |
3389 | static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { |
3390 | .probe = wm8994_codec_probe, | |
3391 | .remove = wm8994_codec_remove, | |
3392 | .suspend = wm8994_suspend, | |
3393 | .resume = wm8994_resume, | |
ca9aef50 MB |
3394 | .read = wm8994_read, |
3395 | .write = wm8994_write, | |
eba19fdd MB |
3396 | .readable_register = wm8994_readable, |
3397 | .volatile_register = wm8994_volatile, | |
f0fba2ad | 3398 | .set_bias_level = wm8994_set_bias_level, |
ca9aef50 MB |
3399 | |
3400 | .reg_cache_size = WM8994_CACHE_SIZE, | |
3401 | .reg_cache_default = wm8994_reg_defaults, | |
3402 | .reg_word_size = 2, | |
2e19b0c8 | 3403 | .compress_type = SND_SOC_RBTREE_COMPRESSION, |
f0fba2ad LG |
3404 | }; |
3405 | ||
3406 | static int __devinit wm8994_probe(struct platform_device *pdev) | |
3407 | { | |
3408 | return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, | |
3409 | wm8994_dai, ARRAY_SIZE(wm8994_dai)); | |
3410 | } | |
3411 | ||
3412 | static int __devexit wm8994_remove(struct platform_device *pdev) | |
3413 | { | |
3414 | snd_soc_unregister_codec(&pdev->dev); | |
3415 | return 0; | |
3416 | } | |
3417 | ||
9e6e96a1 MB |
3418 | static struct platform_driver wm8994_codec_driver = { |
3419 | .driver = { | |
3420 | .name = "wm8994-codec", | |
3421 | .owner = THIS_MODULE, | |
3422 | }, | |
f0fba2ad LG |
3423 | .probe = wm8994_probe, |
3424 | .remove = __devexit_p(wm8994_remove), | |
9e6e96a1 MB |
3425 | }; |
3426 | ||
3427 | static __init int wm8994_init(void) | |
3428 | { | |
3429 | return platform_driver_register(&wm8994_codec_driver); | |
3430 | } | |
3431 | module_init(wm8994_init); | |
3432 | ||
3433 | static __exit void wm8994_exit(void) | |
3434 | { | |
3435 | platform_driver_unregister(&wm8994_codec_driver); | |
3436 | } | |
3437 | module_exit(wm8994_exit); | |
3438 | ||
3439 | ||
3440 | MODULE_DESCRIPTION("ASoC WM8994 driver"); | |
3441 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
3442 | MODULE_LICENSE("GPL"); | |
3443 | MODULE_ALIAS("platform:wm8994-codec"); |