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ASoC: wm8994: Use the same DCS codes for all WM1811 variants
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
9e6e96a1
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
bfd37bb5
MB		 49static struct {
50 unsigned int reg;
51 unsigned int mask;
52} wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80};
81
9e6e96a1
MB		 82static int wm8994_drc_base[] = {
83 WM8994_AIF1_DRC1_1,
84 WM8994_AIF1_DRC2_1,
85 WM8994_AIF2_DRC_1,
86};
87
88static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
92};
93
b00adf76
MB		 94static void wm8958_default_micdet(u16 status, void *data);
95
af6b6fe4 96static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 97 { 32768, true, 1, 4 },
98 { 32768, false, 1, 1 },
604533de
MB		 99 { 44100 * 256, true, 7, 10 },
100 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 101};
102
af6b6fe4
MB		 103static const struct wm8958_micd_rate jackdet_rates[] = {
104 { 32768, true, 0, 1 },
105 { 32768, false, 0, 1 },
e9d9a968
MB		 106 { 44100 * 256, true, 10, 10 },
107 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 108};
109
b00adf76
MB		 110static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
111{
112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada 113 struct wm8994 *control = wm8994->wm8994;
b00adf76
MB		 114 int best, i, sysclk, val;
115 bool idle;
af6b6fe4
MB		 116 const struct wm8958_micd_rate *rates;
117 int num_rates;
b00adf76 118
d9dd4ada 119 if (wm8994->jack_cb != wm8958_default_micdet)
b00adf76
MB		 120 return;
121
122 idle = !wm8994->jack_mic;
123
124 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
125 if (sysclk & WM8994_SYSCLK_SRC)
126 sysclk = wm8994->aifclk[1];
127 else
128 sysclk = wm8994->aifclk[0];
129
d9dd4ada
MB		 130 if (control->pdata.micd_rates) {
131 rates = control->pdata.micd_rates;
132 num_rates = control->pdata.num_micd_rates;
cd1707a9 133 } else if (wm8994->jackdet) {
af6b6fe4
MB		 134 rates = jackdet_rates;
135 num_rates = ARRAY_SIZE(jackdet_rates);
136 } else {
137 rates = micdet_rates;
138 num_rates = ARRAY_SIZE(micdet_rates);
139 }
140
b00adf76 141 best = 0;
af6b6fe4
MB		 142 for (i = 0; i < num_rates; i++) {
143 if (rates[i].idle != idle)
b00adf76 144 continue;
af6b6fe4
MB		 145 if (abs(rates[i].sysclk - sysclk) <
146 abs(rates[best].sysclk - sysclk))
b00adf76 147 best = i;
af6b6fe4 148 else if (rates[best].idle != idle)
b00adf76
MB		 149 best = i;
150 }
151
af6b6fe4
MB		 152 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
153 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 154
3a334ada
MB		 155 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
156 rates[best].start, rates[best].rate, sysclk,
157 idle ? "idle" : "active");
158
b00adf76
MB		 159 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
160 WM8958_MICD_BIAS_STARTTIME_MASK |
161 WM8958_MICD_RATE_MASK, val);
162}
163
9e6e96a1
MB		 164static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
165{
b2c812e2 166 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 167 int rate;
168 int reg1 = 0;
169 int offset;
170
171 if (aif)
172 offset = 4;
173 else
174 offset = 0;
175
176 switch (wm8994->sysclk[aif]) {
177 case WM8994_SYSCLK_MCLK1:
178 rate = wm8994->mclk[0];
179 break;
180
181 case WM8994_SYSCLK_MCLK2:
182 reg1 |= 0x8;
183 rate = wm8994->mclk[1];
184 break;
185
186 case WM8994_SYSCLK_FLL1:
187 reg1 |= 0x10;
188 rate = wm8994->fll[0].out;
189 break;
190
191 case WM8994_SYSCLK_FLL2:
192 reg1 |= 0x18;
193 rate = wm8994->fll[1].out;
194 break;
195
196 default:
197 return -EINVAL;
198 }
199
200 if (rate >= 13500000) {
201 rate /= 2;
202 reg1 |= WM8994_AIF1CLK_DIV;
203
204 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
205 aif + 1, rate);
206 }
5e5e2bef 207
9e6e96a1
MB		 208 wm8994->aifclk[aif] = rate;
209
210 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
211 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
212 reg1);
213
214 return 0;
215}
216
217static int configure_clock(struct snd_soc_codec *codec)
218{
b2c812e2 219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 220 int change, new;
9e6e96a1
MB		 221
222 /* Bring up the AIF clocks first */
223 configure_aif_clock(codec, 0);
224 configure_aif_clock(codec, 1);
225
226 /* Then switch CLK_SYS over to the higher of them; a change
227 * can only happen as a result of a clocking change which can
228 * only be made outside of DAPM so we can safely redo the
229 * clocking.
230 */
231
232 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 233 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
234 wm8958_micd_set_rate(codec);
9e6e96a1 235 return 0;
b00adf76 236 }
9e6e96a1
MB		 237
238 if (wm8994->aifclk[0] < wm8994->aifclk[1])
239 new = WM8994_SYSCLK_SRC;
240 else
241 new = 0;
242
04f45c49
AL		 243 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
244 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 245 if (change)
246 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 247
b00adf76
MB		 248 wm8958_micd_set_rate(codec);
249
9e6e96a1
MB		 250 return 0;
251}
252
253static int check_clk_sys(struct snd_soc_dapm_widget *source,
254 struct snd_soc_dapm_widget *sink)
255{
256 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
257 const char *clk;
258
259 /* Check what we're currently using for CLK_SYS */
260 if (reg & WM8994_SYSCLK_SRC)
261 clk = "AIF2CLK";
262 else
263 clk = "AIF1CLK";
264
265 return strcmp(source->name, clk) == 0;
266}
267
268static const char *sidetone_hpf_text[] = {
269 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
270};
271
272static const struct soc_enum sidetone_hpf =
273 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
274
146fd574
UK		 275static const char *adc_hpf_text[] = {
276 "HiFi", "Voice 1", "Voice 2", "Voice 3"
277};
278
279static const struct soc_enum aif1adc1_hpf =
280 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
281
282static const struct soc_enum aif1adc2_hpf =
283 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
284
285static const struct soc_enum aif2adc_hpf =
286 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
287
9e6e96a1
MB		 288static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
289static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
290static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
291static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
292static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 293static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 294static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 295
296#define WM8994_DRC_SWITCH(xname, reg, shift) \
297{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
298 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
299 .put = wm8994_put_drc_sw, \
300 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
301
302static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
303 struct snd_ctl_elem_value *ucontrol)
304{
305 struct soc_mixer_control *mc =
306 (struct soc_mixer_control *)kcontrol->private_value;
307 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
308 int mask, ret;
309
310 /* Can't enable both ADC and DAC paths simultaneously */
311 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
312 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
313 WM8994_AIF1ADC1R_DRC_ENA_MASK;
314 else
315 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
316
317 ret = snd_soc_read(codec, mc->reg);
318 if (ret < 0)
319 return ret;
320 if (ret & mask)
321 return -EINVAL;
322
323 return snd_soc_put_volsw(kcontrol, ucontrol);
324}
325
9e6e96a1
MB		 326static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
327{
b2c812e2 328 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 329 struct wm8994 *control = wm8994->wm8994;
330 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 331 int base = wm8994_drc_base[drc];
332 int cfg = wm8994->drc_cfg[drc];
333 int save, i;
334
335 /* Save any enables; the configuration should clear them. */
336 save = snd_soc_read(codec, base);
337 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
338 WM8994_AIF1ADC1R_DRC_ENA;
339
340 for (i = 0; i < WM8994_DRC_REGS; i++)
341 snd_soc_update_bits(codec, base + i, 0xffff,
342 pdata->drc_cfgs[cfg].regs[i]);
343
344 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
345 WM8994_AIF1ADC1L_DRC_ENA |
346 WM8994_AIF1ADC1R_DRC_ENA, save);
347}
348
349/* Icky as hell but saves code duplication */
350static int wm8994_get_drc(const char *name)
351{
352 if (strcmp(name, "AIF1DRC1 Mode") == 0)
353 return 0;
354 if (strcmp(name, "AIF1DRC2 Mode") == 0)
355 return 1;
356 if (strcmp(name, "AIF2DRC Mode") == 0)
357 return 2;
358 return -EINVAL;
359}
360
361static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_value *ucontrol)
363{
364 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 365 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 366 struct wm8994 *control = wm8994->wm8994;
367 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 368 int drc = wm8994_get_drc(kcontrol->id.name);
369 int value = ucontrol->value.integer.value[0];
370
371 if (drc < 0)
372 return drc;
373
374 if (value >= pdata->num_drc_cfgs)
375 return -EINVAL;
376
377 wm8994->drc_cfg[drc] = value;
378
379 wm8994_set_drc(codec, drc);
380
381 return 0;
382}
383
384static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
385 struct snd_ctl_elem_value *ucontrol)
386{
387 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 388 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 389 int drc = wm8994_get_drc(kcontrol->id.name);
390
391 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
392
393 return 0;
394}
395
396static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
397{
b2c812e2 398 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 399 struct wm8994 *control = wm8994->wm8994;
400 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 401 int base = wm8994_retune_mobile_base[block];
402 int iface, best, best_val, save, i, cfg;
403
404 if (!pdata || !wm8994->num_retune_mobile_texts)
405 return;
406
407 switch (block) {
408 case 0:
409 case 1:
410 iface = 0;
411 break;
412 case 2:
413 iface = 1;
414 break;
415 default:
416 return;
417 }
418
419 /* Find the version of the currently selected configuration
420 * with the nearest sample rate. */
421 cfg = wm8994->retune_mobile_cfg[block];
422 best = 0;
423 best_val = INT_MAX;
424 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
425 if (strcmp(pdata->retune_mobile_cfgs[i].name,
426 wm8994->retune_mobile_texts[cfg]) == 0 &&
427 abs(pdata->retune_mobile_cfgs[i].rate
428 - wm8994->dac_rates[iface]) < best_val) {
429 best = i;
430 best_val = abs(pdata->retune_mobile_cfgs[i].rate
431 - wm8994->dac_rates[iface]);
432 }
433 }
434
435 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
436 block,
437 pdata->retune_mobile_cfgs[best].name,
438 pdata->retune_mobile_cfgs[best].rate,
439 wm8994->dac_rates[iface]);
440
441 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 442 * current configuration.
9e6e96a1
MB		 443 */
444 save = snd_soc_read(codec, base);
445 save &= WM8994_AIF1DAC1_EQ_ENA;
446
447 for (i = 0; i < WM8994_EQ_REGS; i++)
448 snd_soc_update_bits(codec, base + i, 0xffff,
449 pdata->retune_mobile_cfgs[best].regs[i]);
450
451 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
452}
453
454/* Icky as hell but saves code duplication */
455static int wm8994_get_retune_mobile_block(const char *name)
456{
457 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
458 return 0;
459 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
460 return 1;
461 if (strcmp(name, "AIF2 EQ Mode") == 0)
462 return 2;
463 return -EINVAL;
464}
465
466static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
467 struct snd_ctl_elem_value *ucontrol)
468{
469 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 470 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 471 struct wm8994 *control = wm8994->wm8994;
472 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 473 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
474 int value = ucontrol->value.integer.value[0];
475
476 if (block < 0)
477 return block;
478
479 if (value >= pdata->num_retune_mobile_cfgs)
480 return -EINVAL;
481
482 wm8994->retune_mobile_cfg[block] = value;
483
484 wm8994_set_retune_mobile(codec, block);
485
486 return 0;
487}
488
489static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
490 struct snd_ctl_elem_value *ucontrol)
491{
492 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 493 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 494 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
495
496 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
497
498 return 0;
499}
500
96b101ef 501static const char *aif_chan_src_text[] = {
f554885f
MB		 502 "Left", "Right"
503};
504
96b101ef
MB		 505static const struct soc_enum aif1adcl_src =
506 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
507
508static const struct soc_enum aif1adcr_src =
509 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
510
511static const struct soc_enum aif2adcl_src =
512 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
513
514static const struct soc_enum aif2adcr_src =
515 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
516
f554885f 517static const struct soc_enum aif1dacl_src =
96b101ef 518 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 519
520static const struct soc_enum aif1dacr_src =
96b101ef 521 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 522
523static const struct soc_enum aif2dacl_src =
96b101ef 524 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 525
526static const struct soc_enum aif2dacr_src =
96b101ef 527 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 528
154b26aa
MB		 529static const char *osr_text[] = {
530 "Low Power", "High Performance",
531};
532
533static const struct soc_enum dac_osr =
534 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
535
536static const struct soc_enum adc_osr =
537 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
538
9e6e96a1
MB		 539static const struct snd_kcontrol_new wm8994_snd_controls[] = {
540SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
541 WM8994_AIF1_ADC1_RIGHT_VOLUME,
542 1, 119, 0, digital_tlv),
543SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
544 WM8994_AIF1_ADC2_RIGHT_VOLUME,
545 1, 119, 0, digital_tlv),
546SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
547 WM8994_AIF2_ADC_RIGHT_VOLUME,
548 1, 119, 0, digital_tlv),
549
96b101ef
MB		 550SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
551SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 552SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
553SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 554
f554885f
MB		 555SOC_ENUM("AIF1DACL Source", aif1dacl_src),
556SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 557SOC_ENUM("AIF2DACL Source", aif2dacl_src),
558SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 559
9e6e96a1
MB		 560SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
561 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
563 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
564SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
565 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
566
567SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
568SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
569
570SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
571SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
572SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
573
574WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
575WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
576WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
577
578WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
579WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
580WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
581
582WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
583WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
584WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
585
586SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
591 5, 12, 0, st_tlv),
592SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
593 0, 12, 0, st_tlv),
594SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
595SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
596
146fd574
UK		 597SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
598SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
599
600SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
601SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
602
603SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
604SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
605
154b26aa
MB		 606SOC_ENUM("ADC OSR", adc_osr),
607SOC_ENUM("DAC OSR", dac_osr),
608
9e6e96a1
MB		 609SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
610 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
611SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
612 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
613
614SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
615 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
616SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
617 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
618
619SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
620 6, 1, 1, wm_hubs_spkmix_tlv),
621SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
622 2, 1, 1, wm_hubs_spkmix_tlv),
623
624SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
625 6, 1, 1, wm_hubs_spkmix_tlv),
626SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
627 2, 1, 1, wm_hubs_spkmix_tlv),
628
629SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
458350b3 631SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 632 8, 1, 0),
633SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
634 10, 15, 0, wm8994_3d_tlv),
635SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
636 8, 1, 0),
458350b3 637SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 638 10, 15, 0, wm8994_3d_tlv),
458350b3 639SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 640 8, 1, 0),
641};
642
643static const struct snd_kcontrol_new wm8994_eq_controls[] = {
644SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
649 eq_tlv),
650SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
651 eq_tlv),
652SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
653 eq_tlv),
654
655SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
660 eq_tlv),
661SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
662 eq_tlv),
663SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
664 eq_tlv),
665
666SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
667 eq_tlv),
668SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
669 eq_tlv),
670SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
671 eq_tlv),
672SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
673 eq_tlv),
674SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
675 eq_tlv),
676};
677
45a690f6
MB		 678static const struct snd_kcontrol_new wm8994_drc_controls[] = {
679SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
680 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
681 WM8994_AIF1ADC1R_DRC_ENA),
682SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
683 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
684 WM8994_AIF1ADC2R_DRC_ENA),
685SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
686 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
687 WM8994_AIF2ADCR_DRC_ENA),
688};
689
1ddc07d0
MB		 690static const char *wm8958_ng_text[] = {
691 "30ms", "125ms", "250ms", "500ms",
692};
693
694static const struct soc_enum wm8958_aif1dac1_ng_hold =
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
696 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
697
698static const struct soc_enum wm8958_aif1dac2_ng_hold =
699 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
700 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
701
702static const struct soc_enum wm8958_aif2dac_ng_hold =
703 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
704 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
705
c4431df0
MB		 706static const struct snd_kcontrol_new wm8958_snd_controls[] = {
707SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 708
709SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
710 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
711SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
712SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
713 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
714 7, 1, ng_tlv),
715
716SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
717 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
718SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
719SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
720 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
721 7, 1, ng_tlv),
722
723SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
724 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
725SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
726SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
727 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
728 7, 1, ng_tlv),
c4431df0
MB		 729};
730
81204c84
MB		 731static const struct snd_kcontrol_new wm1811_snd_controls[] = {
732SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
733 mixin_boost_tlv),
734SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
735 mixin_boost_tlv),
736};
737
af6b6fe4
MB		 738/* We run all mode setting through a function to enforce audio mode */
739static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
740{
741 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
742
28e33269
MB		 743 if (!wm8994->jackdet || !wm8994->jack_cb)
744 return;
745
af6b6fe4
MB		 746 if (wm8994->active_refcount)
747 mode = WM1811_JACKDET_MODE_AUDIO;
748
4752a887 749 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 750 return;
751
4752a887 752 wm8994->jackdet_mode = mode;
1defde2a 753
4752a887
MB		 754 /* Always use audio mode to detect while the system is active */
755 if (mode != WM1811_JACKDET_MODE_NONE)
756 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 757
4752a887
MB		 758 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
759 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 760}
761
762static void active_reference(struct snd_soc_codec *codec)
763{
764 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
765
766 mutex_lock(&wm8994->accdet_lock);
767
768 wm8994->active_refcount++;
769
770 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
771 wm8994->active_refcount);
772
1defde2a
MB		 773 /* If we're using jack detection go into audio mode */
774 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 775
776 mutex_unlock(&wm8994->accdet_lock);
777}
778
779static void active_dereference(struct snd_soc_codec *codec)
780{
781 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
782 u16 mode;
783
784 mutex_lock(&wm8994->accdet_lock);
785
786 wm8994->active_refcount--;
787
788 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
789 wm8994->active_refcount);
790
791 if (wm8994->active_refcount == 0) {
792 /* Go into appropriate detection only mode */
1defde2a
MB		 793 if (wm8994->jack_mic || wm8994->mic_detecting)
794 mode = WM1811_JACKDET_MODE_MIC;
795 else
796 mode = WM1811_JACKDET_MODE_JACK;
797
798 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 799 }
800
801 mutex_unlock(&wm8994->accdet_lock);
802}
803
9e6e96a1
MB		 804static int clk_sys_event(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
806{
807 struct snd_soc_codec *codec = w->codec;
99af79df 808 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 809
810 switch (event) {
811 case SND_SOC_DAPM_PRE_PMU:
812 return configure_clock(codec);
813
99af79df
MB		 814 case SND_SOC_DAPM_POST_PMU:
815 /*
816 * JACKDET won't run until we start the clock and it
817 * only reports deltas, make sure we notify the state
818 * up the stack on startup. Use a *very* generous
819 * timeout for paranoia, there's no urgency and we
820 * don't want false reports.
821 */
822 if (wm8994->jackdet && !wm8994->clk_has_run) {
823 schedule_delayed_work(&wm8994->jackdet_bootstrap,
824 msecs_to_jiffies(1000));
825 wm8994->clk_has_run = true;
826 }
827 break;
828
9e6e96a1
MB		 829 case SND_SOC_DAPM_POST_PMD:
830 configure_clock(codec);
831 break;
832 }
833
834 return 0;
835}
836
4b7ed83a
MB		 837static void vmid_reference(struct snd_soc_codec *codec)
838{
839 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
840
db966f8a
MB		 841 pm_runtime_get_sync(codec->dev);
842
4b7ed83a
MB		 843 wm8994->vmid_refcount++;
844
845 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
846 wm8994->vmid_refcount);
847
848 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 849 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 850 WM8994_LINEOUT1_DISCH |
22f8d055 851 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 852
f7085641
MB		 853 wm_hubs_vmid_ena(codec);
854
22f8d055
MB		 855 switch (wm8994->vmid_mode) {
856 default:
cbd71f30 857 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 858 case WM8994_VMID_NORMAL:
859 /* Startup bias, VMID ramp & buffer */
860 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
861 WM8994_BIAS_SRC |
862 WM8994_VMID_DISCH |
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
865 WM8994_VMID_RAMP_MASK,
866 WM8994_BIAS_SRC |
867 WM8994_STARTUP_BIAS_ENA |
868 WM8994_VMID_BUF_ENA |
a3a1d9d2 869 (0x2 << WM8994_VMID_RAMP_SHIFT));
22f8d055
MB		 870
871 /* Main bias enable, VMID=2x40k */
872 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
873 WM8994_BIAS_ENA |
874 WM8994_VMID_SEL_MASK,
875 WM8994_BIAS_ENA | 0x2);
876
a3a1d9d2 877 msleep(300);
22f8d055
MB		 878
879 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
880 WM8994_VMID_RAMP_MASK |
881 WM8994_BIAS_SRC,
882 0);
883 break;
cc6d5a8c 884
22f8d055
MB		 885 case WM8994_VMID_FORCE:
886 /* Startup bias, slow VMID ramp & buffer */
887 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
888 WM8994_BIAS_SRC |
889 WM8994_VMID_DISCH |
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 WM8994_VMID_RAMP_MASK,
893 WM8994_BIAS_SRC |
894 WM8994_STARTUP_BIAS_ENA |
895 WM8994_VMID_BUF_ENA |
896 (0x2 << WM8994_VMID_RAMP_SHIFT));
897
898 /* Main bias enable, VMID=2x40k */
899 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
900 WM8994_BIAS_ENA |
901 WM8994_VMID_SEL_MASK,
902 WM8994_BIAS_ENA | 0x2);
903
904 msleep(400);
905
906 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
907 WM8994_VMID_RAMP_MASK |
908 WM8994_BIAS_SRC,
909 0);
910 break;
911 }
4b7ed83a
MB		 912 }
913}
914
915static void vmid_dereference(struct snd_soc_codec *codec)
916{
917 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
918
919 wm8994->vmid_refcount--;
920
921 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
922 wm8994->vmid_refcount);
923
924 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 925 if (wm8994->hubs.lineout1_se)
926 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
927 WM8994_LINEOUT1N_ENA |
928 WM8994_LINEOUT1P_ENA,
929 WM8994_LINEOUT1N_ENA |
930 WM8994_LINEOUT1P_ENA);
931
932 if (wm8994->hubs.lineout2_se)
933 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
934 WM8994_LINEOUT2N_ENA |
935 WM8994_LINEOUT2P_ENA,
936 WM8994_LINEOUT2N_ENA |
937 WM8994_LINEOUT2P_ENA);
938
939 /* Start discharging VMID */
4b7ed83a
MB		 940 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
941 WM8994_BIAS_SRC |
22f8d055 942 WM8994_VMID_DISCH,
4b7ed83a 943 WM8994_BIAS_SRC |
22f8d055 944 WM8994_VMID_DISCH);
4b7ed83a 945
f95be9d6
MB		 946 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
947 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 948
f95be9d6 949 msleep(400);
e85b26ce 950
22f8d055 951 /* Active discharge */
4b7ed83a
MB		 952 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
953 WM8994_LINEOUT1_DISCH |
954 WM8994_LINEOUT2_DISCH,
955 WM8994_LINEOUT1_DISCH |
956 WM8994_LINEOUT2_DISCH);
957
22f8d055
MB		 958 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
959 WM8994_LINEOUT1N_ENA |
960 WM8994_LINEOUT1P_ENA |
961 WM8994_LINEOUT2N_ENA |
962 WM8994_LINEOUT2P_ENA, 0);
963
4b7ed83a
MB		 964 /* Switch off startup biases */
965 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
966 WM8994_BIAS_SRC |
967 WM8994_STARTUP_BIAS_ENA |
968 WM8994_VMID_BUF_ENA |
969 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 970
971 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 972 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 973 }
db966f8a
MB		 974
975 pm_runtime_put(codec->dev);
4b7ed83a
MB		 976}
977
978static int vmid_event(struct snd_soc_dapm_widget *w,
979 struct snd_kcontrol *kcontrol, int event)
980{
981 struct snd_soc_codec *codec = w->codec;
982
983 switch (event) {
984 case SND_SOC_DAPM_PRE_PMU:
985 vmid_reference(codec);
986 break;
987
988 case SND_SOC_DAPM_POST_PMD:
989 vmid_dereference(codec);
990 break;
991 }
992
993 return 0;
994}
995
c340304d 996static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 997{
9e6e96a1
MB		 998 int source = 0; /* GCC flow analysis can't track enable */
999 int reg, reg_r;
1000
c340304d 1001 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 1002 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1003 switch (reg) {
1004 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1005 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 1006 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1009 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 1010 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1013 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 1014 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1015 break;
1016 default:
ee839a21 1017 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1018 return false;
9e6e96a1
MB		 1019 }
1020
1021 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1022 if (reg_r != reg) {
ee839a21 1023 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1024 return false;
9e6e96a1
MB		 1025 }
1026
c340304d
MB		 1027 /* Set the source up */
1028 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1029 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1030
c340304d 1031 return true;
9e6e96a1
MB		 1032}
1033
1a38336b
MB		 1034static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1035 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1036{
1037 struct snd_soc_codec *codec = w->codec;
1a38336b
MB		 1038 struct wm8994 *control = codec->control_data;
1039 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1040 int i;
1a38336b
MB		 1041 int dac;
1042 int adc;
1043 int val;
1044
1045 switch (control->type) {
1046 case WM8994:
1047 case WM8958:
1048 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1049 break;
1050 default:
1051 break;
1052 }
173efa09
DP		 1053
1054 switch (event) {
1055 case SND_SOC_DAPM_PRE_PMU:
1a38336b
MB		 1056 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1057 if ((val & WM8994_AIF1ADCL_SRC) &&
1058 (val & WM8994_AIF1ADCR_SRC))
1059 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1060 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1061 !(val & WM8994_AIF1ADCR_SRC))
1062 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1063 else
1064 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1065 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1066
1067 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1068 if ((val & WM8994_AIF1DACL_SRC) &&
1069 (val & WM8994_AIF1DACR_SRC))
1070 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1071 else if (!(val & WM8994_AIF1DACL_SRC) &&
1072 !(val & WM8994_AIF1DACR_SRC))
1073 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1074 else
1075 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1076 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1077
1078 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1079 mask, adc);
1080 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1081 mask, dac);
1082 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1083 WM8994_AIF1DSPCLK_ENA |
1084 WM8994_SYSDSPCLK_ENA,
1085 WM8994_AIF1DSPCLK_ENA |
1086 WM8994_SYSDSPCLK_ENA);
1087 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1088 WM8994_AIF1ADC1R_ENA |
1089 WM8994_AIF1ADC1L_ENA |
1090 WM8994_AIF1ADC2R_ENA |
1091 WM8994_AIF1ADC2L_ENA);
1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1093 WM8994_AIF1DAC1R_ENA |
1094 WM8994_AIF1DAC1L_ENA |
1095 WM8994_AIF1DAC2R_ENA |
1096 WM8994_AIF1DAC2L_ENA);
173efa09 1097 break;
173efa09 1098
bfd37bb5
MB		 1099 case SND_SOC_DAPM_POST_PMU:
1100 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1101 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1102 snd_soc_read(codec,
1103 wm8994_vu_bits[i].reg));
1104 break;
1105
1a38336b
MB		 1106 case SND_SOC_DAPM_PRE_PMD:
1107 case SND_SOC_DAPM_POST_PMD:
1108 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1109 mask, 0);
1110 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1111 mask, 0);
1112
1113 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1114 if (val & WM8994_AIF2DSPCLK_ENA)
1115 val = WM8994_SYSDSPCLK_ENA;
1116 else
1117 val = 0;
1118 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1119 WM8994_SYSDSPCLK_ENA |
1120 WM8994_AIF1DSPCLK_ENA, val);
1121 break;
1122 }
c6b7b570 1123
173efa09
DP		 1124 return 0;
1125}
1126
1a38336b
MB		 1127static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1128 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1129{
1130 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1131 int i;
1a38336b
MB		 1132 int dac;
1133 int adc;
1134 int val;
173efa09
DP		 1135
1136 switch (event) {
1a38336b
MB		 1137 case SND_SOC_DAPM_PRE_PMU:
1138 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1139 if ((val & WM8994_AIF2ADCL_SRC) &&
1140 (val & WM8994_AIF2ADCR_SRC))
1141 adc = WM8994_AIF2ADCR_ENA;
1142 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1143 !(val & WM8994_AIF2ADCR_SRC))
1144 adc = WM8994_AIF2ADCL_ENA;
1145 else
1146 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1147
1148
1149 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1150 if ((val & WM8994_AIF2DACL_SRC) &&
1151 (val & WM8994_AIF2DACR_SRC))
1152 dac = WM8994_AIF2DACR_ENA;
1153 else if (!(val & WM8994_AIF2DACL_SRC) &&
1154 !(val & WM8994_AIF2DACR_SRC))
1155 dac = WM8994_AIF2DACL_ENA;
1156 else
1157 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1158
1159 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1160 WM8994_AIF2ADCL_ENA |
1161 WM8994_AIF2ADCR_ENA, adc);
1162 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1163 WM8994_AIF2DACL_ENA |
1164 WM8994_AIF2DACR_ENA, dac);
1165 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1166 WM8994_AIF2DSPCLK_ENA |
1167 WM8994_SYSDSPCLK_ENA,
1168 WM8994_AIF2DSPCLK_ENA |
1169 WM8994_SYSDSPCLK_ENA);
1170 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1171 WM8994_AIF2ADCL_ENA |
1172 WM8994_AIF2ADCR_ENA,
1173 WM8994_AIF2ADCL_ENA |
1174 WM8994_AIF2ADCR_ENA);
1175 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1176 WM8994_AIF2DACL_ENA |
1177 WM8994_AIF2DACR_ENA,
1178 WM8994_AIF2DACL_ENA |
1179 WM8994_AIF2DACR_ENA);
1180 break;
1181
bfd37bb5
MB		 1182 case SND_SOC_DAPM_POST_PMU:
1183 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1184 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1185 snd_soc_read(codec,
1186 wm8994_vu_bits[i].reg));
1187 break;
1188
1a38336b 1189 case SND_SOC_DAPM_PRE_PMD:
173efa09 1190 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1191 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1192 WM8994_AIF2DACL_ENA |
1193 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1194 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1195 WM8994_AIF2ADCL_ENA |
1196 WM8994_AIF2ADCR_ENA, 0);
1197
1198 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1199 if (val & WM8994_AIF1DSPCLK_ENA)
1200 val = WM8994_SYSDSPCLK_ENA;
1201 else
1202 val = 0;
1203 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1204 WM8994_SYSDSPCLK_ENA |
1205 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1206 break;
1207 }
1208
1209 return 0;
1210}
1211
1a38336b
MB		 1212static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1213 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1214{
1215 struct snd_soc_codec *codec = w->codec;
1216 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1217
1218 switch (event) {
1219 case SND_SOC_DAPM_PRE_PMU:
1220 wm8994->aif1clk_enable = 1;
1221 break;
a3cff81a
DP		 1222 case SND_SOC_DAPM_POST_PMD:
1223 wm8994->aif1clk_disable = 1;
1224 break;
173efa09
DP		 1225 }
1226
1227 return 0;
1228}
1229
1a38336b
MB		 1230static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1231 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1232{
1233 struct snd_soc_codec *codec = w->codec;
1234 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1235
1236 switch (event) {
1237 case SND_SOC_DAPM_PRE_PMU:
1238 wm8994->aif2clk_enable = 1;
1239 break;
a3cff81a
DP		 1240 case SND_SOC_DAPM_POST_PMD:
1241 wm8994->aif2clk_disable = 1;
1242 break;
173efa09
DP		 1243 }
1244
1245 return 0;
1246}
1247
1a38336b
MB		 1248static int late_enable_ev(struct snd_soc_dapm_widget *w,
1249 struct snd_kcontrol *kcontrol, int event)
1250{
1251 struct snd_soc_codec *codec = w->codec;
1252 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1253
1254 switch (event) {
1255 case SND_SOC_DAPM_PRE_PMU:
1256 if (wm8994->aif1clk_enable) {
c8fdc1b5 1257 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1258 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1259 WM8994_AIF1CLK_ENA_MASK,
1260 WM8994_AIF1CLK_ENA);
c8fdc1b5 1261 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1262 wm8994->aif1clk_enable = 0;
1263 }
1264 if (wm8994->aif2clk_enable) {
c8fdc1b5 1265 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1266 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1267 WM8994_AIF2CLK_ENA_MASK,
1268 WM8994_AIF2CLK_ENA);
c8fdc1b5 1269 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1270 wm8994->aif2clk_enable = 0;
1271 }
1272 break;
1273 }
1274
1275 /* We may also have postponed startup of DSP, handle that. */
1276 wm8958_aif_ev(w, kcontrol, event);
1277
1278 return 0;
1279}
1280
1281static int late_disable_ev(struct snd_soc_dapm_widget *w,
1282 struct snd_kcontrol *kcontrol, int event)
1283{
1284 struct snd_soc_codec *codec = w->codec;
1285 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1286
1287 switch (event) {
1288 case SND_SOC_DAPM_POST_PMD:
1289 if (wm8994->aif1clk_disable) {
c8fdc1b5 1290 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1291 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1292 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1293 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1294 wm8994->aif1clk_disable = 0;
1295 }
1296 if (wm8994->aif2clk_disable) {
c8fdc1b5 1297 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1298 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1299 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1300 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1301 wm8994->aif2clk_disable = 0;
1302 }
1303 break;
1304 }
1305
1306 return 0;
1307}
1308
04d28681
DP		 1309static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1310 struct snd_kcontrol *kcontrol, int event)
1311{
1312 late_enable_ev(w, kcontrol, event);
1313 return 0;
1314}
1315
b462c6e6
DP		 1316static int micbias_ev(struct snd_soc_dapm_widget *w,
1317 struct snd_kcontrol *kcontrol, int event)
1318{
1319 late_enable_ev(w, kcontrol, event);
1320 return 0;
1321}
1322
c52fd021
DP		 1323static int dac_ev(struct snd_soc_dapm_widget *w,
1324 struct snd_kcontrol *kcontrol, int event)
1325{
1326 struct snd_soc_codec *codec = w->codec;
1327 unsigned int mask = 1 << w->shift;
1328
1329 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1330 mask, mask);
1331 return 0;
1332}
1333
9e6e96a1
MB		 1334static const char *adc_mux_text[] = {
1335 "ADC",
1336 "DMIC",
1337};
1338
1339static const struct soc_enum adc_enum =
1340 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1341
1342static const struct snd_kcontrol_new adcl_mux =
1343 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1344
1345static const struct snd_kcontrol_new adcr_mux =
1346 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1347
1348static const struct snd_kcontrol_new left_speaker_mixer[] = {
1349SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1350SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1351SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1352SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1353SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1354};
1355
1356static const struct snd_kcontrol_new right_speaker_mixer[] = {
1357SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1358SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1359SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1360SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1361SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1362};
1363
1364/* Debugging; dump chip status after DAPM transitions */
1365static int post_ev(struct snd_soc_dapm_widget *w,
1366 struct snd_kcontrol *kcontrol, int event)
1367{
1368 struct snd_soc_codec *codec = w->codec;
1369 dev_dbg(codec->dev, "SRC status: %x\n",
1370 snd_soc_read(codec,
1371 WM8994_RATE_STATUS));
1372 return 0;
1373}
1374
1375static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1376SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1377 1, 1, 0),
1378SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1379 0, 1, 0),
1380};
1381
1382static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1383SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1384 1, 1, 0),
1385SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1386 0, 1, 0),
1387};
1388
a3257ba8
MB		 1389static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1390SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1391 1, 1, 0),
1392SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1393 0, 1, 0),
1394};
1395
1396static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1397SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1398 1, 1, 0),
1399SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1400 0, 1, 0),
1401};
1402
9e6e96a1
MB		 1403static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1404SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1405 5, 1, 0),
1406SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1407 4, 1, 0),
1408SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1409 2, 1, 0),
1410SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1411 1, 1, 0),
1412SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1413 0, 1, 0),
1414};
1415
1416static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1417SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1418 5, 1, 0),
1419SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1420 4, 1, 0),
1421SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1422 2, 1, 0),
1423SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1424 1, 1, 0),
1425SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1426 0, 1, 0),
1427};
1428
1429#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1430{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1431 .info = snd_soc_info_volsw, \
1432 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1433 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1434
1435static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1436 struct snd_ctl_elem_value *ucontrol)
1437{
9d03545d
JN		 1438 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1439 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1440 struct snd_soc_codec *codec = w->codec;
1441 int ret;
1442
1443 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1444
c340304d 1445 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1446
1447 return ret;
1448}
1449
1450static const struct snd_kcontrol_new dac1l_mix[] = {
1451WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1452 5, 1, 0),
1453WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1454 4, 1, 0),
1455WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456 2, 1, 0),
1457WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458 1, 1, 0),
1459WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1460 0, 1, 0),
1461};
1462
1463static const struct snd_kcontrol_new dac1r_mix[] = {
1464WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1465 5, 1, 0),
1466WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1467 4, 1, 0),
1468WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469 2, 1, 0),
1470WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471 1, 1, 0),
1472WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1473 0, 1, 0),
1474};
1475
1476static const char *sidetone_text[] = {
1477 "ADC/DMIC1", "DMIC2",
1478};
1479
1480static const struct soc_enum sidetone1_enum =
1481 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1482
1483static const struct snd_kcontrol_new sidetone1_mux =
1484 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1485
1486static const struct soc_enum sidetone2_enum =
1487 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1488
1489static const struct snd_kcontrol_new sidetone2_mux =
1490 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1491
1492static const char *aif1dac_text[] = {
1493 "AIF1DACDAT", "AIF3DACDAT",
1494};
1495
1496static const struct soc_enum aif1dac_enum =
1497 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1498
1499static const struct snd_kcontrol_new aif1dac_mux =
1500 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1501
1502static const char *aif2dac_text[] = {
1503 "AIF2DACDAT", "AIF3DACDAT",
1504};
1505
1506static const struct soc_enum aif2dac_enum =
1507 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1508
1509static const struct snd_kcontrol_new aif2dac_mux =
1510 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1511
1512static const char *aif2adc_text[] = {
1513 "AIF2ADCDAT", "AIF3DACDAT",
1514};
1515
1516static const struct soc_enum aif2adc_enum =
1517 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1518
1519static const struct snd_kcontrol_new aif2adc_mux =
1520 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1521
1522static const char *aif3adc_text[] = {
c4431df0 1523 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1524};
1525
c4431df0 1526static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1527 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1528
c4431df0
MB		 1529static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1530 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1531
1532static const struct soc_enum wm8958_aif3adc_enum =
1533 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1534
1535static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1536 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1537
1538static const char *mono_pcm_out_text[] = {
c1a4ecd9 1539 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1540};
1541
1542static const struct soc_enum mono_pcm_out_enum =
1543 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1544
1545static const struct snd_kcontrol_new mono_pcm_out_mux =
1546 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1547
1548static const char *aif2dac_src_text[] = {
1549 "AIF2", "AIF3",
1550};
1551
1552/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1553static const struct soc_enum aif2dacl_src_enum =
1554 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1555
1556static const struct snd_kcontrol_new aif2dacl_src_mux =
1557 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1558
1559static const struct soc_enum aif2dacr_src_enum =
1560 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1561
1562static const struct snd_kcontrol_new aif2dacr_src_mux =
1563 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1564
173efa09 1565static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1566SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1567 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1568SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1569 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1570
1571SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1572 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1573SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1574 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1575SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1576 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1577SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1578 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1579SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1580 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1581
1582SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1583 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1584 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1585SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1586 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1587 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1588SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1589 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1590SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1591 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1592
1593SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1594};
1595
1596static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1597SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1599 SND_SOC_DAPM_PRE_PMD),
1a38336b 1600SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1602 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1603SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1604SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1605 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1606SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1607 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1608SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1609SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1610};
1611
c52fd021
DP		 1612static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1613SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1614 dac_ev, SND_SOC_DAPM_PRE_PMU),
1615SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1616 dac_ev, SND_SOC_DAPM_PRE_PMU),
1617SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1618 dac_ev, SND_SOC_DAPM_PRE_PMU),
1619SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1620 dac_ev, SND_SOC_DAPM_PRE_PMU),
1621};
1622
1623static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1624SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1625SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1626SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1627SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1628};
1629
04d28681 1630static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1631SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1632 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1633SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1634 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1635};
1636
1637static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1638SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1639SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1640};
1641
9e6e96a1
MB		 1642static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1643SND_SOC_DAPM_INPUT("DMIC1DAT"),
1644SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1645SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1646
b462c6e6
DP		 1647SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1648 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1649SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1650 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1651
9e6e96a1 1652SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB		 1653 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1654 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1655
1a38336b
MB		 1656SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1657SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1658SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1659
7f94de48 1660SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1661 0, SND_SOC_NOPM, 9, 0),
7f94de48 1662SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1663 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1664SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1665 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1666 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1667SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1668 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1669 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1670
7f94de48 1671SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1672 0, SND_SOC_NOPM, 11, 0),
7f94de48 1673SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1674 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1675SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1676 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1677 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1678SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1679 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1680 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1681
1682SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1683 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1684SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1685 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1686
a3257ba8
MB		 1687SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1688 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1689SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1690 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1691
9e6e96a1
MB		 1692SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1693 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1694SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1695 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1696
1697SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1698SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1699
1700SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1701 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1702SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1703 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1704
1705SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1706 SND_SOC_NOPM, 13, 0),
9e6e96a1 1707SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1708 SND_SOC_NOPM, 12, 0),
d6addcc9 1709SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1710 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1711 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1712SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1713 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1714 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1715
5567d8c6
MB		 1716SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1717SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1718SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1719SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1720
1721SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1722SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1723SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1724
5567d8c6
MB		 1725SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1726SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1727
1728SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1729
1730SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1731SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1732SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1733SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1734
1735/* Power is done with the muxes since the ADC power also controls the
1736 * downsampling chain, the chip will automatically manage the analogue
1737 * specific portions.
1738 */
1739SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1740SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1741
9e6e96a1
MB		 1742SND_SOC_DAPM_POST("Debug log", post_ev),
1743};
1744
c4431df0
MB		 1745static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1746SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1747};
9e6e96a1 1748
c4431df0 1749static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1750SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1751SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1752SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1753SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1754SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1755};
1756
1757static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1758 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1759 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1760
1761 { "DSP1CLK", NULL, "CLK_SYS" },
1762 { "DSP2CLK", NULL, "CLK_SYS" },
1763 { "DSPINTCLK", NULL, "CLK_SYS" },
1764
1765 { "AIF1ADC1L", NULL, "AIF1CLK" },
1766 { "AIF1ADC1L", NULL, "DSP1CLK" },
1767 { "AIF1ADC1R", NULL, "AIF1CLK" },
1768 { "AIF1ADC1R", NULL, "DSP1CLK" },
1769 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1770
1771 { "AIF1DAC1L", NULL, "AIF1CLK" },
1772 { "AIF1DAC1L", NULL, "DSP1CLK" },
1773 { "AIF1DAC1R", NULL, "AIF1CLK" },
1774 { "AIF1DAC1R", NULL, "DSP1CLK" },
1775 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1776
1777 { "AIF1ADC2L", NULL, "AIF1CLK" },
1778 { "AIF1ADC2L", NULL, "DSP1CLK" },
1779 { "AIF1ADC2R", NULL, "AIF1CLK" },
1780 { "AIF1ADC2R", NULL, "DSP1CLK" },
1781 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1782
1783 { "AIF1DAC2L", NULL, "AIF1CLK" },
1784 { "AIF1DAC2L", NULL, "DSP1CLK" },
1785 { "AIF1DAC2R", NULL, "AIF1CLK" },
1786 { "AIF1DAC2R", NULL, "DSP1CLK" },
1787 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1788
1789 { "AIF2ADCL", NULL, "AIF2CLK" },
1790 { "AIF2ADCL", NULL, "DSP2CLK" },
1791 { "AIF2ADCR", NULL, "AIF2CLK" },
1792 { "AIF2ADCR", NULL, "DSP2CLK" },
1793 { "AIF2ADCR", NULL, "DSPINTCLK" },
1794
1795 { "AIF2DACL", NULL, "AIF2CLK" },
1796 { "AIF2DACL", NULL, "DSP2CLK" },
1797 { "AIF2DACR", NULL, "AIF2CLK" },
1798 { "AIF2DACR", NULL, "DSP2CLK" },
1799 { "AIF2DACR", NULL, "DSPINTCLK" },
1800
1801 { "DMIC1L", NULL, "DMIC1DAT" },
1802 { "DMIC1L", NULL, "CLK_SYS" },
1803 { "DMIC1R", NULL, "DMIC1DAT" },
1804 { "DMIC1R", NULL, "CLK_SYS" },
1805 { "DMIC2L", NULL, "DMIC2DAT" },
1806 { "DMIC2L", NULL, "CLK_SYS" },
1807 { "DMIC2R", NULL, "DMIC2DAT" },
1808 { "DMIC2R", NULL, "CLK_SYS" },
1809
1810 { "ADCL", NULL, "AIF1CLK" },
1811 { "ADCL", NULL, "DSP1CLK" },
1812 { "ADCL", NULL, "DSPINTCLK" },
1813
1814 { "ADCR", NULL, "AIF1CLK" },
1815 { "ADCR", NULL, "DSP1CLK" },
1816 { "ADCR", NULL, "DSPINTCLK" },
1817
1818 { "ADCL Mux", "ADC", "ADCL" },
1819 { "ADCL Mux", "DMIC", "DMIC1L" },
1820 { "ADCR Mux", "ADC", "ADCR" },
1821 { "ADCR Mux", "DMIC", "DMIC1R" },
1822
1823 { "DAC1L", NULL, "AIF1CLK" },
1824 { "DAC1L", NULL, "DSP1CLK" },
1825 { "DAC1L", NULL, "DSPINTCLK" },
1826
1827 { "DAC1R", NULL, "AIF1CLK" },
1828 { "DAC1R", NULL, "DSP1CLK" },
1829 { "DAC1R", NULL, "DSPINTCLK" },
1830
1831 { "DAC2L", NULL, "AIF2CLK" },
1832 { "DAC2L", NULL, "DSP2CLK" },
1833 { "DAC2L", NULL, "DSPINTCLK" },
1834
1835 { "DAC2R", NULL, "AIF2DACR" },
1836 { "DAC2R", NULL, "AIF2CLK" },
1837 { "DAC2R", NULL, "DSP2CLK" },
1838 { "DAC2R", NULL, "DSPINTCLK" },
1839
1840 { "TOCLK", NULL, "CLK_SYS" },
1841
5567d8c6
MB		 1842 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1843 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1844 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1845
1846 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1847 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1848 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1849
9e6e96a1
MB		 1850 /* AIF1 outputs */
1851 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1852 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1853 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1854
1855 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1856 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1857 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1858
a3257ba8
MB		 1859 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1860 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1861 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1862
1863 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1864 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1865 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1866
9e6e96a1
MB		 1867 /* Pin level routing for AIF3 */
1868 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1869 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1870 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1871 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1872
9e6e96a1
MB		 1873 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1874 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1875 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1876 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1877 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1878 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1879 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1880
1881 /* DAC1 inputs */
9e6e96a1
MB		 1882 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1883 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1884 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1885 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1886 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1887
9e6e96a1
MB		 1888 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1889 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1890 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1891 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1892 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1893
1894 /* DAC2/AIF2 outputs */
1895 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1896 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1897 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1898 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1899 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1900 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1901
1902 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1903 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1904 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1905 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1906 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1907 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1908
7f94de48
MB		 1909 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1910 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1911 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1912 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1913
9e6e96a1
MB		 1914 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1915
1916 /* AIF3 output */
1917 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1918 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1919 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1920 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1921 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1922 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1923 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1924 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1925
1926 /* Sidetone */
1927 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1928 { "Left Sidetone", "DMIC2", "DMIC2L" },
1929 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1930 { "Right Sidetone", "DMIC2", "DMIC2R" },
1931
1932 /* Output stages */
1933 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1934 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1935
1936 { "SPKL", "DAC1 Switch", "DAC1L" },
1937 { "SPKL", "DAC2 Switch", "DAC2L" },
1938
1939 { "SPKR", "DAC1 Switch", "DAC1R" },
1940 { "SPKR", "DAC2 Switch", "DAC2R" },
1941
1942 { "Left Headphone Mux", "DAC", "DAC1L" },
1943 { "Right Headphone Mux", "DAC", "DAC1R" },
1944};
1945
173efa09
DP		 1946static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1947 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1948 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1949 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1950 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1951 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1952 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1953 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1954 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1955};
1956
1957static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1958 { "DAC1L", NULL, "DAC1L Mixer" },
1959 { "DAC1R", NULL, "DAC1R Mixer" },
1960 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1961 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1962};
1963
6ed8f148
MB		 1964static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1965 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1966 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1967 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1968 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1969 { "MICBIAS1", NULL, "CLK_SYS" },
1970 { "MICBIAS1", NULL, "MICBIAS Supply" },
1971 { "MICBIAS2", NULL, "CLK_SYS" },
1972 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1973};
1974
c4431df0
MB		 1975static const struct snd_soc_dapm_route wm8994_intercon[] = {
1976 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1977 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1978 { "MICBIAS1", NULL, "VMID" },
1979 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1980};
1981
1982static const struct snd_soc_dapm_route wm8958_intercon[] = {
1983 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1984 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1985
1986 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1987 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1988 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1989 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1990
8c5b842b
MB		 1991 { "AIF3DACDAT", NULL, "AIF3" },
1992 { "AIF3ADCDAT", NULL, "AIF3" },
1993
c4431df0
MB		 1994 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1995 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1996
1997 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1998};
1999
9e6e96a1
MB		 2000/* The size in bits of the FLL divide multiplied by 10
2001 * to allow rounding later */
2002#define FIXED_FLL_SIZE ((1 << 16) * 10)
2003
2004struct fll_div {
2005 u16 outdiv;
2006 u16 n;
2007 u16 k;
2008 u16 clk_ref_div;
2009 u16 fll_fratio;
2010};
2011
2012static int wm8994_get_fll_config(struct fll_div *fll,
2013 int freq_in, int freq_out)
2014{
2015 u64 Kpart;
2016 unsigned int K, Ndiv, Nmod;
2017
2018 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2019
2020 /* Scale the input frequency down to <= 13.5MHz */
2021 fll->clk_ref_div = 0;
2022 while (freq_in > 13500000) {
2023 fll->clk_ref_div++;
2024 freq_in /= 2;
2025
2026 if (fll->clk_ref_div > 3)
2027 return -EINVAL;
2028 }
2029 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2030
2031 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2032 fll->outdiv = 3;
2033 while (freq_out * (fll->outdiv + 1) < 90000000) {
2034 fll->outdiv++;
2035 if (fll->outdiv > 63)
2036 return -EINVAL;
2037 }
2038 freq_out *= fll->outdiv + 1;
2039 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2040
2041 if (freq_in > 1000000) {
2042 fll->fll_fratio = 0;
7d48a6ac
MB		 2043 } else if (freq_in > 256000) {
2044 fll->fll_fratio = 1;
2045 freq_in *= 2;
2046 } else if (freq_in > 128000) {
2047 fll->fll_fratio = 2;
2048 freq_in *= 4;
2049 } else if (freq_in > 64000) {
9e6e96a1
MB		 2050 fll->fll_fratio = 3;
2051 freq_in *= 8;
7d48a6ac
MB		 2052 } else {
2053 fll->fll_fratio = 4;
2054 freq_in *= 16;
9e6e96a1
MB		 2055 }
2056 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2057
2058 /* Now, calculate N.K */
2059 Ndiv = freq_out / freq_in;
2060
2061 fll->n = Ndiv;
2062 Nmod = freq_out % freq_in;
2063 pr_debug("Nmod=%d\n", Nmod);
2064
2065 /* Calculate fractional part - scale up so we can round. */
2066 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2067
2068 do_div(Kpart, freq_in);
2069
2070 K = Kpart & 0xFFFFFFFF;
2071
2072 if ((K % 10) >= 5)
2073 K += 5;
2074
2075 /* Move down to proper range now rounding is done */
2076 fll->k = K / 10;
2077
2078 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2079
2080 return 0;
2081}
2082
f0fba2ad 2083static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2084 unsigned int freq_in, unsigned int freq_out)
2085{
b2c812e2 2086 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2087 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2088 int reg_offset, ret;
2089 struct fll_div fll;
e413ba88 2090 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2091 unsigned long timeout;
4b7ed83a 2092 bool was_enabled;
9e6e96a1 2093
9e6e96a1
MB		 2094 switch (id) {
2095 case WM8994_FLL1:
2096 reg_offset = 0;
2097 id = 0;
e413ba88 2098 aif_src = 0x10;
9e6e96a1
MB		 2099 break;
2100 case WM8994_FLL2:
2101 reg_offset = 0x20;
2102 id = 1;
e413ba88 2103 aif_src = 0x18;
9e6e96a1
MB		 2104 break;
2105 default:
2106 return -EINVAL;
2107 }
2108
4b7ed83a
MB		 2109 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2110 was_enabled = reg & WM8994_FLL1_ENA;
2111
136ff2a2 2112 switch (src) {
7add84aa
MB		 2113 case 0:
2114 /* Allow no source specification when stopping */
2115 if (freq_out)
2116 return -EINVAL;
4514e899 2117 src = wm8994->fll[id].src;
7add84aa 2118 break;
136ff2a2
MB		 2119 case WM8994_FLL_SRC_MCLK1:
2120 case WM8994_FLL_SRC_MCLK2:
2121 case WM8994_FLL_SRC_LRCLK:
2122 case WM8994_FLL_SRC_BCLK:
2123 break;
fbfe6983
MB		 2124 case WM8994_FLL_SRC_INTERNAL:
2125 freq_in = 12000000;
2126 freq_out = 12000000;
2127 break;
136ff2a2
MB		 2128 default:
2129 return -EINVAL;
2130 }
2131
9e6e96a1
MB		 2132 /* Are we changing anything? */
2133 if (wm8994->fll[id].src == src &&
2134 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2135 return 0;
2136
2137 /* If we're stopping the FLL redo the old config - no
2138 * registers will actually be written but we avoid GCC flow
2139 * analysis bugs spewing warnings.
2140 */
2141 if (freq_out)
2142 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2143 else
2144 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2145 wm8994->fll[id].out);
2146 if (ret < 0)
2147 return ret;
2148
e413ba88
MB		 2149 /* Make sure that we're not providing SYSCLK right now */
2150 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2151 if (clk1 & WM8994_SYSCLK_SRC)
2152 aif_reg = WM8994_AIF2_CLOCKING_1;
2153 else
2154 aif_reg = WM8994_AIF1_CLOCKING_1;
2155 reg = snd_soc_read(codec, aif_reg);
2156
2157 if ((reg & WM8994_AIF1CLK_ENA) &&
2158 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2159 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2160 id + 1);
2161 return -EBUSY;
2162 }
9e6e96a1
MB		 2163
2164 /* We always need to disable the FLL while reconfiguring */
2165 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2166 WM8994_FLL1_ENA, 0);
2167
20dc24a9 2168 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2169 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2170 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2171 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2172 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2173 goto out;
2174 }
2175
9e6e96a1
MB		 2176 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2177 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2178 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2179 WM8994_FLL1_OUTDIV_MASK |
2180 WM8994_FLL1_FRATIO_MASK, reg);
2181
b16db745
MB		 2182 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2183 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2184
2185 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2186 WM8994_FLL1_N_MASK,
7435d4ee 2187 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1
MB		 2188
2189 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2190 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB		 2191 WM8994_FLL1_REFCLK_DIV_MASK |
2192 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB		 2193 ((src == WM8994_FLL_SRC_INTERNAL)
2194 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB		 2195 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2196 (src - 1));
9e6e96a1 2197
f0f5039c
MB		 2198 /* Clear any pending completion from a previous failure */
2199 try_wait_for_completion(&wm8994->fll_locked[id]);
2200
9e6e96a1
MB		 2201 /* Enable (with fractional mode if required) */
2202 if (freq_out) {
4b7ed83a
MB		 2203 /* Enable VMID if we need it */
2204 if (!was_enabled) {
af6b6fe4
MB		 2205 active_reference(codec);
2206
4b7ed83a
MB		 2207 switch (control->type) {
2208 case WM8994:
2209 vmid_reference(codec);
2210 break;
2211 case WM8958:
2212 if (wm8994->revision < 1)
2213 vmid_reference(codec);
2214 break;
2215 default:
2216 break;
2217 }
2218 }
2219
fbfe6983
MB		 2220 reg = WM8994_FLL1_ENA;
2221
9e6e96a1 2222 if (fll.k)
fbfe6983
MB		 2223 reg |= WM8994_FLL1_FRAC;
2224 if (src == WM8994_FLL_SRC_INTERNAL)
2225 reg |= WM8994_FLL1_OSC_ENA;
2226
9e6e96a1 2227 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB		 2228 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2229 WM8994_FLL1_FRAC, reg);
8e9ddf81 2230
c7ebf932
MB		 2231 if (wm8994->fll_locked_irq) {
2232 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2233 msecs_to_jiffies(10));
2234 if (timeout == 0)
2235 dev_warn(codec->dev,
2236 "Timed out waiting for FLL lock\n");
2237 } else {
2238 msleep(5);
2239 }
4b7ed83a
MB		 2240 } else {
2241 if (was_enabled) {
2242 switch (control->type) {
2243 case WM8994:
2244 vmid_dereference(codec);
2245 break;
2246 case WM8958:
2247 if (wm8994->revision < 1)
2248 vmid_dereference(codec);
2249 break;
2250 default:
2251 break;
2252 }
af6b6fe4
MB		 2253
2254 active_dereference(codec);
4b7ed83a 2255 }
9e6e96a1
MB		 2256 }
2257
20dc24a9 2258out:
9e6e96a1
MB		 2259 wm8994->fll[id].in = freq_in;
2260 wm8994->fll[id].out = freq_out;
136ff2a2 2261 wm8994->fll[id].src = src;
9e6e96a1 2262
9e6e96a1
MB		 2263 configure_clock(codec);
2264
cd22000a
MB		 2265 /*
2266 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2267 * for detection.
2268 */
2269 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2270 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2271 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2272 WM8994_AIF1CLK_RATE_MASK, 0x1);
2273 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2274 WM8994_AIF2CLK_RATE_MASK, 0x1);
2275 }
2276
9e6e96a1
MB		 2277 return 0;
2278}
2279
c7ebf932
MB		 2280static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2281{
2282 struct completion *completion = data;
2283
2284 complete(completion);
2285
2286 return IRQ_HANDLED;
2287}
f0fba2ad 2288
66b47fdb
MB		 2289static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2290
f0fba2ad
LG		 2291static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2292 unsigned int freq_in, unsigned int freq_out)
2293{
2294 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2295}
2296
9e6e96a1
MB		 2297static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2298 int clk_id, unsigned int freq, int dir)
2299{
2300 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2301 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2302 int i;
9e6e96a1
MB		 2303
2304 switch (dai->id) {
2305 case 1:
2306 case 2:
2307 break;
2308
2309 default:
2310 /* AIF3 shares clocking with AIF1/2 */
2311 return -EINVAL;
2312 }
2313
2314 switch (clk_id) {
2315 case WM8994_SYSCLK_MCLK1:
2316 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2317 wm8994->mclk[0] = freq;
2318 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2319 dai->id, freq);
2320 break;
2321
2322 case WM8994_SYSCLK_MCLK2:
2323 /* TODO: Set GPIO AF */
2324 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2325 wm8994->mclk[1] = freq;
2326 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2327 dai->id, freq);
2328 break;
2329
2330 case WM8994_SYSCLK_FLL1:
2331 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2332 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2333 break;
2334
2335 case WM8994_SYSCLK_FLL2:
2336 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2337 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2338 break;
2339
66b47fdb
MB		 2340 case WM8994_SYSCLK_OPCLK:
2341 /* Special case - a division (times 10) is given and
c1a4ecd9 2342 * no effect on main clocking.
66b47fdb
MB		 2343 */
2344 if (freq) {
2345 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2346 if (opclk_divs[i] == freq)
2347 break;
2348 if (i == ARRAY_SIZE(opclk_divs))
2349 return -EINVAL;
2350 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2351 WM8994_OPCLK_DIV_MASK, i);
2352 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2353 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2354 } else {
2355 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2356 WM8994_OPCLK_ENA, 0);
2357 }
2358
9e6e96a1
MB		 2359 default:
2360 return -EINVAL;
2361 }
2362
2363 configure_clock(codec);
2364
6730049a
MB		 2365 /*
2366 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2367 * for detection.
2368 */
2369 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2370 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2371 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2372 WM8994_AIF1CLK_RATE_MASK, 0x1);
2373 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2374 WM8994_AIF2CLK_RATE_MASK, 0x1);
2375 }
2376
9e6e96a1
MB		 2377 return 0;
2378}
2379
2380static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2381 enum snd_soc_bias_level level)
2382{
b6b05691 2383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2384 struct wm8994 *control = wm8994->wm8994;
b6b05691 2385
5f2f3890
MB		 2386 wm_hubs_set_bias_level(codec, level);
2387
9e6e96a1
MB		 2388 switch (level) {
2389 case SND_SOC_BIAS_ON:
2390 break;
2391
2392 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2393 /* MICBIAS into regulating mode */
2394 switch (control->type) {
2395 case WM8958:
2396 case WM1811:
2397 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2398 WM8958_MICB1_MODE, 0);
2399 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2400 WM8958_MICB2_MODE, 0);
2401 break;
2402 default:
2403 break;
2404 }
af6b6fe4
MB		 2405
2406 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2407 active_reference(codec);
9e6e96a1
MB		 2408 break;
2409
2410 case SND_SOC_BIAS_STANDBY:
ce6120cc 2411 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2412 switch (control->type) {
8bc3c2c2
MB		 2413 case WM8958:
2414 if (wm8994->revision == 0) {
2415 /* Optimise performance for rev A */
8bc3c2c2
MB		 2416 snd_soc_update_bits(codec,
2417 WM8958_CHARGE_PUMP_2,
2418 WM8958_CP_DISCH,
2419 WM8958_CP_DISCH);
2420 }
2421 break;
81204c84 2422
462835e4 2423 default:
81204c84 2424 break;
b6b05691 2425 }
9e6e96a1
MB		 2426
2427 /* Discharge LINEOUT1 & 2 */
2428 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2429 WM8994_LINEOUT1_DISCH |
2430 WM8994_LINEOUT2_DISCH,
2431 WM8994_LINEOUT1_DISCH |
2432 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2433 }
2434
af6b6fe4
MB		 2435 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2436 active_dereference(codec);
2437
500fa30e
MB		 2438 /* MICBIAS into bypass mode on newer devices */
2439 switch (control->type) {
2440 case WM8958:
2441 case WM1811:
2442 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2443 WM8958_MICB1_MODE,
2444 WM8958_MICB1_MODE);
2445 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2446 WM8958_MICB2_MODE,
2447 WM8958_MICB2_MODE);
2448 break;
2449 default:
2450 break;
2451 }
9e6e96a1
MB		 2452 break;
2453
2454 case SND_SOC_BIAS_OFF:
4105ab84 2455 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2456 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2457 break;
2458 }
5f2f3890 2459
ce6120cc 2460 codec->dapm.bias_level = level;
af6b6fe4 2461
22f8d055
MB		 2462 return 0;
2463}
2464
2465int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2466{
2467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2468
2469 switch (mode) {
2470 case WM8994_VMID_NORMAL:
2471 if (wm8994->hubs.lineout1_se) {
2472 snd_soc_dapm_disable_pin(&codec->dapm,
2473 "LINEOUT1N Driver");
2474 snd_soc_dapm_disable_pin(&codec->dapm,
2475 "LINEOUT1P Driver");
2476 }
2477 if (wm8994->hubs.lineout2_se) {
2478 snd_soc_dapm_disable_pin(&codec->dapm,
2479 "LINEOUT2N Driver");
2480 snd_soc_dapm_disable_pin(&codec->dapm,
2481 "LINEOUT2P Driver");
2482 }
2483
2484 /* Do the sync with the old mode to allow it to clean up */
2485 snd_soc_dapm_sync(&codec->dapm);
2486 wm8994->vmid_mode = mode;
2487 break;
2488
2489 case WM8994_VMID_FORCE:
2490 if (wm8994->hubs.lineout1_se) {
2491 snd_soc_dapm_force_enable_pin(&codec->dapm,
2492 "LINEOUT1N Driver");
2493 snd_soc_dapm_force_enable_pin(&codec->dapm,
2494 "LINEOUT1P Driver");
2495 }
2496 if (wm8994->hubs.lineout2_se) {
2497 snd_soc_dapm_force_enable_pin(&codec->dapm,
2498 "LINEOUT2N Driver");
2499 snd_soc_dapm_force_enable_pin(&codec->dapm,
2500 "LINEOUT2P Driver");
2501 }
2502
2503 wm8994->vmid_mode = mode;
2504 snd_soc_dapm_sync(&codec->dapm);
2505 break;
2506
2507 default:
2508 return -EINVAL;
2509 }
2510
9e6e96a1
MB		 2511 return 0;
2512}
2513
2514static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2515{
2516 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2517 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2518 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2519 int ms_reg;
2520 int aif1_reg;
2521 int ms = 0;
2522 int aif1 = 0;
2523
2524 switch (dai->id) {
2525 case 1:
2526 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2527 aif1_reg = WM8994_AIF1_CONTROL_1;
2528 break;
2529 case 2:
2530 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2531 aif1_reg = WM8994_AIF2_CONTROL_1;
2532 break;
2533 default:
2534 return -EINVAL;
2535 }
2536
2537 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2538 case SND_SOC_DAIFMT_CBS_CFS:
2539 break;
2540 case SND_SOC_DAIFMT_CBM_CFM:
2541 ms = WM8994_AIF1_MSTR;
2542 break;
2543 default:
2544 return -EINVAL;
2545 }
2546
2547 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2548 case SND_SOC_DAIFMT_DSP_B:
2549 aif1 |= WM8994_AIF1_LRCLK_INV;
2550 case SND_SOC_DAIFMT_DSP_A:
2551 aif1 |= 0x18;
2552 break;
2553 case SND_SOC_DAIFMT_I2S:
2554 aif1 |= 0x10;
2555 break;
2556 case SND_SOC_DAIFMT_RIGHT_J:
2557 break;
2558 case SND_SOC_DAIFMT_LEFT_J:
2559 aif1 |= 0x8;
2560 break;
2561 default:
2562 return -EINVAL;
2563 }
2564
2565 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2566 case SND_SOC_DAIFMT_DSP_A:
2567 case SND_SOC_DAIFMT_DSP_B:
2568 /* frame inversion not valid for DSP modes */
2569 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2570 case SND_SOC_DAIFMT_NB_NF:
2571 break;
2572 case SND_SOC_DAIFMT_IB_NF:
2573 aif1 |= WM8994_AIF1_BCLK_INV;
2574 break;
2575 default:
2576 return -EINVAL;
2577 }
2578 break;
2579
2580 case SND_SOC_DAIFMT_I2S:
2581 case SND_SOC_DAIFMT_RIGHT_J:
2582 case SND_SOC_DAIFMT_LEFT_J:
2583 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2584 case SND_SOC_DAIFMT_NB_NF:
2585 break;
2586 case SND_SOC_DAIFMT_IB_IF:
2587 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2588 break;
2589 case SND_SOC_DAIFMT_IB_NF:
2590 aif1 |= WM8994_AIF1_BCLK_INV;
2591 break;
2592 case SND_SOC_DAIFMT_NB_IF:
2593 aif1 |= WM8994_AIF1_LRCLK_INV;
2594 break;
2595 default:
2596 return -EINVAL;
2597 }
2598 break;
2599 default:
2600 return -EINVAL;
2601 }
2602
c4431df0
MB		 2603 /* The AIF2 format configuration needs to be mirrored to AIF3
2604 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2605 switch (control->type) {
2606 case WM1811:
2607 case WM8958:
2608 if (dai->id == 2)
2609 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2610 WM8994_AIF1_LRCLK_INV |
2611 WM8958_AIF3_FMT_MASK, aif1);
2612 break;
2613
2614 default:
2615 break;
2616 }
c4431df0 2617
9e6e96a1
MB		 2618 snd_soc_update_bits(codec, aif1_reg,
2619 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2620 WM8994_AIF1_FMT_MASK,
2621 aif1);
2622 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2623 ms);
2624
2625 return 0;
2626}
2627
2628static struct {
2629 int val, rate;
2630} srs[] = {
2631 { 0, 8000 },
2632 { 1, 11025 },
2633 { 2, 12000 },
2634 { 3, 16000 },
2635 { 4, 22050 },
2636 { 5, 24000 },
2637 { 6, 32000 },
2638 { 7, 44100 },
2639 { 8, 48000 },
2640 { 9, 88200 },
2641 { 10, 96000 },
2642};
2643
2644static int fs_ratios[] = {
2645 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2646};
2647
2648static int bclk_divs[] = {
2649 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2650 640, 880, 960, 1280, 1760, 1920
2651};
2652
2653static int wm8994_hw_params(struct snd_pcm_substream *substream,
2654 struct snd_pcm_hw_params *params,
2655 struct snd_soc_dai *dai)
2656{
2657 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2658 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2659 int aif1_reg;
b1e43d93 2660 int aif2_reg;
9e6e96a1
MB		 2661 int bclk_reg;
2662 int lrclk_reg;
2663 int rate_reg;
2664 int aif1 = 0;
b1e43d93 2665 int aif2 = 0;
9e6e96a1
MB		 2666 int bclk = 0;
2667 int lrclk = 0;
2668 int rate_val = 0;
2669 int id = dai->id - 1;
2670
2671 int i, cur_val, best_val, bclk_rate, best;
2672
2673 switch (dai->id) {
2674 case 1:
2675 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2676 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2677 bclk_reg = WM8994_AIF1_BCLK;
2678 rate_reg = WM8994_AIF1_RATE;
2679 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2680 wm8994->lrclk_shared[0]) {
9e6e96a1 2681 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2682 } else {
9e6e96a1 2683 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2684 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2685 }
9e6e96a1
MB		 2686 break;
2687 case 2:
2688 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2689 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2690 bclk_reg = WM8994_AIF2_BCLK;
2691 rate_reg = WM8994_AIF2_RATE;
2692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2693 wm8994->lrclk_shared[1]) {
9e6e96a1 2694 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2695 } else {
9e6e96a1 2696 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2697 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2698 }
9e6e96a1
MB		 2699 break;
2700 default:
2701 return -EINVAL;
2702 }
2703
b8edf3e5 2704 bclk_rate = params_rate(params) * 4;
9e6e96a1
MB		 2705 switch (params_format(params)) {
2706 case SNDRV_PCM_FORMAT_S16_LE:
2707 bclk_rate *= 16;
2708 break;
2709 case SNDRV_PCM_FORMAT_S20_3LE:
2710 bclk_rate *= 20;
2711 aif1 |= 0x20;
2712 break;
2713 case SNDRV_PCM_FORMAT_S24_LE:
2714 bclk_rate *= 24;
2715 aif1 |= 0x40;
2716 break;
2717 case SNDRV_PCM_FORMAT_S32_LE:
2718 bclk_rate *= 32;
2719 aif1 |= 0x60;
2720 break;
2721 default:
2722 return -EINVAL;
2723 }
2724
2725 /* Try to find an appropriate sample rate; look for an exact match. */
2726 for (i = 0; i < ARRAY_SIZE(srs); i++)
2727 if (srs[i].rate == params_rate(params))
2728 break;
2729 if (i == ARRAY_SIZE(srs))
2730 return -EINVAL;
2731 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2732
2733 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2734 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2735 dai->id, wm8994->aifclk[id], bclk_rate);
2736
b1e43d93
MB		 2737 if (params_channels(params) == 1 &&
2738 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2739 aif2 |= WM8994_AIF1_MONO;
2740
9e6e96a1
MB		 2741 if (wm8994->aifclk[id] == 0) {
2742 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2743 return -EINVAL;
2744 }
2745
2746 /* AIFCLK/fs ratio; look for a close match in either direction */
2747 best = 0;
2748 best_val = abs((fs_ratios[0] * params_rate(params))
2749 - wm8994->aifclk[id]);
2750 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2751 cur_val = abs((fs_ratios[i] * params_rate(params))
2752 - wm8994->aifclk[id]);
2753 if (cur_val >= best_val)
2754 continue;
2755 best = i;
2756 best_val = cur_val;
2757 }
2758 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2759 dai->id, fs_ratios[best]);
2760 rate_val |= best;
2761
2762 /* We may not get quite the right frequency if using
2763 * approximate clocks so look for the closest match that is
2764 * higher than the target (we need to ensure that there enough
2765 * BCLKs to clock out the samples).
2766 */
2767 best = 0;
2768 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2769 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2770 if (cur_val < 0) /* BCLK table is sorted */
2771 break;
2772 best = i;
2773 }
07cd8ada 2774 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2775 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2776 bclk_divs[best], bclk_rate);
2777 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2778
2779 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2780 if (!lrclk) {
2781 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2782 bclk_rate);
2783 return -EINVAL;
2784 }
9e6e96a1
MB		 2785 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2786 lrclk, bclk_rate / lrclk);
2787
2788 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2789 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2790 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2791 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2792 lrclk);
2793 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2794 WM8994_AIF1CLK_RATE_MASK, rate_val);
2795
2796 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2797 switch (dai->id) {
2798 case 1:
2799 wm8994->dac_rates[0] = params_rate(params);
2800 wm8994_set_retune_mobile(codec, 0);
2801 wm8994_set_retune_mobile(codec, 1);
2802 break;
2803 case 2:
2804 wm8994->dac_rates[1] = params_rate(params);
2805 wm8994_set_retune_mobile(codec, 2);
2806 break;
2807 }
2808 }
2809
2810 return 0;
2811}
2812
c4431df0
MB		 2813static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2814 struct snd_pcm_hw_params *params,
2815 struct snd_soc_dai *dai)
2816{
2817 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2818 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2819 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2820 int aif1_reg;
2821 int aif1 = 0;
2822
2823 switch (dai->id) {
2824 case 3:
2825 switch (control->type) {
81204c84 2826 case WM1811:
c4431df0
MB		 2827 case WM8958:
2828 aif1_reg = WM8958_AIF3_CONTROL_1;
2829 break;
2830 default:
2831 return 0;
2832 }
2833 default:
2834 return 0;
2835 }
2836
2837 switch (params_format(params)) {
2838 case SNDRV_PCM_FORMAT_S16_LE:
2839 break;
2840 case SNDRV_PCM_FORMAT_S20_3LE:
2841 aif1 |= 0x20;
2842 break;
2843 case SNDRV_PCM_FORMAT_S24_LE:
2844 aif1 |= 0x40;
2845 break;
2846 case SNDRV_PCM_FORMAT_S32_LE:
2847 aif1 |= 0x60;
2848 break;
2849 default:
2850 return -EINVAL;
2851 }
2852
2853 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2854}
2855
9e6e96a1
MB		 2856static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2857{
2858 struct snd_soc_codec *codec = codec_dai->codec;
2859 int mute_reg;
2860 int reg;
2861
2862 switch (codec_dai->id) {
2863 case 1:
2864 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2865 break;
2866 case 2:
2867 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2868 break;
2869 default:
2870 return -EINVAL;
2871 }
2872
2873 if (mute)
2874 reg = WM8994_AIF1DAC1_MUTE;
2875 else
2876 reg = 0;
2877
2878 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2879
2880 return 0;
2881}
2882
778a76e2
MB		 2883static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2884{
2885 struct snd_soc_codec *codec = codec_dai->codec;
2886 int reg, val, mask;
2887
2888 switch (codec_dai->id) {
2889 case 1:
2890 reg = WM8994_AIF1_MASTER_SLAVE;
2891 mask = WM8994_AIF1_TRI;
2892 break;
2893 case 2:
2894 reg = WM8994_AIF2_MASTER_SLAVE;
2895 mask = WM8994_AIF2_TRI;
2896 break;
778a76e2
MB		 2897 default:
2898 return -EINVAL;
2899 }
2900
2901 if (tristate)
2902 val = mask;
2903 else
2904 val = 0;
2905
78b3fb46 2906 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2907}
2908
d09f3ecf
MB		 2909static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2910{
2911 struct snd_soc_codec *codec = dai->codec;
2912
2913 /* Disable the pulls on the AIF if we're using it to save power. */
2914 snd_soc_update_bits(codec, WM8994_GPIO_3,
2915 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2916 snd_soc_update_bits(codec, WM8994_GPIO_4,
2917 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2918 snd_soc_update_bits(codec, WM8994_GPIO_5,
2919 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2920
2921 return 0;
2922}
2923
9e6e96a1
MB		 2924#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2925
2926#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2927 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2928
85e7652d 2929static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2930 .set_sysclk = wm8994_set_dai_sysclk,
2931 .set_fmt = wm8994_set_dai_fmt,
2932 .hw_params = wm8994_hw_params,
2933 .digital_mute = wm8994_aif_mute,
2934 .set_pll = wm8994_set_fll,
778a76e2 2935 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2936};
2937
85e7652d 2938static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2939 .set_sysclk = wm8994_set_dai_sysclk,
2940 .set_fmt = wm8994_set_dai_fmt,
2941 .hw_params = wm8994_hw_params,
2942 .digital_mute = wm8994_aif_mute,
2943 .set_pll = wm8994_set_fll,
778a76e2
MB		 2944 .set_tristate = wm8994_set_tristate,
2945};
2946
85e7652d 2947static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2948 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 2949};
2950
f0fba2ad 2951static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2952 {
f0fba2ad 2953 .name = "wm8994-aif1",
8c7f78b3 2954 .id = 1,
9e6e96a1
MB		 2955 .playback = {
2956 .stream_name = "AIF1 Playback",
b1e43d93 2957 .channels_min = 1,
9e6e96a1
MB		 2958 .channels_max = 2,
2959 .rates = WM8994_RATES,
2960 .formats = WM8994_FORMATS,
99b0292d 2961 .sig_bits = 24,
9e6e96a1
MB		 2962 },
2963 .capture = {
2964 .stream_name = "AIF1 Capture",
b1e43d93 2965 .channels_min = 1,
9e6e96a1
MB		 2966 .channels_max = 2,
2967 .rates = WM8994_RATES,
2968 .formats = WM8994_FORMATS,
99b0292d 2969 .sig_bits = 24,
9e6e96a1
MB		 2970 },
2971 .ops = &wm8994_aif1_dai_ops,
2972 },
2973 {
f0fba2ad 2974 .name = "wm8994-aif2",
8c7f78b3 2975 .id = 2,
9e6e96a1
MB		 2976 .playback = {
2977 .stream_name = "AIF2 Playback",
b1e43d93 2978 .channels_min = 1,
9e6e96a1
MB		 2979 .channels_max = 2,
2980 .rates = WM8994_RATES,
2981 .formats = WM8994_FORMATS,
99b0292d 2982 .sig_bits = 24,
9e6e96a1
MB		 2983 },
2984 .capture = {
2985 .stream_name = "AIF2 Capture",
b1e43d93 2986 .channels_min = 1,
9e6e96a1
MB		 2987 .channels_max = 2,
2988 .rates = WM8994_RATES,
2989 .formats = WM8994_FORMATS,
99b0292d 2990 .sig_bits = 24,
9e6e96a1 2991 },
d09f3ecf 2992 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2993 .ops = &wm8994_aif2_dai_ops,
2994 },
2995 {
f0fba2ad 2996 .name = "wm8994-aif3",
8c7f78b3 2997 .id = 3,
9e6e96a1
MB		 2998 .playback = {
2999 .stream_name = "AIF3 Playback",
b1e43d93 3000 .channels_min = 1,
9e6e96a1
MB		 3001 .channels_max = 2,
3002 .rates = WM8994_RATES,
3003 .formats = WM8994_FORMATS,
99b0292d 3004 .sig_bits = 24,
9e6e96a1 3005 },
a8462bde 3006 .capture = {
9e6e96a1 3007 .stream_name = "AIF3 Capture",
b1e43d93 3008 .channels_min = 1,
9e6e96a1
MB		 3009 .channels_max = 2,
3010 .rates = WM8994_RATES,
3011 .formats = WM8994_FORMATS,
99b0292d
MB		 3012 .sig_bits = 24,
3013 },
778a76e2 3014 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 3015 }
3016};
9e6e96a1
MB		 3017
3018#ifdef CONFIG_PM
4752a887 3019static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3020{
b2c812e2 3021 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3022 int i, ret;
3023
3024 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3025 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3026 sizeof(struct wm8994_fll_config));
f0fba2ad 3027 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 3028 if (ret < 0)
3029 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3030 i + 1, ret);
3031 }
3032
3033 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3034
3035 return 0;
3036}
3037
4752a887 3038static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3039{
b2c812e2 3040 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3041 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 3042 int i, ret;
c52fd021
DP		 3043 unsigned int val, mask;
3044
3045 if (wm8994->revision < 4) {
3046 /* force a HW read */
d9a7666f
MB		 3047 ret = regmap_read(control->regmap,
3048 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 3049
3050 /* modify the cache only */
3051 codec->cache_only = 1;
3052 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3053 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3054 val &= mask;
3055 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3056 mask, val);
3057 codec->cache_only = 0;
3058 }
9e6e96a1 3059
9e6e96a1 3060 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3061 if (!wm8994->fll_suspend[i].out)
3062 continue;
3063
f0fba2ad 3064 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3065 wm8994->fll_suspend[i].src,
3066 wm8994->fll_suspend[i].in,
3067 wm8994->fll_suspend[i].out);
3068 if (ret < 0)
3069 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3070 i + 1, ret);
3071 }
3072
3073 return 0;
3074}
3075#else
4752a887
MB		 3076#define wm8994_codec_suspend NULL
3077#define wm8994_codec_resume NULL
9e6e96a1
MB		 3078#endif
3079
3080static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3081{
8cb8e83b 3082 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3083 struct wm8994 *control = wm8994->wm8994;
3084 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3085 struct snd_kcontrol_new controls[] = {
3086 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3087 wm8994->retune_mobile_enum,
3088 wm8994_get_retune_mobile_enum,
3089 wm8994_put_retune_mobile_enum),
3090 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3091 wm8994->retune_mobile_enum,
3092 wm8994_get_retune_mobile_enum,
3093 wm8994_put_retune_mobile_enum),
3094 SOC_ENUM_EXT("AIF2 EQ Mode",
3095 wm8994->retune_mobile_enum,
3096 wm8994_get_retune_mobile_enum,
3097 wm8994_put_retune_mobile_enum),
3098 };
3099 int ret, i, j;
3100 const char **t;
3101
3102 /* We need an array of texts for the enum API but the number
3103 * of texts is likely to be less than the number of
3104 * configurations due to the sample rate dependency of the
3105 * configurations. */
3106 wm8994->num_retune_mobile_texts = 0;
3107 wm8994->retune_mobile_texts = NULL;
3108 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3109 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3110 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3111 wm8994->retune_mobile_texts[j]) == 0)
3112 break;
3113 }
3114
3115 if (j != wm8994->num_retune_mobile_texts)
3116 continue;
3117
3118 /* Expand the array... */
3119 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3120 sizeof(char *) *
9e6e96a1
MB		 3121 (wm8994->num_retune_mobile_texts + 1),
3122 GFP_KERNEL);
3123 if (t == NULL)
3124 continue;
3125
3126 /* ...store the new entry... */
c1a4ecd9 3127 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3128 pdata->retune_mobile_cfgs[i].name;
3129
3130 /* ...and remember the new version. */
3131 wm8994->num_retune_mobile_texts++;
3132 wm8994->retune_mobile_texts = t;
3133 }
3134
3135 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3136 wm8994->num_retune_mobile_texts);
3137
3138 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3139 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3140
8cb8e83b 3141 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB		 3142 ARRAY_SIZE(controls));
3143 if (ret != 0)
8cb8e83b 3144 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3145 "Failed to add ReTune Mobile controls: %d\n", ret);
3146}
3147
3148static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3149{
8cb8e83b 3150 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3151 struct wm8994 *control = wm8994->wm8994;
3152 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3153 int ret, i;
3154
3155 if (!pdata)
3156 return;
3157
3158 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3159 pdata->lineout2_diff,
3160 pdata->lineout1fb,
3161 pdata->lineout2fb,
3162 pdata->jd_scthr,
3163 pdata->jd_thr,
02e79476
MB		 3164 pdata->micb1_delay,
3165 pdata->micb2_delay,
9e6e96a1
MB		 3166 pdata->micbias1_lvl,
3167 pdata->micbias2_lvl);
3168
3169 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3170
3171 if (pdata->num_drc_cfgs) {
3172 struct snd_kcontrol_new controls[] = {
3173 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3174 wm8994_get_drc_enum, wm8994_put_drc_enum),
3175 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3176 wm8994_get_drc_enum, wm8994_put_drc_enum),
3177 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3178 wm8994_get_drc_enum, wm8994_put_drc_enum),
3179 };
3180
3181 /* We need an array of texts for the enum API */
8cb8e83b 3182 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3183 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3184 if (!wm8994->drc_texts) {
8cb8e83b 3185 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3186 "Failed to allocate %d DRC config texts\n",
3187 pdata->num_drc_cfgs);
3188 return;
3189 }
3190
3191 for (i = 0; i < pdata->num_drc_cfgs; i++)
3192 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3193
3194 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3195 wm8994->drc_enum.texts = wm8994->drc_texts;
3196
8cb8e83b 3197 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3198 ARRAY_SIZE(controls));
9e6e96a1
MB		 3199 for (i = 0; i < WM8994_NUM_DRC; i++)
3200 wm8994_set_drc(codec, i);
45a690f6
MB		 3201 } else {
3202 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3203 wm8994_drc_controls,
3204 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB		 3205 }
3206
45a690f6
MB		 3207 if (ret != 0)
3208 dev_err(wm8994->hubs.codec->dev,
3209 "Failed to add DRC mode controls: %d\n", ret);
3210
3211
9e6e96a1
MB		 3212 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3213 pdata->num_retune_mobile_cfgs);
3214
3215 if (pdata->num_retune_mobile_cfgs)
3216 wm8994_handle_retune_mobile_pdata(wm8994);
3217 else
8cb8e83b 3218 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3219 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3220
3221 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3222 if (pdata->micbias[i]) {
3223 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3224 pdata->micbias[i] & 0xffff);
3225 }
3226 }
9e6e96a1
MB		 3227}
3228
88766984
MB		 3229/**
3230 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3231 *
3232 * @codec: WM8994 codec
3233 * @jack: jack to report detection events on
3234 * @micbias: microphone bias to detect on
88766984
MB		 3235 *
3236 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3237 * being used to bring out signals to the processor then only platform
5ab230a7 3238 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3239 * be configured using snd_soc_jack_add_gpios() instead.
3240 *
3241 * Configuration of detection levels is available via the micbias1_lvl
3242 * and micbias2_lvl platform data members.
3243 */
3244int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3245 int micbias)
88766984 3246{
b2c812e2 3247 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3248 struct wm8994_micdet *micdet;
2a8a856d 3249 struct wm8994 *control = wm8994->wm8994;
87092e3c 3250 int reg, ret;
88766984 3251
87092e3c
MB		 3252 if (control->type != WM8994) {
3253 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3254 return -EINVAL;
87092e3c 3255 }
3a423157 3256
88766984
MB		 3257 switch (micbias) {
3258 case 1:
3259 micdet = &wm8994->micdet[0];
87092e3c
MB		 3260 if (jack)
3261 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3262 "MICBIAS1");
3263 else
3264 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3265 "MICBIAS1");
88766984
MB		 3266 break;
3267 case 2:
3268 micdet = &wm8994->micdet[1];
87092e3c
MB		 3269 if (jack)
3270 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3271 "MICBIAS1");
3272 else
3273 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3274 "MICBIAS1");
88766984
MB		 3275 break;
3276 default:
87092e3c 3277 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3278 return -EINVAL;
87092e3c 3279 }
88766984 3280
87092e3c
MB		 3281 if (ret != 0)
3282 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3283 micbias, ret);
3284
3285 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3286 micbias, jack);
88766984
MB		 3287
3288 /* Store the configuration */
3289 micdet->jack = jack;
87092e3c 3290 micdet->detecting = true;
88766984
MB		 3291
3292 /* If either of the jacks is set up then enable detection */
3293 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3294 reg = WM8994_MICD_ENA;
87092e3c 3295 else
88766984
MB		 3296 reg = 0;
3297
3298 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3299
d9f34df7
CR		 3300 /* enable MICDET and MICSHRT deboune */
3301 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3302 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3303 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3304 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3305
87092e3c
MB		 3306 snd_soc_dapm_sync(&codec->dapm);
3307
88766984
MB		 3308 return 0;
3309}
3310EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3311
e9b54de4 3312static void wm8994_mic_work(struct work_struct *work)
88766984 3313{
e9b54de4
MB		 3314 struct wm8994_priv *priv = container_of(work,
3315 struct wm8994_priv,
3316 mic_work.work);
fdfc4f3e
MB		 3317 struct regmap *regmap = priv->wm8994->regmap;
3318 struct device *dev = priv->wm8994->dev;
3319 unsigned int reg;
3320 int ret;
88766984
MB		 3321 int report;
3322
b8176627
MB		 3323 pm_runtime_get_sync(dev);
3324
fdfc4f3e
MB		 3325 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3326 if (ret < 0) {
3327 dev_err(dev, "Failed to read microphone status: %d\n",
3328 ret);
b8176627 3329 pm_runtime_put(dev);
e9b54de4 3330 return;
88766984
MB		 3331 }
3332
fdfc4f3e 3333 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3334
3335 report = 0;
87092e3c
MB		 3336 if (reg & WM8994_MIC1_DET_STS) {
3337 if (priv->micdet[0].detecting)
3338 report = SND_JACK_HEADSET;
3339 }
3340 if (reg & WM8994_MIC1_SHRT_STS) {
3341 if (priv->micdet[0].detecting)
3342 report = SND_JACK_HEADPHONE;
3343 else
3344 report |= SND_JACK_BTN_0;
3345 }
3346 if (report)
3347 priv->micdet[0].detecting = false;
3348 else
3349 priv->micdet[0].detecting = true;
3350
88766984 3351 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3352 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3353
3354 report = 0;
87092e3c
MB		 3355 if (reg & WM8994_MIC2_DET_STS) {
3356 if (priv->micdet[1].detecting)
3357 report = SND_JACK_HEADSET;
3358 }
3359 if (reg & WM8994_MIC2_SHRT_STS) {
3360 if (priv->micdet[1].detecting)
3361 report = SND_JACK_HEADPHONE;
3362 else
3363 report |= SND_JACK_BTN_0;
3364 }
3365 if (report)
3366 priv->micdet[1].detecting = false;
3367 else
3368 priv->micdet[1].detecting = true;
3369
88766984 3370 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3371 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB		 3372
3373 pm_runtime_put(dev);
e9b54de4
MB		 3374}
3375
3376static irqreturn_t wm8994_mic_irq(int irq, void *data)
3377{
3378 struct wm8994_priv *priv = data;
8cb8e83b 3379 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB		 3380
3381#ifndef CONFIG_SND_SOC_WM8994_MODULE
3382 trace_snd_soc_jack_irq(dev_name(codec->dev));
3383#endif
3384
3385 pm_wakeup_event(codec->dev, 300);
3386
3387 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3388
3389 return IRQ_HANDLED;
3390}
3391
821edd2f
MB		 3392/* Default microphone detection handler for WM8958 - the user can
3393 * override this if they wish.
3394 */
3395static void wm8958_default_micdet(u16 status, void *data)
3396{
3397 struct snd_soc_codec *codec = data;
3398 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3399 int report;
821edd2f 3400
a1691343
MB		 3401 dev_dbg(codec->dev, "MICDET %x\n", status);
3402
af6b6fe4 3403 /* Either nothing present or just starting detection */
b00adf76 3404 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3405 if (!wm8994->jackdet) {
3406 /* If nothing present then clear our statuses */
3407 dev_dbg(codec->dev, "Detected open circuit\n");
3408 wm8994->jack_mic = false;
3409 wm8994->mic_detecting = true;
b00adf76 3410
af6b6fe4 3411 wm8958_micd_set_rate(codec);
b00adf76 3412
af6b6fe4
MB		 3413 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3414 wm8994->btn_mask |
7435d4ee 3415 SND_JACK_HEADSET);
af6b6fe4 3416 }
b00adf76
MB		 3417 return;
3418 }
821edd2f 3419
b00adf76
MB		 3420 /* If the measurement is showing a high impedence we've got a
3421 * microphone.
3422 */
157a75e6 3423 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3424 dev_dbg(codec->dev, "Detected microphone\n");
3425
157a75e6 3426 wm8994->mic_detecting = false;
b00adf76
MB		 3427 wm8994->jack_mic = true;
3428
3429 wm8958_micd_set_rate(codec);
3430
3431 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3432 SND_JACK_HEADSET);
3433 }
821edd2f 3434
b00adf76 3435
7c08b51f 3436 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3437 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3438 wm8994->mic_detecting = false;
b00adf76
MB		 3439
3440 wm8958_micd_set_rate(codec);
3441
af6b6fe4
MB		 3442 /* If we have jackdet that will detect removal */
3443 if (wm8994->jackdet) {
c986564b
MB		 3444 mutex_lock(&wm8994->accdet_lock);
3445
af6b6fe4
MB		 3446 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3447 WM8958_MICD_ENA, 0);
3448
c986564b
MB		 3449 wm1811_jackdet_set_mode(codec,
3450 WM1811_JACKDET_MODE_JACK);
3451
3452 mutex_unlock(&wm8994->accdet_lock);
3453
d9dd4ada 3454 if (wm8994->wm8994->pdata.jd_ext_cap)
07fb9d9e
MB		 3455 snd_soc_dapm_disable_pin(&codec->dapm,
3456 "MICBIAS2");
af6b6fe4 3457 }
ecd1732f
MB		 3458
3459 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3460 SND_JACK_HEADSET);
b00adf76
MB		 3461 }
3462
3463 /* Report short circuit as a button */
3464 if (wm8994->jack_mic) {
4585790d 3465 report = 0;
b00adf76 3466 if (status & 0x4)
4585790d
MB		 3467 report |= SND_JACK_BTN_0;
3468
3469 if (status & 0x8)
3470 report |= SND_JACK_BTN_1;
3471
3472 if (status & 0x10)
3473 report |= SND_JACK_BTN_2;
3474
3475 if (status & 0x20)
3476 report |= SND_JACK_BTN_3;
3477
3478 if (status & 0x40)
3479 report |= SND_JACK_BTN_4;
3480
3481 if (status & 0x80)
3482 report |= SND_JACK_BTN_5;
3483
3484 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3485 wm8994->btn_mask);
b00adf76 3486 }
821edd2f
MB		 3487}
3488
c0cc3f16
MB		 3489/* Deferred mic detection to allow for extra settling time */
3490static void wm1811_mic_work(struct work_struct *work)
3491{
3492 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3493 mic_work.work);
d9dd4ada 3494 struct wm8994 *control = wm8994->wm8994;
c0cc3f16
MB		 3495 struct snd_soc_codec *codec = wm8994->hubs.codec;
3496
3497 pm_runtime_get_sync(codec->dev);
3498
3499 /* If required for an external cap force MICBIAS on */
d9dd4ada 3500 if (control->pdata.jd_ext_cap) {
c0cc3f16
MB		 3501 snd_soc_dapm_force_enable_pin(&codec->dapm,
3502 "MICBIAS2");
3503 snd_soc_dapm_sync(&codec->dapm);
3504 }
3505
3506 mutex_lock(&wm8994->accdet_lock);
3507
3508 dev_dbg(codec->dev, "Starting mic detection\n");
3509
3510 /*
3511 * Start off measument of microphone impedence to find out
3512 * what's actually there.
3513 */
3514 wm8994->mic_detecting = true;
3515 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3516
3517 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3518 WM8958_MICD_ENA, WM8958_MICD_ENA);
3519
3520 mutex_unlock(&wm8994->accdet_lock);
3521
3522 pm_runtime_put(codec->dev);
3523}
3524
af6b6fe4
MB		 3525static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3526{
3527 struct wm8994_priv *wm8994 = data;
d9dd4ada 3528 struct wm8994 *control = wm8994->wm8994;
8cb8e83b 3529 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3530 int reg, delay;
c986564b 3531 bool present;
af6b6fe4 3532
b8176627
MB		 3533 pm_runtime_get_sync(codec->dev);
3534
af6b6fe4
MB		 3535 mutex_lock(&wm8994->accdet_lock);
3536
3537 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3538 if (reg < 0) {
3539 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3540 mutex_unlock(&wm8994->accdet_lock);
b8176627 3541 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3542 return IRQ_NONE;
3543 }
3544
3545 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3546
c986564b 3547 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3548
c986564b
MB		 3549 if (present) {
3550 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3551
e9d9a968
MB		 3552 wm8958_micd_set_rate(codec);
3553
55a27786
MB		 3554 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3555 WM8958_MICB2_DISCH, 0);
3556
378ec0ca
MB		 3557 /* Disable debounce while inserted */
3558 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3559 WM1811_JACKDET_DB, 0);
3560
d9dd4ada 3561 delay = control->pdata.micdet_delay;
c0cc3f16
MB		 3562 schedule_delayed_work(&wm8994->mic_work,
3563 msecs_to_jiffies(delay));
af6b6fe4
MB		 3564 } else {
3565 dev_dbg(codec->dev, "Jack not detected\n");
3566
c0cc3f16
MB		 3567 cancel_delayed_work_sync(&wm8994->mic_work);
3568
55a27786
MB		 3569 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3570 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3571
378ec0ca
MB		 3572 /* Enable debounce while removed */
3573 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3574 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3575
af6b6fe4
MB		 3576 wm8994->mic_detecting = false;
3577 wm8994->jack_mic = false;
3578 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3579 WM8958_MICD_ENA, 0);
3580 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3581 }
3582
3583 mutex_unlock(&wm8994->accdet_lock);
3584
c0cc3f16 3585 /* Turn off MICBIAS if it was on for an external cap */
d9dd4ada 3586 if (control->pdata.jd_ext_cap && !present)
c0cc3f16 3587 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3588
3589 if (present)
3590 snd_soc_jack_report(wm8994->micdet[0].jack,
3591 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3592 else
3593 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3594 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3595 wm8994->btn_mask);
3596
99af79df
MB		 3597 /* Since we only report deltas force an update, ensures we
3598 * avoid bootstrapping issues with the core. */
3599 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3600
b8176627 3601 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3602 return IRQ_HANDLED;
3603}
3604
99af79df
MB		 3605static void wm1811_jackdet_bootstrap(struct work_struct *work)
3606{
3607 struct wm8994_priv *wm8994 = container_of(work,
3608 struct wm8994_priv,
3609 jackdet_bootstrap.work);
3610 wm1811_jackdet_irq(0, wm8994);
3611}
3612
821edd2f
MB		 3613/**
3614 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3615 *
3616 * @codec: WM8958 codec
3617 * @jack: jack to report detection events on
3618 *
3619 * Enable microphone detection functionality for the WM8958. By
3620 * default simple detection which supports the detection of up to 6
3621 * buttons plus video and microphone functionality is supported.
3622 *
3623 * The WM8958 has an advanced jack detection facility which is able to
3624 * support complex accessory detection, especially when used in
3625 * conjunction with external circuitry. In order to provide maximum
3626 * flexiblity a callback is provided which allows a completely custom
3627 * detection algorithm.
3628 */
3629int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3630 wm8958_micdet_cb cb, void *cb_data)
3631{
3632 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3633 struct wm8994 *control = wm8994->wm8994;
4585790d 3634 u16 micd_lvl_sel;
821edd2f 3635
81204c84
MB		 3636 switch (control->type) {
3637 case WM1811:
3638 case WM8958:
3639 break;
3640 default:
821edd2f 3641 return -EINVAL;
81204c84 3642 }
821edd2f
MB		 3643
3644 if (jack) {
3645 if (!cb) {
3646 dev_dbg(codec->dev, "Using default micdet callback\n");
3647 cb = wm8958_default_micdet;
3648 cb_data = codec;
3649 }
3650
4cdf5e49 3651 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3652 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3653
821edd2f
MB		 3654 wm8994->micdet[0].jack = jack;
3655 wm8994->jack_cb = cb;
3656 wm8994->jack_cb_data = cb_data;
3657
157a75e6 3658 wm8994->mic_detecting = true;
b00adf76
MB		 3659 wm8994->jack_mic = false;
3660
3661 wm8958_micd_set_rate(codec);
3662
4585790d 3663 /* Detect microphones and short circuits by default */
d9dd4ada
MB		 3664 if (control->pdata.micd_lvl_sel)
3665 micd_lvl_sel = control->pdata.micd_lvl_sel;
4585790d
MB		 3666 else
3667 micd_lvl_sel = 0x41;
3668
3669 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3670 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3671 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3672
b00adf76 3673 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3674 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3675
af6b6fe4
MB		 3676 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3677
3678 /*
3679 * If we can use jack detection start off with that,
3680 * otherwise jump straight to microphone detection.
3681 */
3682 if (wm8994->jackdet) {
99af79df
MB		 3683 /* Disable debounce for the initial detect */
3684 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3685 WM1811_JACKDET_DB, 0);
3686
55a27786
MB		 3687 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3688 WM8958_MICB2_DISCH,
3689 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3690 snd_soc_update_bits(codec, WM8994_LDO_1,
3691 WM8994_LDO1_DISCH, 0);
3692 wm1811_jackdet_set_mode(codec,
3693 WM1811_JACKDET_MODE_JACK);
3694 } else {
3695 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3696 WM8958_MICD_ENA, WM8958_MICD_ENA);
3697 }
3698
821edd2f
MB		 3699 } else {
3700 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3701 WM8958_MICD_ENA, 0);
afaf1591 3702 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3703 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3704 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3705 }
3706
3707 return 0;
3708}
3709EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3710
3711static irqreturn_t wm8958_mic_irq(int irq, void *data)
3712{
3713 struct wm8994_priv *wm8994 = data;
8cb8e83b 3714 struct snd_soc_codec *codec = wm8994->hubs.codec;
19940b3d 3715 int reg, count;
821edd2f 3716
af6b6fe4
MB		 3717 /*
3718 * Jack detection may have detected a removal simulataneously
3719 * with an update of the MICDET status; if so it will have
3720 * stopped detection and we can ignore this interrupt.
3721 */
c986564b 3722 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3723 return IRQ_HANDLED;
af6b6fe4 3724
b8176627
MB		 3725 pm_runtime_get_sync(codec->dev);
3726
19940b3d
MB		 3727 /* We may occasionally read a detection without an impedence
3728 * range being provided - if that happens loop again.
3729 */
3730 count = 10;
3731 do {
3732 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3733 if (reg < 0) {
3734 dev_err(codec->dev,
3735 "Failed to read mic detect status: %d\n",
3736 reg);
b8176627 3737 pm_runtime_put(codec->dev);
19940b3d
MB		 3738 return IRQ_NONE;
3739 }
821edd2f 3740
19940b3d
MB		 3741 if (!(reg & WM8958_MICD_VALID)) {
3742 dev_dbg(codec->dev, "Mic detect data not valid\n");
3743 goto out;
3744 }
3745
3746 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3747 break;
3748
3749 msleep(1);
3750 } while (count--);
3751
3752 if (count == 0)
3753 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3754
7116f452 3755#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3756 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3757#endif
2bbb5d66 3758
821edd2f
MB		 3759 if (wm8994->jack_cb)
3760 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3761 else
3762 dev_warn(codec->dev, "Accessory detection with no callback\n");
3763
3764out:
b8176627 3765 pm_runtime_put(codec->dev);
821edd2f
MB		 3766 return IRQ_HANDLED;
3767}
3768
3b1af3f8
MB		 3769static irqreturn_t wm8994_fifo_error(int irq, void *data)
3770{
3771 struct snd_soc_codec *codec = data;
3772
3773 dev_err(codec->dev, "FIFO error\n");
3774
3775 return IRQ_HANDLED;
3776}
3777
f0b182b0
MB		 3778static irqreturn_t wm8994_temp_warn(int irq, void *data)
3779{
3780 struct snd_soc_codec *codec = data;
3781
3782 dev_err(codec->dev, "Thermal warning\n");
3783
3784 return IRQ_HANDLED;
3785}
3786
3787static irqreturn_t wm8994_temp_shut(int irq, void *data)
3788{
3789 struct snd_soc_codec *codec = data;
3790
3791 dev_crit(codec->dev, "Thermal shutdown\n");
3792
3793 return IRQ_HANDLED;
3794}
3795
f0fba2ad 3796static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3797{
d9a7666f 3798 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3799 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3800 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3801 unsigned int reg;
ec62dbd7 3802 int ret, i;
9e6e96a1 3803
8cb8e83b 3804 wm8994->hubs.codec = codec;
d9a7666f 3805 codec->control_data = control->regmap;
9e6e96a1 3806
d9a7666f 3807 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3808
af6b6fe4 3809 mutex_init(&wm8994->accdet_lock);
99af79df
MB		 3810 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3811 wm1811_jackdet_bootstrap);
af6b6fe4 3812
c0cc3f16
MB		 3813 switch (control->type) {
3814 case WM8994:
3815 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3816 break;
3817 case WM1811:
3818 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3819 break;
3820 default:
3821 break;
3822 }
3823
c7ebf932
MB		 3824 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3825 init_completion(&wm8994->fll_locked[i]);
3826
d9dd4ada 3827 wm8994->micdet_irq = control->pdata.micdet_irq;
9b7c525d 3828
39fb51a1 3829 pm_runtime_enable(codec->dev);
5fab5174 3830 pm_runtime_idle(codec->dev);
39fb51a1 3831
f959dee9
MB		 3832 /* By default use idle_bias_off, will override for WM8994 */
3833 codec->dapm.idle_bias_off = 1;
3834
9e6e96a1 3835 /* Set revision-specific configuration */
b6b05691 3836 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3837 switch (control->type) {
3838 case WM8994:
f959dee9 3839 /* Single ended line outputs should have VMID on. */
d9dd4ada
MB		 3840 if (!control->pdata.lineout1_diff ||
3841 !control->pdata.lineout2_diff)
f959dee9
MB		 3842 codec->dapm.idle_bias_off = 0;
3843
3a423157
MB		 3844 switch (wm8994->revision) {
3845 case 2:
3846 case 3:
4537c4e7
MB		 3847 wm8994->hubs.dcs_codes_l = -5;
3848 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3849 wm8994->hubs.hp_startup_mode = 1;
3850 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3851 wm8994->hubs.series_startup = 1;
3a423157
MB		 3852 break;
3853 default:
79ef0abc 3854 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3855 break;
3856 }
280ec8b7 3857 break;
3a423157
MB		 3858
3859 case WM8958:
8437f700 3860 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3861 wm8994->hubs.hp_startup_mode = 1;
20dc24a9
MB		 3862
3863 switch (wm8994->revision) {
3864 case 0:
3865 break;
3866 default:
3867 wm8994->fll_byp = true;
3868 break;
3869 }
9e6e96a1 3870 break;
3a423157 3871
81204c84
MB		 3872 case WM1811:
3873 wm8994->hubs.dcs_readback_mode = 2;
3874 wm8994->hubs.no_series_update = 1;
29fdc360 3875 wm8994->hubs.hp_startup_mode = 1;
af31a227 3876 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 3877 wm8994->fll_byp = true;
81204c84 3878
72222be3
MB		 3879 wm8994->hubs.dcs_codes_l = -9;
3880 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 3881
3882 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3883 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3884 break;
3885
9e6e96a1
MB		 3886 default:
3887 break;
3888 }
9e6e96a1 3889
2a8a856d 3890 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3891 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3892 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3893 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3894 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3895 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3896
2a8a856d 3897 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3898 wm_hubs_dcs_done, "DC servo done",
3899 &wm8994->hubs);
3900 if (ret == 0)
3901 wm8994->hubs.dcs_done_irq = true;
3902
3a423157
MB		 3903 switch (control->type) {
3904 case WM8994:
9b7c525d
MB		 3905 if (wm8994->micdet_irq) {
3906 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3907 wm8994_mic_irq,
3908 IRQF_TRIGGER_RISING,
3909 "Mic1 detect",
3910 wm8994);
3911 if (ret != 0)
3912 dev_warn(codec->dev,
3913 "Failed to request Mic1 detect IRQ: %d\n",
3914 ret);
3915 }
3a423157 3916
2a8a856d 3917 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3918 WM8994_IRQ_MIC1_SHRT,
3919 wm8994_mic_irq, "Mic 1 short",
3920 wm8994);
3921 if (ret != 0)
3922 dev_warn(codec->dev,
3923 "Failed to request Mic1 short IRQ: %d\n",
3924 ret);
3925
2a8a856d 3926 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3927 WM8994_IRQ_MIC2_DET,
3928 wm8994_mic_irq, "Mic 2 detect",
3929 wm8994);
3930 if (ret != 0)
3931 dev_warn(codec->dev,
3932 "Failed to request Mic2 detect IRQ: %d\n",
3933 ret);
3934
2a8a856d 3935 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3936 WM8994_IRQ_MIC2_SHRT,
3937 wm8994_mic_irq, "Mic 2 short",
3938 wm8994);
3939 if (ret != 0)
3940 dev_warn(codec->dev,
3941 "Failed to request Mic2 short IRQ: %d\n",
3942 ret);
3943 break;
821edd2f
MB		 3944
3945 case WM8958:
81204c84 3946 case WM1811:
9b7c525d
MB		 3947 if (wm8994->micdet_irq) {
3948 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3949 wm8958_mic_irq,
3950 IRQF_TRIGGER_RISING,
3951 "Mic detect",
3952 wm8994);
3953 if (ret != 0)
3954 dev_warn(codec->dev,
3955 "Failed to request Mic detect IRQ: %d\n",
3956 ret);
b4046d01
MB		 3957 } else {
3958 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3959 wm8958_mic_irq, "Mic detect",
3960 wm8994);
9b7c525d 3961 }
3a423157 3962 }
88766984 3963
af6b6fe4
MB		 3964 switch (control->type) {
3965 case WM1811:
52ca1138 3966 if (control->cust_id > 1 || wm8994->revision > 1) {
af6b6fe4
MB		 3967 ret = wm8994_request_irq(wm8994->wm8994,
3968 WM8994_IRQ_GPIO(6),
3969 wm1811_jackdet_irq, "JACKDET",
3970 wm8994);
3971 if (ret == 0)
3972 wm8994->jackdet = true;
3973 }
3974 break;
3975 default:
3976 break;
3977 }
3978
c7ebf932
MB		 3979 wm8994->fll_locked_irq = true;
3980 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3981 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3982 WM8994_IRQ_FLL1_LOCK + i,
3983 wm8994_fll_locked_irq, "FLL lock",
3984 &wm8994->fll_locked[i]);
3985 if (ret != 0)
3986 wm8994->fll_locked_irq = false;
3987 }
3988
27060b3c
MB		 3989 /* Make sure we can read from the GPIOs if they're inputs */
3990 pm_runtime_get_sync(codec->dev);
3991
9e6e96a1
MB		 3992 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3993 * configured on init - if a system wants to do this dynamically
3994 * at runtime we can deal with that then.
3995 */
d9a7666f 3996 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3997 if (ret < 0) {
3998 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3999 goto err_irq;
9e6e96a1 4000 }
d9a7666f 4001 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4002 wm8994->lrclk_shared[0] = 1;
4003 wm8994_dai[0].symmetric_rates = 1;
4004 } else {
4005 wm8994->lrclk_shared[0] = 0;
4006 }
4007
d9a7666f 4008 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 4009 if (ret < 0) {
4010 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4011 goto err_irq;
9e6e96a1 4012 }
d9a7666f 4013 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4014 wm8994->lrclk_shared[1] = 1;
4015 wm8994_dai[1].symmetric_rates = 1;
4016 } else {
4017 wm8994->lrclk_shared[1] = 0;
4018 }
4019
27060b3c
MB		 4020 pm_runtime_put(codec->dev);
4021
bfd37bb5
MB		 4022 /* Latch volume update bits */
4023 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4024 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4025 wm8994_vu_bits[i].mask,
4026 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 4027
4028 /* Set the low bit of the 3D stereo depth so TLV matches */
4029 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4030 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4031 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4032 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4033 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4034 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4035 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4036 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4037 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4038
5b739670
MB		 4039 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4040 * use this; it only affects behaviour on idle TDM clock
4041 * cycles. */
4042 switch (control->type) {
4043 case WM8994:
4044 case WM8958:
4045 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4046 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4047 break;
4048 default:
4049 break;
4050 }
d1ce6b20 4051
500fa30e
MB		 4052 /* Put MICBIAS into bypass mode by default on newer devices */
4053 switch (control->type) {
4054 case WM8958:
4055 case WM1811:
4056 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4057 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4058 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4059 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4060 break;
4061 default:
4062 break;
4063 }
4064
c340304d
MB		 4065 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4066 wm_hubs_update_class_w(codec);
9e6e96a1 4067
f0fba2ad 4068 wm8994_handle_pdata(wm8994);
9e6e96a1 4069
f0fba2ad 4070 wm_hubs_add_analogue_controls(codec);
022658be 4071 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4072 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4073 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4074 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 4075
4076 switch (control->type) {
4077 case WM8994:
4078 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4079 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 4080 if (wm8994->revision < 4) {
173efa09
DP		 4081 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4082 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 4083 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4084 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 4085 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4086 ARRAY_SIZE(wm8994_dac_revd_widgets));
4087 } else {
173efa09
DP		 4088 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4089 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4090 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4091 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4092 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4093 ARRAY_SIZE(wm8994_dac_widgets));
4094 }
c4431df0
MB		 4095 break;
4096 case WM8958:
022658be 4097 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4098 ARRAY_SIZE(wm8958_snd_controls));
4099 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4100 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 4101 if (wm8994->revision < 1) {
4102 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4103 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4104 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4105 ARRAY_SIZE(wm8994_adc_revd_widgets));
4106 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4107 ARRAY_SIZE(wm8994_dac_revd_widgets));
4108 } else {
4109 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4110 ARRAY_SIZE(wm8994_lateclk_widgets));
4111 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4112 ARRAY_SIZE(wm8994_adc_widgets));
4113 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4114 ARRAY_SIZE(wm8994_dac_widgets));
4115 }
c4431df0 4116 break;
81204c84
MB		 4117
4118 case WM1811:
022658be 4119 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4120 ARRAY_SIZE(wm8958_snd_controls));
4121 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4122 ARRAY_SIZE(wm8958_dapm_widgets));
4123 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4124 ARRAY_SIZE(wm8994_lateclk_widgets));
4125 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4126 ARRAY_SIZE(wm8994_adc_widgets));
4127 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4128 ARRAY_SIZE(wm8994_dac_widgets));
4129 break;
c4431df0 4130 }
c4431df0 4131
f0fba2ad 4132 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 4133 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4134
c4431df0
MB		 4135 switch (control->type) {
4136 case WM8994:
4137 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4138 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4139
173efa09 4140 if (wm8994->revision < 4) {
6ed8f148
MB		 4141 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4142 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4143 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4144 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4145 } else {
4146 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4147 ARRAY_SIZE(wm8994_lateclk_intercon));
4148 }
c4431df0
MB		 4149 break;
4150 case WM8958:
780e2806 4151 if (wm8994->revision < 1) {
15676937
CR		 4152 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4153 ARRAY_SIZE(wm8994_intercon));
780e2806
MB		 4154 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4155 ARRAY_SIZE(wm8994_revd_intercon));
4156 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4157 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4158 } else {
4159 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4160 ARRAY_SIZE(wm8994_lateclk_intercon));
4161 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4162 ARRAY_SIZE(wm8958_intercon));
4163 }
f701a2e5
MB		 4164
4165 wm8958_dsp2_init(codec);
c4431df0 4166 break;
81204c84
MB		 4167 case WM1811:
4168 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4169 ARRAY_SIZE(wm8994_lateclk_intercon));
4170 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4171 ARRAY_SIZE(wm8958_intercon));
4172 break;
c4431df0
MB		 4173 }
4174
9e6e96a1
MB		 4175 return 0;
4176
88766984 4177err_irq:
af6b6fe4
MB		 4178 if (wm8994->jackdet)
4179 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4180 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4181 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4182 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4183 if (wm8994->micdet_irq)
4184 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4185 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4186 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4187 &wm8994->fll_locked[i]);
2a8a856d 4188 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4189 &wm8994->hubs);
2a8a856d
MB		 4190 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4191 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4192 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4193
9e6e96a1
MB		 4194 return ret;
4195}
4196
34ff0f95 4197static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4198{
f0fba2ad 4199 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4200 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4201 int i;
9e6e96a1
MB		 4202
4203 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4204
39fb51a1
MB		 4205 pm_runtime_disable(codec->dev);
4206
c7ebf932 4207 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4208 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4209 &wm8994->fll_locked[i]);
4210
2a8a856d 4211 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4212 &wm8994->hubs);
2a8a856d
MB		 4213 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4214 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4215 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4216
af6b6fe4
MB		 4217 if (wm8994->jackdet)
4218 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4219
3a423157
MB		 4220 switch (control->type) {
4221 case WM8994:
9b7c525d
MB		 4222 if (wm8994->micdet_irq)
4223 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4224 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4225 wm8994);
2a8a856d 4226 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4227 wm8994);
2a8a856d 4228 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4229 wm8994);
4230 break;
821edd2f 4231
81204c84 4232 case WM1811:
821edd2f 4233 case WM8958:
9b7c525d
MB		 4234 if (wm8994->micdet_irq)
4235 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4236 break;
3a423157 4237 }
34ff0f95
JJ		 4238 release_firmware(wm8994->mbc);
4239 release_firmware(wm8994->mbc_vss);
4240 release_firmware(wm8994->enh_eq);
24fb2b11 4241 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4242 return 0;
4243}
4244
f0fba2ad
LG		 4245static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4246 .probe = wm8994_codec_probe,
4247 .remove = wm8994_codec_remove,
4752a887
MB		 4248 .suspend = wm8994_codec_suspend,
4249 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4250 .set_bias_level = wm8994_set_bias_level,
4251};
4252
4253static int __devinit wm8994_probe(struct platform_device *pdev)
4254{
2bc16ed8
MB		 4255 struct wm8994_priv *wm8994;
4256
4257 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4258 GFP_KERNEL);
4259 if (wm8994 == NULL)
4260 return -ENOMEM;
4261 platform_set_drvdata(pdev, wm8994);
4262
4263 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
2bc16ed8 4264
f0fba2ad
LG		 4265 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4266 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4267}
4268
4269static int __devexit wm8994_remove(struct platform_device *pdev)
4270{
4271 snd_soc_unregister_codec(&pdev->dev);
4272 return 0;
4273}
4274
4752a887
MB		 4275#ifdef CONFIG_PM_SLEEP
4276static int wm8994_suspend(struct device *dev)
4277{
4278 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4279
4280 /* Drop down to power saving mode when system is suspended */
4281 if (wm8994->jackdet && !wm8994->active_refcount)
4282 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4283 WM1811_JACKDET_MODE_MASK,
4284 wm8994->jackdet_mode);
4285
4286 return 0;
4287}
4288
4289static int wm8994_resume(struct device *dev)
4290{
4291 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4292
4293 if (wm8994->jackdet && wm8994->jack_cb)
4294 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4295 WM1811_JACKDET_MODE_MASK,
4296 WM1811_JACKDET_MODE_AUDIO);
4297
4298 return 0;
4299}
4300#endif
4301
4302static const struct dev_pm_ops wm8994_pm_ops = {
4303 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4304};
4305
9e6e96a1
MB		 4306static struct platform_driver wm8994_codec_driver = {
4307 .driver = {
4752a887
MB		 4308 .name = "wm8994-codec",
4309 .owner = THIS_MODULE,
4310 .pm = &wm8994_pm_ops,
4311 },
f0fba2ad
LG		 4312 .probe = wm8994_probe,
4313 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 4314};
4315
5bbcc3c0 4316module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4317
4318MODULE_DESCRIPTION("ASoC WM8994 driver");
4319MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4320MODULE_LICENSE("GPL");
4321MODULE_ALIAS("platform:wm8994-codec");
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