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ASoC: wm8994: Simplify button detection code
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
9e6e96a1
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
bfd37bb5
MB		 49static struct {
50 unsigned int reg;
51 unsigned int mask;
52} wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80};
81
9e6e96a1
MB		 82static int wm8994_drc_base[] = {
83 WM8994_AIF1_DRC1_1,
84 WM8994_AIF1_DRC2_1,
85 WM8994_AIF2_DRC_1,
86};
87
88static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
92};
93
af6b6fe4 94static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 95 { 32768, true, 1, 4 },
96 { 32768, false, 1, 1 },
604533de
MB		 97 { 44100 * 256, true, 7, 10 },
98 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 99};
100
af6b6fe4
MB		 101static const struct wm8958_micd_rate jackdet_rates[] = {
102 { 32768, true, 0, 1 },
103 { 32768, false, 0, 1 },
e9d9a968
MB		 104 { 44100 * 256, true, 10, 10 },
105 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 106};
107
b00adf76
MB		 108static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
109{
110 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada 111 struct wm8994 *control = wm8994->wm8994;
b00adf76
MB		 112 int best, i, sysclk, val;
113 bool idle;
af6b6fe4
MB		 114 const struct wm8958_micd_rate *rates;
115 int num_rates;
b00adf76 116
b00adf76
MB		 117 idle = !wm8994->jack_mic;
118
119 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
120 if (sysclk & WM8994_SYSCLK_SRC)
121 sysclk = wm8994->aifclk[1];
122 else
123 sysclk = wm8994->aifclk[0];
124
d9dd4ada
MB		 125 if (control->pdata.micd_rates) {
126 rates = control->pdata.micd_rates;
127 num_rates = control->pdata.num_micd_rates;
cd1707a9 128 } else if (wm8994->jackdet) {
af6b6fe4
MB		 129 rates = jackdet_rates;
130 num_rates = ARRAY_SIZE(jackdet_rates);
131 } else {
132 rates = micdet_rates;
133 num_rates = ARRAY_SIZE(micdet_rates);
134 }
135
b00adf76 136 best = 0;
af6b6fe4
MB		 137 for (i = 0; i < num_rates; i++) {
138 if (rates[i].idle != idle)
b00adf76 139 continue;
af6b6fe4
MB		 140 if (abs(rates[i].sysclk - sysclk) <
141 abs(rates[best].sysclk - sysclk))
b00adf76 142 best = i;
af6b6fe4 143 else if (rates[best].idle != idle)
b00adf76
MB		 144 best = i;
145 }
146
af6b6fe4
MB		 147 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
148 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 149
3a334ada
MB		 150 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
151 rates[best].start, rates[best].rate, sysclk,
152 idle ? "idle" : "active");
153
b00adf76
MB		 154 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
155 WM8958_MICD_BIAS_STARTTIME_MASK |
156 WM8958_MICD_RATE_MASK, val);
157}
158
9e6e96a1
MB		 159static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
160{
b2c812e2 161 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 162 int rate;
163 int reg1 = 0;
164 int offset;
165
166 if (aif)
167 offset = 4;
168 else
169 offset = 0;
170
171 switch (wm8994->sysclk[aif]) {
172 case WM8994_SYSCLK_MCLK1:
173 rate = wm8994->mclk[0];
174 break;
175
176 case WM8994_SYSCLK_MCLK2:
177 reg1 |= 0x8;
178 rate = wm8994->mclk[1];
179 break;
180
181 case WM8994_SYSCLK_FLL1:
182 reg1 |= 0x10;
183 rate = wm8994->fll[0].out;
184 break;
185
186 case WM8994_SYSCLK_FLL2:
187 reg1 |= 0x18;
188 rate = wm8994->fll[1].out;
189 break;
190
191 default:
192 return -EINVAL;
193 }
194
195 if (rate >= 13500000) {
196 rate /= 2;
197 reg1 |= WM8994_AIF1CLK_DIV;
198
199 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
200 aif + 1, rate);
201 }
5e5e2bef 202
9e6e96a1
MB		 203 wm8994->aifclk[aif] = rate;
204
205 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
206 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
207 reg1);
208
209 return 0;
210}
211
212static int configure_clock(struct snd_soc_codec *codec)
213{
b2c812e2 214 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 215 int change, new;
9e6e96a1
MB		 216
217 /* Bring up the AIF clocks first */
218 configure_aif_clock(codec, 0);
219 configure_aif_clock(codec, 1);
220
221 /* Then switch CLK_SYS over to the higher of them; a change
222 * can only happen as a result of a clocking change which can
223 * only be made outside of DAPM so we can safely redo the
224 * clocking.
225 */
226
227 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 228 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
229 wm8958_micd_set_rate(codec);
9e6e96a1 230 return 0;
b00adf76 231 }
9e6e96a1
MB		 232
233 if (wm8994->aifclk[0] < wm8994->aifclk[1])
234 new = WM8994_SYSCLK_SRC;
235 else
236 new = 0;
237
04f45c49
AL		 238 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
239 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 240 if (change)
241 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 242
b00adf76
MB		 243 wm8958_micd_set_rate(codec);
244
9e6e96a1
MB		 245 return 0;
246}
247
248static int check_clk_sys(struct snd_soc_dapm_widget *source,
249 struct snd_soc_dapm_widget *sink)
250{
251 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
252 const char *clk;
253
254 /* Check what we're currently using for CLK_SYS */
255 if (reg & WM8994_SYSCLK_SRC)
256 clk = "AIF2CLK";
257 else
258 clk = "AIF1CLK";
259
260 return strcmp(source->name, clk) == 0;
261}
262
263static const char *sidetone_hpf_text[] = {
264 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
265};
266
267static const struct soc_enum sidetone_hpf =
268 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
269
146fd574
UK		 270static const char *adc_hpf_text[] = {
271 "HiFi", "Voice 1", "Voice 2", "Voice 3"
272};
273
274static const struct soc_enum aif1adc1_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
276
277static const struct soc_enum aif1adc2_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
279
280static const struct soc_enum aif2adc_hpf =
281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
282
9e6e96a1
MB		 283static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
284static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
285static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
286static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
287static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 288static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 289static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 290
291#define WM8994_DRC_SWITCH(xname, reg, shift) \
292{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
293 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
294 .put = wm8994_put_drc_sw, \
295 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
296
297static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
299{
300 struct soc_mixer_control *mc =
301 (struct soc_mixer_control *)kcontrol->private_value;
302 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
303 int mask, ret;
304
305 /* Can't enable both ADC and DAC paths simultaneously */
306 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
307 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
308 WM8994_AIF1ADC1R_DRC_ENA_MASK;
309 else
310 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
311
312 ret = snd_soc_read(codec, mc->reg);
313 if (ret < 0)
314 return ret;
315 if (ret & mask)
316 return -EINVAL;
317
318 return snd_soc_put_volsw(kcontrol, ucontrol);
319}
320
9e6e96a1
MB		 321static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
322{
b2c812e2 323 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 324 struct wm8994 *control = wm8994->wm8994;
325 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 326 int base = wm8994_drc_base[drc];
327 int cfg = wm8994->drc_cfg[drc];
328 int save, i;
329
330 /* Save any enables; the configuration should clear them. */
331 save = snd_soc_read(codec, base);
332 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
333 WM8994_AIF1ADC1R_DRC_ENA;
334
335 for (i = 0; i < WM8994_DRC_REGS; i++)
336 snd_soc_update_bits(codec, base + i, 0xffff,
337 pdata->drc_cfgs[cfg].regs[i]);
338
339 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
340 WM8994_AIF1ADC1L_DRC_ENA |
341 WM8994_AIF1ADC1R_DRC_ENA, save);
342}
343
344/* Icky as hell but saves code duplication */
345static int wm8994_get_drc(const char *name)
346{
347 if (strcmp(name, "AIF1DRC1 Mode") == 0)
348 return 0;
349 if (strcmp(name, "AIF1DRC2 Mode") == 0)
350 return 1;
351 if (strcmp(name, "AIF2DRC Mode") == 0)
352 return 2;
353 return -EINVAL;
354}
355
356static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
357 struct snd_ctl_elem_value *ucontrol)
358{
359 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 360 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 361 struct wm8994 *control = wm8994->wm8994;
362 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 363 int drc = wm8994_get_drc(kcontrol->id.name);
364 int value = ucontrol->value.integer.value[0];
365
366 if (drc < 0)
367 return drc;
368
369 if (value >= pdata->num_drc_cfgs)
370 return -EINVAL;
371
372 wm8994->drc_cfg[drc] = value;
373
374 wm8994_set_drc(codec, drc);
375
376 return 0;
377}
378
379static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381{
382 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 384 int drc = wm8994_get_drc(kcontrol->id.name);
385
386 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
387
388 return 0;
389}
390
391static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
392{
b2c812e2 393 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 394 struct wm8994 *control = wm8994->wm8994;
395 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 396 int base = wm8994_retune_mobile_base[block];
397 int iface, best, best_val, save, i, cfg;
398
399 if (!pdata || !wm8994->num_retune_mobile_texts)
400 return;
401
402 switch (block) {
403 case 0:
404 case 1:
405 iface = 0;
406 break;
407 case 2:
408 iface = 1;
409 break;
410 default:
411 return;
412 }
413
414 /* Find the version of the currently selected configuration
415 * with the nearest sample rate. */
416 cfg = wm8994->retune_mobile_cfg[block];
417 best = 0;
418 best_val = INT_MAX;
419 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
420 if (strcmp(pdata->retune_mobile_cfgs[i].name,
421 wm8994->retune_mobile_texts[cfg]) == 0 &&
422 abs(pdata->retune_mobile_cfgs[i].rate
423 - wm8994->dac_rates[iface]) < best_val) {
424 best = i;
425 best_val = abs(pdata->retune_mobile_cfgs[i].rate
426 - wm8994->dac_rates[iface]);
427 }
428 }
429
430 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
431 block,
432 pdata->retune_mobile_cfgs[best].name,
433 pdata->retune_mobile_cfgs[best].rate,
434 wm8994->dac_rates[iface]);
435
436 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 437 * current configuration.
9e6e96a1
MB		 438 */
439 save = snd_soc_read(codec, base);
440 save &= WM8994_AIF1DAC1_EQ_ENA;
441
442 for (i = 0; i < WM8994_EQ_REGS; i++)
443 snd_soc_update_bits(codec, base + i, 0xffff,
444 pdata->retune_mobile_cfgs[best].regs[i]);
445
446 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
447}
448
449/* Icky as hell but saves code duplication */
450static int wm8994_get_retune_mobile_block(const char *name)
451{
452 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
453 return 0;
454 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
455 return 1;
456 if (strcmp(name, "AIF2 EQ Mode") == 0)
457 return 2;
458 return -EINVAL;
459}
460
461static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
462 struct snd_ctl_elem_value *ucontrol)
463{
464 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 465 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 466 struct wm8994 *control = wm8994->wm8994;
467 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 468 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
469 int value = ucontrol->value.integer.value[0];
470
471 if (block < 0)
472 return block;
473
474 if (value >= pdata->num_retune_mobile_cfgs)
475 return -EINVAL;
476
477 wm8994->retune_mobile_cfg[block] = value;
478
479 wm8994_set_retune_mobile(codec, block);
480
481 return 0;
482}
483
484static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol)
486{
487 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 488 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 489 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
490
491 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
492
493 return 0;
494}
495
96b101ef 496static const char *aif_chan_src_text[] = {
f554885f
MB		 497 "Left", "Right"
498};
499
96b101ef
MB		 500static const struct soc_enum aif1adcl_src =
501 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
502
503static const struct soc_enum aif1adcr_src =
504 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
505
506static const struct soc_enum aif2adcl_src =
507 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
508
509static const struct soc_enum aif2adcr_src =
510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
511
f554885f 512static const struct soc_enum aif1dacl_src =
96b101ef 513 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 514
515static const struct soc_enum aif1dacr_src =
96b101ef 516 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 517
518static const struct soc_enum aif2dacl_src =
96b101ef 519 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 520
521static const struct soc_enum aif2dacr_src =
96b101ef 522 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 523
154b26aa
MB		 524static const char *osr_text[] = {
525 "Low Power", "High Performance",
526};
527
528static const struct soc_enum dac_osr =
529 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
530
531static const struct soc_enum adc_osr =
532 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
533
9e6e96a1
MB		 534static const struct snd_kcontrol_new wm8994_snd_controls[] = {
535SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
536 WM8994_AIF1_ADC1_RIGHT_VOLUME,
537 1, 119, 0, digital_tlv),
538SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
539 WM8994_AIF1_ADC2_RIGHT_VOLUME,
540 1, 119, 0, digital_tlv),
541SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
542 WM8994_AIF2_ADC_RIGHT_VOLUME,
543 1, 119, 0, digital_tlv),
544
96b101ef
MB		 545SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
546SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 547SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
548SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 549
f554885f
MB		 550SOC_ENUM("AIF1DACL Source", aif1dacl_src),
551SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 552SOC_ENUM("AIF2DACL Source", aif2dacl_src),
553SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 554
9e6e96a1
MB		 555SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
556 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
557SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
558 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
559SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
560 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561
562SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
563SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
564
565SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
566SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
567SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
568
569WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
570WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
571WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
572
573WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
574WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
575WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
576
577WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
578WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
579WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
580
581SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
582 5, 12, 0, st_tlv),
583SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
584 0, 12, 0, st_tlv),
585SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
586 5, 12, 0, st_tlv),
587SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
588 0, 12, 0, st_tlv),
589SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
590SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
591
146fd574
UK		 592SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
593SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
594
595SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
596SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
597
598SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
599SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
600
154b26aa
MB		 601SOC_ENUM("ADC OSR", adc_osr),
602SOC_ENUM("DAC OSR", dac_osr),
603
9e6e96a1
MB		 604SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
605 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
606SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
607 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
608
609SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
610 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
611SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
612 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
613
614SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
615 6, 1, 1, wm_hubs_spkmix_tlv),
616SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
617 2, 1, 1, wm_hubs_spkmix_tlv),
618
619SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
620 6, 1, 1, wm_hubs_spkmix_tlv),
621SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
622 2, 1, 1, wm_hubs_spkmix_tlv),
623
624SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
625 10, 15, 0, wm8994_3d_tlv),
458350b3 626SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 627 8, 1, 0),
628SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
629 10, 15, 0, wm8994_3d_tlv),
630SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
631 8, 1, 0),
458350b3 632SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 633 10, 15, 0, wm8994_3d_tlv),
458350b3 634SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 635 8, 1, 0),
636};
637
638static const struct snd_kcontrol_new wm8994_eq_controls[] = {
639SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
640 eq_tlv),
641SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
642 eq_tlv),
643SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
644 eq_tlv),
645SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
646 eq_tlv),
647SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
648 eq_tlv),
649
650SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
651 eq_tlv),
652SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
653 eq_tlv),
654SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
655 eq_tlv),
656SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
657 eq_tlv),
658SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
659 eq_tlv),
660
661SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
662 eq_tlv),
663SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
664 eq_tlv),
665SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
666 eq_tlv),
667SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
668 eq_tlv),
669SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
670 eq_tlv),
671};
672
45a690f6
MB		 673static const struct snd_kcontrol_new wm8994_drc_controls[] = {
674SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
675 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
676 WM8994_AIF1ADC1R_DRC_ENA),
677SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
678 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
679 WM8994_AIF1ADC2R_DRC_ENA),
680SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
681 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
682 WM8994_AIF2ADCR_DRC_ENA),
683};
684
1ddc07d0
MB		 685static const char *wm8958_ng_text[] = {
686 "30ms", "125ms", "250ms", "500ms",
687};
688
689static const struct soc_enum wm8958_aif1dac1_ng_hold =
690 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
691 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
692
693static const struct soc_enum wm8958_aif1dac2_ng_hold =
694 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
695 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
696
697static const struct soc_enum wm8958_aif2dac_ng_hold =
698 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
699 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
700
c4431df0
MB		 701static const struct snd_kcontrol_new wm8958_snd_controls[] = {
702SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 703
704SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
705 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
706SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
707SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
708 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
709 7, 1, ng_tlv),
710
711SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
712 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
713SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
714SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
715 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
716 7, 1, ng_tlv),
717
718SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
719 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
720SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
721SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
722 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
723 7, 1, ng_tlv),
c4431df0
MB		 724};
725
81204c84
MB		 726static const struct snd_kcontrol_new wm1811_snd_controls[] = {
727SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
728 mixin_boost_tlv),
729SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
730 mixin_boost_tlv),
731};
732
af6b6fe4
MB		 733/* We run all mode setting through a function to enforce audio mode */
734static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
735{
736 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
737
78b76dbe 738 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
28e33269
MB		 739 return;
740
af6b6fe4
MB		 741 if (wm8994->active_refcount)
742 mode = WM1811_JACKDET_MODE_AUDIO;
743
4752a887 744 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 745 return;
746
4752a887 747 wm8994->jackdet_mode = mode;
1defde2a 748
4752a887
MB		 749 /* Always use audio mode to detect while the system is active */
750 if (mode != WM1811_JACKDET_MODE_NONE)
751 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 752
4752a887
MB		 753 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
754 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 755}
756
757static void active_reference(struct snd_soc_codec *codec)
758{
759 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
760
761 mutex_lock(&wm8994->accdet_lock);
762
763 wm8994->active_refcount++;
764
765 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
766 wm8994->active_refcount);
767
1defde2a
MB		 768 /* If we're using jack detection go into audio mode */
769 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 770
771 mutex_unlock(&wm8994->accdet_lock);
772}
773
774static void active_dereference(struct snd_soc_codec *codec)
775{
776 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
777 u16 mode;
778
779 mutex_lock(&wm8994->accdet_lock);
780
781 wm8994->active_refcount--;
782
783 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
784 wm8994->active_refcount);
785
786 if (wm8994->active_refcount == 0) {
787 /* Go into appropriate detection only mode */
1defde2a
MB		 788 if (wm8994->jack_mic || wm8994->mic_detecting)
789 mode = WM1811_JACKDET_MODE_MIC;
790 else
791 mode = WM1811_JACKDET_MODE_JACK;
792
793 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 794 }
795
796 mutex_unlock(&wm8994->accdet_lock);
797}
798
9e6e96a1
MB		 799static int clk_sys_event(struct snd_soc_dapm_widget *w,
800 struct snd_kcontrol *kcontrol, int event)
801{
802 struct snd_soc_codec *codec = w->codec;
99af79df 803 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 804
805 switch (event) {
806 case SND_SOC_DAPM_PRE_PMU:
807 return configure_clock(codec);
808
99af79df
MB		 809 case SND_SOC_DAPM_POST_PMU:
810 /*
811 * JACKDET won't run until we start the clock and it
812 * only reports deltas, make sure we notify the state
813 * up the stack on startup. Use a *very* generous
814 * timeout for paranoia, there's no urgency and we
815 * don't want false reports.
816 */
817 if (wm8994->jackdet && !wm8994->clk_has_run) {
818 schedule_delayed_work(&wm8994->jackdet_bootstrap,
819 msecs_to_jiffies(1000));
820 wm8994->clk_has_run = true;
821 }
822 break;
823
9e6e96a1
MB		 824 case SND_SOC_DAPM_POST_PMD:
825 configure_clock(codec);
826 break;
827 }
828
829 return 0;
830}
831
4b7ed83a
MB		 832static void vmid_reference(struct snd_soc_codec *codec)
833{
834 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
835
db966f8a
MB		 836 pm_runtime_get_sync(codec->dev);
837
4b7ed83a
MB		 838 wm8994->vmid_refcount++;
839
840 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
841 wm8994->vmid_refcount);
842
843 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 844 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 845 WM8994_LINEOUT1_DISCH |
22f8d055 846 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 847
f7085641
MB		 848 wm_hubs_vmid_ena(codec);
849
22f8d055
MB		 850 switch (wm8994->vmid_mode) {
851 default:
cbd71f30 852 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 853 case WM8994_VMID_NORMAL:
854 /* Startup bias, VMID ramp & buffer */
855 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
856 WM8994_BIAS_SRC |
857 WM8994_VMID_DISCH |
858 WM8994_STARTUP_BIAS_ENA |
859 WM8994_VMID_BUF_ENA |
860 WM8994_VMID_RAMP_MASK,
861 WM8994_BIAS_SRC |
862 WM8994_STARTUP_BIAS_ENA |
863 WM8994_VMID_BUF_ENA |
a3a1d9d2 864 (0x2 << WM8994_VMID_RAMP_SHIFT));
22f8d055
MB		 865
866 /* Main bias enable, VMID=2x40k */
867 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
868 WM8994_BIAS_ENA |
869 WM8994_VMID_SEL_MASK,
870 WM8994_BIAS_ENA | 0x2);
871
a3a1d9d2 872 msleep(300);
22f8d055
MB		 873
874 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
875 WM8994_VMID_RAMP_MASK |
876 WM8994_BIAS_SRC,
877 0);
878 break;
cc6d5a8c 879
22f8d055
MB		 880 case WM8994_VMID_FORCE:
881 /* Startup bias, slow VMID ramp & buffer */
882 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
883 WM8994_BIAS_SRC |
884 WM8994_VMID_DISCH |
885 WM8994_STARTUP_BIAS_ENA |
886 WM8994_VMID_BUF_ENA |
887 WM8994_VMID_RAMP_MASK,
888 WM8994_BIAS_SRC |
889 WM8994_STARTUP_BIAS_ENA |
890 WM8994_VMID_BUF_ENA |
891 (0x2 << WM8994_VMID_RAMP_SHIFT));
892
893 /* Main bias enable, VMID=2x40k */
894 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
895 WM8994_BIAS_ENA |
896 WM8994_VMID_SEL_MASK,
897 WM8994_BIAS_ENA | 0x2);
898
899 msleep(400);
900
901 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
902 WM8994_VMID_RAMP_MASK |
903 WM8994_BIAS_SRC,
904 0);
905 break;
906 }
4b7ed83a
MB		 907 }
908}
909
910static void vmid_dereference(struct snd_soc_codec *codec)
911{
912 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
913
914 wm8994->vmid_refcount--;
915
916 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
917 wm8994->vmid_refcount);
918
919 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 920 if (wm8994->hubs.lineout1_se)
921 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
922 WM8994_LINEOUT1N_ENA |
923 WM8994_LINEOUT1P_ENA,
924 WM8994_LINEOUT1N_ENA |
925 WM8994_LINEOUT1P_ENA);
926
927 if (wm8994->hubs.lineout2_se)
928 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
929 WM8994_LINEOUT2N_ENA |
930 WM8994_LINEOUT2P_ENA,
931 WM8994_LINEOUT2N_ENA |
932 WM8994_LINEOUT2P_ENA);
933
934 /* Start discharging VMID */
4b7ed83a
MB		 935 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
936 WM8994_BIAS_SRC |
22f8d055 937 WM8994_VMID_DISCH,
4b7ed83a 938 WM8994_BIAS_SRC |
22f8d055 939 WM8994_VMID_DISCH);
4b7ed83a 940
f95be9d6
MB		 941 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
942 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 943
f95be9d6 944 msleep(400);
e85b26ce 945
22f8d055 946 /* Active discharge */
4b7ed83a
MB		 947 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
948 WM8994_LINEOUT1_DISCH |
949 WM8994_LINEOUT2_DISCH,
950 WM8994_LINEOUT1_DISCH |
951 WM8994_LINEOUT2_DISCH);
952
22f8d055
MB		 953 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
954 WM8994_LINEOUT1N_ENA |
955 WM8994_LINEOUT1P_ENA |
956 WM8994_LINEOUT2N_ENA |
957 WM8994_LINEOUT2P_ENA, 0);
958
4b7ed83a
MB		 959 /* Switch off startup biases */
960 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
961 WM8994_BIAS_SRC |
962 WM8994_STARTUP_BIAS_ENA |
963 WM8994_VMID_BUF_ENA |
964 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 965
966 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 967 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 968 }
db966f8a
MB		 969
970 pm_runtime_put(codec->dev);
4b7ed83a
MB		 971}
972
973static int vmid_event(struct snd_soc_dapm_widget *w,
974 struct snd_kcontrol *kcontrol, int event)
975{
976 struct snd_soc_codec *codec = w->codec;
977
978 switch (event) {
979 case SND_SOC_DAPM_PRE_PMU:
980 vmid_reference(codec);
981 break;
982
983 case SND_SOC_DAPM_POST_PMD:
984 vmid_dereference(codec);
985 break;
986 }
987
988 return 0;
989}
990
c340304d 991static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 992{
9e6e96a1
MB		 993 int source = 0; /* GCC flow analysis can't track enable */
994 int reg, reg_r;
995
c340304d 996 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 997 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
998 switch (reg) {
999 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1000 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 1001 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1002 break;
1003 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1004 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 1005 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1006 break;
1007 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1008 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 1009 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1010 break;
1011 default:
ee839a21 1012 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1013 return false;
9e6e96a1
MB		 1014 }
1015
1016 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1017 if (reg_r != reg) {
ee839a21 1018 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1019 return false;
9e6e96a1
MB		 1020 }
1021
c340304d
MB		 1022 /* Set the source up */
1023 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1024 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1025
c340304d 1026 return true;
9e6e96a1
MB		 1027}
1028
1a38336b
MB		 1029static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1030 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1031{
1032 struct snd_soc_codec *codec = w->codec;
1a38336b
MB		 1033 struct wm8994 *control = codec->control_data;
1034 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1035 int i;
1a38336b
MB		 1036 int dac;
1037 int adc;
1038 int val;
1039
1040 switch (control->type) {
1041 case WM8994:
1042 case WM8958:
1043 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1044 break;
1045 default:
1046 break;
1047 }
173efa09
DP		 1048
1049 switch (event) {
1050 case SND_SOC_DAPM_PRE_PMU:
1a38336b
MB		 1051 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1052 if ((val & WM8994_AIF1ADCL_SRC) &&
1053 (val & WM8994_AIF1ADCR_SRC))
1054 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1055 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1056 !(val & WM8994_AIF1ADCR_SRC))
1057 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1058 else
1059 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1060 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1061
1062 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1063 if ((val & WM8994_AIF1DACL_SRC) &&
1064 (val & WM8994_AIF1DACR_SRC))
1065 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1066 else if (!(val & WM8994_AIF1DACL_SRC) &&
1067 !(val & WM8994_AIF1DACR_SRC))
1068 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1069 else
1070 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1071 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1072
1073 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1074 mask, adc);
1075 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1076 mask, dac);
1077 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1078 WM8994_AIF1DSPCLK_ENA |
1079 WM8994_SYSDSPCLK_ENA,
1080 WM8994_AIF1DSPCLK_ENA |
1081 WM8994_SYSDSPCLK_ENA);
1082 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1083 WM8994_AIF1ADC1R_ENA |
1084 WM8994_AIF1ADC1L_ENA |
1085 WM8994_AIF1ADC2R_ENA |
1086 WM8994_AIF1ADC2L_ENA);
1087 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1088 WM8994_AIF1DAC1R_ENA |
1089 WM8994_AIF1DAC1L_ENA |
1090 WM8994_AIF1DAC2R_ENA |
1091 WM8994_AIF1DAC2L_ENA);
173efa09 1092 break;
173efa09 1093
bfd37bb5
MB		 1094 case SND_SOC_DAPM_POST_PMU:
1095 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1096 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1097 snd_soc_read(codec,
1098 wm8994_vu_bits[i].reg));
1099 break;
1100
1a38336b
MB		 1101 case SND_SOC_DAPM_PRE_PMD:
1102 case SND_SOC_DAPM_POST_PMD:
1103 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1104 mask, 0);
1105 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1106 mask, 0);
1107
1108 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1109 if (val & WM8994_AIF2DSPCLK_ENA)
1110 val = WM8994_SYSDSPCLK_ENA;
1111 else
1112 val = 0;
1113 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1114 WM8994_SYSDSPCLK_ENA |
1115 WM8994_AIF1DSPCLK_ENA, val);
1116 break;
1117 }
c6b7b570 1118
173efa09
DP		 1119 return 0;
1120}
1121
1a38336b
MB		 1122static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1123 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1124{
1125 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1126 int i;
1a38336b
MB		 1127 int dac;
1128 int adc;
1129 int val;
173efa09
DP		 1130
1131 switch (event) {
1a38336b
MB		 1132 case SND_SOC_DAPM_PRE_PMU:
1133 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1134 if ((val & WM8994_AIF2ADCL_SRC) &&
1135 (val & WM8994_AIF2ADCR_SRC))
1136 adc = WM8994_AIF2ADCR_ENA;
1137 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1138 !(val & WM8994_AIF2ADCR_SRC))
1139 adc = WM8994_AIF2ADCL_ENA;
1140 else
1141 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1142
1143
1144 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1145 if ((val & WM8994_AIF2DACL_SRC) &&
1146 (val & WM8994_AIF2DACR_SRC))
1147 dac = WM8994_AIF2DACR_ENA;
1148 else if (!(val & WM8994_AIF2DACL_SRC) &&
1149 !(val & WM8994_AIF2DACR_SRC))
1150 dac = WM8994_AIF2DACL_ENA;
1151 else
1152 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1153
1154 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1155 WM8994_AIF2ADCL_ENA |
1156 WM8994_AIF2ADCR_ENA, adc);
1157 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1158 WM8994_AIF2DACL_ENA |
1159 WM8994_AIF2DACR_ENA, dac);
1160 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1161 WM8994_AIF2DSPCLK_ENA |
1162 WM8994_SYSDSPCLK_ENA,
1163 WM8994_AIF2DSPCLK_ENA |
1164 WM8994_SYSDSPCLK_ENA);
1165 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1166 WM8994_AIF2ADCL_ENA |
1167 WM8994_AIF2ADCR_ENA,
1168 WM8994_AIF2ADCL_ENA |
1169 WM8994_AIF2ADCR_ENA);
1170 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1171 WM8994_AIF2DACL_ENA |
1172 WM8994_AIF2DACR_ENA,
1173 WM8994_AIF2DACL_ENA |
1174 WM8994_AIF2DACR_ENA);
1175 break;
1176
bfd37bb5
MB		 1177 case SND_SOC_DAPM_POST_PMU:
1178 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1179 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1180 snd_soc_read(codec,
1181 wm8994_vu_bits[i].reg));
1182 break;
1183
1a38336b 1184 case SND_SOC_DAPM_PRE_PMD:
173efa09 1185 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1186 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1187 WM8994_AIF2DACL_ENA |
1188 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1189 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1190 WM8994_AIF2ADCL_ENA |
1191 WM8994_AIF2ADCR_ENA, 0);
1192
1193 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1194 if (val & WM8994_AIF1DSPCLK_ENA)
1195 val = WM8994_SYSDSPCLK_ENA;
1196 else
1197 val = 0;
1198 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1199 WM8994_SYSDSPCLK_ENA |
1200 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1201 break;
1202 }
1203
1204 return 0;
1205}
1206
1a38336b
MB		 1207static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1208 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1209{
1210 struct snd_soc_codec *codec = w->codec;
1211 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1212
1213 switch (event) {
1214 case SND_SOC_DAPM_PRE_PMU:
1215 wm8994->aif1clk_enable = 1;
1216 break;
a3cff81a
DP		 1217 case SND_SOC_DAPM_POST_PMD:
1218 wm8994->aif1clk_disable = 1;
1219 break;
173efa09
DP		 1220 }
1221
1222 return 0;
1223}
1224
1a38336b
MB		 1225static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1226 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1227{
1228 struct snd_soc_codec *codec = w->codec;
1229 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1230
1231 switch (event) {
1232 case SND_SOC_DAPM_PRE_PMU:
1233 wm8994->aif2clk_enable = 1;
1234 break;
a3cff81a
DP		 1235 case SND_SOC_DAPM_POST_PMD:
1236 wm8994->aif2clk_disable = 1;
1237 break;
173efa09
DP		 1238 }
1239
1240 return 0;
1241}
1242
1a38336b
MB		 1243static int late_enable_ev(struct snd_soc_dapm_widget *w,
1244 struct snd_kcontrol *kcontrol, int event)
1245{
1246 struct snd_soc_codec *codec = w->codec;
1247 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1248
1249 switch (event) {
1250 case SND_SOC_DAPM_PRE_PMU:
1251 if (wm8994->aif1clk_enable) {
c8fdc1b5 1252 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1253 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1254 WM8994_AIF1CLK_ENA_MASK,
1255 WM8994_AIF1CLK_ENA);
c8fdc1b5 1256 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1257 wm8994->aif1clk_enable = 0;
1258 }
1259 if (wm8994->aif2clk_enable) {
c8fdc1b5 1260 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1261 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1262 WM8994_AIF2CLK_ENA_MASK,
1263 WM8994_AIF2CLK_ENA);
c8fdc1b5 1264 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1265 wm8994->aif2clk_enable = 0;
1266 }
1267 break;
1268 }
1269
1270 /* We may also have postponed startup of DSP, handle that. */
1271 wm8958_aif_ev(w, kcontrol, event);
1272
1273 return 0;
1274}
1275
1276static int late_disable_ev(struct snd_soc_dapm_widget *w,
1277 struct snd_kcontrol *kcontrol, int event)
1278{
1279 struct snd_soc_codec *codec = w->codec;
1280 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1281
1282 switch (event) {
1283 case SND_SOC_DAPM_POST_PMD:
1284 if (wm8994->aif1clk_disable) {
c8fdc1b5 1285 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1286 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1287 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1288 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1289 wm8994->aif1clk_disable = 0;
1290 }
1291 if (wm8994->aif2clk_disable) {
c8fdc1b5 1292 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1293 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1294 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1295 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1296 wm8994->aif2clk_disable = 0;
1297 }
1298 break;
1299 }
1300
1301 return 0;
1302}
1303
04d28681
DP		 1304static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1305 struct snd_kcontrol *kcontrol, int event)
1306{
1307 late_enable_ev(w, kcontrol, event);
1308 return 0;
1309}
1310
b462c6e6
DP		 1311static int micbias_ev(struct snd_soc_dapm_widget *w,
1312 struct snd_kcontrol *kcontrol, int event)
1313{
1314 late_enable_ev(w, kcontrol, event);
1315 return 0;
1316}
1317
c52fd021
DP		 1318static int dac_ev(struct snd_soc_dapm_widget *w,
1319 struct snd_kcontrol *kcontrol, int event)
1320{
1321 struct snd_soc_codec *codec = w->codec;
1322 unsigned int mask = 1 << w->shift;
1323
1324 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1325 mask, mask);
1326 return 0;
1327}
1328
9e6e96a1
MB		 1329static const char *adc_mux_text[] = {
1330 "ADC",
1331 "DMIC",
1332};
1333
1334static const struct soc_enum adc_enum =
1335 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1336
1337static const struct snd_kcontrol_new adcl_mux =
1338 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1339
1340static const struct snd_kcontrol_new adcr_mux =
1341 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1342
1343static const struct snd_kcontrol_new left_speaker_mixer[] = {
1344SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1345SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1346SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1347SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1348SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1349};
1350
1351static const struct snd_kcontrol_new right_speaker_mixer[] = {
1352SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1353SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1354SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1355SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1356SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1357};
1358
1359/* Debugging; dump chip status after DAPM transitions */
1360static int post_ev(struct snd_soc_dapm_widget *w,
1361 struct snd_kcontrol *kcontrol, int event)
1362{
1363 struct snd_soc_codec *codec = w->codec;
1364 dev_dbg(codec->dev, "SRC status: %x\n",
1365 snd_soc_read(codec,
1366 WM8994_RATE_STATUS));
1367 return 0;
1368}
1369
1370static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1371SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1372 1, 1, 0),
1373SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1374 0, 1, 0),
1375};
1376
1377static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1378SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1379 1, 1, 0),
1380SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1381 0, 1, 0),
1382};
1383
a3257ba8
MB		 1384static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1385SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1386 1, 1, 0),
1387SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1388 0, 1, 0),
1389};
1390
1391static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1392SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1393 1, 1, 0),
1394SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1395 0, 1, 0),
1396};
1397
9e6e96a1
MB		 1398static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1399SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1400 5, 1, 0),
1401SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1402 4, 1, 0),
1403SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1404 2, 1, 0),
1405SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1406 1, 1, 0),
1407SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1408 0, 1, 0),
1409};
1410
1411static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1412SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1413 5, 1, 0),
1414SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1415 4, 1, 0),
1416SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1417 2, 1, 0),
1418SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1419 1, 1, 0),
1420SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1421 0, 1, 0),
1422};
1423
1424#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1425{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1426 .info = snd_soc_info_volsw, \
1427 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1428 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1429
1430static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1431 struct snd_ctl_elem_value *ucontrol)
1432{
9d03545d
JN		 1433 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1434 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1435 struct snd_soc_codec *codec = w->codec;
1436 int ret;
1437
1438 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1439
c340304d 1440 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1441
1442 return ret;
1443}
1444
1445static const struct snd_kcontrol_new dac1l_mix[] = {
1446WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1447 5, 1, 0),
1448WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1449 4, 1, 0),
1450WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1451 2, 1, 0),
1452WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1453 1, 1, 0),
1454WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455 0, 1, 0),
1456};
1457
1458static const struct snd_kcontrol_new dac1r_mix[] = {
1459WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1460 5, 1, 0),
1461WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1462 4, 1, 0),
1463WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1464 2, 1, 0),
1465WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1466 1, 1, 0),
1467WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468 0, 1, 0),
1469};
1470
1471static const char *sidetone_text[] = {
1472 "ADC/DMIC1", "DMIC2",
1473};
1474
1475static const struct soc_enum sidetone1_enum =
1476 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1477
1478static const struct snd_kcontrol_new sidetone1_mux =
1479 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1480
1481static const struct soc_enum sidetone2_enum =
1482 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1483
1484static const struct snd_kcontrol_new sidetone2_mux =
1485 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1486
1487static const char *aif1dac_text[] = {
1488 "AIF1DACDAT", "AIF3DACDAT",
1489};
1490
1491static const struct soc_enum aif1dac_enum =
1492 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1493
1494static const struct snd_kcontrol_new aif1dac_mux =
1495 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1496
1497static const char *aif2dac_text[] = {
1498 "AIF2DACDAT", "AIF3DACDAT",
1499};
1500
1501static const struct soc_enum aif2dac_enum =
1502 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1503
1504static const struct snd_kcontrol_new aif2dac_mux =
1505 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1506
1507static const char *aif2adc_text[] = {
1508 "AIF2ADCDAT", "AIF3DACDAT",
1509};
1510
1511static const struct soc_enum aif2adc_enum =
1512 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1513
1514static const struct snd_kcontrol_new aif2adc_mux =
1515 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1516
1517static const char *aif3adc_text[] = {
c4431df0 1518 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1519};
1520
c4431df0 1521static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1522 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1523
c4431df0
MB		 1524static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1525 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1526
1527static const struct soc_enum wm8958_aif3adc_enum =
1528 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1529
1530static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1531 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1532
1533static const char *mono_pcm_out_text[] = {
c1a4ecd9 1534 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1535};
1536
1537static const struct soc_enum mono_pcm_out_enum =
1538 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1539
1540static const struct snd_kcontrol_new mono_pcm_out_mux =
1541 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1542
1543static const char *aif2dac_src_text[] = {
1544 "AIF2", "AIF3",
1545};
1546
1547/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1548static const struct soc_enum aif2dacl_src_enum =
1549 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1550
1551static const struct snd_kcontrol_new aif2dacl_src_mux =
1552 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1553
1554static const struct soc_enum aif2dacr_src_enum =
1555 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1556
1557static const struct snd_kcontrol_new aif2dacr_src_mux =
1558 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1559
173efa09 1560static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1561SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1562 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1563SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1564 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1565
1566SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1567 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1568SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1569 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1570SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1571 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1572SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1573 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1574SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1575 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1576
1577SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1578 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1579 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1580SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1581 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1582 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1583SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1584 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1585SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1586 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1587
1588SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1589};
1590
1591static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1592SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1593 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1594 SND_SOC_DAPM_PRE_PMD),
1a38336b 1595SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1596 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1597 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1598SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1599SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1600 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1601SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1602 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1603SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1604SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1605};
1606
c52fd021
DP		 1607static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1608SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1609 dac_ev, SND_SOC_DAPM_PRE_PMU),
1610SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1611 dac_ev, SND_SOC_DAPM_PRE_PMU),
1612SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1613 dac_ev, SND_SOC_DAPM_PRE_PMU),
1614SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1615 dac_ev, SND_SOC_DAPM_PRE_PMU),
1616};
1617
1618static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1619SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1620SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1621SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1622SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1623};
1624
04d28681 1625static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1626SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1627 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1628SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1629 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1630};
1631
1632static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1633SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1634SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1635};
1636
9e6e96a1
MB		 1637static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1638SND_SOC_DAPM_INPUT("DMIC1DAT"),
1639SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1640SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1641
b462c6e6
DP		 1642SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1643 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1644SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1645 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1646
9e6e96a1 1647SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB		 1648 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1649 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1650
1a38336b
MB		 1651SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1652SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1653SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1654
7f94de48 1655SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1656 0, SND_SOC_NOPM, 9, 0),
7f94de48 1657SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1658 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1659SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1660 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1661 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1662SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1663 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1664 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1665
7f94de48 1666SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1667 0, SND_SOC_NOPM, 11, 0),
7f94de48 1668SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1669 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1670SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1671 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1672 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1673SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1674 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1675 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1676
1677SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1678 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1679SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1680 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1681
a3257ba8
MB		 1682SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1683 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1684SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1685 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1686
9e6e96a1
MB		 1687SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1688 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1689SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1690 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1691
1692SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1693SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1694
1695SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1696 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1697SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1698 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1699
1700SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1701 SND_SOC_NOPM, 13, 0),
9e6e96a1 1702SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1703 SND_SOC_NOPM, 12, 0),
d6addcc9 1704SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1705 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1706 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1707SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1708 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1709 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1710
5567d8c6
MB		 1711SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1712SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1713SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1714SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1715
1716SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1717SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1718SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1719
5567d8c6
MB		 1720SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1721SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1722
1723SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1724
1725SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1726SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1727SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1728SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1729
1730/* Power is done with the muxes since the ADC power also controls the
1731 * downsampling chain, the chip will automatically manage the analogue
1732 * specific portions.
1733 */
1734SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1735SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1736
9e6e96a1
MB		 1737SND_SOC_DAPM_POST("Debug log", post_ev),
1738};
1739
c4431df0
MB		 1740static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1741SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1742};
9e6e96a1 1743
c4431df0 1744static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1745SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1746SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1747SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1748SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1749SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1750};
1751
1752static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1753 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1754 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1755
1756 { "DSP1CLK", NULL, "CLK_SYS" },
1757 { "DSP2CLK", NULL, "CLK_SYS" },
1758 { "DSPINTCLK", NULL, "CLK_SYS" },
1759
1760 { "AIF1ADC1L", NULL, "AIF1CLK" },
1761 { "AIF1ADC1L", NULL, "DSP1CLK" },
1762 { "AIF1ADC1R", NULL, "AIF1CLK" },
1763 { "AIF1ADC1R", NULL, "DSP1CLK" },
1764 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1765
1766 { "AIF1DAC1L", NULL, "AIF1CLK" },
1767 { "AIF1DAC1L", NULL, "DSP1CLK" },
1768 { "AIF1DAC1R", NULL, "AIF1CLK" },
1769 { "AIF1DAC1R", NULL, "DSP1CLK" },
1770 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1771
1772 { "AIF1ADC2L", NULL, "AIF1CLK" },
1773 { "AIF1ADC2L", NULL, "DSP1CLK" },
1774 { "AIF1ADC2R", NULL, "AIF1CLK" },
1775 { "AIF1ADC2R", NULL, "DSP1CLK" },
1776 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1777
1778 { "AIF1DAC2L", NULL, "AIF1CLK" },
1779 { "AIF1DAC2L", NULL, "DSP1CLK" },
1780 { "AIF1DAC2R", NULL, "AIF1CLK" },
1781 { "AIF1DAC2R", NULL, "DSP1CLK" },
1782 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1783
1784 { "AIF2ADCL", NULL, "AIF2CLK" },
1785 { "AIF2ADCL", NULL, "DSP2CLK" },
1786 { "AIF2ADCR", NULL, "AIF2CLK" },
1787 { "AIF2ADCR", NULL, "DSP2CLK" },
1788 { "AIF2ADCR", NULL, "DSPINTCLK" },
1789
1790 { "AIF2DACL", NULL, "AIF2CLK" },
1791 { "AIF2DACL", NULL, "DSP2CLK" },
1792 { "AIF2DACR", NULL, "AIF2CLK" },
1793 { "AIF2DACR", NULL, "DSP2CLK" },
1794 { "AIF2DACR", NULL, "DSPINTCLK" },
1795
1796 { "DMIC1L", NULL, "DMIC1DAT" },
1797 { "DMIC1L", NULL, "CLK_SYS" },
1798 { "DMIC1R", NULL, "DMIC1DAT" },
1799 { "DMIC1R", NULL, "CLK_SYS" },
1800 { "DMIC2L", NULL, "DMIC2DAT" },
1801 { "DMIC2L", NULL, "CLK_SYS" },
1802 { "DMIC2R", NULL, "DMIC2DAT" },
1803 { "DMIC2R", NULL, "CLK_SYS" },
1804
1805 { "ADCL", NULL, "AIF1CLK" },
1806 { "ADCL", NULL, "DSP1CLK" },
1807 { "ADCL", NULL, "DSPINTCLK" },
1808
1809 { "ADCR", NULL, "AIF1CLK" },
1810 { "ADCR", NULL, "DSP1CLK" },
1811 { "ADCR", NULL, "DSPINTCLK" },
1812
1813 { "ADCL Mux", "ADC", "ADCL" },
1814 { "ADCL Mux", "DMIC", "DMIC1L" },
1815 { "ADCR Mux", "ADC", "ADCR" },
1816 { "ADCR Mux", "DMIC", "DMIC1R" },
1817
1818 { "DAC1L", NULL, "AIF1CLK" },
1819 { "DAC1L", NULL, "DSP1CLK" },
1820 { "DAC1L", NULL, "DSPINTCLK" },
1821
1822 { "DAC1R", NULL, "AIF1CLK" },
1823 { "DAC1R", NULL, "DSP1CLK" },
1824 { "DAC1R", NULL, "DSPINTCLK" },
1825
1826 { "DAC2L", NULL, "AIF2CLK" },
1827 { "DAC2L", NULL, "DSP2CLK" },
1828 { "DAC2L", NULL, "DSPINTCLK" },
1829
1830 { "DAC2R", NULL, "AIF2DACR" },
1831 { "DAC2R", NULL, "AIF2CLK" },
1832 { "DAC2R", NULL, "DSP2CLK" },
1833 { "DAC2R", NULL, "DSPINTCLK" },
1834
1835 { "TOCLK", NULL, "CLK_SYS" },
1836
5567d8c6
MB		 1837 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1838 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1839 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1840
1841 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1842 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1843 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1844
9e6e96a1
MB		 1845 /* AIF1 outputs */
1846 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1847 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1848 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1849
1850 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1851 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1852 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1853
a3257ba8
MB		 1854 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1855 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1856 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1857
1858 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1859 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1860 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1861
9e6e96a1
MB		 1862 /* Pin level routing for AIF3 */
1863 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1864 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1865 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1866 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1867
9e6e96a1
MB		 1868 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1869 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1870 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1871 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1872 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1873 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1874 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1875
1876 /* DAC1 inputs */
9e6e96a1
MB		 1877 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1878 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1879 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1880 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1881 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1882
9e6e96a1
MB		 1883 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1884 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1885 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1886 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1887 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1888
1889 /* DAC2/AIF2 outputs */
1890 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1891 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1892 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1893 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1894 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1895 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1896
1897 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1898 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1899 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1900 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1901 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1902 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1903
7f94de48
MB		 1904 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1905 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1906 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1907 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1908
9e6e96a1
MB		 1909 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1910
1911 /* AIF3 output */
1912 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1913 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1914 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1915 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1916 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1917 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1918 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1919 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1920
1921 /* Sidetone */
1922 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1923 { "Left Sidetone", "DMIC2", "DMIC2L" },
1924 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1925 { "Right Sidetone", "DMIC2", "DMIC2R" },
1926
1927 /* Output stages */
1928 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1929 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1930
1931 { "SPKL", "DAC1 Switch", "DAC1L" },
1932 { "SPKL", "DAC2 Switch", "DAC2L" },
1933
1934 { "SPKR", "DAC1 Switch", "DAC1R" },
1935 { "SPKR", "DAC2 Switch", "DAC2R" },
1936
1937 { "Left Headphone Mux", "DAC", "DAC1L" },
1938 { "Right Headphone Mux", "DAC", "DAC1R" },
1939};
1940
173efa09
DP		 1941static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1942 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1943 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1944 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1945 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1946 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1947 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1948 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1949 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1950};
1951
1952static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1953 { "DAC1L", NULL, "DAC1L Mixer" },
1954 { "DAC1R", NULL, "DAC1R Mixer" },
1955 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1956 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1957};
1958
6ed8f148
MB		 1959static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1960 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1961 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1962 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1963 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1964 { "MICBIAS1", NULL, "CLK_SYS" },
1965 { "MICBIAS1", NULL, "MICBIAS Supply" },
1966 { "MICBIAS2", NULL, "CLK_SYS" },
1967 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1968};
1969
c4431df0
MB		 1970static const struct snd_soc_dapm_route wm8994_intercon[] = {
1971 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1972 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1973 { "MICBIAS1", NULL, "VMID" },
1974 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1975};
1976
1977static const struct snd_soc_dapm_route wm8958_intercon[] = {
1978 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1979 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1980
1981 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1982 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1983 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1984 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1985
8c5b842b
MB		 1986 { "AIF3DACDAT", NULL, "AIF3" },
1987 { "AIF3ADCDAT", NULL, "AIF3" },
1988
c4431df0
MB		 1989 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1990 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1991
1992 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1993};
1994
9e6e96a1
MB		 1995/* The size in bits of the FLL divide multiplied by 10
1996 * to allow rounding later */
1997#define FIXED_FLL_SIZE ((1 << 16) * 10)
1998
1999struct fll_div {
2000 u16 outdiv;
2001 u16 n;
2002 u16 k;
2003 u16 clk_ref_div;
2004 u16 fll_fratio;
2005};
2006
2007static int wm8994_get_fll_config(struct fll_div *fll,
2008 int freq_in, int freq_out)
2009{
2010 u64 Kpart;
2011 unsigned int K, Ndiv, Nmod;
2012
2013 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2014
2015 /* Scale the input frequency down to <= 13.5MHz */
2016 fll->clk_ref_div = 0;
2017 while (freq_in > 13500000) {
2018 fll->clk_ref_div++;
2019 freq_in /= 2;
2020
2021 if (fll->clk_ref_div > 3)
2022 return -EINVAL;
2023 }
2024 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2025
2026 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2027 fll->outdiv = 3;
2028 while (freq_out * (fll->outdiv + 1) < 90000000) {
2029 fll->outdiv++;
2030 if (fll->outdiv > 63)
2031 return -EINVAL;
2032 }
2033 freq_out *= fll->outdiv + 1;
2034 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2035
2036 if (freq_in > 1000000) {
2037 fll->fll_fratio = 0;
7d48a6ac
MB		 2038 } else if (freq_in > 256000) {
2039 fll->fll_fratio = 1;
2040 freq_in *= 2;
2041 } else if (freq_in > 128000) {
2042 fll->fll_fratio = 2;
2043 freq_in *= 4;
2044 } else if (freq_in > 64000) {
9e6e96a1
MB		 2045 fll->fll_fratio = 3;
2046 freq_in *= 8;
7d48a6ac
MB		 2047 } else {
2048 fll->fll_fratio = 4;
2049 freq_in *= 16;
9e6e96a1
MB		 2050 }
2051 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2052
2053 /* Now, calculate N.K */
2054 Ndiv = freq_out / freq_in;
2055
2056 fll->n = Ndiv;
2057 Nmod = freq_out % freq_in;
2058 pr_debug("Nmod=%d\n", Nmod);
2059
2060 /* Calculate fractional part - scale up so we can round. */
2061 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2062
2063 do_div(Kpart, freq_in);
2064
2065 K = Kpart & 0xFFFFFFFF;
2066
2067 if ((K % 10) >= 5)
2068 K += 5;
2069
2070 /* Move down to proper range now rounding is done */
2071 fll->k = K / 10;
2072
2073 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2074
2075 return 0;
2076}
2077
f0fba2ad 2078static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2079 unsigned int freq_in, unsigned int freq_out)
2080{
b2c812e2 2081 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2082 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2083 int reg_offset, ret;
2084 struct fll_div fll;
e413ba88 2085 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2086 unsigned long timeout;
4b7ed83a 2087 bool was_enabled;
9e6e96a1 2088
9e6e96a1
MB		 2089 switch (id) {
2090 case WM8994_FLL1:
2091 reg_offset = 0;
2092 id = 0;
e413ba88 2093 aif_src = 0x10;
9e6e96a1
MB		 2094 break;
2095 case WM8994_FLL2:
2096 reg_offset = 0x20;
2097 id = 1;
e413ba88 2098 aif_src = 0x18;
9e6e96a1
MB		 2099 break;
2100 default:
2101 return -EINVAL;
2102 }
2103
4b7ed83a
MB		 2104 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2105 was_enabled = reg & WM8994_FLL1_ENA;
2106
136ff2a2 2107 switch (src) {
7add84aa
MB		 2108 case 0:
2109 /* Allow no source specification when stopping */
2110 if (freq_out)
2111 return -EINVAL;
4514e899 2112 src = wm8994->fll[id].src;
7add84aa 2113 break;
136ff2a2
MB		 2114 case WM8994_FLL_SRC_MCLK1:
2115 case WM8994_FLL_SRC_MCLK2:
2116 case WM8994_FLL_SRC_LRCLK:
2117 case WM8994_FLL_SRC_BCLK:
2118 break;
fbfe6983
MB		 2119 case WM8994_FLL_SRC_INTERNAL:
2120 freq_in = 12000000;
2121 freq_out = 12000000;
2122 break;
136ff2a2
MB		 2123 default:
2124 return -EINVAL;
2125 }
2126
9e6e96a1
MB		 2127 /* Are we changing anything? */
2128 if (wm8994->fll[id].src == src &&
2129 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2130 return 0;
2131
2132 /* If we're stopping the FLL redo the old config - no
2133 * registers will actually be written but we avoid GCC flow
2134 * analysis bugs spewing warnings.
2135 */
2136 if (freq_out)
2137 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2138 else
2139 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2140 wm8994->fll[id].out);
2141 if (ret < 0)
2142 return ret;
2143
e413ba88
MB		 2144 /* Make sure that we're not providing SYSCLK right now */
2145 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2146 if (clk1 & WM8994_SYSCLK_SRC)
2147 aif_reg = WM8994_AIF2_CLOCKING_1;
2148 else
2149 aif_reg = WM8994_AIF1_CLOCKING_1;
2150 reg = snd_soc_read(codec, aif_reg);
2151
2152 if ((reg & WM8994_AIF1CLK_ENA) &&
2153 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2154 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2155 id + 1);
2156 return -EBUSY;
2157 }
9e6e96a1
MB		 2158
2159 /* We always need to disable the FLL while reconfiguring */
2160 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2161 WM8994_FLL1_ENA, 0);
2162
20dc24a9 2163 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2164 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2165 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2166 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2167 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2168 goto out;
2169 }
2170
9e6e96a1
MB		 2171 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2172 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2173 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2174 WM8994_FLL1_OUTDIV_MASK |
2175 WM8994_FLL1_FRATIO_MASK, reg);
2176
b16db745
MB		 2177 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2178 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2179
2180 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2181 WM8994_FLL1_N_MASK,
7435d4ee 2182 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1
MB		 2183
2184 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2185 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB		 2186 WM8994_FLL1_REFCLK_DIV_MASK |
2187 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB		 2188 ((src == WM8994_FLL_SRC_INTERNAL)
2189 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB		 2190 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2191 (src - 1));
9e6e96a1 2192
f0f5039c
MB		 2193 /* Clear any pending completion from a previous failure */
2194 try_wait_for_completion(&wm8994->fll_locked[id]);
2195
9e6e96a1
MB		 2196 /* Enable (with fractional mode if required) */
2197 if (freq_out) {
4b7ed83a
MB		 2198 /* Enable VMID if we need it */
2199 if (!was_enabled) {
af6b6fe4
MB		 2200 active_reference(codec);
2201
4b7ed83a
MB		 2202 switch (control->type) {
2203 case WM8994:
2204 vmid_reference(codec);
2205 break;
2206 case WM8958:
2207 if (wm8994->revision < 1)
2208 vmid_reference(codec);
2209 break;
2210 default:
2211 break;
2212 }
2213 }
2214
fbfe6983
MB		 2215 reg = WM8994_FLL1_ENA;
2216
9e6e96a1 2217 if (fll.k)
fbfe6983
MB		 2218 reg |= WM8994_FLL1_FRAC;
2219 if (src == WM8994_FLL_SRC_INTERNAL)
2220 reg |= WM8994_FLL1_OSC_ENA;
2221
9e6e96a1 2222 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB		 2223 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2224 WM8994_FLL1_FRAC, reg);
8e9ddf81 2225
c7ebf932
MB		 2226 if (wm8994->fll_locked_irq) {
2227 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2228 msecs_to_jiffies(10));
2229 if (timeout == 0)
2230 dev_warn(codec->dev,
2231 "Timed out waiting for FLL lock\n");
2232 } else {
2233 msleep(5);
2234 }
4b7ed83a
MB		 2235 } else {
2236 if (was_enabled) {
2237 switch (control->type) {
2238 case WM8994:
2239 vmid_dereference(codec);
2240 break;
2241 case WM8958:
2242 if (wm8994->revision < 1)
2243 vmid_dereference(codec);
2244 break;
2245 default:
2246 break;
2247 }
af6b6fe4
MB		 2248
2249 active_dereference(codec);
4b7ed83a 2250 }
9e6e96a1
MB		 2251 }
2252
20dc24a9 2253out:
9e6e96a1
MB		 2254 wm8994->fll[id].in = freq_in;
2255 wm8994->fll[id].out = freq_out;
136ff2a2 2256 wm8994->fll[id].src = src;
9e6e96a1 2257
9e6e96a1
MB		 2258 configure_clock(codec);
2259
cd22000a
MB		 2260 /*
2261 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2262 * for detection.
2263 */
2264 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2265 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2266 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2267 WM8994_AIF1CLK_RATE_MASK, 0x1);
2268 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2269 WM8994_AIF2CLK_RATE_MASK, 0x1);
2270 }
2271
9e6e96a1
MB		 2272 return 0;
2273}
2274
c7ebf932
MB		 2275static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2276{
2277 struct completion *completion = data;
2278
2279 complete(completion);
2280
2281 return IRQ_HANDLED;
2282}
f0fba2ad 2283
66b47fdb
MB		 2284static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2285
f0fba2ad
LG		 2286static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2287 unsigned int freq_in, unsigned int freq_out)
2288{
2289 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2290}
2291
9e6e96a1
MB		 2292static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2293 int clk_id, unsigned int freq, int dir)
2294{
2295 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2296 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2297 int i;
9e6e96a1
MB		 2298
2299 switch (dai->id) {
2300 case 1:
2301 case 2:
2302 break;
2303
2304 default:
2305 /* AIF3 shares clocking with AIF1/2 */
2306 return -EINVAL;
2307 }
2308
2309 switch (clk_id) {
2310 case WM8994_SYSCLK_MCLK1:
2311 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2312 wm8994->mclk[0] = freq;
2313 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2314 dai->id, freq);
2315 break;
2316
2317 case WM8994_SYSCLK_MCLK2:
2318 /* TODO: Set GPIO AF */
2319 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2320 wm8994->mclk[1] = freq;
2321 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2322 dai->id, freq);
2323 break;
2324
2325 case WM8994_SYSCLK_FLL1:
2326 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2327 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2328 break;
2329
2330 case WM8994_SYSCLK_FLL2:
2331 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2332 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2333 break;
2334
66b47fdb
MB		 2335 case WM8994_SYSCLK_OPCLK:
2336 /* Special case - a division (times 10) is given and
c1a4ecd9 2337 * no effect on main clocking.
66b47fdb
MB		 2338 */
2339 if (freq) {
2340 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2341 if (opclk_divs[i] == freq)
2342 break;
2343 if (i == ARRAY_SIZE(opclk_divs))
2344 return -EINVAL;
2345 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2346 WM8994_OPCLK_DIV_MASK, i);
2347 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2348 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2349 } else {
2350 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2351 WM8994_OPCLK_ENA, 0);
2352 }
2353
9e6e96a1
MB		 2354 default:
2355 return -EINVAL;
2356 }
2357
2358 configure_clock(codec);
2359
6730049a
MB		 2360 /*
2361 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2362 * for detection.
2363 */
2364 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2365 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2366 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2367 WM8994_AIF1CLK_RATE_MASK, 0x1);
2368 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2369 WM8994_AIF2CLK_RATE_MASK, 0x1);
2370 }
2371
9e6e96a1
MB		 2372 return 0;
2373}
2374
2375static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2376 enum snd_soc_bias_level level)
2377{
b6b05691 2378 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2379 struct wm8994 *control = wm8994->wm8994;
b6b05691 2380
5f2f3890
MB		 2381 wm_hubs_set_bias_level(codec, level);
2382
9e6e96a1
MB		 2383 switch (level) {
2384 case SND_SOC_BIAS_ON:
2385 break;
2386
2387 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2388 /* MICBIAS into regulating mode */
2389 switch (control->type) {
2390 case WM8958:
2391 case WM1811:
2392 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2393 WM8958_MICB1_MODE, 0);
2394 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2395 WM8958_MICB2_MODE, 0);
2396 break;
2397 default:
2398 break;
2399 }
af6b6fe4
MB		 2400
2401 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2402 active_reference(codec);
9e6e96a1
MB		 2403 break;
2404
2405 case SND_SOC_BIAS_STANDBY:
ce6120cc 2406 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2407 switch (control->type) {
8bc3c2c2
MB		 2408 case WM8958:
2409 if (wm8994->revision == 0) {
2410 /* Optimise performance for rev A */
8bc3c2c2
MB		 2411 snd_soc_update_bits(codec,
2412 WM8958_CHARGE_PUMP_2,
2413 WM8958_CP_DISCH,
2414 WM8958_CP_DISCH);
2415 }
2416 break;
81204c84 2417
462835e4 2418 default:
81204c84 2419 break;
b6b05691 2420 }
9e6e96a1
MB		 2421
2422 /* Discharge LINEOUT1 & 2 */
2423 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2424 WM8994_LINEOUT1_DISCH |
2425 WM8994_LINEOUT2_DISCH,
2426 WM8994_LINEOUT1_DISCH |
2427 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2428 }
2429
af6b6fe4
MB		 2430 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2431 active_dereference(codec);
2432
500fa30e
MB		 2433 /* MICBIAS into bypass mode on newer devices */
2434 switch (control->type) {
2435 case WM8958:
2436 case WM1811:
2437 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2438 WM8958_MICB1_MODE,
2439 WM8958_MICB1_MODE);
2440 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2441 WM8958_MICB2_MODE,
2442 WM8958_MICB2_MODE);
2443 break;
2444 default:
2445 break;
2446 }
9e6e96a1
MB		 2447 break;
2448
2449 case SND_SOC_BIAS_OFF:
4105ab84 2450 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2451 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2452 break;
2453 }
5f2f3890 2454
ce6120cc 2455 codec->dapm.bias_level = level;
af6b6fe4 2456
22f8d055
MB		 2457 return 0;
2458}
2459
2460int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2461{
2462 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2463
2464 switch (mode) {
2465 case WM8994_VMID_NORMAL:
2466 if (wm8994->hubs.lineout1_se) {
2467 snd_soc_dapm_disable_pin(&codec->dapm,
2468 "LINEOUT1N Driver");
2469 snd_soc_dapm_disable_pin(&codec->dapm,
2470 "LINEOUT1P Driver");
2471 }
2472 if (wm8994->hubs.lineout2_se) {
2473 snd_soc_dapm_disable_pin(&codec->dapm,
2474 "LINEOUT2N Driver");
2475 snd_soc_dapm_disable_pin(&codec->dapm,
2476 "LINEOUT2P Driver");
2477 }
2478
2479 /* Do the sync with the old mode to allow it to clean up */
2480 snd_soc_dapm_sync(&codec->dapm);
2481 wm8994->vmid_mode = mode;
2482 break;
2483
2484 case WM8994_VMID_FORCE:
2485 if (wm8994->hubs.lineout1_se) {
2486 snd_soc_dapm_force_enable_pin(&codec->dapm,
2487 "LINEOUT1N Driver");
2488 snd_soc_dapm_force_enable_pin(&codec->dapm,
2489 "LINEOUT1P Driver");
2490 }
2491 if (wm8994->hubs.lineout2_se) {
2492 snd_soc_dapm_force_enable_pin(&codec->dapm,
2493 "LINEOUT2N Driver");
2494 snd_soc_dapm_force_enable_pin(&codec->dapm,
2495 "LINEOUT2P Driver");
2496 }
2497
2498 wm8994->vmid_mode = mode;
2499 snd_soc_dapm_sync(&codec->dapm);
2500 break;
2501
2502 default:
2503 return -EINVAL;
2504 }
2505
9e6e96a1
MB		 2506 return 0;
2507}
2508
2509static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2510{
2511 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2512 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2513 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2514 int ms_reg;
2515 int aif1_reg;
2516 int ms = 0;
2517 int aif1 = 0;
2518
2519 switch (dai->id) {
2520 case 1:
2521 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2522 aif1_reg = WM8994_AIF1_CONTROL_1;
2523 break;
2524 case 2:
2525 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2526 aif1_reg = WM8994_AIF2_CONTROL_1;
2527 break;
2528 default:
2529 return -EINVAL;
2530 }
2531
2532 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2533 case SND_SOC_DAIFMT_CBS_CFS:
2534 break;
2535 case SND_SOC_DAIFMT_CBM_CFM:
2536 ms = WM8994_AIF1_MSTR;
2537 break;
2538 default:
2539 return -EINVAL;
2540 }
2541
2542 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2543 case SND_SOC_DAIFMT_DSP_B:
2544 aif1 |= WM8994_AIF1_LRCLK_INV;
2545 case SND_SOC_DAIFMT_DSP_A:
2546 aif1 |= 0x18;
2547 break;
2548 case SND_SOC_DAIFMT_I2S:
2549 aif1 |= 0x10;
2550 break;
2551 case SND_SOC_DAIFMT_RIGHT_J:
2552 break;
2553 case SND_SOC_DAIFMT_LEFT_J:
2554 aif1 |= 0x8;
2555 break;
2556 default:
2557 return -EINVAL;
2558 }
2559
2560 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2561 case SND_SOC_DAIFMT_DSP_A:
2562 case SND_SOC_DAIFMT_DSP_B:
2563 /* frame inversion not valid for DSP modes */
2564 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2565 case SND_SOC_DAIFMT_NB_NF:
2566 break;
2567 case SND_SOC_DAIFMT_IB_NF:
2568 aif1 |= WM8994_AIF1_BCLK_INV;
2569 break;
2570 default:
2571 return -EINVAL;
2572 }
2573 break;
2574
2575 case SND_SOC_DAIFMT_I2S:
2576 case SND_SOC_DAIFMT_RIGHT_J:
2577 case SND_SOC_DAIFMT_LEFT_J:
2578 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2579 case SND_SOC_DAIFMT_NB_NF:
2580 break;
2581 case SND_SOC_DAIFMT_IB_IF:
2582 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2583 break;
2584 case SND_SOC_DAIFMT_IB_NF:
2585 aif1 |= WM8994_AIF1_BCLK_INV;
2586 break;
2587 case SND_SOC_DAIFMT_NB_IF:
2588 aif1 |= WM8994_AIF1_LRCLK_INV;
2589 break;
2590 default:
2591 return -EINVAL;
2592 }
2593 break;
2594 default:
2595 return -EINVAL;
2596 }
2597
c4431df0
MB		 2598 /* The AIF2 format configuration needs to be mirrored to AIF3
2599 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2600 switch (control->type) {
2601 case WM1811:
2602 case WM8958:
2603 if (dai->id == 2)
2604 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2605 WM8994_AIF1_LRCLK_INV |
2606 WM8958_AIF3_FMT_MASK, aif1);
2607 break;
2608
2609 default:
2610 break;
2611 }
c4431df0 2612
9e6e96a1
MB		 2613 snd_soc_update_bits(codec, aif1_reg,
2614 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2615 WM8994_AIF1_FMT_MASK,
2616 aif1);
2617 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2618 ms);
2619
2620 return 0;
2621}
2622
2623static struct {
2624 int val, rate;
2625} srs[] = {
2626 { 0, 8000 },
2627 { 1, 11025 },
2628 { 2, 12000 },
2629 { 3, 16000 },
2630 { 4, 22050 },
2631 { 5, 24000 },
2632 { 6, 32000 },
2633 { 7, 44100 },
2634 { 8, 48000 },
2635 { 9, 88200 },
2636 { 10, 96000 },
2637};
2638
2639static int fs_ratios[] = {
2640 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2641};
2642
2643static int bclk_divs[] = {
2644 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2645 640, 880, 960, 1280, 1760, 1920
2646};
2647
2648static int wm8994_hw_params(struct snd_pcm_substream *substream,
2649 struct snd_pcm_hw_params *params,
2650 struct snd_soc_dai *dai)
2651{
2652 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2653 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2654 int aif1_reg;
b1e43d93 2655 int aif2_reg;
9e6e96a1
MB		 2656 int bclk_reg;
2657 int lrclk_reg;
2658 int rate_reg;
2659 int aif1 = 0;
b1e43d93 2660 int aif2 = 0;
9e6e96a1
MB		 2661 int bclk = 0;
2662 int lrclk = 0;
2663 int rate_val = 0;
2664 int id = dai->id - 1;
2665
2666 int i, cur_val, best_val, bclk_rate, best;
2667
2668 switch (dai->id) {
2669 case 1:
2670 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2671 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2672 bclk_reg = WM8994_AIF1_BCLK;
2673 rate_reg = WM8994_AIF1_RATE;
2674 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2675 wm8994->lrclk_shared[0]) {
9e6e96a1 2676 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2677 } else {
9e6e96a1 2678 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2679 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2680 }
9e6e96a1
MB		 2681 break;
2682 case 2:
2683 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2684 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2685 bclk_reg = WM8994_AIF2_BCLK;
2686 rate_reg = WM8994_AIF2_RATE;
2687 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2688 wm8994->lrclk_shared[1]) {
9e6e96a1 2689 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2690 } else {
9e6e96a1 2691 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2692 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2693 }
9e6e96a1
MB		 2694 break;
2695 default:
2696 return -EINVAL;
2697 }
2698
b8edf3e5 2699 bclk_rate = params_rate(params) * 4;
9e6e96a1
MB		 2700 switch (params_format(params)) {
2701 case SNDRV_PCM_FORMAT_S16_LE:
2702 bclk_rate *= 16;
2703 break;
2704 case SNDRV_PCM_FORMAT_S20_3LE:
2705 bclk_rate *= 20;
2706 aif1 |= 0x20;
2707 break;
2708 case SNDRV_PCM_FORMAT_S24_LE:
2709 bclk_rate *= 24;
2710 aif1 |= 0x40;
2711 break;
2712 case SNDRV_PCM_FORMAT_S32_LE:
2713 bclk_rate *= 32;
2714 aif1 |= 0x60;
2715 break;
2716 default:
2717 return -EINVAL;
2718 }
2719
2720 /* Try to find an appropriate sample rate; look for an exact match. */
2721 for (i = 0; i < ARRAY_SIZE(srs); i++)
2722 if (srs[i].rate == params_rate(params))
2723 break;
2724 if (i == ARRAY_SIZE(srs))
2725 return -EINVAL;
2726 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2727
2728 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2729 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2730 dai->id, wm8994->aifclk[id], bclk_rate);
2731
b1e43d93
MB		 2732 if (params_channels(params) == 1 &&
2733 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2734 aif2 |= WM8994_AIF1_MONO;
2735
9e6e96a1
MB		 2736 if (wm8994->aifclk[id] == 0) {
2737 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2738 return -EINVAL;
2739 }
2740
2741 /* AIFCLK/fs ratio; look for a close match in either direction */
2742 best = 0;
2743 best_val = abs((fs_ratios[0] * params_rate(params))
2744 - wm8994->aifclk[id]);
2745 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2746 cur_val = abs((fs_ratios[i] * params_rate(params))
2747 - wm8994->aifclk[id]);
2748 if (cur_val >= best_val)
2749 continue;
2750 best = i;
2751 best_val = cur_val;
2752 }
2753 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2754 dai->id, fs_ratios[best]);
2755 rate_val |= best;
2756
2757 /* We may not get quite the right frequency if using
2758 * approximate clocks so look for the closest match that is
2759 * higher than the target (we need to ensure that there enough
2760 * BCLKs to clock out the samples).
2761 */
2762 best = 0;
2763 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2764 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2765 if (cur_val < 0) /* BCLK table is sorted */
2766 break;
2767 best = i;
2768 }
07cd8ada 2769 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2770 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2771 bclk_divs[best], bclk_rate);
2772 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2773
2774 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2775 if (!lrclk) {
2776 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2777 bclk_rate);
2778 return -EINVAL;
2779 }
9e6e96a1
MB		 2780 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2781 lrclk, bclk_rate / lrclk);
2782
2783 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2784 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2785 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2786 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2787 lrclk);
2788 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2789 WM8994_AIF1CLK_RATE_MASK, rate_val);
2790
2791 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2792 switch (dai->id) {
2793 case 1:
2794 wm8994->dac_rates[0] = params_rate(params);
2795 wm8994_set_retune_mobile(codec, 0);
2796 wm8994_set_retune_mobile(codec, 1);
2797 break;
2798 case 2:
2799 wm8994->dac_rates[1] = params_rate(params);
2800 wm8994_set_retune_mobile(codec, 2);
2801 break;
2802 }
2803 }
2804
2805 return 0;
2806}
2807
c4431df0
MB		 2808static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2809 struct snd_pcm_hw_params *params,
2810 struct snd_soc_dai *dai)
2811{
2812 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2813 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2814 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2815 int aif1_reg;
2816 int aif1 = 0;
2817
2818 switch (dai->id) {
2819 case 3:
2820 switch (control->type) {
81204c84 2821 case WM1811:
c4431df0
MB		 2822 case WM8958:
2823 aif1_reg = WM8958_AIF3_CONTROL_1;
2824 break;
2825 default:
2826 return 0;
2827 }
2828 default:
2829 return 0;
2830 }
2831
2832 switch (params_format(params)) {
2833 case SNDRV_PCM_FORMAT_S16_LE:
2834 break;
2835 case SNDRV_PCM_FORMAT_S20_3LE:
2836 aif1 |= 0x20;
2837 break;
2838 case SNDRV_PCM_FORMAT_S24_LE:
2839 aif1 |= 0x40;
2840 break;
2841 case SNDRV_PCM_FORMAT_S32_LE:
2842 aif1 |= 0x60;
2843 break;
2844 default:
2845 return -EINVAL;
2846 }
2847
2848 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2849}
2850
9e6e96a1
MB		 2851static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2852{
2853 struct snd_soc_codec *codec = codec_dai->codec;
2854 int mute_reg;
2855 int reg;
2856
2857 switch (codec_dai->id) {
2858 case 1:
2859 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2860 break;
2861 case 2:
2862 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2863 break;
2864 default:
2865 return -EINVAL;
2866 }
2867
2868 if (mute)
2869 reg = WM8994_AIF1DAC1_MUTE;
2870 else
2871 reg = 0;
2872
2873 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2874
2875 return 0;
2876}
2877
778a76e2
MB		 2878static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2879{
2880 struct snd_soc_codec *codec = codec_dai->codec;
2881 int reg, val, mask;
2882
2883 switch (codec_dai->id) {
2884 case 1:
2885 reg = WM8994_AIF1_MASTER_SLAVE;
2886 mask = WM8994_AIF1_TRI;
2887 break;
2888 case 2:
2889 reg = WM8994_AIF2_MASTER_SLAVE;
2890 mask = WM8994_AIF2_TRI;
2891 break;
778a76e2
MB		 2892 default:
2893 return -EINVAL;
2894 }
2895
2896 if (tristate)
2897 val = mask;
2898 else
2899 val = 0;
2900
78b3fb46 2901 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2902}
2903
d09f3ecf
MB		 2904static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2905{
2906 struct snd_soc_codec *codec = dai->codec;
2907
2908 /* Disable the pulls on the AIF if we're using it to save power. */
2909 snd_soc_update_bits(codec, WM8994_GPIO_3,
2910 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2911 snd_soc_update_bits(codec, WM8994_GPIO_4,
2912 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2913 snd_soc_update_bits(codec, WM8994_GPIO_5,
2914 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2915
2916 return 0;
2917}
2918
9e6e96a1
MB		 2919#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2920
2921#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2922 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2923
85e7652d 2924static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2925 .set_sysclk = wm8994_set_dai_sysclk,
2926 .set_fmt = wm8994_set_dai_fmt,
2927 .hw_params = wm8994_hw_params,
2928 .digital_mute = wm8994_aif_mute,
2929 .set_pll = wm8994_set_fll,
778a76e2 2930 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2931};
2932
85e7652d 2933static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2934 .set_sysclk = wm8994_set_dai_sysclk,
2935 .set_fmt = wm8994_set_dai_fmt,
2936 .hw_params = wm8994_hw_params,
2937 .digital_mute = wm8994_aif_mute,
2938 .set_pll = wm8994_set_fll,
778a76e2
MB		 2939 .set_tristate = wm8994_set_tristate,
2940};
2941
85e7652d 2942static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2943 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 2944};
2945
f0fba2ad 2946static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2947 {
f0fba2ad 2948 .name = "wm8994-aif1",
8c7f78b3 2949 .id = 1,
9e6e96a1
MB		 2950 .playback = {
2951 .stream_name = "AIF1 Playback",
b1e43d93 2952 .channels_min = 1,
9e6e96a1
MB		 2953 .channels_max = 2,
2954 .rates = WM8994_RATES,
2955 .formats = WM8994_FORMATS,
99b0292d 2956 .sig_bits = 24,
9e6e96a1
MB		 2957 },
2958 .capture = {
2959 .stream_name = "AIF1 Capture",
b1e43d93 2960 .channels_min = 1,
9e6e96a1
MB		 2961 .channels_max = 2,
2962 .rates = WM8994_RATES,
2963 .formats = WM8994_FORMATS,
99b0292d 2964 .sig_bits = 24,
9e6e96a1
MB		 2965 },
2966 .ops = &wm8994_aif1_dai_ops,
2967 },
2968 {
f0fba2ad 2969 .name = "wm8994-aif2",
8c7f78b3 2970 .id = 2,
9e6e96a1
MB		 2971 .playback = {
2972 .stream_name = "AIF2 Playback",
b1e43d93 2973 .channels_min = 1,
9e6e96a1
MB		 2974 .channels_max = 2,
2975 .rates = WM8994_RATES,
2976 .formats = WM8994_FORMATS,
99b0292d 2977 .sig_bits = 24,
9e6e96a1
MB		 2978 },
2979 .capture = {
2980 .stream_name = "AIF2 Capture",
b1e43d93 2981 .channels_min = 1,
9e6e96a1
MB		 2982 .channels_max = 2,
2983 .rates = WM8994_RATES,
2984 .formats = WM8994_FORMATS,
99b0292d 2985 .sig_bits = 24,
9e6e96a1 2986 },
d09f3ecf 2987 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2988 .ops = &wm8994_aif2_dai_ops,
2989 },
2990 {
f0fba2ad 2991 .name = "wm8994-aif3",
8c7f78b3 2992 .id = 3,
9e6e96a1
MB		 2993 .playback = {
2994 .stream_name = "AIF3 Playback",
b1e43d93 2995 .channels_min = 1,
9e6e96a1
MB		 2996 .channels_max = 2,
2997 .rates = WM8994_RATES,
2998 .formats = WM8994_FORMATS,
99b0292d 2999 .sig_bits = 24,
9e6e96a1 3000 },
a8462bde 3001 .capture = {
9e6e96a1 3002 .stream_name = "AIF3 Capture",
b1e43d93 3003 .channels_min = 1,
9e6e96a1
MB		 3004 .channels_max = 2,
3005 .rates = WM8994_RATES,
3006 .formats = WM8994_FORMATS,
99b0292d
MB		 3007 .sig_bits = 24,
3008 },
778a76e2 3009 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 3010 }
3011};
9e6e96a1
MB		 3012
3013#ifdef CONFIG_PM
4752a887 3014static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3015{
b2c812e2 3016 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3017 int i, ret;
3018
3019 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3020 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3021 sizeof(struct wm8994_fll_config));
f0fba2ad 3022 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 3023 if (ret < 0)
3024 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3025 i + 1, ret);
3026 }
3027
3028 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3029
3030 return 0;
3031}
3032
4752a887 3033static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3034{
b2c812e2 3035 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3036 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 3037 int i, ret;
c52fd021
DP		 3038 unsigned int val, mask;
3039
3040 if (wm8994->revision < 4) {
3041 /* force a HW read */
d9a7666f
MB		 3042 ret = regmap_read(control->regmap,
3043 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 3044
3045 /* modify the cache only */
3046 codec->cache_only = 1;
3047 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3048 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3049 val &= mask;
3050 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3051 mask, val);
3052 codec->cache_only = 0;
3053 }
9e6e96a1 3054
9e6e96a1 3055 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3056 if (!wm8994->fll_suspend[i].out)
3057 continue;
3058
f0fba2ad 3059 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3060 wm8994->fll_suspend[i].src,
3061 wm8994->fll_suspend[i].in,
3062 wm8994->fll_suspend[i].out);
3063 if (ret < 0)
3064 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3065 i + 1, ret);
3066 }
3067
3068 return 0;
3069}
3070#else
4752a887
MB		 3071#define wm8994_codec_suspend NULL
3072#define wm8994_codec_resume NULL
9e6e96a1
MB		 3073#endif
3074
3075static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3076{
8cb8e83b 3077 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3078 struct wm8994 *control = wm8994->wm8994;
3079 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3080 struct snd_kcontrol_new controls[] = {
3081 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3082 wm8994->retune_mobile_enum,
3083 wm8994_get_retune_mobile_enum,
3084 wm8994_put_retune_mobile_enum),
3085 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3086 wm8994->retune_mobile_enum,
3087 wm8994_get_retune_mobile_enum,
3088 wm8994_put_retune_mobile_enum),
3089 SOC_ENUM_EXT("AIF2 EQ Mode",
3090 wm8994->retune_mobile_enum,
3091 wm8994_get_retune_mobile_enum,
3092 wm8994_put_retune_mobile_enum),
3093 };
3094 int ret, i, j;
3095 const char **t;
3096
3097 /* We need an array of texts for the enum API but the number
3098 * of texts is likely to be less than the number of
3099 * configurations due to the sample rate dependency of the
3100 * configurations. */
3101 wm8994->num_retune_mobile_texts = 0;
3102 wm8994->retune_mobile_texts = NULL;
3103 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3104 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3105 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3106 wm8994->retune_mobile_texts[j]) == 0)
3107 break;
3108 }
3109
3110 if (j != wm8994->num_retune_mobile_texts)
3111 continue;
3112
3113 /* Expand the array... */
3114 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3115 sizeof(char *) *
9e6e96a1
MB		 3116 (wm8994->num_retune_mobile_texts + 1),
3117 GFP_KERNEL);
3118 if (t == NULL)
3119 continue;
3120
3121 /* ...store the new entry... */
c1a4ecd9 3122 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3123 pdata->retune_mobile_cfgs[i].name;
3124
3125 /* ...and remember the new version. */
3126 wm8994->num_retune_mobile_texts++;
3127 wm8994->retune_mobile_texts = t;
3128 }
3129
3130 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3131 wm8994->num_retune_mobile_texts);
3132
3133 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3134 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3135
8cb8e83b 3136 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB		 3137 ARRAY_SIZE(controls));
3138 if (ret != 0)
8cb8e83b 3139 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3140 "Failed to add ReTune Mobile controls: %d\n", ret);
3141}
3142
3143static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3144{
8cb8e83b 3145 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3146 struct wm8994 *control = wm8994->wm8994;
3147 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3148 int ret, i;
3149
3150 if (!pdata)
3151 return;
3152
3153 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3154 pdata->lineout2_diff,
3155 pdata->lineout1fb,
3156 pdata->lineout2fb,
3157 pdata->jd_scthr,
3158 pdata->jd_thr,
02e79476
MB		 3159 pdata->micb1_delay,
3160 pdata->micb2_delay,
9e6e96a1
MB		 3161 pdata->micbias1_lvl,
3162 pdata->micbias2_lvl);
3163
3164 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3165
3166 if (pdata->num_drc_cfgs) {
3167 struct snd_kcontrol_new controls[] = {
3168 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3169 wm8994_get_drc_enum, wm8994_put_drc_enum),
3170 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3171 wm8994_get_drc_enum, wm8994_put_drc_enum),
3172 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3173 wm8994_get_drc_enum, wm8994_put_drc_enum),
3174 };
3175
3176 /* We need an array of texts for the enum API */
8cb8e83b 3177 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3178 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3179 if (!wm8994->drc_texts) {
8cb8e83b 3180 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3181 "Failed to allocate %d DRC config texts\n",
3182 pdata->num_drc_cfgs);
3183 return;
3184 }
3185
3186 for (i = 0; i < pdata->num_drc_cfgs; i++)
3187 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3188
3189 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3190 wm8994->drc_enum.texts = wm8994->drc_texts;
3191
8cb8e83b 3192 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3193 ARRAY_SIZE(controls));
9e6e96a1
MB		 3194 for (i = 0; i < WM8994_NUM_DRC; i++)
3195 wm8994_set_drc(codec, i);
45a690f6
MB		 3196 } else {
3197 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3198 wm8994_drc_controls,
3199 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB		 3200 }
3201
45a690f6
MB		 3202 if (ret != 0)
3203 dev_err(wm8994->hubs.codec->dev,
3204 "Failed to add DRC mode controls: %d\n", ret);
3205
3206
9e6e96a1
MB		 3207 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3208 pdata->num_retune_mobile_cfgs);
3209
3210 if (pdata->num_retune_mobile_cfgs)
3211 wm8994_handle_retune_mobile_pdata(wm8994);
3212 else
8cb8e83b 3213 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3214 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3215
3216 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3217 if (pdata->micbias[i]) {
3218 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3219 pdata->micbias[i] & 0xffff);
3220 }
3221 }
9e6e96a1
MB		 3222}
3223
88766984
MB		 3224/**
3225 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3226 *
3227 * @codec: WM8994 codec
3228 * @jack: jack to report detection events on
3229 * @micbias: microphone bias to detect on
88766984
MB		 3230 *
3231 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3232 * being used to bring out signals to the processor then only platform
5ab230a7 3233 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3234 * be configured using snd_soc_jack_add_gpios() instead.
3235 *
3236 * Configuration of detection levels is available via the micbias1_lvl
3237 * and micbias2_lvl platform data members.
3238 */
3239int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3240 int micbias)
88766984 3241{
b2c812e2 3242 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3243 struct wm8994_micdet *micdet;
2a8a856d 3244 struct wm8994 *control = wm8994->wm8994;
87092e3c 3245 int reg, ret;
88766984 3246
87092e3c
MB		 3247 if (control->type != WM8994) {
3248 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3249 return -EINVAL;
87092e3c 3250 }
3a423157 3251
88766984
MB		 3252 switch (micbias) {
3253 case 1:
3254 micdet = &wm8994->micdet[0];
87092e3c
MB		 3255 if (jack)
3256 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3257 "MICBIAS1");
3258 else
3259 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3260 "MICBIAS1");
88766984
MB		 3261 break;
3262 case 2:
3263 micdet = &wm8994->micdet[1];
87092e3c
MB		 3264 if (jack)
3265 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3266 "MICBIAS1");
3267 else
3268 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3269 "MICBIAS1");
88766984
MB		 3270 break;
3271 default:
87092e3c 3272 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3273 return -EINVAL;
87092e3c 3274 }
88766984 3275
87092e3c
MB		 3276 if (ret != 0)
3277 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3278 micbias, ret);
3279
3280 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3281 micbias, jack);
88766984
MB		 3282
3283 /* Store the configuration */
3284 micdet->jack = jack;
87092e3c 3285 micdet->detecting = true;
88766984
MB		 3286
3287 /* If either of the jacks is set up then enable detection */
3288 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3289 reg = WM8994_MICD_ENA;
87092e3c 3290 else
88766984
MB		 3291 reg = 0;
3292
3293 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3294
d9f34df7
CR		 3295 /* enable MICDET and MICSHRT deboune */
3296 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3297 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3298 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3299 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3300
87092e3c
MB		 3301 snd_soc_dapm_sync(&codec->dapm);
3302
88766984
MB		 3303 return 0;
3304}
3305EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3306
e9b54de4 3307static void wm8994_mic_work(struct work_struct *work)
88766984 3308{
e9b54de4
MB		 3309 struct wm8994_priv *priv = container_of(work,
3310 struct wm8994_priv,
3311 mic_work.work);
fdfc4f3e
MB		 3312 struct regmap *regmap = priv->wm8994->regmap;
3313 struct device *dev = priv->wm8994->dev;
3314 unsigned int reg;
3315 int ret;
88766984
MB		 3316 int report;
3317
b8176627
MB		 3318 pm_runtime_get_sync(dev);
3319
fdfc4f3e
MB		 3320 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3321 if (ret < 0) {
3322 dev_err(dev, "Failed to read microphone status: %d\n",
3323 ret);
b8176627 3324 pm_runtime_put(dev);
e9b54de4 3325 return;
88766984
MB		 3326 }
3327
fdfc4f3e 3328 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3329
3330 report = 0;
87092e3c
MB		 3331 if (reg & WM8994_MIC1_DET_STS) {
3332 if (priv->micdet[0].detecting)
3333 report = SND_JACK_HEADSET;
3334 }
3335 if (reg & WM8994_MIC1_SHRT_STS) {
3336 if (priv->micdet[0].detecting)
3337 report = SND_JACK_HEADPHONE;
3338 else
3339 report |= SND_JACK_BTN_0;
3340 }
3341 if (report)
3342 priv->micdet[0].detecting = false;
3343 else
3344 priv->micdet[0].detecting = true;
3345
88766984 3346 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3347 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3348
3349 report = 0;
87092e3c
MB		 3350 if (reg & WM8994_MIC2_DET_STS) {
3351 if (priv->micdet[1].detecting)
3352 report = SND_JACK_HEADSET;
3353 }
3354 if (reg & WM8994_MIC2_SHRT_STS) {
3355 if (priv->micdet[1].detecting)
3356 report = SND_JACK_HEADPHONE;
3357 else
3358 report |= SND_JACK_BTN_0;
3359 }
3360 if (report)
3361 priv->micdet[1].detecting = false;
3362 else
3363 priv->micdet[1].detecting = true;
3364
88766984 3365 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3366 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB		 3367
3368 pm_runtime_put(dev);
e9b54de4
MB		 3369}
3370
3371static irqreturn_t wm8994_mic_irq(int irq, void *data)
3372{
3373 struct wm8994_priv *priv = data;
8cb8e83b 3374 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB		 3375
3376#ifndef CONFIG_SND_SOC_WM8994_MODULE
3377 trace_snd_soc_jack_irq(dev_name(codec->dev));
3378#endif
3379
3380 pm_wakeup_event(codec->dev, 300);
3381
3382 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3383
3384 return IRQ_HANDLED;
3385}
3386
f02b0de0
MB		 3387static void wm1811_micd_stop(struct snd_soc_codec *codec)
3388{
3389 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3390
3391 if (!wm8994->jackdet)
3392 return;
3393
3394 mutex_lock(&wm8994->accdet_lock);
3395
3396 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3397
3398 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3399
3400 mutex_unlock(&wm8994->accdet_lock);
3401
3402 if (wm8994->wm8994->pdata.jd_ext_cap)
3403 snd_soc_dapm_disable_pin(&codec->dapm,
3404 "MICBIAS2");
3405}
3406
78b76dbe 3407static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
821edd2f 3408{
821edd2f 3409 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3410 int report;
821edd2f 3411
78b76dbe
MB		 3412 report = 0;
3413 if (status & 0x4)
3414 report |= SND_JACK_BTN_0;
3415
3416 if (status & 0x8)
3417 report |= SND_JACK_BTN_1;
3418
3419 if (status & 0x10)
3420 report |= SND_JACK_BTN_2;
3421
3422 if (status & 0x20)
3423 report |= SND_JACK_BTN_3;
3424
3425 if (status & 0x40)
3426 report |= SND_JACK_BTN_4;
3427
3428 if (status & 0x80)
3429 report |= SND_JACK_BTN_5;
3430
3431 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3432 wm8994->btn_mask);
3433}
3434
3435static void wm8958_mic_id(struct snd_soc_codec *codec, u16 status)
3436{
3437 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
a1691343 3438
af6b6fe4 3439 /* Either nothing present or just starting detection */
b00adf76 3440 if (!(status & WM8958_MICD_STS)) {
f02b0de0
MB		 3441 /* If nothing present then clear our statuses */
3442 dev_dbg(codec->dev, "Detected open circuit\n");
3443 wm8994->jack_mic = false;
3444 wm8994->mic_detecting = true;
b00adf76 3445
f02b0de0 3446 wm1811_micd_stop(codec);
b00adf76 3447
f02b0de0
MB		 3448 wm8958_micd_set_rate(codec);
3449
3450 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3451 wm8994->btn_mask |
3452 SND_JACK_HEADSET);
b00adf76
MB		 3453 return;
3454 }
821edd2f 3455
b00adf76
MB		 3456 /* If the measurement is showing a high impedence we've got a
3457 * microphone.
3458 */
78b76dbe 3459 if (status & 0x600) {
b00adf76
MB		 3460 dev_dbg(codec->dev, "Detected microphone\n");
3461
157a75e6 3462 wm8994->mic_detecting = false;
b00adf76
MB		 3463 wm8994->jack_mic = true;
3464
3465 wm8958_micd_set_rate(codec);
3466
3467 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3468 SND_JACK_HEADSET);
3469 }
821edd2f 3470
b00adf76 3471
78b76dbe 3472 if (status & 0xfc) {
b00adf76 3473 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3474 wm8994->mic_detecting = false;
b00adf76
MB		 3475
3476 wm8958_micd_set_rate(codec);
3477
af6b6fe4 3478 /* If we have jackdet that will detect removal */
f02b0de0 3479 wm1811_micd_stop(codec);
ecd1732f
MB		 3480
3481 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3482 SND_JACK_HEADSET);
b00adf76 3483 }
821edd2f
MB		 3484}
3485
c0cc3f16
MB		 3486/* Deferred mic detection to allow for extra settling time */
3487static void wm1811_mic_work(struct work_struct *work)
3488{
3489 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3490 mic_work.work);
d9dd4ada 3491 struct wm8994 *control = wm8994->wm8994;
c0cc3f16
MB		 3492 struct snd_soc_codec *codec = wm8994->hubs.codec;
3493
3494 pm_runtime_get_sync(codec->dev);
3495
3496 /* If required for an external cap force MICBIAS on */
d9dd4ada 3497 if (control->pdata.jd_ext_cap) {
c0cc3f16
MB		 3498 snd_soc_dapm_force_enable_pin(&codec->dapm,
3499 "MICBIAS2");
3500 snd_soc_dapm_sync(&codec->dapm);
3501 }
3502
3503 mutex_lock(&wm8994->accdet_lock);
3504
3505 dev_dbg(codec->dev, "Starting mic detection\n");
3506
3507 /*
3508 * Start off measument of microphone impedence to find out
3509 * what's actually there.
3510 */
3511 wm8994->mic_detecting = true;
3512 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3513
3514 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3515 WM8958_MICD_ENA, WM8958_MICD_ENA);
3516
3517 mutex_unlock(&wm8994->accdet_lock);
3518
3519 pm_runtime_put(codec->dev);
3520}
3521
af6b6fe4
MB		 3522static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3523{
3524 struct wm8994_priv *wm8994 = data;
d9dd4ada 3525 struct wm8994 *control = wm8994->wm8994;
8cb8e83b 3526 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3527 int reg, delay;
c986564b 3528 bool present;
af6b6fe4 3529
b8176627
MB		 3530 pm_runtime_get_sync(codec->dev);
3531
af6b6fe4
MB		 3532 mutex_lock(&wm8994->accdet_lock);
3533
3534 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3535 if (reg < 0) {
3536 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3537 mutex_unlock(&wm8994->accdet_lock);
b8176627 3538 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3539 return IRQ_NONE;
3540 }
3541
3542 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3543
c986564b 3544 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3545
c986564b
MB		 3546 if (present) {
3547 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3548
e9d9a968
MB		 3549 wm8958_micd_set_rate(codec);
3550
55a27786
MB		 3551 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3552 WM8958_MICB2_DISCH, 0);
3553
378ec0ca
MB		 3554 /* Disable debounce while inserted */
3555 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3556 WM1811_JACKDET_DB, 0);
3557
d9dd4ada 3558 delay = control->pdata.micdet_delay;
c0cc3f16
MB		 3559 schedule_delayed_work(&wm8994->mic_work,
3560 msecs_to_jiffies(delay));
af6b6fe4
MB		 3561 } else {
3562 dev_dbg(codec->dev, "Jack not detected\n");
3563
c0cc3f16
MB		 3564 cancel_delayed_work_sync(&wm8994->mic_work);
3565
55a27786
MB		 3566 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3567 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3568
378ec0ca
MB		 3569 /* Enable debounce while removed */
3570 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3571 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3572
af6b6fe4
MB		 3573 wm8994->mic_detecting = false;
3574 wm8994->jack_mic = false;
3575 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3576 WM8958_MICD_ENA, 0);
3577 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3578 }
3579
3580 mutex_unlock(&wm8994->accdet_lock);
3581
c0cc3f16 3582 /* Turn off MICBIAS if it was on for an external cap */
d9dd4ada 3583 if (control->pdata.jd_ext_cap && !present)
c0cc3f16 3584 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3585
3586 if (present)
3587 snd_soc_jack_report(wm8994->micdet[0].jack,
3588 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3589 else
3590 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3591 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3592 wm8994->btn_mask);
3593
99af79df
MB		 3594 /* Since we only report deltas force an update, ensures we
3595 * avoid bootstrapping issues with the core. */
3596 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3597
b8176627 3598 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3599 return IRQ_HANDLED;
3600}
3601
99af79df
MB		 3602static void wm1811_jackdet_bootstrap(struct work_struct *work)
3603{
3604 struct wm8994_priv *wm8994 = container_of(work,
3605 struct wm8994_priv,
3606 jackdet_bootstrap.work);
3607 wm1811_jackdet_irq(0, wm8994);
3608}
3609
821edd2f
MB		 3610/**
3611 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3612 *
3613 * @codec: WM8958 codec
3614 * @jack: jack to report detection events on
3615 *
3616 * Enable microphone detection functionality for the WM8958. By
3617 * default simple detection which supports the detection of up to 6
3618 * buttons plus video and microphone functionality is supported.
3619 *
3620 * The WM8958 has an advanced jack detection facility which is able to
3621 * support complex accessory detection, especially when used in
3622 * conjunction with external circuitry. In order to provide maximum
3623 * flexiblity a callback is provided which allows a completely custom
3624 * detection algorithm.
3625 */
3626int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3627 wm8958_micdet_cb cb, void *cb_data)
3628{
3629 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3630 struct wm8994 *control = wm8994->wm8994;
4585790d 3631 u16 micd_lvl_sel;
821edd2f 3632
81204c84
MB		 3633 switch (control->type) {
3634 case WM1811:
3635 case WM8958:
3636 break;
3637 default:
821edd2f 3638 return -EINVAL;
81204c84 3639 }
821edd2f
MB		 3640
3641 if (jack) {
78b76dbe
MB		 3642 /* No longer supported */
3643 if (cb)
3644 return -EINVAL;
821edd2f 3645
4cdf5e49 3646 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3647 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3648
821edd2f 3649 wm8994->micdet[0].jack = jack;
821edd2f 3650
157a75e6 3651 wm8994->mic_detecting = true;
b00adf76
MB		 3652 wm8994->jack_mic = false;
3653
3654 wm8958_micd_set_rate(codec);
3655
4585790d 3656 /* Detect microphones and short circuits by default */
d9dd4ada
MB		 3657 if (control->pdata.micd_lvl_sel)
3658 micd_lvl_sel = control->pdata.micd_lvl_sel;
4585790d
MB		 3659 else
3660 micd_lvl_sel = 0x41;
3661
3662 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3663 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3664 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3665
b00adf76 3666 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3667 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3668
af6b6fe4
MB		 3669 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3670
3671 /*
3672 * If we can use jack detection start off with that,
3673 * otherwise jump straight to microphone detection.
3674 */
3675 if (wm8994->jackdet) {
99af79df
MB		 3676 /* Disable debounce for the initial detect */
3677 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3678 WM1811_JACKDET_DB, 0);
3679
55a27786
MB		 3680 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3681 WM8958_MICB2_DISCH,
3682 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3683 snd_soc_update_bits(codec, WM8994_LDO_1,
3684 WM8994_LDO1_DISCH, 0);
3685 wm1811_jackdet_set_mode(codec,
3686 WM1811_JACKDET_MODE_JACK);
3687 } else {
3688 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3689 WM8958_MICD_ENA, WM8958_MICD_ENA);
3690 }
3691
821edd2f
MB		 3692 } else {
3693 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3694 WM8958_MICD_ENA, 0);
afaf1591 3695 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3696 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3697 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3698 }
3699
3700 return 0;
3701}
3702EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3703
3704static irqreturn_t wm8958_mic_irq(int irq, void *data)
3705{
3706 struct wm8994_priv *wm8994 = data;
8cb8e83b 3707 struct snd_soc_codec *codec = wm8994->hubs.codec;
19940b3d 3708 int reg, count;
821edd2f 3709
af6b6fe4
MB		 3710 /*
3711 * Jack detection may have detected a removal simulataneously
3712 * with an update of the MICDET status; if so it will have
3713 * stopped detection and we can ignore this interrupt.
3714 */
c986564b 3715 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3716 return IRQ_HANDLED;
af6b6fe4 3717
b8176627
MB		 3718 pm_runtime_get_sync(codec->dev);
3719
19940b3d
MB		 3720 /* We may occasionally read a detection without an impedence
3721 * range being provided - if that happens loop again.
3722 */
3723 count = 10;
3724 do {
3725 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3726 if (reg < 0) {
3727 dev_err(codec->dev,
3728 "Failed to read mic detect status: %d\n",
3729 reg);
b8176627 3730 pm_runtime_put(codec->dev);
19940b3d
MB		 3731 return IRQ_NONE;
3732 }
821edd2f 3733
19940b3d
MB		 3734 if (!(reg & WM8958_MICD_VALID)) {
3735 dev_dbg(codec->dev, "Mic detect data not valid\n");
3736 goto out;
3737 }
3738
3739 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3740 break;
3741
3742 msleep(1);
3743 } while (count--);
3744
3745 if (count == 0)
3746 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3747
7116f452 3748#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3749 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3750#endif
2bbb5d66 3751
78b76dbe
MB		 3752 if (wm8994->mic_detecting)
3753 wm8958_mic_id(codec, reg);
821edd2f 3754 else
78b76dbe 3755 wm8958_button_det(codec, reg);
821edd2f
MB		 3756
3757out:
b8176627 3758 pm_runtime_put(codec->dev);
821edd2f
MB		 3759 return IRQ_HANDLED;
3760}
3761
3b1af3f8
MB		 3762static irqreturn_t wm8994_fifo_error(int irq, void *data)
3763{
3764 struct snd_soc_codec *codec = data;
3765
3766 dev_err(codec->dev, "FIFO error\n");
3767
3768 return IRQ_HANDLED;
3769}
3770
f0b182b0
MB		 3771static irqreturn_t wm8994_temp_warn(int irq, void *data)
3772{
3773 struct snd_soc_codec *codec = data;
3774
3775 dev_err(codec->dev, "Thermal warning\n");
3776
3777 return IRQ_HANDLED;
3778}
3779
3780static irqreturn_t wm8994_temp_shut(int irq, void *data)
3781{
3782 struct snd_soc_codec *codec = data;
3783
3784 dev_crit(codec->dev, "Thermal shutdown\n");
3785
3786 return IRQ_HANDLED;
3787}
3788
f0fba2ad 3789static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3790{
d9a7666f 3791 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3792 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3793 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3794 unsigned int reg;
ec62dbd7 3795 int ret, i;
9e6e96a1 3796
8cb8e83b 3797 wm8994->hubs.codec = codec;
d9a7666f 3798 codec->control_data = control->regmap;
9e6e96a1 3799
d9a7666f 3800 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3801
af6b6fe4 3802 mutex_init(&wm8994->accdet_lock);
99af79df
MB		 3803 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3804 wm1811_jackdet_bootstrap);
af6b6fe4 3805
c0cc3f16
MB		 3806 switch (control->type) {
3807 case WM8994:
3808 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3809 break;
3810 case WM1811:
3811 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3812 break;
3813 default:
3814 break;
3815 }
3816
c7ebf932
MB		 3817 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3818 init_completion(&wm8994->fll_locked[i]);
3819
d9dd4ada 3820 wm8994->micdet_irq = control->pdata.micdet_irq;
9b7c525d 3821
39fb51a1 3822 pm_runtime_enable(codec->dev);
5fab5174 3823 pm_runtime_idle(codec->dev);
39fb51a1 3824
f959dee9
MB		 3825 /* By default use idle_bias_off, will override for WM8994 */
3826 codec->dapm.idle_bias_off = 1;
3827
9e6e96a1 3828 /* Set revision-specific configuration */
b6b05691 3829 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3830 switch (control->type) {
3831 case WM8994:
f959dee9 3832 /* Single ended line outputs should have VMID on. */
d9dd4ada
MB		 3833 if (!control->pdata.lineout1_diff ||
3834 !control->pdata.lineout2_diff)
f959dee9
MB		 3835 codec->dapm.idle_bias_off = 0;
3836
3a423157
MB		 3837 switch (wm8994->revision) {
3838 case 2:
3839 case 3:
4537c4e7
MB		 3840 wm8994->hubs.dcs_codes_l = -5;
3841 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3842 wm8994->hubs.hp_startup_mode = 1;
3843 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3844 wm8994->hubs.series_startup = 1;
3a423157
MB		 3845 break;
3846 default:
79ef0abc 3847 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3848 break;
3849 }
280ec8b7 3850 break;
3a423157
MB		 3851
3852 case WM8958:
8437f700 3853 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3854 wm8994->hubs.hp_startup_mode = 1;
20dc24a9
MB		 3855
3856 switch (wm8994->revision) {
3857 case 0:
3858 break;
3859 default:
3860 wm8994->fll_byp = true;
3861 break;
3862 }
9e6e96a1 3863 break;
3a423157 3864
81204c84
MB		 3865 case WM1811:
3866 wm8994->hubs.dcs_readback_mode = 2;
3867 wm8994->hubs.no_series_update = 1;
29fdc360 3868 wm8994->hubs.hp_startup_mode = 1;
af31a227 3869 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 3870 wm8994->fll_byp = true;
81204c84 3871
72222be3
MB		 3872 wm8994->hubs.dcs_codes_l = -9;
3873 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 3874
3875 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3876 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3877 break;
3878
9e6e96a1
MB		 3879 default:
3880 break;
3881 }
9e6e96a1 3882
2a8a856d 3883 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3884 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3885 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3886 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3887 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3888 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3889
2a8a856d 3890 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3891 wm_hubs_dcs_done, "DC servo done",
3892 &wm8994->hubs);
3893 if (ret == 0)
3894 wm8994->hubs.dcs_done_irq = true;
3895
3a423157
MB		 3896 switch (control->type) {
3897 case WM8994:
9b7c525d
MB		 3898 if (wm8994->micdet_irq) {
3899 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3900 wm8994_mic_irq,
3901 IRQF_TRIGGER_RISING,
3902 "Mic1 detect",
3903 wm8994);
3904 if (ret != 0)
3905 dev_warn(codec->dev,
3906 "Failed to request Mic1 detect IRQ: %d\n",
3907 ret);
3908 }
3a423157 3909
2a8a856d 3910 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3911 WM8994_IRQ_MIC1_SHRT,
3912 wm8994_mic_irq, "Mic 1 short",
3913 wm8994);
3914 if (ret != 0)
3915 dev_warn(codec->dev,
3916 "Failed to request Mic1 short IRQ: %d\n",
3917 ret);
3918
2a8a856d 3919 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3920 WM8994_IRQ_MIC2_DET,
3921 wm8994_mic_irq, "Mic 2 detect",
3922 wm8994);
3923 if (ret != 0)
3924 dev_warn(codec->dev,
3925 "Failed to request Mic2 detect IRQ: %d\n",
3926 ret);
3927
2a8a856d 3928 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3929 WM8994_IRQ_MIC2_SHRT,
3930 wm8994_mic_irq, "Mic 2 short",
3931 wm8994);
3932 if (ret != 0)
3933 dev_warn(codec->dev,
3934 "Failed to request Mic2 short IRQ: %d\n",
3935 ret);
3936 break;
821edd2f
MB		 3937
3938 case WM8958:
81204c84 3939 case WM1811:
9b7c525d
MB		 3940 if (wm8994->micdet_irq) {
3941 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3942 wm8958_mic_irq,
3943 IRQF_TRIGGER_RISING,
3944 "Mic detect",
3945 wm8994);
3946 if (ret != 0)
3947 dev_warn(codec->dev,
3948 "Failed to request Mic detect IRQ: %d\n",
3949 ret);
b4046d01
MB		 3950 } else {
3951 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3952 wm8958_mic_irq, "Mic detect",
3953 wm8994);
9b7c525d 3954 }
3a423157 3955 }
88766984 3956
af6b6fe4
MB		 3957 switch (control->type) {
3958 case WM1811:
52ca1138 3959 if (control->cust_id > 1 || wm8994->revision > 1) {
af6b6fe4
MB		 3960 ret = wm8994_request_irq(wm8994->wm8994,
3961 WM8994_IRQ_GPIO(6),
3962 wm1811_jackdet_irq, "JACKDET",
3963 wm8994);
3964 if (ret == 0)
3965 wm8994->jackdet = true;
3966 }
3967 break;
3968 default:
3969 break;
3970 }
3971
c7ebf932
MB		 3972 wm8994->fll_locked_irq = true;
3973 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3974 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3975 WM8994_IRQ_FLL1_LOCK + i,
3976 wm8994_fll_locked_irq, "FLL lock",
3977 &wm8994->fll_locked[i]);
3978 if (ret != 0)
3979 wm8994->fll_locked_irq = false;
3980 }
3981
27060b3c
MB		 3982 /* Make sure we can read from the GPIOs if they're inputs */
3983 pm_runtime_get_sync(codec->dev);
3984
9e6e96a1
MB		 3985 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3986 * configured on init - if a system wants to do this dynamically
3987 * at runtime we can deal with that then.
3988 */
d9a7666f 3989 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3990 if (ret < 0) {
3991 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3992 goto err_irq;
9e6e96a1 3993 }
d9a7666f 3994 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3995 wm8994->lrclk_shared[0] = 1;
3996 wm8994_dai[0].symmetric_rates = 1;
3997 } else {
3998 wm8994->lrclk_shared[0] = 0;
3999 }
4000
d9a7666f 4001 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 4002 if (ret < 0) {
4003 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4004 goto err_irq;
9e6e96a1 4005 }
d9a7666f 4006 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4007 wm8994->lrclk_shared[1] = 1;
4008 wm8994_dai[1].symmetric_rates = 1;
4009 } else {
4010 wm8994->lrclk_shared[1] = 0;
4011 }
4012
27060b3c
MB		 4013 pm_runtime_put(codec->dev);
4014
bfd37bb5
MB		 4015 /* Latch volume update bits */
4016 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4017 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4018 wm8994_vu_bits[i].mask,
4019 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 4020
4021 /* Set the low bit of the 3D stereo depth so TLV matches */
4022 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4023 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4024 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4025 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4026 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4027 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4028 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4029 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4030 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4031
5b739670
MB		 4032 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4033 * use this; it only affects behaviour on idle TDM clock
4034 * cycles. */
4035 switch (control->type) {
4036 case WM8994:
4037 case WM8958:
4038 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4039 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4040 break;
4041 default:
4042 break;
4043 }
d1ce6b20 4044
500fa30e
MB		 4045 /* Put MICBIAS into bypass mode by default on newer devices */
4046 switch (control->type) {
4047 case WM8958:
4048 case WM1811:
4049 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4050 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4051 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4052 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4053 break;
4054 default:
4055 break;
4056 }
4057
c340304d
MB		 4058 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4059 wm_hubs_update_class_w(codec);
9e6e96a1 4060
f0fba2ad 4061 wm8994_handle_pdata(wm8994);
9e6e96a1 4062
f0fba2ad 4063 wm_hubs_add_analogue_controls(codec);
022658be 4064 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4065 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4066 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4067 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 4068
4069 switch (control->type) {
4070 case WM8994:
4071 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4072 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 4073 if (wm8994->revision < 4) {
173efa09
DP		 4074 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4075 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 4076 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4077 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 4078 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4079 ARRAY_SIZE(wm8994_dac_revd_widgets));
4080 } else {
173efa09
DP		 4081 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4082 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4083 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4084 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4085 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4086 ARRAY_SIZE(wm8994_dac_widgets));
4087 }
c4431df0
MB		 4088 break;
4089 case WM8958:
022658be 4090 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4091 ARRAY_SIZE(wm8958_snd_controls));
4092 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4093 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 4094 if (wm8994->revision < 1) {
4095 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4096 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4097 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4098 ARRAY_SIZE(wm8994_adc_revd_widgets));
4099 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4100 ARRAY_SIZE(wm8994_dac_revd_widgets));
4101 } else {
4102 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4103 ARRAY_SIZE(wm8994_lateclk_widgets));
4104 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4105 ARRAY_SIZE(wm8994_adc_widgets));
4106 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4107 ARRAY_SIZE(wm8994_dac_widgets));
4108 }
c4431df0 4109 break;
81204c84
MB		 4110
4111 case WM1811:
022658be 4112 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4113 ARRAY_SIZE(wm8958_snd_controls));
4114 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4115 ARRAY_SIZE(wm8958_dapm_widgets));
4116 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4117 ARRAY_SIZE(wm8994_lateclk_widgets));
4118 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4119 ARRAY_SIZE(wm8994_adc_widgets));
4120 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4121 ARRAY_SIZE(wm8994_dac_widgets));
4122 break;
c4431df0 4123 }
c4431df0 4124
f0fba2ad 4125 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 4126 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4127
c4431df0
MB		 4128 switch (control->type) {
4129 case WM8994:
4130 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4131 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4132
173efa09 4133 if (wm8994->revision < 4) {
6ed8f148
MB		 4134 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4135 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4136 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4137 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4138 } else {
4139 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4140 ARRAY_SIZE(wm8994_lateclk_intercon));
4141 }
c4431df0
MB		 4142 break;
4143 case WM8958:
780e2806 4144 if (wm8994->revision < 1) {
15676937
CR		 4145 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4146 ARRAY_SIZE(wm8994_intercon));
780e2806
MB		 4147 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4148 ARRAY_SIZE(wm8994_revd_intercon));
4149 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4150 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4151 } else {
4152 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4153 ARRAY_SIZE(wm8994_lateclk_intercon));
4154 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4155 ARRAY_SIZE(wm8958_intercon));
4156 }
f701a2e5
MB		 4157
4158 wm8958_dsp2_init(codec);
c4431df0 4159 break;
81204c84
MB		 4160 case WM1811:
4161 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4162 ARRAY_SIZE(wm8994_lateclk_intercon));
4163 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4164 ARRAY_SIZE(wm8958_intercon));
4165 break;
c4431df0
MB		 4166 }
4167
9e6e96a1
MB		 4168 return 0;
4169
88766984 4170err_irq:
af6b6fe4
MB		 4171 if (wm8994->jackdet)
4172 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4173 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4174 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4175 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4176 if (wm8994->micdet_irq)
4177 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4178 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4179 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4180 &wm8994->fll_locked[i]);
2a8a856d 4181 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4182 &wm8994->hubs);
2a8a856d
MB		 4183 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4184 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4185 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4186
9e6e96a1
MB		 4187 return ret;
4188}
4189
34ff0f95 4190static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4191{
f0fba2ad 4192 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4193 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4194 int i;
9e6e96a1
MB		 4195
4196 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4197
39fb51a1
MB		 4198 pm_runtime_disable(codec->dev);
4199
c7ebf932 4200 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4201 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4202 &wm8994->fll_locked[i]);
4203
2a8a856d 4204 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4205 &wm8994->hubs);
2a8a856d
MB		 4206 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4207 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4208 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4209
af6b6fe4
MB		 4210 if (wm8994->jackdet)
4211 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4212
3a423157
MB		 4213 switch (control->type) {
4214 case WM8994:
9b7c525d
MB		 4215 if (wm8994->micdet_irq)
4216 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4217 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4218 wm8994);
2a8a856d 4219 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4220 wm8994);
2a8a856d 4221 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4222 wm8994);
4223 break;
821edd2f 4224
81204c84 4225 case WM1811:
821edd2f 4226 case WM8958:
9b7c525d
MB		 4227 if (wm8994->micdet_irq)
4228 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4229 break;
3a423157 4230 }
34ff0f95
JJ		 4231 release_firmware(wm8994->mbc);
4232 release_firmware(wm8994->mbc_vss);
4233 release_firmware(wm8994->enh_eq);
24fb2b11 4234 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4235 return 0;
4236}
4237
f0fba2ad
LG		 4238static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4239 .probe = wm8994_codec_probe,
4240 .remove = wm8994_codec_remove,
4752a887
MB		 4241 .suspend = wm8994_codec_suspend,
4242 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4243 .set_bias_level = wm8994_set_bias_level,
4244};
4245
4246static int __devinit wm8994_probe(struct platform_device *pdev)
4247{
2bc16ed8
MB		 4248 struct wm8994_priv *wm8994;
4249
4250 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4251 GFP_KERNEL);
4252 if (wm8994 == NULL)
4253 return -ENOMEM;
4254 platform_set_drvdata(pdev, wm8994);
4255
4256 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
2bc16ed8 4257
f0fba2ad
LG		 4258 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4259 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4260}
4261
4262static int __devexit wm8994_remove(struct platform_device *pdev)
4263{
4264 snd_soc_unregister_codec(&pdev->dev);
4265 return 0;
4266}
4267
4752a887
MB		 4268#ifdef CONFIG_PM_SLEEP
4269static int wm8994_suspend(struct device *dev)
4270{
4271 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4272
4273 /* Drop down to power saving mode when system is suspended */
4274 if (wm8994->jackdet && !wm8994->active_refcount)
4275 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4276 WM1811_JACKDET_MODE_MASK,
4277 wm8994->jackdet_mode);
4278
4279 return 0;
4280}
4281
4282static int wm8994_resume(struct device *dev)
4283{
4284 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4285
78b76dbe 4286 if (wm8994->jackdet && wm8994->jackdet_mode)
4752a887
MB		 4287 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4288 WM1811_JACKDET_MODE_MASK,
4289 WM1811_JACKDET_MODE_AUDIO);
4290
4291 return 0;
4292}
4293#endif
4294
4295static const struct dev_pm_ops wm8994_pm_ops = {
4296 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4297};
4298
9e6e96a1
MB		 4299static struct platform_driver wm8994_codec_driver = {
4300 .driver = {
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MB		 4301 .name = "wm8994-codec",
4302 .owner = THIS_MODULE,
4303 .pm = &wm8994_pm_ops,
4304 },
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LG		 4305 .probe = wm8994_probe,
4306 .remove = __devexit_p(wm8994_remove),
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MB		 4307};
4308
5bbcc3c0 4309module_platform_driver(wm8994_codec_driver);
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MB		 4310
4311MODULE_DESCRIPTION("ASoC WM8994 driver");
4312MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4313MODULE_LICENSE("GPL");
4314MODULE_ALIAS("platform:wm8994-codec");
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