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ASoC: Add WM8958 microphone detection support
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8994.c
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9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
5a0e3ad6 22#include <linux/slab.h>
9e6e96a1 23#include <sound/core.h>
821edd2f 24#include <sound/jack.h>
9e6e96a1
MB		 25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
9e6e96a1
MB		 28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include <linux/mfd/wm8994/core.h>
32#include <linux/mfd/wm8994/registers.h>
33#include <linux/mfd/wm8994/pdata.h>
34#include <linux/mfd/wm8994/gpio.h>
35
36#include "wm8994.h"
37#include "wm_hubs.h"
38
9e6e96a1
MB		 39struct fll_config {
40 int src;
41 int in;
42 int out;
43};
44
45#define WM8994_NUM_DRC 3
46#define WM8994_NUM_EQ 3
47
48static int wm8994_drc_base[] = {
49 WM8994_AIF1_DRC1_1,
50 WM8994_AIF1_DRC2_1,
51 WM8994_AIF2_DRC_1,
52};
53
54static int wm8994_retune_mobile_base[] = {
55 WM8994_AIF1_DAC1_EQ_GAINS_1,
56 WM8994_AIF1_DAC2_EQ_GAINS_1,
57 WM8994_AIF2_EQ_GAINS_1,
58};
59
60#define WM8994_REG_CACHE_SIZE 0x621
61
88766984
MB		 62struct wm8994_micdet {
63 struct snd_soc_jack *jack;
64 int det;
65 int shrt;
66};
67
9e6e96a1
MB		 68/* codec private data */
69struct wm8994_priv {
70 struct wm_hubs_data hubs;
f0fba2ad
LG		 71 enum snd_soc_control_type control_type;
72 void *control_data;
73 struct snd_soc_codec *codec;
9e6e96a1
MB		 74 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
75 int sysclk[2];
76 int sysclk_rate[2];
77 int mclk[2];
78 int aifclk[2];
79 struct fll_config fll[2], fll_suspend[2];
80
81 int dac_rates[2];
82 int lrclk_shared[2];
83
d6addcc9
MB		 84 int mbc_ena[3];
85
9e6e96a1
MB		 86 /* Platform dependant DRC configuration */
87 const char **drc_texts;
88 int drc_cfg[WM8994_NUM_DRC];
89 struct soc_enum drc_enum;
90
91 /* Platform dependant ReTune mobile configuration */
92 int num_retune_mobile_texts;
93 const char **retune_mobile_texts;
94 int retune_mobile_cfg[WM8994_NUM_EQ];
95 struct soc_enum retune_mobile_enum;
96
88766984
MB		 97 struct wm8994_micdet micdet[2];
98
821edd2f
MB		 99 wm8958_micdet_cb jack_cb;
100 void *jack_cb_data;
101 bool jack_is_mic;
102 bool jack_is_video;
103
b6b05691 104 int revision;
9e6e96a1
MB		 105 struct wm8994_pdata *pdata;
106};
107
9e6e96a1
MB		 108static int wm8994_readable(unsigned int reg)
109{
e88ff1e6
MB		 110 switch (reg) {
111 case WM8994_GPIO_1:
112 case WM8994_GPIO_2:
113 case WM8994_GPIO_3:
114 case WM8994_GPIO_4:
115 case WM8994_GPIO_5:
116 case WM8994_GPIO_6:
117 case WM8994_GPIO_7:
118 case WM8994_GPIO_8:
119 case WM8994_GPIO_9:
120 case WM8994_GPIO_10:
121 case WM8994_GPIO_11:
122 case WM8994_INTERRUPT_STATUS_1:
123 case WM8994_INTERRUPT_STATUS_2:
124 case WM8994_INTERRUPT_RAW_STATUS_2:
125 return 1;
126 default:
127 break;
128 }
129
7b306dae 130 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 131 return 0;
7b306dae 132 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 133}
134
135static int wm8994_volatile(unsigned int reg)
136{
137 if (reg >= WM8994_REG_CACHE_SIZE)
138 return 1;
139
140 switch (reg) {
141 case WM8994_SOFTWARE_RESET:
142 case WM8994_CHIP_REVISION:
143 case WM8994_DC_SERVO_1:
144 case WM8994_DC_SERVO_READBACK:
145 case WM8994_RATE_STATUS:
146 case WM8994_LDO_1:
147 case WM8994_LDO_2:
d6addcc9 148 case WM8958_DSP2_EXECCONTROL:
821edd2f 149 case WM8958_MIC_DETECT_3:
9e6e96a1
MB		 150 return 1;
151 default:
152 return 0;
153 }
154}
155
156static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
157 unsigned int value)
158{
b2c812e2 159 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 160
161 BUG_ON(reg > WM8994_MAX_REGISTER);
162
163 if (!wm8994_volatile(reg))
164 wm8994->reg_cache[reg] = value;
165
166 return wm8994_reg_write(codec->control_data, reg, value);
167}
168
169static unsigned int wm8994_read(struct snd_soc_codec *codec,
170 unsigned int reg)
171{
172 u16 *reg_cache = codec->reg_cache;
173
174 BUG_ON(reg > WM8994_MAX_REGISTER);
175
176 if (wm8994_volatile(reg))
177 return wm8994_reg_read(codec->control_data, reg);
178 else
179 return reg_cache[reg];
180}
181
182static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
183{
b2c812e2 184 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 185 int rate;
186 int reg1 = 0;
187 int offset;
188
189 if (aif)
190 offset = 4;
191 else
192 offset = 0;
193
194 switch (wm8994->sysclk[aif]) {
195 case WM8994_SYSCLK_MCLK1:
196 rate = wm8994->mclk[0];
197 break;
198
199 case WM8994_SYSCLK_MCLK2:
200 reg1 |= 0x8;
201 rate = wm8994->mclk[1];
202 break;
203
204 case WM8994_SYSCLK_FLL1:
205 reg1 |= 0x10;
206 rate = wm8994->fll[0].out;
207 break;
208
209 case WM8994_SYSCLK_FLL2:
210 reg1 |= 0x18;
211 rate = wm8994->fll[1].out;
212 break;
213
214 default:
215 return -EINVAL;
216 }
217
218 if (rate >= 13500000) {
219 rate /= 2;
220 reg1 |= WM8994_AIF1CLK_DIV;
221
222 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
223 aif + 1, rate);
224 }
5e5e2bef
MB		 225
226 if (rate && rate < 3000000)
227 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
228 aif + 1, rate);
229
9e6e96a1
MB		 230 wm8994->aifclk[aif] = rate;
231
232 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
233 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
234 reg1);
235
236 return 0;
237}
238
239static int configure_clock(struct snd_soc_codec *codec)
240{
b2c812e2 241 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 242 int old, new;
243
244 /* Bring up the AIF clocks first */
245 configure_aif_clock(codec, 0);
246 configure_aif_clock(codec, 1);
247
248 /* Then switch CLK_SYS over to the higher of them; a change
249 * can only happen as a result of a clocking change which can
250 * only be made outside of DAPM so we can safely redo the
251 * clocking.
252 */
253
254 /* If they're equal it doesn't matter which is used */
255 if (wm8994->aifclk[0] == wm8994->aifclk[1])
256 return 0;
257
258 if (wm8994->aifclk[0] < wm8994->aifclk[1])
259 new = WM8994_SYSCLK_SRC;
260 else
261 new = 0;
262
263 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
264
265 /* If there's no change then we're done. */
266 if (old == new)
267 return 0;
268
269 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
270
ce6120cc 271 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 272
273 return 0;
274}
275
276static int check_clk_sys(struct snd_soc_dapm_widget *source,
277 struct snd_soc_dapm_widget *sink)
278{
279 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
280 const char *clk;
281
282 /* Check what we're currently using for CLK_SYS */
283 if (reg & WM8994_SYSCLK_SRC)
284 clk = "AIF2CLK";
285 else
286 clk = "AIF1CLK";
287
288 return strcmp(source->name, clk) == 0;
289}
290
291static const char *sidetone_hpf_text[] = {
292 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
293};
294
295static const struct soc_enum sidetone_hpf =
296 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
297
298static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
299static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
300static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
301static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
302static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
303
304#define WM8994_DRC_SWITCH(xname, reg, shift) \
305{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
306 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
307 .put = wm8994_put_drc_sw, \
308 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
309
310static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
311 struct snd_ctl_elem_value *ucontrol)
312{
313 struct soc_mixer_control *mc =
314 (struct soc_mixer_control *)kcontrol->private_value;
315 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
316 int mask, ret;
317
318 /* Can't enable both ADC and DAC paths simultaneously */
319 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
320 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
321 WM8994_AIF1ADC1R_DRC_ENA_MASK;
322 else
323 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
324
325 ret = snd_soc_read(codec, mc->reg);
326 if (ret < 0)
327 return ret;
328 if (ret & mask)
329 return -EINVAL;
330
331 return snd_soc_put_volsw(kcontrol, ucontrol);
332}
333
9e6e96a1
MB		 334static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
335{
b2c812e2 336 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 337 struct wm8994_pdata *pdata = wm8994->pdata;
338 int base = wm8994_drc_base[drc];
339 int cfg = wm8994->drc_cfg[drc];
340 int save, i;
341
342 /* Save any enables; the configuration should clear them. */
343 save = snd_soc_read(codec, base);
344 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
345 WM8994_AIF1ADC1R_DRC_ENA;
346
347 for (i = 0; i < WM8994_DRC_REGS; i++)
348 snd_soc_update_bits(codec, base + i, 0xffff,
349 pdata->drc_cfgs[cfg].regs[i]);
350
351 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
352 WM8994_AIF1ADC1L_DRC_ENA |
353 WM8994_AIF1ADC1R_DRC_ENA, save);
354}
355
356/* Icky as hell but saves code duplication */
357static int wm8994_get_drc(const char *name)
358{
359 if (strcmp(name, "AIF1DRC1 Mode") == 0)
360 return 0;
361 if (strcmp(name, "AIF1DRC2 Mode") == 0)
362 return 1;
363 if (strcmp(name, "AIF2DRC Mode") == 0)
364 return 2;
365 return -EINVAL;
366}
367
368static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_value *ucontrol)
370{
371 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 372 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 373 struct wm8994_pdata *pdata = wm8994->pdata;
374 int drc = wm8994_get_drc(kcontrol->id.name);
375 int value = ucontrol->value.integer.value[0];
376
377 if (drc < 0)
378 return drc;
379
380 if (value >= pdata->num_drc_cfgs)
381 return -EINVAL;
382
383 wm8994->drc_cfg[drc] = value;
384
385 wm8994_set_drc(codec, drc);
386
387 return 0;
388}
389
390static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
391 struct snd_ctl_elem_value *ucontrol)
392{
393 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 395 int drc = wm8994_get_drc(kcontrol->id.name);
396
397 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
398
399 return 0;
400}
401
402static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
403{
b2c812e2 404 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 405 struct wm8994_pdata *pdata = wm8994->pdata;
406 int base = wm8994_retune_mobile_base[block];
407 int iface, best, best_val, save, i, cfg;
408
409 if (!pdata || !wm8994->num_retune_mobile_texts)
410 return;
411
412 switch (block) {
413 case 0:
414 case 1:
415 iface = 0;
416 break;
417 case 2:
418 iface = 1;
419 break;
420 default:
421 return;
422 }
423
424 /* Find the version of the currently selected configuration
425 * with the nearest sample rate. */
426 cfg = wm8994->retune_mobile_cfg[block];
427 best = 0;
428 best_val = INT_MAX;
429 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
430 if (strcmp(pdata->retune_mobile_cfgs[i].name,
431 wm8994->retune_mobile_texts[cfg]) == 0 &&
432 abs(pdata->retune_mobile_cfgs[i].rate
433 - wm8994->dac_rates[iface]) < best_val) {
434 best = i;
435 best_val = abs(pdata->retune_mobile_cfgs[i].rate
436 - wm8994->dac_rates[iface]);
437 }
438 }
439
440 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
441 block,
442 pdata->retune_mobile_cfgs[best].name,
443 pdata->retune_mobile_cfgs[best].rate,
444 wm8994->dac_rates[iface]);
445
446 /* The EQ will be disabled while reconfiguring it, remember the
447 * current configuration.
448 */
449 save = snd_soc_read(codec, base);
450 save &= WM8994_AIF1DAC1_EQ_ENA;
451
452 for (i = 0; i < WM8994_EQ_REGS; i++)
453 snd_soc_update_bits(codec, base + i, 0xffff,
454 pdata->retune_mobile_cfgs[best].regs[i]);
455
456 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
457}
458
459/* Icky as hell but saves code duplication */
460static int wm8994_get_retune_mobile_block(const char *name)
461{
462 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
463 return 0;
464 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
465 return 1;
466 if (strcmp(name, "AIF2 EQ Mode") == 0)
467 return 2;
468 return -EINVAL;
469}
470
471static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_value *ucontrol)
473{
474 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 475 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 476 struct wm8994_pdata *pdata = wm8994->pdata;
477 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
478 int value = ucontrol->value.integer.value[0];
479
480 if (block < 0)
481 return block;
482
483 if (value >= pdata->num_retune_mobile_cfgs)
484 return -EINVAL;
485
486 wm8994->retune_mobile_cfg[block] = value;
487
488 wm8994_set_retune_mobile(codec, block);
489
490 return 0;
491}
492
493static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
494 struct snd_ctl_elem_value *ucontrol)
495{
496 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 497 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 498 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
499
500 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
501
502 return 0;
503}
504
96b101ef 505static const char *aif_chan_src_text[] = {
f554885f
MB		 506 "Left", "Right"
507};
508
96b101ef
MB		 509static const struct soc_enum aif1adcl_src =
510 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
511
512static const struct soc_enum aif1adcr_src =
513 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
514
515static const struct soc_enum aif2adcl_src =
516 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
517
518static const struct soc_enum aif2adcr_src =
519 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
520
f554885f 521static const struct soc_enum aif1dacl_src =
96b101ef 522 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 523
524static const struct soc_enum aif1dacr_src =
96b101ef 525 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 526
527static const struct soc_enum aif2dacl_src =
96b101ef 528 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 529
530static const struct soc_enum aif2dacr_src =
96b101ef 531 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 532
d6addcc9
MB		 533static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
534{
535 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
536 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
537 int ena, reg, aif;
538
539 switch (mbc) {
540 case 0:
541 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
542 aif = 0;
543 break;
544 case 1:
545 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
546 aif = 0;
547 break;
548 case 2:
549 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
550 aif = 1;
551 break;
552 default:
553 BUG();
554 return;
555 }
556
557 /* We can only enable the MBC if the AIF is enabled and we
558 * want it to be enabled. */
559 ena = pwr_reg && wm8994->mbc_ena[mbc];
560
561 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
562
563 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
564 mbc, start, pwr_reg, reg);
565
566 if (start && ena) {
567 /* If the DSP is already running then noop */
568 if (reg & WM8958_DSP2_ENA)
569 return;
570
571 /* Switch the clock over to the appropriate AIF */
572 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
573 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
574 aif << WM8958_DSP2CLK_SRC_SHIFT |
575 WM8958_DSP2CLK_ENA);
576
577 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
578 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
579
580 /* TODO: Apply any user specified MBC settings */
581
582 /* Run the DSP */
583 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
584 WM8958_DSP2_RUNR);
585
586 /* And we're off! */
587 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
588 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
589 mbc << WM8958_MBC_SEL_SHIFT |
590 WM8958_MBC_ENA);
591 } else {
592 /* If the DSP is already stopped then noop */
593 if (!(reg & WM8958_DSP2_ENA))
594 return;
595
596 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
597 WM8958_MBC_ENA, 0);
598 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
599 WM8958_DSP2_ENA, 0);
600 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
601 WM8958_DSP2CLK_ENA, 0);
602 }
603}
604
605static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
606 struct snd_kcontrol *kcontrol, int event)
607{
608 struct snd_soc_codec *codec = w->codec;
609 int mbc;
610
611 switch (w->shift) {
612 case 13:
613 case 12:
614 mbc = 2;
615 break;
616 case 11:
617 case 10:
618 mbc = 1;
619 break;
620 case 9:
621 case 8:
622 mbc = 0;
623 break;
624 default:
625 BUG();
626 return -EINVAL;
627 }
628
629 switch (event) {
630 case SND_SOC_DAPM_POST_PMU:
631 wm8958_mbc_apply(codec, mbc, 1);
632 break;
633 case SND_SOC_DAPM_POST_PMD:
634 wm8958_mbc_apply(codec, mbc, 0);
635 break;
636 }
637
638 return 0;
639}
640
641static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
642 struct snd_ctl_elem_info *uinfo)
643{
644 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
645 uinfo->count = 1;
646 uinfo->value.integer.min = 0;
647 uinfo->value.integer.max = 1;
648 return 0;
649}
650
651static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
652 struct snd_ctl_elem_value *ucontrol)
653{
654 int mbc = kcontrol->private_value;
655 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
656 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
657
658 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
659
660 return 0;
661}
662
663static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
664 struct snd_ctl_elem_value *ucontrol)
665{
666 int mbc = kcontrol->private_value;
667 int i;
668 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
669 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
670
671 if (ucontrol->value.integer.value[0] > 1)
672 return -EINVAL;
673
674 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
675 if (mbc != i && wm8994->mbc_ena[i]) {
676 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
677 return -EBUSY;
678 }
679 }
680
681 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
682
683 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
684
685 return 0;
686}
687
688#define WM8958_MBC_SWITCH(xname, xval) {\
689 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
690 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
691 .info = wm8958_mbc_info, \
692 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
693 .private_value = xval }
694
9e6e96a1
MB		 695static const struct snd_kcontrol_new wm8994_snd_controls[] = {
696SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
697 WM8994_AIF1_ADC1_RIGHT_VOLUME,
698 1, 119, 0, digital_tlv),
699SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
700 WM8994_AIF1_ADC2_RIGHT_VOLUME,
701 1, 119, 0, digital_tlv),
702SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
703 WM8994_AIF2_ADC_RIGHT_VOLUME,
704 1, 119, 0, digital_tlv),
705
96b101ef
MB		 706SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
707SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
708SOC_ENUM("AIF2ADCL Source", aif1adcl_src),
709SOC_ENUM("AIF2ADCR Source", aif1adcr_src),
710
f554885f
MB		 711SOC_ENUM("AIF1DACL Source", aif1dacl_src),
712SOC_ENUM("AIF1DACR Source", aif1dacr_src),
713SOC_ENUM("AIF2DACL Source", aif1dacl_src),
714SOC_ENUM("AIF2DACR Source", aif1dacr_src),
715
9e6e96a1
MB		 716SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
717 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
718SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
719 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
720SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
721 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
722
723SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
724SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
725
726SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
727SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
728SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
729
730WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
731WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
732WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
733
734WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
735WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
736WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
737
738WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
739WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
740WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
741
742SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
743 5, 12, 0, st_tlv),
744SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
745 0, 12, 0, st_tlv),
746SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
747 5, 12, 0, st_tlv),
748SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
749 0, 12, 0, st_tlv),
750SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
751SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
752
753SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
754 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
755SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
756 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
757
758SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
759 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
760SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
761 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
762
763SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
764 6, 1, 1, wm_hubs_spkmix_tlv),
765SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
766 2, 1, 1, wm_hubs_spkmix_tlv),
767
768SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
769 6, 1, 1, wm_hubs_spkmix_tlv),
770SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
771 2, 1, 1, wm_hubs_spkmix_tlv),
772
773SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
774 10, 15, 0, wm8994_3d_tlv),
775SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
776 8, 1, 0),
777SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
778 10, 15, 0, wm8994_3d_tlv),
779SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
780 8, 1, 0),
781SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
782 10, 15, 0, wm8994_3d_tlv),
783SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
784 8, 1, 0),
785};
786
787static const struct snd_kcontrol_new wm8994_eq_controls[] = {
788SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
789 eq_tlv),
790SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
791 eq_tlv),
792SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
793 eq_tlv),
794SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
795 eq_tlv),
796SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
797 eq_tlv),
798
799SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
800 eq_tlv),
801SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
802 eq_tlv),
803SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
804 eq_tlv),
805SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
806 eq_tlv),
807SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
808 eq_tlv),
809
810SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
811 eq_tlv),
812SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
813 eq_tlv),
814SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
815 eq_tlv),
816SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
817 eq_tlv),
818SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
819 eq_tlv),
820};
821
c4431df0
MB		 822static const struct snd_kcontrol_new wm8958_snd_controls[] = {
823SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
d6addcc9
MB		 824WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
825WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
826WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
c4431df0
MB		 827};
828
9e6e96a1
MB		 829static int clk_sys_event(struct snd_soc_dapm_widget *w,
830 struct snd_kcontrol *kcontrol, int event)
831{
832 struct snd_soc_codec *codec = w->codec;
833
834 switch (event) {
835 case SND_SOC_DAPM_PRE_PMU:
836 return configure_clock(codec);
837
838 case SND_SOC_DAPM_POST_PMD:
839 configure_clock(codec);
840 break;
841 }
842
843 return 0;
844}
845
846static void wm8994_update_class_w(struct snd_soc_codec *codec)
847{
fec6dd83 848 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 849 int enable = 1;
850 int source = 0; /* GCC flow analysis can't track enable */
851 int reg, reg_r;
852
853 /* Only support direct DAC->headphone paths */
854 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
855 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 856 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 857 enable = 0;
858 }
859
860 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
861 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 862 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 863 enable = 0;
864 }
865
866 /* We also need the same setting for L/R and only one path */
867 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
868 switch (reg) {
869 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 870 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 871 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
872 break;
873 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 874 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 875 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
876 break;
877 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 878 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 879 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
880 break;
881 default:
ee839a21 882 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 883 enable = 0;
884 break;
885 }
886
887 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
888 if (reg_r != reg) {
ee839a21 889 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 890 enable = 0;
891 }
892
893 if (enable) {
894 dev_dbg(codec->dev, "Class W enabled\n");
895 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
896 WM8994_CP_DYN_PWR |
897 WM8994_CP_DYN_SRC_SEL_MASK,
898 source | WM8994_CP_DYN_PWR);
fec6dd83 899 wm8994->hubs.class_w = true;
9e6e96a1
MB		 900
901 } else {
902 dev_dbg(codec->dev, "Class W disabled\n");
903 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
904 WM8994_CP_DYN_PWR, 0);
fec6dd83 905 wm8994->hubs.class_w = false;
9e6e96a1
MB		 906 }
907}
908
909static const char *hp_mux_text[] = {
910 "Mixer",
911 "DAC",
912};
913
914#define WM8994_HP_ENUM(xname, xenum) \
915{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
916 .info = snd_soc_info_enum_double, \
917 .get = snd_soc_dapm_get_enum_double, \
918 .put = wm8994_put_hp_enum, \
919 .private_value = (unsigned long)&xenum }
920
921static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
922 struct snd_ctl_elem_value *ucontrol)
923{
924 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
925 struct snd_soc_codec *codec = w->codec;
926 int ret;
927
928 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
929
930 wm8994_update_class_w(codec);
931
932 return ret;
933}
934
935static const struct soc_enum hpl_enum =
936 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
937
938static const struct snd_kcontrol_new hpl_mux =
939 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
940
941static const struct soc_enum hpr_enum =
942 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
943
944static const struct snd_kcontrol_new hpr_mux =
945 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
946
947static const char *adc_mux_text[] = {
948 "ADC",
949 "DMIC",
950};
951
952static const struct soc_enum adc_enum =
953 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
954
955static const struct snd_kcontrol_new adcl_mux =
956 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
957
958static const struct snd_kcontrol_new adcr_mux =
959 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
960
961static const struct snd_kcontrol_new left_speaker_mixer[] = {
962SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
963SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
964SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
965SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
966SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
967};
968
969static const struct snd_kcontrol_new right_speaker_mixer[] = {
970SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
971SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
972SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
973SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
974SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
975};
976
977/* Debugging; dump chip status after DAPM transitions */
978static int post_ev(struct snd_soc_dapm_widget *w,
979 struct snd_kcontrol *kcontrol, int event)
980{
981 struct snd_soc_codec *codec = w->codec;
982 dev_dbg(codec->dev, "SRC status: %x\n",
983 snd_soc_read(codec,
984 WM8994_RATE_STATUS));
985 return 0;
986}
987
988static const struct snd_kcontrol_new aif1adc1l_mix[] = {
989SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
990 1, 1, 0),
991SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
992 0, 1, 0),
993};
994
995static const struct snd_kcontrol_new aif1adc1r_mix[] = {
996SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
997 1, 1, 0),
998SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
999 0, 1, 0),
1000};
1001
a3257ba8
MB		 1002static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1003SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1004 1, 1, 0),
1005SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1006 0, 1, 0),
1007};
1008
1009static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1010SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1011 1, 1, 0),
1012SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1013 0, 1, 0),
1014};
1015
9e6e96a1
MB		 1016static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1017SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1018 5, 1, 0),
1019SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1020 4, 1, 0),
1021SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1022 2, 1, 0),
1023SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1024 1, 1, 0),
1025SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1026 0, 1, 0),
1027};
1028
1029static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1030SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1031 5, 1, 0),
1032SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1033 4, 1, 0),
1034SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1035 2, 1, 0),
1036SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1037 1, 1, 0),
1038SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1039 0, 1, 0),
1040};
1041
1042#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1043{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1044 .info = snd_soc_info_volsw, \
1045 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1046 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1047
1048static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1049 struct snd_ctl_elem_value *ucontrol)
1050{
1051 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1052 struct snd_soc_codec *codec = w->codec;
1053 int ret;
1054
1055 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1056
1057 wm8994_update_class_w(codec);
1058
1059 return ret;
1060}
1061
1062static const struct snd_kcontrol_new dac1l_mix[] = {
1063WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1064 5, 1, 0),
1065WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1066 4, 1, 0),
1067WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1068 2, 1, 0),
1069WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1070 1, 1, 0),
1071WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1072 0, 1, 0),
1073};
1074
1075static const struct snd_kcontrol_new dac1r_mix[] = {
1076WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1077 5, 1, 0),
1078WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1079 4, 1, 0),
1080WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1081 2, 1, 0),
1082WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1083 1, 1, 0),
1084WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1085 0, 1, 0),
1086};
1087
1088static const char *sidetone_text[] = {
1089 "ADC/DMIC1", "DMIC2",
1090};
1091
1092static const struct soc_enum sidetone1_enum =
1093 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1094
1095static const struct snd_kcontrol_new sidetone1_mux =
1096 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1097
1098static const struct soc_enum sidetone2_enum =
1099 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1100
1101static const struct snd_kcontrol_new sidetone2_mux =
1102 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1103
1104static const char *aif1dac_text[] = {
1105 "AIF1DACDAT", "AIF3DACDAT",
1106};
1107
1108static const struct soc_enum aif1dac_enum =
1109 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1110
1111static const struct snd_kcontrol_new aif1dac_mux =
1112 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1113
1114static const char *aif2dac_text[] = {
1115 "AIF2DACDAT", "AIF3DACDAT",
1116};
1117
1118static const struct soc_enum aif2dac_enum =
1119 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1120
1121static const struct snd_kcontrol_new aif2dac_mux =
1122 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1123
1124static const char *aif2adc_text[] = {
1125 "AIF2ADCDAT", "AIF3DACDAT",
1126};
1127
1128static const struct soc_enum aif2adc_enum =
1129 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1130
1131static const struct snd_kcontrol_new aif2adc_mux =
1132 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1133
1134static const char *aif3adc_text[] = {
c4431df0 1135 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1136};
1137
c4431df0 1138static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1139 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1140
c4431df0
MB		 1141static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1142 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1143
1144static const struct soc_enum wm8958_aif3adc_enum =
1145 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1146
1147static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1148 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1149
1150static const char *mono_pcm_out_text[] = {
1151 "None", "AIF2ADCL", "AIF2ADCR",
1152};
1153
1154static const struct soc_enum mono_pcm_out_enum =
1155 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1156
1157static const struct snd_kcontrol_new mono_pcm_out_mux =
1158 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1159
1160static const char *aif2dac_src_text[] = {
1161 "AIF2", "AIF3",
1162};
1163
1164/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1165static const struct soc_enum aif2dacl_src_enum =
1166 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1167
1168static const struct snd_kcontrol_new aif2dacl_src_mux =
1169 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1170
1171static const struct soc_enum aif2dacr_src_enum =
1172 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1173
1174static const struct snd_kcontrol_new aif2dacr_src_mux =
1175 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1
MB		 1176
1177static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1178SND_SOC_DAPM_INPUT("DMIC1DAT"),
1179SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1180SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1
MB		 1181
1182SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1183 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1184
1185SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1186SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1187SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1188
1189SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1190SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1191
1192SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
1193 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1194SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
1195 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1196SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1197 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1198 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1199SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1200 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1201 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1202
1203SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
1204 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1205SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
1206 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1207SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1208 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1209 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1210SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1211 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1212 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1213
1214SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1215 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1216SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1217 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1218
a3257ba8
MB		 1219SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1220 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1221SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1222 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1223
9e6e96a1
MB		 1224SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1225 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1226SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1227 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1228
1229SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1230SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1231
1232SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1233 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1234SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1235 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1236
1237SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1238 WM8994_POWER_MANAGEMENT_4, 13, 0),
1239SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1240 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1241SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1242 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1243 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1244SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1245 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1246 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1247
1248SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1249SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1250SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1251
1252SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1253SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1254SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1255
1256SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1257SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1258
1259SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1260
1261SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1262SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1263SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1264SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1265
1266/* Power is done with the muxes since the ADC power also controls the
1267 * downsampling chain, the chip will automatically manage the analogue
1268 * specific portions.
1269 */
1270SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1271SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1272
1273SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1274SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1275
1276SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1277SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1278SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1279SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1280
1281SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1282SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1283
1284SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1285 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1286SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1287 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1288
1289SND_SOC_DAPM_POST("Debug log", post_ev),
1290};
1291
c4431df0
MB		 1292static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1293SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1294};
9e6e96a1 1295
c4431df0
MB		 1296static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1297SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1298SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1299SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1300SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1301};
1302
1303static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1304 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1305 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1306
1307 { "DSP1CLK", NULL, "CLK_SYS" },
1308 { "DSP2CLK", NULL, "CLK_SYS" },
1309 { "DSPINTCLK", NULL, "CLK_SYS" },
1310
1311 { "AIF1ADC1L", NULL, "AIF1CLK" },
1312 { "AIF1ADC1L", NULL, "DSP1CLK" },
1313 { "AIF1ADC1R", NULL, "AIF1CLK" },
1314 { "AIF1ADC1R", NULL, "DSP1CLK" },
1315 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1316
1317 { "AIF1DAC1L", NULL, "AIF1CLK" },
1318 { "AIF1DAC1L", NULL, "DSP1CLK" },
1319 { "AIF1DAC1R", NULL, "AIF1CLK" },
1320 { "AIF1DAC1R", NULL, "DSP1CLK" },
1321 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1322
1323 { "AIF1ADC2L", NULL, "AIF1CLK" },
1324 { "AIF1ADC2L", NULL, "DSP1CLK" },
1325 { "AIF1ADC2R", NULL, "AIF1CLK" },
1326 { "AIF1ADC2R", NULL, "DSP1CLK" },
1327 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1328
1329 { "AIF1DAC2L", NULL, "AIF1CLK" },
1330 { "AIF1DAC2L", NULL, "DSP1CLK" },
1331 { "AIF1DAC2R", NULL, "AIF1CLK" },
1332 { "AIF1DAC2R", NULL, "DSP1CLK" },
1333 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1334
1335 { "AIF2ADCL", NULL, "AIF2CLK" },
1336 { "AIF2ADCL", NULL, "DSP2CLK" },
1337 { "AIF2ADCR", NULL, "AIF2CLK" },
1338 { "AIF2ADCR", NULL, "DSP2CLK" },
1339 { "AIF2ADCR", NULL, "DSPINTCLK" },
1340
1341 { "AIF2DACL", NULL, "AIF2CLK" },
1342 { "AIF2DACL", NULL, "DSP2CLK" },
1343 { "AIF2DACR", NULL, "AIF2CLK" },
1344 { "AIF2DACR", NULL, "DSP2CLK" },
1345 { "AIF2DACR", NULL, "DSPINTCLK" },
1346
1347 { "DMIC1L", NULL, "DMIC1DAT" },
1348 { "DMIC1L", NULL, "CLK_SYS" },
1349 { "DMIC1R", NULL, "DMIC1DAT" },
1350 { "DMIC1R", NULL, "CLK_SYS" },
1351 { "DMIC2L", NULL, "DMIC2DAT" },
1352 { "DMIC2L", NULL, "CLK_SYS" },
1353 { "DMIC2R", NULL, "DMIC2DAT" },
1354 { "DMIC2R", NULL, "CLK_SYS" },
1355
1356 { "ADCL", NULL, "AIF1CLK" },
1357 { "ADCL", NULL, "DSP1CLK" },
1358 { "ADCL", NULL, "DSPINTCLK" },
1359
1360 { "ADCR", NULL, "AIF1CLK" },
1361 { "ADCR", NULL, "DSP1CLK" },
1362 { "ADCR", NULL, "DSPINTCLK" },
1363
1364 { "ADCL Mux", "ADC", "ADCL" },
1365 { "ADCL Mux", "DMIC", "DMIC1L" },
1366 { "ADCR Mux", "ADC", "ADCR" },
1367 { "ADCR Mux", "DMIC", "DMIC1R" },
1368
1369 { "DAC1L", NULL, "AIF1CLK" },
1370 { "DAC1L", NULL, "DSP1CLK" },
1371 { "DAC1L", NULL, "DSPINTCLK" },
1372
1373 { "DAC1R", NULL, "AIF1CLK" },
1374 { "DAC1R", NULL, "DSP1CLK" },
1375 { "DAC1R", NULL, "DSPINTCLK" },
1376
1377 { "DAC2L", NULL, "AIF2CLK" },
1378 { "DAC2L", NULL, "DSP2CLK" },
1379 { "DAC2L", NULL, "DSPINTCLK" },
1380
1381 { "DAC2R", NULL, "AIF2DACR" },
1382 { "DAC2R", NULL, "AIF2CLK" },
1383 { "DAC2R", NULL, "DSP2CLK" },
1384 { "DAC2R", NULL, "DSPINTCLK" },
1385
1386 { "TOCLK", NULL, "CLK_SYS" },
1387
1388 /* AIF1 outputs */
1389 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1390 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1391 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1392
1393 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1394 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1395 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1396
a3257ba8
MB		 1397 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1398 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1399 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1400
1401 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1402 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1403 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1404
9e6e96a1
MB		 1405 /* Pin level routing for AIF3 */
1406 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1407 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1408 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1409 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1410
9e6e96a1
MB		 1411 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1412 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1413 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1414 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1415 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1416 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1417 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1418
1419 /* DAC1 inputs */
1420 { "DAC1L", NULL, "DAC1L Mixer" },
1421 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1422 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1423 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1424 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1425 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1426
1427 { "DAC1R", NULL, "DAC1R Mixer" },
1428 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1429 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1430 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1431 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1432 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1433
1434 /* DAC2/AIF2 outputs */
1435 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1436 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1437 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1438 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1439 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1440 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1441 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1442
1443 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1444 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1445 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1446 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1447 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1448 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1449 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1450
1451 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1452
1453 /* AIF3 output */
1454 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1455 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1456 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1457 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1458 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1459 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1460 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1461 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1462
1463 /* Sidetone */
1464 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1465 { "Left Sidetone", "DMIC2", "DMIC2L" },
1466 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1467 { "Right Sidetone", "DMIC2", "DMIC2R" },
1468
1469 /* Output stages */
1470 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1471 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1472
1473 { "SPKL", "DAC1 Switch", "DAC1L" },
1474 { "SPKL", "DAC2 Switch", "DAC2L" },
1475
1476 { "SPKR", "DAC1 Switch", "DAC1R" },
1477 { "SPKR", "DAC2 Switch", "DAC2R" },
1478
1479 { "Left Headphone Mux", "DAC", "DAC1L" },
1480 { "Right Headphone Mux", "DAC", "DAC1R" },
1481};
1482
c4431df0
MB		 1483static const struct snd_soc_dapm_route wm8994_intercon[] = {
1484 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1485 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1486};
1487
1488static const struct snd_soc_dapm_route wm8958_intercon[] = {
1489 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1490 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1491
1492 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1493 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1494 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1495 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1496
1497 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1498 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1499
1500 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1501};
1502
9e6e96a1
MB		 1503/* The size in bits of the FLL divide multiplied by 10
1504 * to allow rounding later */
1505#define FIXED_FLL_SIZE ((1 << 16) * 10)
1506
1507struct fll_div {
1508 u16 outdiv;
1509 u16 n;
1510 u16 k;
1511 u16 clk_ref_div;
1512 u16 fll_fratio;
1513};
1514
1515static int wm8994_get_fll_config(struct fll_div *fll,
1516 int freq_in, int freq_out)
1517{
1518 u64 Kpart;
1519 unsigned int K, Ndiv, Nmod;
1520
1521 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1522
1523 /* Scale the input frequency down to <= 13.5MHz */
1524 fll->clk_ref_div = 0;
1525 while (freq_in > 13500000) {
1526 fll->clk_ref_div++;
1527 freq_in /= 2;
1528
1529 if (fll->clk_ref_div > 3)
1530 return -EINVAL;
1531 }
1532 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1533
1534 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1535 fll->outdiv = 3;
1536 while (freq_out * (fll->outdiv + 1) < 90000000) {
1537 fll->outdiv++;
1538 if (fll->outdiv > 63)
1539 return -EINVAL;
1540 }
1541 freq_out *= fll->outdiv + 1;
1542 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1543
1544 if (freq_in > 1000000) {
1545 fll->fll_fratio = 0;
7d48a6ac
MB		 1546 } else if (freq_in > 256000) {
1547 fll->fll_fratio = 1;
1548 freq_in *= 2;
1549 } else if (freq_in > 128000) {
1550 fll->fll_fratio = 2;
1551 freq_in *= 4;
1552 } else if (freq_in > 64000) {
9e6e96a1
MB		 1553 fll->fll_fratio = 3;
1554 freq_in *= 8;
7d48a6ac
MB		 1555 } else {
1556 fll->fll_fratio = 4;
1557 freq_in *= 16;
9e6e96a1
MB		 1558 }
1559 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1560
1561 /* Now, calculate N.K */
1562 Ndiv = freq_out / freq_in;
1563
1564 fll->n = Ndiv;
1565 Nmod = freq_out % freq_in;
1566 pr_debug("Nmod=%d\n", Nmod);
1567
1568 /* Calculate fractional part - scale up so we can round. */
1569 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1570
1571 do_div(Kpart, freq_in);
1572
1573 K = Kpart & 0xFFFFFFFF;
1574
1575 if ((K % 10) >= 5)
1576 K += 5;
1577
1578 /* Move down to proper range now rounding is done */
1579 fll->k = K / 10;
1580
1581 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1582
1583 return 0;
1584}
1585
f0fba2ad 1586static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1587 unsigned int freq_in, unsigned int freq_out)
1588{
b2c812e2 1589 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1590 int reg_offset, ret;
1591 struct fll_div fll;
1592 u16 reg, aif1, aif2;
1593
1594 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1595 & WM8994_AIF1CLK_ENA;
1596
1597 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1598 & WM8994_AIF2CLK_ENA;
1599
1600 switch (id) {
1601 case WM8994_FLL1:
1602 reg_offset = 0;
1603 id = 0;
1604 break;
1605 case WM8994_FLL2:
1606 reg_offset = 0x20;
1607 id = 1;
1608 break;
1609 default:
1610 return -EINVAL;
1611 }
1612
136ff2a2 1613 switch (src) {
7add84aa
MB		 1614 case 0:
1615 /* Allow no source specification when stopping */
1616 if (freq_out)
1617 return -EINVAL;
1618 break;
136ff2a2
MB		 1619 case WM8994_FLL_SRC_MCLK1:
1620 case WM8994_FLL_SRC_MCLK2:
1621 case WM8994_FLL_SRC_LRCLK:
1622 case WM8994_FLL_SRC_BCLK:
1623 break;
1624 default:
1625 return -EINVAL;
1626 }
1627
9e6e96a1
MB		 1628 /* Are we changing anything? */
1629 if (wm8994->fll[id].src == src &&
1630 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1631 return 0;
1632
1633 /* If we're stopping the FLL redo the old config - no
1634 * registers will actually be written but we avoid GCC flow
1635 * analysis bugs spewing warnings.
1636 */
1637 if (freq_out)
1638 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1639 else
1640 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1641 wm8994->fll[id].out);
1642 if (ret < 0)
1643 return ret;
1644
1645 /* Gate the AIF clocks while we reclock */
1646 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1647 WM8994_AIF1CLK_ENA, 0);
1648 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1649 WM8994_AIF2CLK_ENA, 0);
1650
1651 /* We always need to disable the FLL while reconfiguring */
1652 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1653 WM8994_FLL1_ENA, 0);
1654
1655 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1656 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1657 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1658 WM8994_FLL1_OUTDIV_MASK |
1659 WM8994_FLL1_FRATIO_MASK, reg);
1660
1661 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1662
1663 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1664 WM8994_FLL1_N_MASK,
1665 fll.n << WM8994_FLL1_N_SHIFT);
1666
1667 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1668 WM8994_FLL1_REFCLK_DIV_MASK |
1669 WM8994_FLL1_REFCLK_SRC_MASK,
1670 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1671 (src - 1));
9e6e96a1
MB		 1672
1673 /* Enable (with fractional mode if required) */
1674 if (freq_out) {
1675 if (fll.k)
1676 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1677 else
1678 reg = WM8994_FLL1_ENA;
1679 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1680 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1681 reg);
1682 }
1683
1684 wm8994->fll[id].in = freq_in;
1685 wm8994->fll[id].out = freq_out;
136ff2a2 1686 wm8994->fll[id].src = src;
9e6e96a1
MB		 1687
1688 /* Enable any gated AIF clocks */
1689 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1690 WM8994_AIF1CLK_ENA, aif1);
1691 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1692 WM8994_AIF2CLK_ENA, aif2);
1693
1694 configure_clock(codec);
1695
1696 return 0;
1697}
1698
f0fba2ad 1699
66b47fdb
MB		 1700static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1701
f0fba2ad
LG		 1702static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1703 unsigned int freq_in, unsigned int freq_out)
1704{
1705 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1706}
1707
9e6e96a1
MB		 1708static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1709 int clk_id, unsigned int freq, int dir)
1710{
1711 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1712 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1713 int i;
9e6e96a1
MB		 1714
1715 switch (dai->id) {
1716 case 1:
1717 case 2:
1718 break;
1719
1720 default:
1721 /* AIF3 shares clocking with AIF1/2 */
1722 return -EINVAL;
1723 }
1724
1725 switch (clk_id) {
1726 case WM8994_SYSCLK_MCLK1:
1727 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1728 wm8994->mclk[0] = freq;
1729 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1730 dai->id, freq);
1731 break;
1732
1733 case WM8994_SYSCLK_MCLK2:
1734 /* TODO: Set GPIO AF */
1735 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1736 wm8994->mclk[1] = freq;
1737 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1738 dai->id, freq);
1739 break;
1740
1741 case WM8994_SYSCLK_FLL1:
1742 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1743 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1744 break;
1745
1746 case WM8994_SYSCLK_FLL2:
1747 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1748 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1749 break;
1750
66b47fdb
MB		 1751 case WM8994_SYSCLK_OPCLK:
1752 /* Special case - a division (times 10) is given and
1753 * no effect on main clocking.
1754 */
1755 if (freq) {
1756 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1757 if (opclk_divs[i] == freq)
1758 break;
1759 if (i == ARRAY_SIZE(opclk_divs))
1760 return -EINVAL;
1761 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1762 WM8994_OPCLK_DIV_MASK, i);
1763 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1764 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1765 } else {
1766 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1767 WM8994_OPCLK_ENA, 0);
1768 }
1769
9e6e96a1
MB		 1770 default:
1771 return -EINVAL;
1772 }
1773
1774 configure_clock(codec);
1775
1776 return 0;
1777}
1778
1779static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1780 enum snd_soc_bias_level level)
1781{
3a423157 1782 struct wm8994 *control = codec->control_data;
b6b05691
MB		 1783 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1784
9e6e96a1
MB		 1785 switch (level) {
1786 case SND_SOC_BIAS_ON:
1787 break;
1788
1789 case SND_SOC_BIAS_PREPARE:
1790 /* VMID=2x40k */
1791 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1792 WM8994_VMID_SEL_MASK, 0x2);
1793 break;
1794
1795 case SND_SOC_BIAS_STANDBY:
ce6120cc 1796 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0c17b393
MB		 1797 /* Tweak DC servo and DSP configuration for
1798 * improved performance. */
3a423157 1799 if (control->type == WM8994 && wm8994->revision < 4) {
b6b05691
MB		 1800 /* Tweak DC servo and DSP configuration for
1801 * improved performance. */
1802 snd_soc_write(codec, 0x102, 0x3);
1803 snd_soc_write(codec, 0x56, 0x3);
1804 snd_soc_write(codec, 0x817, 0);
1805 snd_soc_write(codec, 0x102, 0);
1806 }
9e6e96a1
MB		 1807
1808 /* Discharge LINEOUT1 & 2 */
1809 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1810 WM8994_LINEOUT1_DISCH |
1811 WM8994_LINEOUT2_DISCH,
1812 WM8994_LINEOUT1_DISCH |
1813 WM8994_LINEOUT2_DISCH);
1814
1815 /* Startup bias, VMID ramp & buffer */
1816 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1817 WM8994_STARTUP_BIAS_ENA |
1818 WM8994_VMID_BUF_ENA |
1819 WM8994_VMID_RAMP_MASK,
1820 WM8994_STARTUP_BIAS_ENA |
1821 WM8994_VMID_BUF_ENA |
1822 (0x11 << WM8994_VMID_RAMP_SHIFT));
1823
1824 /* Main bias enable, VMID=2x40k */
1825 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1826 WM8994_BIAS_ENA |
1827 WM8994_VMID_SEL_MASK,
1828 WM8994_BIAS_ENA | 0x2);
1829
1830 msleep(20);
1831 }
1832
1833 /* VMID=2x500k */
1834 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1835 WM8994_VMID_SEL_MASK, 0x4);
1836
1837 break;
1838
1839 case SND_SOC_BIAS_OFF:
ce6120cc 1840 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1841 /* Switch over to startup biases */
1842 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1843 WM8994_BIAS_SRC |
1844 WM8994_STARTUP_BIAS_ENA |
1845 WM8994_VMID_BUF_ENA |
1846 WM8994_VMID_RAMP_MASK,
1847 WM8994_BIAS_SRC |
1848 WM8994_STARTUP_BIAS_ENA |
1849 WM8994_VMID_BUF_ENA |
1850 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1851
d522ffbf
MB		 1852 /* Disable main biases */
1853 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1854 WM8994_BIAS_ENA |
1855 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1856
d522ffbf
MB		 1857 /* Discharge line */
1858 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1859 WM8994_LINEOUT1_DISCH |
1860 WM8994_LINEOUT2_DISCH,
1861 WM8994_LINEOUT1_DISCH |
1862 WM8994_LINEOUT2_DISCH);
9e6e96a1 1863
d522ffbf 1864 msleep(5);
9e6e96a1 1865
d522ffbf
MB		 1866 /* Switch off startup biases */
1867 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1868 WM8994_BIAS_SRC |
1869 WM8994_STARTUP_BIAS_ENA |
1870 WM8994_VMID_BUF_ENA |
1871 WM8994_VMID_RAMP_MASK, 0);
1872 }
9e6e96a1
MB		 1873 break;
1874 }
ce6120cc 1875 codec->dapm.bias_level = level;
9e6e96a1
MB		 1876 return 0;
1877}
1878
1879static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1880{
1881 struct snd_soc_codec *codec = dai->codec;
c4431df0 1882 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 1883 int ms_reg;
1884 int aif1_reg;
1885 int ms = 0;
1886 int aif1 = 0;
1887
1888 switch (dai->id) {
1889 case 1:
1890 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1891 aif1_reg = WM8994_AIF1_CONTROL_1;
1892 break;
1893 case 2:
1894 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1895 aif1_reg = WM8994_AIF2_CONTROL_1;
1896 break;
1897 default:
1898 return -EINVAL;
1899 }
1900
1901 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1902 case SND_SOC_DAIFMT_CBS_CFS:
1903 break;
1904 case SND_SOC_DAIFMT_CBM_CFM:
1905 ms = WM8994_AIF1_MSTR;
1906 break;
1907 default:
1908 return -EINVAL;
1909 }
1910
1911 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1912 case SND_SOC_DAIFMT_DSP_B:
1913 aif1 |= WM8994_AIF1_LRCLK_INV;
1914 case SND_SOC_DAIFMT_DSP_A:
1915 aif1 |= 0x18;
1916 break;
1917 case SND_SOC_DAIFMT_I2S:
1918 aif1 |= 0x10;
1919 break;
1920 case SND_SOC_DAIFMT_RIGHT_J:
1921 break;
1922 case SND_SOC_DAIFMT_LEFT_J:
1923 aif1 |= 0x8;
1924 break;
1925 default:
1926 return -EINVAL;
1927 }
1928
1929 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1930 case SND_SOC_DAIFMT_DSP_A:
1931 case SND_SOC_DAIFMT_DSP_B:
1932 /* frame inversion not valid for DSP modes */
1933 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1934 case SND_SOC_DAIFMT_NB_NF:
1935 break;
1936 case SND_SOC_DAIFMT_IB_NF:
1937 aif1 |= WM8994_AIF1_BCLK_INV;
1938 break;
1939 default:
1940 return -EINVAL;
1941 }
1942 break;
1943
1944 case SND_SOC_DAIFMT_I2S:
1945 case SND_SOC_DAIFMT_RIGHT_J:
1946 case SND_SOC_DAIFMT_LEFT_J:
1947 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1948 case SND_SOC_DAIFMT_NB_NF:
1949 break;
1950 case SND_SOC_DAIFMT_IB_IF:
1951 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
1952 break;
1953 case SND_SOC_DAIFMT_IB_NF:
1954 aif1 |= WM8994_AIF1_BCLK_INV;
1955 break;
1956 case SND_SOC_DAIFMT_NB_IF:
1957 aif1 |= WM8994_AIF1_LRCLK_INV;
1958 break;
1959 default:
1960 return -EINVAL;
1961 }
1962 break;
1963 default:
1964 return -EINVAL;
1965 }
1966
c4431df0
MB		 1967 /* The AIF2 format configuration needs to be mirrored to AIF3
1968 * on WM8958 if it's in use so just do it all the time. */
1969 if (control->type == WM8958 && dai->id == 2)
1970 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
1971 WM8994_AIF1_LRCLK_INV |
1972 WM8958_AIF3_FMT_MASK, aif1);
1973
9e6e96a1
MB		 1974 snd_soc_update_bits(codec, aif1_reg,
1975 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
1976 WM8994_AIF1_FMT_MASK,
1977 aif1);
1978 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
1979 ms);
1980
1981 return 0;
1982}
1983
1984static struct {
1985 int val, rate;
1986} srs[] = {
1987 { 0, 8000 },
1988 { 1, 11025 },
1989 { 2, 12000 },
1990 { 3, 16000 },
1991 { 4, 22050 },
1992 { 5, 24000 },
1993 { 6, 32000 },
1994 { 7, 44100 },
1995 { 8, 48000 },
1996 { 9, 88200 },
1997 { 10, 96000 },
1998};
1999
2000static int fs_ratios[] = {
2001 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2002};
2003
2004static int bclk_divs[] = {
2005 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2006 640, 880, 960, 1280, 1760, 1920
2007};
2008
2009static int wm8994_hw_params(struct snd_pcm_substream *substream,
2010 struct snd_pcm_hw_params *params,
2011 struct snd_soc_dai *dai)
2012{
2013 struct snd_soc_codec *codec = dai->codec;
c4431df0 2014 struct wm8994 *control = codec->control_data;
b2c812e2 2015 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2016 int aif1_reg;
2017 int bclk_reg;
2018 int lrclk_reg;
2019 int rate_reg;
2020 int aif1 = 0;
2021 int bclk = 0;
2022 int lrclk = 0;
2023 int rate_val = 0;
2024 int id = dai->id - 1;
2025
2026 int i, cur_val, best_val, bclk_rate, best;
2027
2028 switch (dai->id) {
2029 case 1:
2030 aif1_reg = WM8994_AIF1_CONTROL_1;
2031 bclk_reg = WM8994_AIF1_BCLK;
2032 rate_reg = WM8994_AIF1_RATE;
2033 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2034 wm8994->lrclk_shared[0]) {
9e6e96a1 2035 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2036 } else {
9e6e96a1 2037 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2038 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2039 }
9e6e96a1
MB		 2040 break;
2041 case 2:
2042 aif1_reg = WM8994_AIF2_CONTROL_1;
2043 bclk_reg = WM8994_AIF2_BCLK;
2044 rate_reg = WM8994_AIF2_RATE;
2045 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2046 wm8994->lrclk_shared[1]) {
9e6e96a1 2047 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2048 } else {
9e6e96a1 2049 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2050 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2051 }
9e6e96a1 2052 break;
c4431df0
MB		 2053 case 3:
2054 switch (control->type) {
2055 case WM8958:
2056 aif1_reg = WM8958_AIF3_CONTROL_1;
2057 break;
2058 default:
2059 return 0;
2060 }
9e6e96a1
MB		 2061 default:
2062 return -EINVAL;
2063 }
2064
2065 bclk_rate = params_rate(params) * 2;
2066 switch (params_format(params)) {
2067 case SNDRV_PCM_FORMAT_S16_LE:
2068 bclk_rate *= 16;
2069 break;
2070 case SNDRV_PCM_FORMAT_S20_3LE:
2071 bclk_rate *= 20;
2072 aif1 |= 0x20;
2073 break;
2074 case SNDRV_PCM_FORMAT_S24_LE:
2075 bclk_rate *= 24;
2076 aif1 |= 0x40;
2077 break;
2078 case SNDRV_PCM_FORMAT_S32_LE:
2079 bclk_rate *= 32;
2080 aif1 |= 0x60;
2081 break;
2082 default:
2083 return -EINVAL;
2084 }
2085
2086 /* Try to find an appropriate sample rate; look for an exact match. */
2087 for (i = 0; i < ARRAY_SIZE(srs); i++)
2088 if (srs[i].rate == params_rate(params))
2089 break;
2090 if (i == ARRAY_SIZE(srs))
2091 return -EINVAL;
2092 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2093
2094 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2095 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2096 dai->id, wm8994->aifclk[id], bclk_rate);
2097
2098 if (wm8994->aifclk[id] == 0) {
2099 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2100 return -EINVAL;
2101 }
2102
2103 /* AIFCLK/fs ratio; look for a close match in either direction */
2104 best = 0;
2105 best_val = abs((fs_ratios[0] * params_rate(params))
2106 - wm8994->aifclk[id]);
2107 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2108 cur_val = abs((fs_ratios[i] * params_rate(params))
2109 - wm8994->aifclk[id]);
2110 if (cur_val >= best_val)
2111 continue;
2112 best = i;
2113 best_val = cur_val;
2114 }
2115 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2116 dai->id, fs_ratios[best]);
2117 rate_val |= best;
2118
2119 /* We may not get quite the right frequency if using
2120 * approximate clocks so look for the closest match that is
2121 * higher than the target (we need to ensure that there enough
2122 * BCLKs to clock out the samples).
2123 */
2124 best = 0;
2125 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2126 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2127 if (cur_val < 0) /* BCLK table is sorted */
2128 break;
2129 best = i;
2130 }
07cd8ada 2131 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2132 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2133 bclk_divs[best], bclk_rate);
2134 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2135
2136 lrclk = bclk_rate / params_rate(params);
2137 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2138 lrclk, bclk_rate / lrclk);
2139
2140 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2141 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2142 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2143 lrclk);
2144 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2145 WM8994_AIF1CLK_RATE_MASK, rate_val);
2146
2147 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2148 switch (dai->id) {
2149 case 1:
2150 wm8994->dac_rates[0] = params_rate(params);
2151 wm8994_set_retune_mobile(codec, 0);
2152 wm8994_set_retune_mobile(codec, 1);
2153 break;
2154 case 2:
2155 wm8994->dac_rates[1] = params_rate(params);
2156 wm8994_set_retune_mobile(codec, 2);
2157 break;
2158 }
2159 }
2160
2161 return 0;
2162}
2163
c4431df0
MB		 2164static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2165 struct snd_pcm_hw_params *params,
2166 struct snd_soc_dai *dai)
2167{
2168 struct snd_soc_codec *codec = dai->codec;
2169 struct wm8994 *control = codec->control_data;
2170 int aif1_reg;
2171 int aif1 = 0;
2172
2173 switch (dai->id) {
2174 case 3:
2175 switch (control->type) {
2176 case WM8958:
2177 aif1_reg = WM8958_AIF3_CONTROL_1;
2178 break;
2179 default:
2180 return 0;
2181 }
2182 default:
2183 return 0;
2184 }
2185
2186 switch (params_format(params)) {
2187 case SNDRV_PCM_FORMAT_S16_LE:
2188 break;
2189 case SNDRV_PCM_FORMAT_S20_3LE:
2190 aif1 |= 0x20;
2191 break;
2192 case SNDRV_PCM_FORMAT_S24_LE:
2193 aif1 |= 0x40;
2194 break;
2195 case SNDRV_PCM_FORMAT_S32_LE:
2196 aif1 |= 0x60;
2197 break;
2198 default:
2199 return -EINVAL;
2200 }
2201
2202 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2203}
2204
9e6e96a1
MB		 2205static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2206{
2207 struct snd_soc_codec *codec = codec_dai->codec;
2208 int mute_reg;
2209 int reg;
2210
2211 switch (codec_dai->id) {
2212 case 1:
2213 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2214 break;
2215 case 2:
2216 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2217 break;
2218 default:
2219 return -EINVAL;
2220 }
2221
2222 if (mute)
2223 reg = WM8994_AIF1DAC1_MUTE;
2224 else
2225 reg = 0;
2226
2227 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2228
2229 return 0;
2230}
2231
778a76e2
MB		 2232static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2233{
2234 struct snd_soc_codec *codec = codec_dai->codec;
2235 int reg, val, mask;
2236
2237 switch (codec_dai->id) {
2238 case 1:
2239 reg = WM8994_AIF1_MASTER_SLAVE;
2240 mask = WM8994_AIF1_TRI;
2241 break;
2242 case 2:
2243 reg = WM8994_AIF2_MASTER_SLAVE;
2244 mask = WM8994_AIF2_TRI;
2245 break;
2246 case 3:
2247 reg = WM8994_POWER_MANAGEMENT_6;
2248 mask = WM8994_AIF3_TRI;
2249 break;
2250 default:
2251 return -EINVAL;
2252 }
2253
2254 if (tristate)
2255 val = mask;
2256 else
2257 val = 0;
2258
2259 return snd_soc_update_bits(codec, reg, mask, reg);
2260}
2261
9e6e96a1
MB		 2262#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2263
2264#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2265 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2266
2267static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2268 .set_sysclk = wm8994_set_dai_sysclk,
2269 .set_fmt = wm8994_set_dai_fmt,
2270 .hw_params = wm8994_hw_params,
2271 .digital_mute = wm8994_aif_mute,
2272 .set_pll = wm8994_set_fll,
778a76e2 2273 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2274};
2275
2276static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2277 .set_sysclk = wm8994_set_dai_sysclk,
2278 .set_fmt = wm8994_set_dai_fmt,
2279 .hw_params = wm8994_hw_params,
2280 .digital_mute = wm8994_aif_mute,
2281 .set_pll = wm8994_set_fll,
778a76e2
MB		 2282 .set_tristate = wm8994_set_tristate,
2283};
2284
2285static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2286 .hw_params = wm8994_aif3_hw_params,
778a76e2 2287 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2288};
2289
f0fba2ad 2290static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2291 {
f0fba2ad 2292 .name = "wm8994-aif1",
8c7f78b3 2293 .id = 1,
9e6e96a1
MB		 2294 .playback = {
2295 .stream_name = "AIF1 Playback",
2296 .channels_min = 2,
2297 .channels_max = 2,
2298 .rates = WM8994_RATES,
2299 .formats = WM8994_FORMATS,
2300 },
2301 .capture = {
2302 .stream_name = "AIF1 Capture",
2303 .channels_min = 2,
2304 .channels_max = 2,
2305 .rates = WM8994_RATES,
2306 .formats = WM8994_FORMATS,
2307 },
2308 .ops = &wm8994_aif1_dai_ops,
2309 },
2310 {
f0fba2ad 2311 .name = "wm8994-aif2",
8c7f78b3 2312 .id = 2,
9e6e96a1
MB		 2313 .playback = {
2314 .stream_name = "AIF2 Playback",
2315 .channels_min = 2,
2316 .channels_max = 2,
2317 .rates = WM8994_RATES,
2318 .formats = WM8994_FORMATS,
2319 },
2320 .capture = {
2321 .stream_name = "AIF2 Capture",
2322 .channels_min = 2,
2323 .channels_max = 2,
2324 .rates = WM8994_RATES,
2325 .formats = WM8994_FORMATS,
2326 },
2327 .ops = &wm8994_aif2_dai_ops,
2328 },
2329 {
f0fba2ad 2330 .name = "wm8994-aif3",
8c7f78b3 2331 .id = 3,
9e6e96a1
MB		 2332 .playback = {
2333 .stream_name = "AIF3 Playback",
2334 .channels_min = 2,
2335 .channels_max = 2,
2336 .rates = WM8994_RATES,
2337 .formats = WM8994_FORMATS,
2338 },
a8462bde 2339 .capture = {
9e6e96a1
MB		 2340 .stream_name = "AIF3 Capture",
2341 .channels_min = 2,
2342 .channels_max = 2,
2343 .rates = WM8994_RATES,
2344 .formats = WM8994_FORMATS,
2345 },
778a76e2 2346 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2347 }
2348};
9e6e96a1
MB		 2349
2350#ifdef CONFIG_PM
f0fba2ad 2351static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2352{
b2c812e2 2353 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2354 int i, ret;
2355
2356 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2357 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2358 sizeof(struct fll_config));
f0fba2ad 2359 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2360 if (ret < 0)
2361 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2362 i + 1, ret);
2363 }
2364
2365 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2366
2367 return 0;
2368}
2369
f0fba2ad 2370static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2371{
b2c812e2 2372 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2373 u16 *reg_cache = codec->reg_cache;
2374 int i, ret;
2375
2376 /* Restore the registers */
2377 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
2378 switch (i) {
2379 case WM8994_LDO_1:
2380 case WM8994_LDO_2:
2381 case WM8994_SOFTWARE_RESET:
2382 /* Handled by other MFD drivers */
2383 continue;
2384 default:
2385 break;
2386 }
2387
7b306dae 2388 if (!wm8994_access_masks[i].writable)
9e6e96a1
MB		 2389 continue;
2390
2391 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
2392 }
2393
2394 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2395
2396 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2397 if (!wm8994->fll_suspend[i].out)
2398 continue;
2399
f0fba2ad 2400 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2401 wm8994->fll_suspend[i].src,
2402 wm8994->fll_suspend[i].in,
2403 wm8994->fll_suspend[i].out);
2404 if (ret < 0)
2405 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2406 i + 1, ret);
2407 }
2408
2409 return 0;
2410}
2411#else
2412#define wm8994_suspend NULL
2413#define wm8994_resume NULL
2414#endif
2415
2416static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2417{
f0fba2ad 2418 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2419 struct wm8994_pdata *pdata = wm8994->pdata;
2420 struct snd_kcontrol_new controls[] = {
2421 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2422 wm8994->retune_mobile_enum,
2423 wm8994_get_retune_mobile_enum,
2424 wm8994_put_retune_mobile_enum),
2425 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2426 wm8994->retune_mobile_enum,
2427 wm8994_get_retune_mobile_enum,
2428 wm8994_put_retune_mobile_enum),
2429 SOC_ENUM_EXT("AIF2 EQ Mode",
2430 wm8994->retune_mobile_enum,
2431 wm8994_get_retune_mobile_enum,
2432 wm8994_put_retune_mobile_enum),
2433 };
2434 int ret, i, j;
2435 const char **t;
2436
2437 /* We need an array of texts for the enum API but the number
2438 * of texts is likely to be less than the number of
2439 * configurations due to the sample rate dependency of the
2440 * configurations. */
2441 wm8994->num_retune_mobile_texts = 0;
2442 wm8994->retune_mobile_texts = NULL;
2443 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2444 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2445 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2446 wm8994->retune_mobile_texts[j]) == 0)
2447 break;
2448 }
2449
2450 if (j != wm8994->num_retune_mobile_texts)
2451 continue;
2452
2453 /* Expand the array... */
2454 t = krealloc(wm8994->retune_mobile_texts,
2455 sizeof(char *) *
2456 (wm8994->num_retune_mobile_texts + 1),
2457 GFP_KERNEL);
2458 if (t == NULL)
2459 continue;
2460
2461 /* ...store the new entry... */
2462 t[wm8994->num_retune_mobile_texts] =
2463 pdata->retune_mobile_cfgs[i].name;
2464
2465 /* ...and remember the new version. */
2466 wm8994->num_retune_mobile_texts++;
2467 wm8994->retune_mobile_texts = t;
2468 }
2469
2470 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2471 wm8994->num_retune_mobile_texts);
2472
2473 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2474 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2475
f0fba2ad 2476 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2477 ARRAY_SIZE(controls));
2478 if (ret != 0)
f0fba2ad 2479 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2480 "Failed to add ReTune Mobile controls: %d\n", ret);
2481}
2482
2483static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2484{
f0fba2ad 2485 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2486 struct wm8994_pdata *pdata = wm8994->pdata;
2487 int ret, i;
2488
2489 if (!pdata)
2490 return;
2491
2492 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2493 pdata->lineout2_diff,
2494 pdata->lineout1fb,
2495 pdata->lineout2fb,
2496 pdata->jd_scthr,
2497 pdata->jd_thr,
2498 pdata->micbias1_lvl,
2499 pdata->micbias2_lvl);
2500
2501 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2502
2503 if (pdata->num_drc_cfgs) {
2504 struct snd_kcontrol_new controls[] = {
2505 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2506 wm8994_get_drc_enum, wm8994_put_drc_enum),
2507 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2508 wm8994_get_drc_enum, wm8994_put_drc_enum),
2509 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2510 wm8994_get_drc_enum, wm8994_put_drc_enum),
2511 };
2512
2513 /* We need an array of texts for the enum API */
2514 wm8994->drc_texts = kmalloc(sizeof(char *)
2515 * pdata->num_drc_cfgs, GFP_KERNEL);
2516 if (!wm8994->drc_texts) {
f0fba2ad 2517 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2518 "Failed to allocate %d DRC config texts\n",
2519 pdata->num_drc_cfgs);
2520 return;
2521 }
2522
2523 for (i = 0; i < pdata->num_drc_cfgs; i++)
2524 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2525
2526 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2527 wm8994->drc_enum.texts = wm8994->drc_texts;
2528
f0fba2ad 2529 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2530 ARRAY_SIZE(controls));
2531 if (ret != 0)
f0fba2ad 2532 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2533 "Failed to add DRC mode controls: %d\n", ret);
2534
2535 for (i = 0; i < WM8994_NUM_DRC; i++)
2536 wm8994_set_drc(codec, i);
2537 }
2538
2539 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2540 pdata->num_retune_mobile_cfgs);
2541
2542 if (pdata->num_retune_mobile_cfgs)
2543 wm8994_handle_retune_mobile_pdata(wm8994);
2544 else
f0fba2ad 2545 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1
MB		 2546 ARRAY_SIZE(wm8994_eq_controls));
2547}
2548
88766984
MB		 2549/**
2550 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2551 *
2552 * @codec: WM8994 codec
2553 * @jack: jack to report detection events on
2554 * @micbias: microphone bias to detect on
2555 * @det: value to report for presence detection
2556 * @shrt: value to report for short detection
2557 *
2558 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2559 * being used to bring out signals to the processor then only platform
5ab230a7 2560 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2561 * be configured using snd_soc_jack_add_gpios() instead.
2562 *
2563 * Configuration of detection levels is available via the micbias1_lvl
2564 * and micbias2_lvl platform data members.
2565 */
2566int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2567 int micbias, int det, int shrt)
2568{
b2c812e2 2569 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2570 struct wm8994_micdet *micdet;
3a423157 2571 struct wm8994 *control = codec->control_data;
88766984
MB		 2572 int reg;
2573
3a423157
MB		 2574 if (control->type != WM8994)
2575 return -EINVAL;
2576
88766984
MB		 2577 switch (micbias) {
2578 case 1:
2579 micdet = &wm8994->micdet[0];
2580 break;
2581 case 2:
2582 micdet = &wm8994->micdet[1];
2583 break;
2584 default:
2585 return -EINVAL;
2586 }
2587
2588 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2589 micbias, det, shrt);
2590
2591 /* Store the configuration */
2592 micdet->jack = jack;
2593 micdet->det = det;
2594 micdet->shrt = shrt;
2595
2596 /* If either of the jacks is set up then enable detection */
2597 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2598 reg = WM8994_MICD_ENA;
2599 else
2600 reg = 0;
2601
2602 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2603
2604 return 0;
2605}
2606EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2607
2608static irqreturn_t wm8994_mic_irq(int irq, void *data)
2609{
2610 struct wm8994_priv *priv = data;
f0fba2ad 2611 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2612 int reg;
2613 int report;
2614
2615 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2616 if (reg < 0) {
2617 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2618 reg);
2619 return IRQ_HANDLED;
2620 }
2621
2622 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2623
2624 report = 0;
2625 if (reg & WM8994_MIC1_DET_STS)
2626 report |= priv->micdet[0].det;
2627 if (reg & WM8994_MIC1_SHRT_STS)
2628 report |= priv->micdet[0].shrt;
2629 snd_soc_jack_report(priv->micdet[0].jack, report,
2630 priv->micdet[0].det | priv->micdet[0].shrt);
2631
2632 report = 0;
2633 if (reg & WM8994_MIC2_DET_STS)
2634 report |= priv->micdet[1].det;
2635 if (reg & WM8994_MIC2_SHRT_STS)
2636 report |= priv->micdet[1].shrt;
2637 snd_soc_jack_report(priv->micdet[1].jack, report,
2638 priv->micdet[1].det | priv->micdet[1].shrt);
2639
2640 return IRQ_HANDLED;
2641}
2642
821edd2f
MB		 2643/* Default microphone detection handler for WM8958 - the user can
2644 * override this if they wish.
2645 */
2646static void wm8958_default_micdet(u16 status, void *data)
2647{
2648 struct snd_soc_codec *codec = data;
2649 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2650 int report = 0;
2651
2652 /* If nothing present then clear our statuses */
2653 if (!(status & WM8958_MICD_STS)) {
2654 wm8994->jack_is_video = false;
2655 wm8994->jack_is_mic = false;
2656 goto done;
2657 }
2658
2659 /* Assume anything over 475 ohms is a microphone and remember
2660 * that we've seen one (since buttons override it) */
2661 if (status & 0x600)
2662 wm8994->jack_is_mic = true;
2663 if (wm8994->jack_is_mic)
2664 report |= SND_JACK_MICROPHONE;
2665
2666 /* Video has an impedence of approximately 75 ohms; assume
2667 * this isn't used as a button and remember it since buttons
2668 * override it. */
2669 if (status & 0x40)
2670 wm8994->jack_is_video = true;
2671 if (wm8994->jack_is_video)
2672 report |= SND_JACK_VIDEOOUT;
2673
2674 /* Everything else is buttons; just assign slots */
2675 if (status & 0x4)
2676 report |= SND_JACK_BTN_0;
2677 if (status & 0x8)
2678 report |= SND_JACK_BTN_1;
2679 if (status & 0x10)
2680 report |= SND_JACK_BTN_2;
2681 if (status & 0x20)
2682 report |= SND_JACK_BTN_3;
2683 if (status & 0x80)
2684 report |= SND_JACK_BTN_4;
2685 if (status & 0x100)
2686 report |= SND_JACK_BTN_5;
2687
2688done:
2689 snd_soc_jack_report(wm8994->micdet[0].jack,
2690 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
2691 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
2692 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
2693 report);
2694}
2695
2696/**
2697 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2698 *
2699 * @codec: WM8958 codec
2700 * @jack: jack to report detection events on
2701 *
2702 * Enable microphone detection functionality for the WM8958. By
2703 * default simple detection which supports the detection of up to 6
2704 * buttons plus video and microphone functionality is supported.
2705 *
2706 * The WM8958 has an advanced jack detection facility which is able to
2707 * support complex accessory detection, especially when used in
2708 * conjunction with external circuitry. In order to provide maximum
2709 * flexiblity a callback is provided which allows a completely custom
2710 * detection algorithm.
2711 */
2712int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2713 wm8958_micdet_cb cb, void *cb_data)
2714{
2715 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2716 struct wm8994 *control = codec->control_data;
2717
2718 if (control->type != WM8958)
2719 return -EINVAL;
2720
2721 if (jack) {
2722 if (!cb) {
2723 dev_dbg(codec->dev, "Using default micdet callback\n");
2724 cb = wm8958_default_micdet;
2725 cb_data = codec;
2726 }
2727
2728 wm8994->micdet[0].jack = jack;
2729 wm8994->jack_cb = cb;
2730 wm8994->jack_cb_data = cb_data;
2731
2732 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2733 WM8958_MICD_ENA, WM8958_MICD_ENA);
2734 } else {
2735 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2736 WM8958_MICD_ENA, 0);
2737 }
2738
2739 return 0;
2740}
2741EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2742
2743static irqreturn_t wm8958_mic_irq(int irq, void *data)
2744{
2745 struct wm8994_priv *wm8994 = data;
2746 struct snd_soc_codec *codec = wm8994->codec;
2747 int reg;
2748
2749 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2750 if (reg < 0) {
2751 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2752 reg);
2753 return IRQ_NONE;
2754 }
2755
2756 if (!(reg & WM8958_MICD_VALID)) {
2757 dev_dbg(codec->dev, "Mic detect data not valid\n");
2758 goto out;
2759 }
2760
2761 if (wm8994->jack_cb)
2762 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2763 else
2764 dev_warn(codec->dev, "Accessory detection with no callback\n");
2765
2766out:
2767 return IRQ_HANDLED;
2768}
2769
f0fba2ad 2770static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2771{
3a423157 2772 struct wm8994 *control;
9e6e96a1 2773 struct wm8994_priv *wm8994;
ce6120cc 2774 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2775 int ret, i;
9e6e96a1 2776
f0fba2ad 2777 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 2778 control = codec->control_data;
9e6e96a1
MB		 2779
2780 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2781 if (wm8994 == NULL)
9e6e96a1 2782 return -ENOMEM;
b2c812e2 2783 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad 2784
11e713a0
MB		 2785 codec->reg_cache = &wm8994->reg_cache;
2786
f0fba2ad
LG		 2787 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2788 wm8994->codec = codec;
9e6e96a1
MB		 2789
2790 /* Fill the cache with physical values we inherited; don't reset */
2791 ret = wm8994_bulk_read(codec->control_data, 0,
2792 ARRAY_SIZE(wm8994->reg_cache) - 1,
2793 codec->reg_cache);
2794 if (ret < 0) {
2795 dev_err(codec->dev, "Failed to fill register cache: %d\n",
2796 ret);
2797 goto err;
2798 }
2799
2800 /* Clear the cached values for unreadable/volatile registers to
2801 * avoid potential confusion.
2802 */
2803 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
2804 if (wm8994_volatile(i) || !wm8994_readable(i))
2805 wm8994->reg_cache[i] = 0;
2806
2807 /* Set revision-specific configuration */
b6b05691 2808 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 2809 switch (control->type) {
2810 case WM8994:
2811 switch (wm8994->revision) {
2812 case 2:
2813 case 3:
2814 wm8994->hubs.dcs_codes = -5;
2815 wm8994->hubs.hp_startup_mode = 1;
2816 wm8994->hubs.dcs_readback_mode = 1;
2817 break;
2818 default:
2819 wm8994->hubs.dcs_readback_mode = 1;
2820 break;
2821 }
2822
2823 case WM8958:
8437f700 2824 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 2825 break;
3a423157 2826
9e6e96a1
MB		 2827 default:
2828 break;
2829 }
9e6e96a1 2830
3a423157
MB		 2831 switch (control->type) {
2832 case WM8994:
2833 ret = wm8994_request_irq(codec->control_data,
2834 WM8994_IRQ_MIC1_DET,
2835 wm8994_mic_irq, "Mic 1 detect",
2836 wm8994);
2837 if (ret != 0)
2838 dev_warn(codec->dev,
2839 "Failed to request Mic1 detect IRQ: %d\n",
2840 ret);
2841
2842 ret = wm8994_request_irq(codec->control_data,
2843 WM8994_IRQ_MIC1_SHRT,
2844 wm8994_mic_irq, "Mic 1 short",
2845 wm8994);
2846 if (ret != 0)
2847 dev_warn(codec->dev,
2848 "Failed to request Mic1 short IRQ: %d\n",
2849 ret);
2850
2851 ret = wm8994_request_irq(codec->control_data,
2852 WM8994_IRQ_MIC2_DET,
2853 wm8994_mic_irq, "Mic 2 detect",
2854 wm8994);
2855 if (ret != 0)
2856 dev_warn(codec->dev,
2857 "Failed to request Mic2 detect IRQ: %d\n",
2858 ret);
2859
2860 ret = wm8994_request_irq(codec->control_data,
2861 WM8994_IRQ_MIC2_SHRT,
2862 wm8994_mic_irq, "Mic 2 short",
2863 wm8994);
2864 if (ret != 0)
2865 dev_warn(codec->dev,
2866 "Failed to request Mic2 short IRQ: %d\n",
2867 ret);
2868 break;
821edd2f
MB		 2869
2870 case WM8958:
2871 ret = wm8994_request_irq(codec->control_data,
2872 WM8994_IRQ_MIC1_DET,
2873 wm8958_mic_irq, "Mic detect",
2874 wm8994);
2875 if (ret != 0)
2876 dev_warn(codec->dev,
2877 "Failed to request Mic detect IRQ: %d\n",
2878 ret);
2879 break;
3a423157 2880 }
88766984 2881
9e6e96a1
MB		 2882 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
2883 * configured on init - if a system wants to do this dynamically
2884 * at runtime we can deal with that then.
2885 */
2886 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2887 if (ret < 0) {
2888 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 2889 goto err_irq;
9e6e96a1
MB		 2890 }
2891 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2892 wm8994->lrclk_shared[0] = 1;
2893 wm8994_dai[0].symmetric_rates = 1;
2894 } else {
2895 wm8994->lrclk_shared[0] = 0;
2896 }
2897
2898 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2899 if (ret < 0) {
2900 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 2901 goto err_irq;
9e6e96a1
MB		 2902 }
2903 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2904 wm8994->lrclk_shared[1] = 1;
2905 wm8994_dai[1].symmetric_rates = 1;
2906 } else {
2907 wm8994->lrclk_shared[1] = 0;
2908 }
2909
9e6e96a1
MB		 2910 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2911
9e6e96a1
MB		 2912 /* Latch volume updates (right only; we always do left then right). */
2913 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
2914 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
2915 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
2916 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
2917 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
2918 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
2919 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
2920 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
2921 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
2922 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
2923 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
2924 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
2925 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
2926 WM8994_DAC1_VU, WM8994_DAC1_VU);
2927 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
2928 WM8994_DAC2_VU, WM8994_DAC2_VU);
2929
2930 /* Set the low bit of the 3D stereo depth so TLV matches */
2931 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
2932 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
2933 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
2934 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
2935 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
2936 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
2937 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
2938 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
2939 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
2940
d1ce6b20
MB		 2941 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
2942 * behaviour on idle TDM clock cycles. */
2943 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
2944 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
2945
9e6e96a1
MB		 2946 wm8994_update_class_w(codec);
2947
f0fba2ad 2948 wm8994_handle_pdata(wm8994);
9e6e96a1 2949
f0fba2ad
LG		 2950 wm_hubs_add_analogue_controls(codec);
2951 snd_soc_add_controls(codec, wm8994_snd_controls,
2952 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 2953 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 2954 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 2955
2956 switch (control->type) {
2957 case WM8994:
2958 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
2959 ARRAY_SIZE(wm8994_specific_dapm_widgets));
2960 break;
2961 case WM8958:
2962 snd_soc_add_controls(codec, wm8958_snd_controls,
2963 ARRAY_SIZE(wm8958_snd_controls));
2964 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
2965 ARRAY_SIZE(wm8958_dapm_widgets));
2966 break;
2967 }
2968
2969
f0fba2ad 2970 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 2971 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 2972
c4431df0
MB		 2973 switch (control->type) {
2974 case WM8994:
2975 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
2976 ARRAY_SIZE(wm8994_intercon));
2977 break;
2978 case WM8958:
2979 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
2980 ARRAY_SIZE(wm8958_intercon));
2981 break;
2982 }
2983
9e6e96a1
MB		 2984 return 0;
2985
88766984
MB		 2986err_irq:
2987 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
2988 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
2989 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
2990 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
9e6e96a1
MB		 2991err:
2992 kfree(wm8994);
2993 return ret;
2994}
2995
f0fba2ad 2996static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 2997{
f0fba2ad 2998 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 2999 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 3000
3001 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3002
3a423157
MB		 3003 switch (control->type) {
3004 case WM8994:
3005 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3006 wm8994);
3007 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3008 wm8994);
3009 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3010 wm8994);
3011 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3012 wm8994);
3013 break;
821edd2f
MB		 3014
3015 case WM8958:
3016 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3017 wm8994);
3018 break;
3a423157 3019 }
24fb2b11
AL		 3020 kfree(wm8994->retune_mobile_texts);
3021 kfree(wm8994->drc_texts);
9e6e96a1 3022 kfree(wm8994);
9e6e96a1
MB		 3023
3024 return 0;
3025}
3026
f0fba2ad
LG		 3027static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3028 .probe = wm8994_codec_probe,
3029 .remove = wm8994_codec_remove,
3030 .suspend = wm8994_suspend,
3031 .resume = wm8994_resume,
3032 .read = wm8994_read,
3033 .write = wm8994_write,
eba19fdd
MB		 3034 .readable_register = wm8994_readable,
3035 .volatile_register = wm8994_volatile,
f0fba2ad
LG		 3036 .set_bias_level = wm8994_set_bias_level,
3037};
3038
3039static int __devinit wm8994_probe(struct platform_device *pdev)
3040{
3041 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3042 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3043}
3044
3045static int __devexit wm8994_remove(struct platform_device *pdev)
3046{
3047 snd_soc_unregister_codec(&pdev->dev);
3048 return 0;
3049}
3050
9e6e96a1
MB		 3051static struct platform_driver wm8994_codec_driver = {
3052 .driver = {
3053 .name = "wm8994-codec",
3054 .owner = THIS_MODULE,
3055 },
f0fba2ad
LG		 3056 .probe = wm8994_probe,
3057 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3058};
3059
3060static __init int wm8994_init(void)
3061{
3062 return platform_driver_register(&wm8994_codec_driver);
3063}
3064module_init(wm8994_init);
3065
3066static __exit void wm8994_exit(void)
3067{
3068 platform_driver_unregister(&wm8994_codec_driver);
3069}
3070module_exit(wm8994_exit);
3071
3072
3073MODULE_DESCRIPTION("ASoC WM8994 driver");
3074MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3075MODULE_LICENSE("GPL");
3076MODULE_ALIAS("platform:wm8994-codec");
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