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ASoC: Support WM8958 direct microphone detection IRQ
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
9e6e96a1
MB		 41struct fll_config {
42 int src;
43 int in;
44 int out;
45};
46
47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
50static int wm8994_drc_base[] = {
51 WM8994_AIF1_DRC1_1,
52 WM8994_AIF1_DRC2_1,
53 WM8994_AIF2_DRC_1,
54};
55
56static int wm8994_retune_mobile_base[] = {
57 WM8994_AIF1_DAC1_EQ_GAINS_1,
58 WM8994_AIF1_DAC2_EQ_GAINS_1,
59 WM8994_AIF2_EQ_GAINS_1,
60};
61
88766984
MB		 62struct wm8994_micdet {
63 struct snd_soc_jack *jack;
64 int det;
65 int shrt;
66};
67
9e6e96a1
MB		 68/* codec private data */
69struct wm8994_priv {
70 struct wm_hubs_data hubs;
f0fba2ad
LG		 71 enum snd_soc_control_type control_type;
72 void *control_data;
73 struct snd_soc_codec *codec;
9e6e96a1
MB		 74 int sysclk[2];
75 int sysclk_rate[2];
76 int mclk[2];
77 int aifclk[2];
78 struct fll_config fll[2], fll_suspend[2];
79
80 int dac_rates[2];
81 int lrclk_shared[2];
82
d6addcc9
MB		 83 int mbc_ena[3];
84
9e6e96a1
MB		 85 /* Platform dependant DRC configuration */
86 const char **drc_texts;
87 int drc_cfg[WM8994_NUM_DRC];
88 struct soc_enum drc_enum;
89
90 /* Platform dependant ReTune mobile configuration */
91 int num_retune_mobile_texts;
92 const char **retune_mobile_texts;
93 int retune_mobile_cfg[WM8994_NUM_EQ];
94 struct soc_enum retune_mobile_enum;
95
131d8106
MB		 96 /* Platform dependant MBC configuration */
97 int mbc_cfg;
98 const char **mbc_texts;
99 struct soc_enum mbc_enum;
100
88766984
MB		 101 struct wm8994_micdet micdet[2];
102
821edd2f
MB		 103 wm8958_micdet_cb jack_cb;
104 void *jack_cb_data;
105 bool jack_is_mic;
106 bool jack_is_video;
9b7c525d 107 int micdet_irq;
821edd2f 108
b6b05691 109 int revision;
9e6e96a1 110 struct wm8994_pdata *pdata;
173efa09
DP		 111
112 unsigned int aif1clk_enable:1;
113 unsigned int aif2clk_enable:1;
9e6e96a1
MB		 114};
115
d4754ec9 116static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 117{
e88ff1e6
MB		 118 switch (reg) {
119 case WM8994_GPIO_1:
120 case WM8994_GPIO_2:
121 case WM8994_GPIO_3:
122 case WM8994_GPIO_4:
123 case WM8994_GPIO_5:
124 case WM8994_GPIO_6:
125 case WM8994_GPIO_7:
126 case WM8994_GPIO_8:
127 case WM8994_GPIO_9:
128 case WM8994_GPIO_10:
129 case WM8994_GPIO_11:
130 case WM8994_INTERRUPT_STATUS_1:
131 case WM8994_INTERRUPT_STATUS_2:
132 case WM8994_INTERRUPT_RAW_STATUS_2:
133 return 1;
134 default:
135 break;
136 }
137
7b306dae 138 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 139 return 0;
7b306dae 140 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 141}
142
d4754ec9 143static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 144{
ca9aef50 145 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1
MB		 146 return 1;
147
148 switch (reg) {
149 case WM8994_SOFTWARE_RESET:
150 case WM8994_CHIP_REVISION:
151 case WM8994_DC_SERVO_1:
152 case WM8994_DC_SERVO_READBACK:
153 case WM8994_RATE_STATUS:
154 case WM8994_LDO_1:
155 case WM8994_LDO_2:
d6addcc9 156 case WM8958_DSP2_EXECCONTROL:
821edd2f 157 case WM8958_MIC_DETECT_3:
9e6e96a1
MB		 158 return 1;
159 default:
160 return 0;
161 }
162}
163
164static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
165 unsigned int value)
166{
ca9aef50 167 int ret;
9e6e96a1
MB		 168
169 BUG_ON(reg > WM8994_MAX_REGISTER);
170
d4754ec9 171 if (!wm8994_volatile(codec, reg)) {
ca9aef50
MB		 172 ret = snd_soc_cache_write(codec, reg, value);
173 if (ret != 0)
174 dev_err(codec->dev, "Cache write to %x failed: %d\n",
175 reg, ret);
176 }
9e6e96a1
MB		 177
178 return wm8994_reg_write(codec->control_data, reg, value);
179}
180
181static unsigned int wm8994_read(struct snd_soc_codec *codec,
182 unsigned int reg)
183{
ca9aef50
MB		 184 unsigned int val;
185 int ret;
9e6e96a1
MB		 186
187 BUG_ON(reg > WM8994_MAX_REGISTER);
188
d4754ec9 189 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
ca9aef50
MB		 190 reg < codec->driver->reg_cache_size) {
191 ret = snd_soc_cache_read(codec, reg, &val);
192 if (ret >= 0)
193 return val;
194 else
195 dev_err(codec->dev, "Cache read from %x failed: %d\n",
196 reg, ret);
197 }
198
199 return wm8994_reg_read(codec->control_data, reg);
9e6e96a1
MB		 200}
201
202static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
203{
b2c812e2 204 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 205 int rate;
206 int reg1 = 0;
207 int offset;
208
209 if (aif)
210 offset = 4;
211 else
212 offset = 0;
213
214 switch (wm8994->sysclk[aif]) {
215 case WM8994_SYSCLK_MCLK1:
216 rate = wm8994->mclk[0];
217 break;
218
219 case WM8994_SYSCLK_MCLK2:
220 reg1 |= 0x8;
221 rate = wm8994->mclk[1];
222 break;
223
224 case WM8994_SYSCLK_FLL1:
225 reg1 |= 0x10;
226 rate = wm8994->fll[0].out;
227 break;
228
229 case WM8994_SYSCLK_FLL2:
230 reg1 |= 0x18;
231 rate = wm8994->fll[1].out;
232 break;
233
234 default:
235 return -EINVAL;
236 }
237
238 if (rate >= 13500000) {
239 rate /= 2;
240 reg1 |= WM8994_AIF1CLK_DIV;
241
242 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
243 aif + 1, rate);
244 }
5e5e2bef
MB		 245
246 if (rate && rate < 3000000)
247 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
248 aif + 1, rate);
249
9e6e96a1
MB		 250 wm8994->aifclk[aif] = rate;
251
252 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
253 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
254 reg1);
255
256 return 0;
257}
258
259static int configure_clock(struct snd_soc_codec *codec)
260{
b2c812e2 261 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 262 int old, new;
263
264 /* Bring up the AIF clocks first */
265 configure_aif_clock(codec, 0);
266 configure_aif_clock(codec, 1);
267
268 /* Then switch CLK_SYS over to the higher of them; a change
269 * can only happen as a result of a clocking change which can
270 * only be made outside of DAPM so we can safely redo the
271 * clocking.
272 */
273
274 /* If they're equal it doesn't matter which is used */
275 if (wm8994->aifclk[0] == wm8994->aifclk[1])
276 return 0;
277
278 if (wm8994->aifclk[0] < wm8994->aifclk[1])
279 new = WM8994_SYSCLK_SRC;
280 else
281 new = 0;
282
283 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
284
285 /* If there's no change then we're done. */
286 if (old == new)
287 return 0;
288
289 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
290
ce6120cc 291 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 292
293 return 0;
294}
295
296static int check_clk_sys(struct snd_soc_dapm_widget *source,
297 struct snd_soc_dapm_widget *sink)
298{
299 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
300 const char *clk;
301
302 /* Check what we're currently using for CLK_SYS */
303 if (reg & WM8994_SYSCLK_SRC)
304 clk = "AIF2CLK";
305 else
306 clk = "AIF1CLK";
307
308 return strcmp(source->name, clk) == 0;
309}
310
311static const char *sidetone_hpf_text[] = {
312 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
313};
314
315static const struct soc_enum sidetone_hpf =
316 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
317
146fd574
UK		 318static const char *adc_hpf_text[] = {
319 "HiFi", "Voice 1", "Voice 2", "Voice 3"
320};
321
322static const struct soc_enum aif1adc1_hpf =
323 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
324
325static const struct soc_enum aif1adc2_hpf =
326 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
327
328static const struct soc_enum aif2adc_hpf =
329 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
330
9e6e96a1
MB		 331static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
332static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
333static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
334static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
335static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
336
337#define WM8994_DRC_SWITCH(xname, reg, shift) \
338{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
339 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
340 .put = wm8994_put_drc_sw, \
341 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
342
343static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
344 struct snd_ctl_elem_value *ucontrol)
345{
346 struct soc_mixer_control *mc =
347 (struct soc_mixer_control *)kcontrol->private_value;
348 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
349 int mask, ret;
350
351 /* Can't enable both ADC and DAC paths simultaneously */
352 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
353 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
354 WM8994_AIF1ADC1R_DRC_ENA_MASK;
355 else
356 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
357
358 ret = snd_soc_read(codec, mc->reg);
359 if (ret < 0)
360 return ret;
361 if (ret & mask)
362 return -EINVAL;
363
364 return snd_soc_put_volsw(kcontrol, ucontrol);
365}
366
9e6e96a1
MB		 367static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
368{
b2c812e2 369 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 370 struct wm8994_pdata *pdata = wm8994->pdata;
371 int base = wm8994_drc_base[drc];
372 int cfg = wm8994->drc_cfg[drc];
373 int save, i;
374
375 /* Save any enables; the configuration should clear them. */
376 save = snd_soc_read(codec, base);
377 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
378 WM8994_AIF1ADC1R_DRC_ENA;
379
380 for (i = 0; i < WM8994_DRC_REGS; i++)
381 snd_soc_update_bits(codec, base + i, 0xffff,
382 pdata->drc_cfgs[cfg].regs[i]);
383
384 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
385 WM8994_AIF1ADC1L_DRC_ENA |
386 WM8994_AIF1ADC1R_DRC_ENA, save);
387}
388
389/* Icky as hell but saves code duplication */
390static int wm8994_get_drc(const char *name)
391{
392 if (strcmp(name, "AIF1DRC1 Mode") == 0)
393 return 0;
394 if (strcmp(name, "AIF1DRC2 Mode") == 0)
395 return 1;
396 if (strcmp(name, "AIF2DRC Mode") == 0)
397 return 2;
398 return -EINVAL;
399}
400
401static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
402 struct snd_ctl_elem_value *ucontrol)
403{
404 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 405 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 406 struct wm8994_pdata *pdata = wm8994->pdata;
407 int drc = wm8994_get_drc(kcontrol->id.name);
408 int value = ucontrol->value.integer.value[0];
409
410 if (drc < 0)
411 return drc;
412
413 if (value >= pdata->num_drc_cfgs)
414 return -EINVAL;
415
416 wm8994->drc_cfg[drc] = value;
417
418 wm8994_set_drc(codec, drc);
419
420 return 0;
421}
422
423static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
424 struct snd_ctl_elem_value *ucontrol)
425{
426 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 427 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 428 int drc = wm8994_get_drc(kcontrol->id.name);
429
430 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
431
432 return 0;
433}
434
435static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
436{
b2c812e2 437 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 438 struct wm8994_pdata *pdata = wm8994->pdata;
439 int base = wm8994_retune_mobile_base[block];
440 int iface, best, best_val, save, i, cfg;
441
442 if (!pdata || !wm8994->num_retune_mobile_texts)
443 return;
444
445 switch (block) {
446 case 0:
447 case 1:
448 iface = 0;
449 break;
450 case 2:
451 iface = 1;
452 break;
453 default:
454 return;
455 }
456
457 /* Find the version of the currently selected configuration
458 * with the nearest sample rate. */
459 cfg = wm8994->retune_mobile_cfg[block];
460 best = 0;
461 best_val = INT_MAX;
462 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
463 if (strcmp(pdata->retune_mobile_cfgs[i].name,
464 wm8994->retune_mobile_texts[cfg]) == 0 &&
465 abs(pdata->retune_mobile_cfgs[i].rate
466 - wm8994->dac_rates[iface]) < best_val) {
467 best = i;
468 best_val = abs(pdata->retune_mobile_cfgs[i].rate
469 - wm8994->dac_rates[iface]);
470 }
471 }
472
473 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
474 block,
475 pdata->retune_mobile_cfgs[best].name,
476 pdata->retune_mobile_cfgs[best].rate,
477 wm8994->dac_rates[iface]);
478
479 /* The EQ will be disabled while reconfiguring it, remember the
480 * current configuration.
481 */
482 save = snd_soc_read(codec, base);
483 save &= WM8994_AIF1DAC1_EQ_ENA;
484
485 for (i = 0; i < WM8994_EQ_REGS; i++)
486 snd_soc_update_bits(codec, base + i, 0xffff,
487 pdata->retune_mobile_cfgs[best].regs[i]);
488
489 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
490}
491
492/* Icky as hell but saves code duplication */
493static int wm8994_get_retune_mobile_block(const char *name)
494{
495 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
496 return 0;
497 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
498 return 1;
499 if (strcmp(name, "AIF2 EQ Mode") == 0)
500 return 2;
501 return -EINVAL;
502}
503
504static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506{
507 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 508 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 509 struct wm8994_pdata *pdata = wm8994->pdata;
510 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
511 int value = ucontrol->value.integer.value[0];
512
513 if (block < 0)
514 return block;
515
516 if (value >= pdata->num_retune_mobile_cfgs)
517 return -EINVAL;
518
519 wm8994->retune_mobile_cfg[block] = value;
520
521 wm8994_set_retune_mobile(codec, block);
522
523 return 0;
524}
525
526static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
527 struct snd_ctl_elem_value *ucontrol)
528{
529 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 530 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 531 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
532
533 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
534
535 return 0;
536}
537
96b101ef 538static const char *aif_chan_src_text[] = {
f554885f
MB		 539 "Left", "Right"
540};
541
96b101ef
MB		 542static const struct soc_enum aif1adcl_src =
543 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
544
545static const struct soc_enum aif1adcr_src =
546 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
547
548static const struct soc_enum aif2adcl_src =
549 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
550
551static const struct soc_enum aif2adcr_src =
552 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
553
f554885f 554static const struct soc_enum aif1dacl_src =
96b101ef 555 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 556
557static const struct soc_enum aif1dacr_src =
96b101ef 558 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 559
560static const struct soc_enum aif2dacl_src =
96b101ef 561 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 562
563static const struct soc_enum aif2dacr_src =
96b101ef 564 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 565
154b26aa
MB		 566static const char *osr_text[] = {
567 "Low Power", "High Performance",
568};
569
570static const struct soc_enum dac_osr =
571 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
572
573static const struct soc_enum adc_osr =
574 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
575
d6addcc9
MB		 576static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
577{
578 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
131d8106 579 struct wm8994_pdata *pdata = wm8994->pdata;
d6addcc9 580 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
131d8106 581 int ena, reg, aif, i;
d6addcc9
MB		 582
583 switch (mbc) {
584 case 0:
585 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
586 aif = 0;
587 break;
588 case 1:
589 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
590 aif = 0;
591 break;
592 case 2:
593 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
594 aif = 1;
595 break;
596 default:
597 BUG();
598 return;
599 }
600
601 /* We can only enable the MBC if the AIF is enabled and we
602 * want it to be enabled. */
603 ena = pwr_reg && wm8994->mbc_ena[mbc];
604
605 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
606
607 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
608 mbc, start, pwr_reg, reg);
609
610 if (start && ena) {
611 /* If the DSP is already running then noop */
612 if (reg & WM8958_DSP2_ENA)
613 return;
614
615 /* Switch the clock over to the appropriate AIF */
616 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
617 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
618 aif << WM8958_DSP2CLK_SRC_SHIFT |
619 WM8958_DSP2CLK_ENA);
620
621 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
622 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
623
131d8106
MB		 624 /* If we've got user supplied MBC settings use them */
625 if (pdata && pdata->num_mbc_cfgs) {
626 struct wm8958_mbc_cfg *cfg
627 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
628
629 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
630 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
631 cfg->coeff_regs[i]);
632
633 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
634 snd_soc_write(codec,
635 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
636 cfg->cutoff_regs[i]);
637 }
d6addcc9
MB		 638
639 /* Run the DSP */
640 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
641 WM8958_DSP2_RUNR);
642
643 /* And we're off! */
644 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
645 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
646 mbc << WM8958_MBC_SEL_SHIFT |
647 WM8958_MBC_ENA);
648 } else {
649 /* If the DSP is already stopped then noop */
650 if (!(reg & WM8958_DSP2_ENA))
651 return;
652
653 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
654 WM8958_MBC_ENA, 0);
655 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
656 WM8958_DSP2_ENA, 0);
657 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
658 WM8958_DSP2CLK_ENA, 0);
659 }
660}
661
662static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
663 struct snd_kcontrol *kcontrol, int event)
664{
665 struct snd_soc_codec *codec = w->codec;
666 int mbc;
667
668 switch (w->shift) {
669 case 13:
670 case 12:
671 mbc = 2;
672 break;
673 case 11:
674 case 10:
675 mbc = 1;
676 break;
677 case 9:
678 case 8:
679 mbc = 0;
680 break;
681 default:
682 BUG();
683 return -EINVAL;
684 }
685
686 switch (event) {
687 case SND_SOC_DAPM_POST_PMU:
688 wm8958_mbc_apply(codec, mbc, 1);
689 break;
690 case SND_SOC_DAPM_POST_PMD:
691 wm8958_mbc_apply(codec, mbc, 0);
692 break;
693 }
694
695 return 0;
696}
697
131d8106
MB		 698static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_value *ucontrol)
700{
701 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
702 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
703 struct wm8994_pdata *pdata = wm8994->pdata;
704 int value = ucontrol->value.integer.value[0];
705 int reg;
706
707 /* Don't allow on the fly reconfiguration */
708 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
709 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
710 return -EBUSY;
711
712 if (value >= pdata->num_mbc_cfgs)
713 return -EINVAL;
714
715 wm8994->mbc_cfg = value;
716
717 return 0;
718}
719
720static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
721 struct snd_ctl_elem_value *ucontrol)
722{
723 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
724 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
725
726 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
727
728 return 0;
729}
730
d6addcc9
MB		 731static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
732 struct snd_ctl_elem_info *uinfo)
733{
734 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
735 uinfo->count = 1;
736 uinfo->value.integer.min = 0;
737 uinfo->value.integer.max = 1;
738 return 0;
739}
740
741static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
742 struct snd_ctl_elem_value *ucontrol)
743{
744 int mbc = kcontrol->private_value;
745 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
746 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
747
748 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
749
750 return 0;
751}
752
753static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
754 struct snd_ctl_elem_value *ucontrol)
755{
756 int mbc = kcontrol->private_value;
757 int i;
758 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
759 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
760
761 if (ucontrol->value.integer.value[0] > 1)
762 return -EINVAL;
763
764 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
765 if (mbc != i && wm8994->mbc_ena[i]) {
766 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
767 return -EBUSY;
768 }
769 }
770
771 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
772
773 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
774
775 return 0;
776}
777
778#define WM8958_MBC_SWITCH(xname, xval) {\
779 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
780 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
781 .info = wm8958_mbc_info, \
782 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
783 .private_value = xval }
784
9e6e96a1
MB		 785static const struct snd_kcontrol_new wm8994_snd_controls[] = {
786SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
787 WM8994_AIF1_ADC1_RIGHT_VOLUME,
788 1, 119, 0, digital_tlv),
789SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
790 WM8994_AIF1_ADC2_RIGHT_VOLUME,
791 1, 119, 0, digital_tlv),
792SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
793 WM8994_AIF2_ADC_RIGHT_VOLUME,
794 1, 119, 0, digital_tlv),
795
96b101ef
MB		 796SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
797SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 798SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
799SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 800
f554885f
MB		 801SOC_ENUM("AIF1DACL Source", aif1dacl_src),
802SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 803SOC_ENUM("AIF2DACL Source", aif2dacl_src),
804SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 805
9e6e96a1
MB		 806SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
807 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
808SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
809 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
810SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
811 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
812
813SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
814SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
815
816SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
817SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
818SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
819
820WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
821WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
822WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
823
824WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
825WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
826WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
827
828WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
829WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
830WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
831
832SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
833 5, 12, 0, st_tlv),
834SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
835 0, 12, 0, st_tlv),
836SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
837 5, 12, 0, st_tlv),
838SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
839 0, 12, 0, st_tlv),
840SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
841SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
842
146fd574
UK		 843SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
844SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
845
846SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
847SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
848
849SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
850SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
851
154b26aa
MB		 852SOC_ENUM("ADC OSR", adc_osr),
853SOC_ENUM("DAC OSR", dac_osr),
854
9e6e96a1
MB		 855SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
856 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
857SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
858 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
859
860SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
861 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
862SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
863 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
864
865SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
866 6, 1, 1, wm_hubs_spkmix_tlv),
867SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
868 2, 1, 1, wm_hubs_spkmix_tlv),
869
870SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
871 6, 1, 1, wm_hubs_spkmix_tlv),
872SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
873 2, 1, 1, wm_hubs_spkmix_tlv),
874
875SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
876 10, 15, 0, wm8994_3d_tlv),
458350b3 877SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 878 8, 1, 0),
879SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
880 10, 15, 0, wm8994_3d_tlv),
881SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
882 8, 1, 0),
458350b3 883SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 884 10, 15, 0, wm8994_3d_tlv),
458350b3 885SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 886 8, 1, 0),
887};
888
889static const struct snd_kcontrol_new wm8994_eq_controls[] = {
890SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
891 eq_tlv),
892SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
893 eq_tlv),
894SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
895 eq_tlv),
896SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
897 eq_tlv),
898SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
899 eq_tlv),
900
901SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
902 eq_tlv),
903SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
904 eq_tlv),
905SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
906 eq_tlv),
907SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
908 eq_tlv),
909SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
910 eq_tlv),
911
912SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
913 eq_tlv),
914SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
915 eq_tlv),
916SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
917 eq_tlv),
918SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
919 eq_tlv),
920SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
921 eq_tlv),
922};
923
c4431df0
MB		 924static const struct snd_kcontrol_new wm8958_snd_controls[] = {
925SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
d6addcc9
MB		 926WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
927WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
928WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
c4431df0
MB		 929};
930
9e6e96a1
MB		 931static int clk_sys_event(struct snd_soc_dapm_widget *w,
932 struct snd_kcontrol *kcontrol, int event)
933{
934 struct snd_soc_codec *codec = w->codec;
935
936 switch (event) {
937 case SND_SOC_DAPM_PRE_PMU:
938 return configure_clock(codec);
939
940 case SND_SOC_DAPM_POST_PMD:
941 configure_clock(codec);
942 break;
943 }
944
945 return 0;
946}
947
948static void wm8994_update_class_w(struct snd_soc_codec *codec)
949{
fec6dd83 950 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 951 int enable = 1;
952 int source = 0; /* GCC flow analysis can't track enable */
953 int reg, reg_r;
954
955 /* Only support direct DAC->headphone paths */
956 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
957 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 958 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 959 enable = 0;
960 }
961
962 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
963 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 964 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 965 enable = 0;
966 }
967
968 /* We also need the same setting for L/R and only one path */
969 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
970 switch (reg) {
971 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 972 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 973 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
974 break;
975 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 976 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 977 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
978 break;
979 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 980 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 981 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
982 break;
983 default:
ee839a21 984 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 985 enable = 0;
986 break;
987 }
988
989 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
990 if (reg_r != reg) {
ee839a21 991 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 992 enable = 0;
993 }
994
995 if (enable) {
996 dev_dbg(codec->dev, "Class W enabled\n");
997 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
998 WM8994_CP_DYN_PWR |
999 WM8994_CP_DYN_SRC_SEL_MASK,
1000 source | WM8994_CP_DYN_PWR);
fec6dd83 1001 wm8994->hubs.class_w = true;
9e6e96a1
MB		 1002
1003 } else {
1004 dev_dbg(codec->dev, "Class W disabled\n");
1005 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1006 WM8994_CP_DYN_PWR, 0);
fec6dd83 1007 wm8994->hubs.class_w = false;
9e6e96a1
MB		 1008 }
1009}
1010
173efa09
DP		 1011static int late_enable_ev(struct snd_soc_dapm_widget *w,
1012 struct snd_kcontrol *kcontrol, int event)
1013{
1014 struct snd_soc_codec *codec = w->codec;
1015 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1016
1017 switch (event) {
1018 case SND_SOC_DAPM_PRE_PMU:
1019 if (wm8994->aif1clk_enable)
1020 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1021 WM8994_AIF1CLK_ENA_MASK,
1022 WM8994_AIF1CLK_ENA);
1023 if (wm8994->aif2clk_enable)
1024 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1025 WM8994_AIF2CLK_ENA_MASK,
1026 WM8994_AIF2CLK_ENA);
1027 break;
1028 }
1029
1030 return 0;
1031}
1032
1033static int late_disable_ev(struct snd_soc_dapm_widget *w,
1034 struct snd_kcontrol *kcontrol, int event)
1035{
1036 struct snd_soc_codec *codec = w->codec;
1037 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1038
1039 switch (event) {
1040 case SND_SOC_DAPM_POST_PMD:
1041 if (wm8994->aif1clk_enable) {
1042 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1043 WM8994_AIF1CLK_ENA_MASK, 0);
1044 wm8994->aif1clk_enable = 0;
1045 }
1046 if (wm8994->aif2clk_enable) {
1047 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1048 WM8994_AIF2CLK_ENA_MASK, 0);
1049 wm8994->aif2clk_enable = 0;
1050 }
1051 break;
1052 }
1053
1054 return 0;
1055}
1056
1057static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1058 struct snd_kcontrol *kcontrol, int event)
1059{
1060 struct snd_soc_codec *codec = w->codec;
1061 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1062
1063 switch (event) {
1064 case SND_SOC_DAPM_PRE_PMU:
1065 wm8994->aif1clk_enable = 1;
1066 break;
1067 }
1068
1069 return 0;
1070}
1071
1072static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1073 struct snd_kcontrol *kcontrol, int event)
1074{
1075 struct snd_soc_codec *codec = w->codec;
1076 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1077
1078 switch (event) {
1079 case SND_SOC_DAPM_PRE_PMU:
1080 wm8994->aif2clk_enable = 1;
1081 break;
1082 }
1083
1084 return 0;
1085}
1086
c52fd021
DP		 1087static int dac_ev(struct snd_soc_dapm_widget *w,
1088 struct snd_kcontrol *kcontrol, int event)
1089{
1090 struct snd_soc_codec *codec = w->codec;
1091 unsigned int mask = 1 << w->shift;
1092
1093 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1094 mask, mask);
1095 return 0;
1096}
1097
9e6e96a1
MB		 1098static const char *hp_mux_text[] = {
1099 "Mixer",
1100 "DAC",
1101};
1102
1103#define WM8994_HP_ENUM(xname, xenum) \
1104{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1105 .info = snd_soc_info_enum_double, \
1106 .get = snd_soc_dapm_get_enum_double, \
1107 .put = wm8994_put_hp_enum, \
1108 .private_value = (unsigned long)&xenum }
1109
1110static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1111 struct snd_ctl_elem_value *ucontrol)
1112{
1113 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1114 struct snd_soc_codec *codec = w->codec;
1115 int ret;
1116
1117 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1118
1119 wm8994_update_class_w(codec);
1120
1121 return ret;
1122}
1123
1124static const struct soc_enum hpl_enum =
1125 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1126
1127static const struct snd_kcontrol_new hpl_mux =
1128 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1129
1130static const struct soc_enum hpr_enum =
1131 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1132
1133static const struct snd_kcontrol_new hpr_mux =
1134 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1135
1136static const char *adc_mux_text[] = {
1137 "ADC",
1138 "DMIC",
1139};
1140
1141static const struct soc_enum adc_enum =
1142 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1143
1144static const struct snd_kcontrol_new adcl_mux =
1145 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1146
1147static const struct snd_kcontrol_new adcr_mux =
1148 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1149
1150static const struct snd_kcontrol_new left_speaker_mixer[] = {
1151SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1152SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1153SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1154SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1155SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1156};
1157
1158static const struct snd_kcontrol_new right_speaker_mixer[] = {
1159SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1160SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1161SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1162SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1163SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1164};
1165
1166/* Debugging; dump chip status after DAPM transitions */
1167static int post_ev(struct snd_soc_dapm_widget *w,
1168 struct snd_kcontrol *kcontrol, int event)
1169{
1170 struct snd_soc_codec *codec = w->codec;
1171 dev_dbg(codec->dev, "SRC status: %x\n",
1172 snd_soc_read(codec,
1173 WM8994_RATE_STATUS));
1174 return 0;
1175}
1176
1177static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1178SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1179 1, 1, 0),
1180SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1181 0, 1, 0),
1182};
1183
1184static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1185SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1186 1, 1, 0),
1187SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1188 0, 1, 0),
1189};
1190
a3257ba8
MB		 1191static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1192SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1193 1, 1, 0),
1194SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1195 0, 1, 0),
1196};
1197
1198static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1199SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1200 1, 1, 0),
1201SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1202 0, 1, 0),
1203};
1204
9e6e96a1
MB		 1205static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1206SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1207 5, 1, 0),
1208SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1209 4, 1, 0),
1210SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1211 2, 1, 0),
1212SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1213 1, 1, 0),
1214SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1215 0, 1, 0),
1216};
1217
1218static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1219SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1220 5, 1, 0),
1221SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1222 4, 1, 0),
1223SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1224 2, 1, 0),
1225SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1226 1, 1, 0),
1227SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1228 0, 1, 0),
1229};
1230
1231#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1232{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1233 .info = snd_soc_info_volsw, \
1234 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1235 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1236
1237static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1238 struct snd_ctl_elem_value *ucontrol)
1239{
1240 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1241 struct snd_soc_codec *codec = w->codec;
1242 int ret;
1243
1244 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1245
1246 wm8994_update_class_w(codec);
1247
1248 return ret;
1249}
1250
1251static const struct snd_kcontrol_new dac1l_mix[] = {
1252WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1253 5, 1, 0),
1254WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1255 4, 1, 0),
1256WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1257 2, 1, 0),
1258WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1259 1, 1, 0),
1260WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1261 0, 1, 0),
1262};
1263
1264static const struct snd_kcontrol_new dac1r_mix[] = {
1265WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1266 5, 1, 0),
1267WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1268 4, 1, 0),
1269WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1270 2, 1, 0),
1271WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1272 1, 1, 0),
1273WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1274 0, 1, 0),
1275};
1276
1277static const char *sidetone_text[] = {
1278 "ADC/DMIC1", "DMIC2",
1279};
1280
1281static const struct soc_enum sidetone1_enum =
1282 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1283
1284static const struct snd_kcontrol_new sidetone1_mux =
1285 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1286
1287static const struct soc_enum sidetone2_enum =
1288 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1289
1290static const struct snd_kcontrol_new sidetone2_mux =
1291 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1292
1293static const char *aif1dac_text[] = {
1294 "AIF1DACDAT", "AIF3DACDAT",
1295};
1296
1297static const struct soc_enum aif1dac_enum =
1298 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1299
1300static const struct snd_kcontrol_new aif1dac_mux =
1301 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1302
1303static const char *aif2dac_text[] = {
1304 "AIF2DACDAT", "AIF3DACDAT",
1305};
1306
1307static const struct soc_enum aif2dac_enum =
1308 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1309
1310static const struct snd_kcontrol_new aif2dac_mux =
1311 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1312
1313static const char *aif2adc_text[] = {
1314 "AIF2ADCDAT", "AIF3DACDAT",
1315};
1316
1317static const struct soc_enum aif2adc_enum =
1318 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1319
1320static const struct snd_kcontrol_new aif2adc_mux =
1321 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1322
1323static const char *aif3adc_text[] = {
c4431df0 1324 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1325};
1326
c4431df0 1327static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1328 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1329
c4431df0
MB		 1330static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1331 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1332
1333static const struct soc_enum wm8958_aif3adc_enum =
1334 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1335
1336static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1337 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1338
1339static const char *mono_pcm_out_text[] = {
1340 "None", "AIF2ADCL", "AIF2ADCR",
1341};
1342
1343static const struct soc_enum mono_pcm_out_enum =
1344 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1345
1346static const struct snd_kcontrol_new mono_pcm_out_mux =
1347 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1348
1349static const char *aif2dac_src_text[] = {
1350 "AIF2", "AIF3",
1351};
1352
1353/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1354static const struct soc_enum aif2dacl_src_enum =
1355 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1356
1357static const struct snd_kcontrol_new aif2dacl_src_mux =
1358 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1359
1360static const struct soc_enum aif2dacr_src_enum =
1361 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1362
1363static const struct snd_kcontrol_new aif2dacr_src_mux =
1364 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1365
173efa09
DP		 1366static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1367SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1368 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1369SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1370 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1371
1372SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1373 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1374SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1375 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1376SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1377 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1378SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1379 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1380
1381SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1382};
1383
1384static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1385SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1386SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1387};
1388
c52fd021
DP		 1389static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1390SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1391 dac_ev, SND_SOC_DAPM_PRE_PMU),
1392SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1393 dac_ev, SND_SOC_DAPM_PRE_PMU),
1394SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1395 dac_ev, SND_SOC_DAPM_PRE_PMU),
1396SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1397 dac_ev, SND_SOC_DAPM_PRE_PMU),
1398};
1399
1400static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1401SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1402SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1403SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1404SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1405};
1406
9e6e96a1
MB		 1407static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1408SND_SOC_DAPM_INPUT("DMIC1DAT"),
1409SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1410SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1
MB		 1411
1412SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1413 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1414
1415SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1416SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1417SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1418
7f94de48 1419SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1420 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1421SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1422 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1423SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1424 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1425 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1426SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1427 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1428 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1429
7f94de48 1430SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1431 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1432SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1433 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1434SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1435 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1436 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1437SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1438 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1439 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1440
1441SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1442 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1443SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1444 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1445
a3257ba8
MB		 1446SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1447 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1448SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1449 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1450
9e6e96a1
MB		 1451SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1452 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1453SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1454 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1455
1456SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1457SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1458
1459SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1460 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1461SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1462 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1463
1464SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1465 WM8994_POWER_MANAGEMENT_4, 13, 0),
1466SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1467 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1468SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1469 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1470 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1471SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1472 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1473 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1474
1475SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1476SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1477SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1478SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1479
1480SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1481SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1482SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1483
1484SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1485SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1486
1487SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1488
1489SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1490SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1491SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1492SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1493
1494/* Power is done with the muxes since the ADC power also controls the
1495 * downsampling chain, the chip will automatically manage the analogue
1496 * specific portions.
1497 */
1498SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1499SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1500
1501SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1502SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1503
9e6e96a1
MB		 1504SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1505SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1506
1507SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1508 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1509SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1510 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1511
1512SND_SOC_DAPM_POST("Debug log", post_ev),
1513};
1514
c4431df0
MB		 1515static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1516SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1517};
9e6e96a1 1518
c4431df0
MB		 1519static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1520SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1521SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1522SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1523SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1524};
1525
1526static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1527 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1528 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1529
1530 { "DSP1CLK", NULL, "CLK_SYS" },
1531 { "DSP2CLK", NULL, "CLK_SYS" },
1532 { "DSPINTCLK", NULL, "CLK_SYS" },
1533
1534 { "AIF1ADC1L", NULL, "AIF1CLK" },
1535 { "AIF1ADC1L", NULL, "DSP1CLK" },
1536 { "AIF1ADC1R", NULL, "AIF1CLK" },
1537 { "AIF1ADC1R", NULL, "DSP1CLK" },
1538 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1539
1540 { "AIF1DAC1L", NULL, "AIF1CLK" },
1541 { "AIF1DAC1L", NULL, "DSP1CLK" },
1542 { "AIF1DAC1R", NULL, "AIF1CLK" },
1543 { "AIF1DAC1R", NULL, "DSP1CLK" },
1544 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1545
1546 { "AIF1ADC2L", NULL, "AIF1CLK" },
1547 { "AIF1ADC2L", NULL, "DSP1CLK" },
1548 { "AIF1ADC2R", NULL, "AIF1CLK" },
1549 { "AIF1ADC2R", NULL, "DSP1CLK" },
1550 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1551
1552 { "AIF1DAC2L", NULL, "AIF1CLK" },
1553 { "AIF1DAC2L", NULL, "DSP1CLK" },
1554 { "AIF1DAC2R", NULL, "AIF1CLK" },
1555 { "AIF1DAC2R", NULL, "DSP1CLK" },
1556 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1557
1558 { "AIF2ADCL", NULL, "AIF2CLK" },
1559 { "AIF2ADCL", NULL, "DSP2CLK" },
1560 { "AIF2ADCR", NULL, "AIF2CLK" },
1561 { "AIF2ADCR", NULL, "DSP2CLK" },
1562 { "AIF2ADCR", NULL, "DSPINTCLK" },
1563
1564 { "AIF2DACL", NULL, "AIF2CLK" },
1565 { "AIF2DACL", NULL, "DSP2CLK" },
1566 { "AIF2DACR", NULL, "AIF2CLK" },
1567 { "AIF2DACR", NULL, "DSP2CLK" },
1568 { "AIF2DACR", NULL, "DSPINTCLK" },
1569
1570 { "DMIC1L", NULL, "DMIC1DAT" },
1571 { "DMIC1L", NULL, "CLK_SYS" },
1572 { "DMIC1R", NULL, "DMIC1DAT" },
1573 { "DMIC1R", NULL, "CLK_SYS" },
1574 { "DMIC2L", NULL, "DMIC2DAT" },
1575 { "DMIC2L", NULL, "CLK_SYS" },
1576 { "DMIC2R", NULL, "DMIC2DAT" },
1577 { "DMIC2R", NULL, "CLK_SYS" },
1578
1579 { "ADCL", NULL, "AIF1CLK" },
1580 { "ADCL", NULL, "DSP1CLK" },
1581 { "ADCL", NULL, "DSPINTCLK" },
1582
1583 { "ADCR", NULL, "AIF1CLK" },
1584 { "ADCR", NULL, "DSP1CLK" },
1585 { "ADCR", NULL, "DSPINTCLK" },
1586
1587 { "ADCL Mux", "ADC", "ADCL" },
1588 { "ADCL Mux", "DMIC", "DMIC1L" },
1589 { "ADCR Mux", "ADC", "ADCR" },
1590 { "ADCR Mux", "DMIC", "DMIC1R" },
1591
1592 { "DAC1L", NULL, "AIF1CLK" },
1593 { "DAC1L", NULL, "DSP1CLK" },
1594 { "DAC1L", NULL, "DSPINTCLK" },
1595
1596 { "DAC1R", NULL, "AIF1CLK" },
1597 { "DAC1R", NULL, "DSP1CLK" },
1598 { "DAC1R", NULL, "DSPINTCLK" },
1599
1600 { "DAC2L", NULL, "AIF2CLK" },
1601 { "DAC2L", NULL, "DSP2CLK" },
1602 { "DAC2L", NULL, "DSPINTCLK" },
1603
1604 { "DAC2R", NULL, "AIF2DACR" },
1605 { "DAC2R", NULL, "AIF2CLK" },
1606 { "DAC2R", NULL, "DSP2CLK" },
1607 { "DAC2R", NULL, "DSPINTCLK" },
1608
1609 { "TOCLK", NULL, "CLK_SYS" },
1610
1611 /* AIF1 outputs */
1612 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1613 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1614 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1615
1616 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1617 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1618 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1619
a3257ba8
MB		 1620 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1621 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1622 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1623
1624 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1625 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1626 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1627
9e6e96a1
MB		 1628 /* Pin level routing for AIF3 */
1629 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1630 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1631 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1632 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1633
9e6e96a1
MB		 1634 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1635 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1636 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1637 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1638 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1639 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1640 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1641
1642 /* DAC1 inputs */
9e6e96a1
MB		 1643 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1644 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1645 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1646 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1647 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1648
9e6e96a1
MB		 1649 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1650 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1651 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1652 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1653 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1654
1655 /* DAC2/AIF2 outputs */
1656 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1657 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1658 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1659 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1660 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1661 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1662
1663 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1664 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1665 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1666 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1667 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1668 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1669
7f94de48
MB		 1670 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1671 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1672 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1673 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1674
9e6e96a1
MB		 1675 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1676
1677 /* AIF3 output */
1678 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1679 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1680 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1681 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1682 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1683 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1684 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1685 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1686
1687 /* Sidetone */
1688 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1689 { "Left Sidetone", "DMIC2", "DMIC2L" },
1690 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1691 { "Right Sidetone", "DMIC2", "DMIC2R" },
1692
1693 /* Output stages */
1694 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1695 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1696
1697 { "SPKL", "DAC1 Switch", "DAC1L" },
1698 { "SPKL", "DAC2 Switch", "DAC2L" },
1699
1700 { "SPKR", "DAC1 Switch", "DAC1R" },
1701 { "SPKR", "DAC2 Switch", "DAC2R" },
1702
1703 { "Left Headphone Mux", "DAC", "DAC1L" },
1704 { "Right Headphone Mux", "DAC", "DAC1R" },
1705};
1706
173efa09
DP		 1707static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1708 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1709 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1710 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1711 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1712 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1713 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1714 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1715 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1716};
1717
1718static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1719 { "DAC1L", NULL, "DAC1L Mixer" },
1720 { "DAC1R", NULL, "DAC1R Mixer" },
1721 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1722 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1723};
1724
6ed8f148
MB		 1725static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1726 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1727 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1728 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1729 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1730};
1731
c4431df0
MB		 1732static const struct snd_soc_dapm_route wm8994_intercon[] = {
1733 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1734 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1735};
1736
1737static const struct snd_soc_dapm_route wm8958_intercon[] = {
1738 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1739 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1740
1741 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1742 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1743 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1744 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1745
1746 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1747 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1748
1749 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1750};
1751
9e6e96a1
MB		 1752/* The size in bits of the FLL divide multiplied by 10
1753 * to allow rounding later */
1754#define FIXED_FLL_SIZE ((1 << 16) * 10)
1755
1756struct fll_div {
1757 u16 outdiv;
1758 u16 n;
1759 u16 k;
1760 u16 clk_ref_div;
1761 u16 fll_fratio;
1762};
1763
1764static int wm8994_get_fll_config(struct fll_div *fll,
1765 int freq_in, int freq_out)
1766{
1767 u64 Kpart;
1768 unsigned int K, Ndiv, Nmod;
1769
1770 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1771
1772 /* Scale the input frequency down to <= 13.5MHz */
1773 fll->clk_ref_div = 0;
1774 while (freq_in > 13500000) {
1775 fll->clk_ref_div++;
1776 freq_in /= 2;
1777
1778 if (fll->clk_ref_div > 3)
1779 return -EINVAL;
1780 }
1781 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1782
1783 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1784 fll->outdiv = 3;
1785 while (freq_out * (fll->outdiv + 1) < 90000000) {
1786 fll->outdiv++;
1787 if (fll->outdiv > 63)
1788 return -EINVAL;
1789 }
1790 freq_out *= fll->outdiv + 1;
1791 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1792
1793 if (freq_in > 1000000) {
1794 fll->fll_fratio = 0;
7d48a6ac
MB		 1795 } else if (freq_in > 256000) {
1796 fll->fll_fratio = 1;
1797 freq_in *= 2;
1798 } else if (freq_in > 128000) {
1799 fll->fll_fratio = 2;
1800 freq_in *= 4;
1801 } else if (freq_in > 64000) {
9e6e96a1
MB		 1802 fll->fll_fratio = 3;
1803 freq_in *= 8;
7d48a6ac
MB		 1804 } else {
1805 fll->fll_fratio = 4;
1806 freq_in *= 16;
9e6e96a1
MB		 1807 }
1808 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1809
1810 /* Now, calculate N.K */
1811 Ndiv = freq_out / freq_in;
1812
1813 fll->n = Ndiv;
1814 Nmod = freq_out % freq_in;
1815 pr_debug("Nmod=%d\n", Nmod);
1816
1817 /* Calculate fractional part - scale up so we can round. */
1818 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1819
1820 do_div(Kpart, freq_in);
1821
1822 K = Kpart & 0xFFFFFFFF;
1823
1824 if ((K % 10) >= 5)
1825 K += 5;
1826
1827 /* Move down to proper range now rounding is done */
1828 fll->k = K / 10;
1829
1830 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1831
1832 return 0;
1833}
1834
f0fba2ad 1835static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1836 unsigned int freq_in, unsigned int freq_out)
1837{
b2c812e2 1838 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1839 int reg_offset, ret;
1840 struct fll_div fll;
1841 u16 reg, aif1, aif2;
1842
1843 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1844 & WM8994_AIF1CLK_ENA;
1845
1846 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1847 & WM8994_AIF2CLK_ENA;
1848
1849 switch (id) {
1850 case WM8994_FLL1:
1851 reg_offset = 0;
1852 id = 0;
1853 break;
1854 case WM8994_FLL2:
1855 reg_offset = 0x20;
1856 id = 1;
1857 break;
1858 default:
1859 return -EINVAL;
1860 }
1861
136ff2a2 1862 switch (src) {
7add84aa
MB		 1863 case 0:
1864 /* Allow no source specification when stopping */
1865 if (freq_out)
1866 return -EINVAL;
4514e899 1867 src = wm8994->fll[id].src;
7add84aa 1868 break;
136ff2a2
MB		 1869 case WM8994_FLL_SRC_MCLK1:
1870 case WM8994_FLL_SRC_MCLK2:
1871 case WM8994_FLL_SRC_LRCLK:
1872 case WM8994_FLL_SRC_BCLK:
1873 break;
1874 default:
1875 return -EINVAL;
1876 }
1877
9e6e96a1
MB		 1878 /* Are we changing anything? */
1879 if (wm8994->fll[id].src == src &&
1880 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1881 return 0;
1882
1883 /* If we're stopping the FLL redo the old config - no
1884 * registers will actually be written but we avoid GCC flow
1885 * analysis bugs spewing warnings.
1886 */
1887 if (freq_out)
1888 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1889 else
1890 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1891 wm8994->fll[id].out);
1892 if (ret < 0)
1893 return ret;
1894
1895 /* Gate the AIF clocks while we reclock */
1896 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1897 WM8994_AIF1CLK_ENA, 0);
1898 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1899 WM8994_AIF2CLK_ENA, 0);
1900
1901 /* We always need to disable the FLL while reconfiguring */
1902 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1903 WM8994_FLL1_ENA, 0);
1904
1905 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1906 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1907 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1908 WM8994_FLL1_OUTDIV_MASK |
1909 WM8994_FLL1_FRATIO_MASK, reg);
1910
1911 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1912
1913 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1914 WM8994_FLL1_N_MASK,
1915 fll.n << WM8994_FLL1_N_SHIFT);
1916
1917 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1918 WM8994_FLL1_REFCLK_DIV_MASK |
1919 WM8994_FLL1_REFCLK_SRC_MASK,
1920 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1921 (src - 1));
9e6e96a1
MB		 1922
1923 /* Enable (with fractional mode if required) */
1924 if (freq_out) {
1925 if (fll.k)
1926 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1927 else
1928 reg = WM8994_FLL1_ENA;
1929 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1930 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1931 reg);
1932 }
1933
1934 wm8994->fll[id].in = freq_in;
1935 wm8994->fll[id].out = freq_out;
136ff2a2 1936 wm8994->fll[id].src = src;
9e6e96a1
MB		 1937
1938 /* Enable any gated AIF clocks */
1939 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1940 WM8994_AIF1CLK_ENA, aif1);
1941 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1942 WM8994_AIF2CLK_ENA, aif2);
1943
1944 configure_clock(codec);
1945
1946 return 0;
1947}
1948
f0fba2ad 1949
66b47fdb
MB		 1950static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1951
f0fba2ad
LG		 1952static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1953 unsigned int freq_in, unsigned int freq_out)
1954{
1955 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1956}
1957
9e6e96a1
MB		 1958static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1959 int clk_id, unsigned int freq, int dir)
1960{
1961 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1962 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1963 int i;
9e6e96a1
MB		 1964
1965 switch (dai->id) {
1966 case 1:
1967 case 2:
1968 break;
1969
1970 default:
1971 /* AIF3 shares clocking with AIF1/2 */
1972 return -EINVAL;
1973 }
1974
1975 switch (clk_id) {
1976 case WM8994_SYSCLK_MCLK1:
1977 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1978 wm8994->mclk[0] = freq;
1979 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1980 dai->id, freq);
1981 break;
1982
1983 case WM8994_SYSCLK_MCLK2:
1984 /* TODO: Set GPIO AF */
1985 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1986 wm8994->mclk[1] = freq;
1987 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1988 dai->id, freq);
1989 break;
1990
1991 case WM8994_SYSCLK_FLL1:
1992 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1993 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1994 break;
1995
1996 case WM8994_SYSCLK_FLL2:
1997 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1998 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1999 break;
2000
66b47fdb
MB		 2001 case WM8994_SYSCLK_OPCLK:
2002 /* Special case - a division (times 10) is given and
2003 * no effect on main clocking.
2004 */
2005 if (freq) {
2006 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2007 if (opclk_divs[i] == freq)
2008 break;
2009 if (i == ARRAY_SIZE(opclk_divs))
2010 return -EINVAL;
2011 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2012 WM8994_OPCLK_DIV_MASK, i);
2013 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2014 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2015 } else {
2016 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2017 WM8994_OPCLK_ENA, 0);
2018 }
2019
9e6e96a1
MB		 2020 default:
2021 return -EINVAL;
2022 }
2023
2024 configure_clock(codec);
2025
2026 return 0;
2027}
2028
2029static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2030 enum snd_soc_bias_level level)
2031{
3a423157 2032 struct wm8994 *control = codec->control_data;
b6b05691
MB		 2033 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2034
9e6e96a1
MB		 2035 switch (level) {
2036 case SND_SOC_BIAS_ON:
2037 break;
2038
2039 case SND_SOC_BIAS_PREPARE:
2040 /* VMID=2x40k */
2041 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2042 WM8994_VMID_SEL_MASK, 0x2);
2043 break;
2044
2045 case SND_SOC_BIAS_STANDBY:
ce6120cc 2046 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
39fb51a1
MB		 2047 pm_runtime_get_sync(codec->dev);
2048
8bc3c2c2
MB		 2049 switch (control->type) {
2050 case WM8994:
2051 if (wm8994->revision < 4) {
2052 /* Tweak DC servo and DSP
2053 * configuration for improved
2054 * performance. */
2055 snd_soc_write(codec, 0x102, 0x3);
2056 snd_soc_write(codec, 0x56, 0x3);
2057 snd_soc_write(codec, 0x817, 0);
2058 snd_soc_write(codec, 0x102, 0);
2059 }
2060 break;
2061
2062 case WM8958:
2063 if (wm8994->revision == 0) {
2064 /* Optimise performance for rev A */
2065 snd_soc_write(codec, 0x102, 0x3);
2066 snd_soc_write(codec, 0xcb, 0x81);
2067 snd_soc_write(codec, 0x817, 0);
2068 snd_soc_write(codec, 0x102, 0);
2069
2070 snd_soc_update_bits(codec,
2071 WM8958_CHARGE_PUMP_2,
2072 WM8958_CP_DISCH,
2073 WM8958_CP_DISCH);
2074 }
2075 break;
b6b05691 2076 }
9e6e96a1
MB		 2077
2078 /* Discharge LINEOUT1 & 2 */
2079 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2080 WM8994_LINEOUT1_DISCH |
2081 WM8994_LINEOUT2_DISCH,
2082 WM8994_LINEOUT1_DISCH |
2083 WM8994_LINEOUT2_DISCH);
2084
2085 /* Startup bias, VMID ramp & buffer */
2086 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2087 WM8994_STARTUP_BIAS_ENA |
2088 WM8994_VMID_BUF_ENA |
2089 WM8994_VMID_RAMP_MASK,
2090 WM8994_STARTUP_BIAS_ENA |
2091 WM8994_VMID_BUF_ENA |
2092 (0x11 << WM8994_VMID_RAMP_SHIFT));
2093
2094 /* Main bias enable, VMID=2x40k */
2095 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2096 WM8994_BIAS_ENA |
2097 WM8994_VMID_SEL_MASK,
2098 WM8994_BIAS_ENA | 0x2);
2099
2100 msleep(20);
2101 }
2102
2103 /* VMID=2x500k */
2104 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2105 WM8994_VMID_SEL_MASK, 0x4);
2106
2107 break;
2108
2109 case SND_SOC_BIAS_OFF:
ce6120cc 2110 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 2111 /* Switch over to startup biases */
2112 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2113 WM8994_BIAS_SRC |
2114 WM8994_STARTUP_BIAS_ENA |
2115 WM8994_VMID_BUF_ENA |
2116 WM8994_VMID_RAMP_MASK,
2117 WM8994_BIAS_SRC |
2118 WM8994_STARTUP_BIAS_ENA |
2119 WM8994_VMID_BUF_ENA |
2120 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 2121
d522ffbf
MB		 2122 /* Disable main biases */
2123 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2124 WM8994_BIAS_ENA |
2125 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 2126
d522ffbf
MB		 2127 /* Discharge line */
2128 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2129 WM8994_LINEOUT1_DISCH |
2130 WM8994_LINEOUT2_DISCH,
2131 WM8994_LINEOUT1_DISCH |
2132 WM8994_LINEOUT2_DISCH);
9e6e96a1 2133
d522ffbf 2134 msleep(5);
9e6e96a1 2135
d522ffbf
MB		 2136 /* Switch off startup biases */
2137 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2138 WM8994_BIAS_SRC |
2139 WM8994_STARTUP_BIAS_ENA |
2140 WM8994_VMID_BUF_ENA |
2141 WM8994_VMID_RAMP_MASK, 0);
39fb51a1
MB		 2142
2143 pm_runtime_put(codec->dev);
d522ffbf 2144 }
9e6e96a1
MB		 2145 break;
2146 }
ce6120cc 2147 codec->dapm.bias_level = level;
9e6e96a1
MB		 2148 return 0;
2149}
2150
2151static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2152{
2153 struct snd_soc_codec *codec = dai->codec;
c4431df0 2154 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 2155 int ms_reg;
2156 int aif1_reg;
2157 int ms = 0;
2158 int aif1 = 0;
2159
2160 switch (dai->id) {
2161 case 1:
2162 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2163 aif1_reg = WM8994_AIF1_CONTROL_1;
2164 break;
2165 case 2:
2166 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2167 aif1_reg = WM8994_AIF2_CONTROL_1;
2168 break;
2169 default:
2170 return -EINVAL;
2171 }
2172
2173 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2174 case SND_SOC_DAIFMT_CBS_CFS:
2175 break;
2176 case SND_SOC_DAIFMT_CBM_CFM:
2177 ms = WM8994_AIF1_MSTR;
2178 break;
2179 default:
2180 return -EINVAL;
2181 }
2182
2183 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2184 case SND_SOC_DAIFMT_DSP_B:
2185 aif1 |= WM8994_AIF1_LRCLK_INV;
2186 case SND_SOC_DAIFMT_DSP_A:
2187 aif1 |= 0x18;
2188 break;
2189 case SND_SOC_DAIFMT_I2S:
2190 aif1 |= 0x10;
2191 break;
2192 case SND_SOC_DAIFMT_RIGHT_J:
2193 break;
2194 case SND_SOC_DAIFMT_LEFT_J:
2195 aif1 |= 0x8;
2196 break;
2197 default:
2198 return -EINVAL;
2199 }
2200
2201 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2202 case SND_SOC_DAIFMT_DSP_A:
2203 case SND_SOC_DAIFMT_DSP_B:
2204 /* frame inversion not valid for DSP modes */
2205 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2206 case SND_SOC_DAIFMT_NB_NF:
2207 break;
2208 case SND_SOC_DAIFMT_IB_NF:
2209 aif1 |= WM8994_AIF1_BCLK_INV;
2210 break;
2211 default:
2212 return -EINVAL;
2213 }
2214 break;
2215
2216 case SND_SOC_DAIFMT_I2S:
2217 case SND_SOC_DAIFMT_RIGHT_J:
2218 case SND_SOC_DAIFMT_LEFT_J:
2219 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2220 case SND_SOC_DAIFMT_NB_NF:
2221 break;
2222 case SND_SOC_DAIFMT_IB_IF:
2223 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2224 break;
2225 case SND_SOC_DAIFMT_IB_NF:
2226 aif1 |= WM8994_AIF1_BCLK_INV;
2227 break;
2228 case SND_SOC_DAIFMT_NB_IF:
2229 aif1 |= WM8994_AIF1_LRCLK_INV;
2230 break;
2231 default:
2232 return -EINVAL;
2233 }
2234 break;
2235 default:
2236 return -EINVAL;
2237 }
2238
c4431df0
MB		 2239 /* The AIF2 format configuration needs to be mirrored to AIF3
2240 * on WM8958 if it's in use so just do it all the time. */
2241 if (control->type == WM8958 && dai->id == 2)
2242 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2243 WM8994_AIF1_LRCLK_INV |
2244 WM8958_AIF3_FMT_MASK, aif1);
2245
9e6e96a1
MB		 2246 snd_soc_update_bits(codec, aif1_reg,
2247 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2248 WM8994_AIF1_FMT_MASK,
2249 aif1);
2250 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2251 ms);
2252
2253 return 0;
2254}
2255
2256static struct {
2257 int val, rate;
2258} srs[] = {
2259 { 0, 8000 },
2260 { 1, 11025 },
2261 { 2, 12000 },
2262 { 3, 16000 },
2263 { 4, 22050 },
2264 { 5, 24000 },
2265 { 6, 32000 },
2266 { 7, 44100 },
2267 { 8, 48000 },
2268 { 9, 88200 },
2269 { 10, 96000 },
2270};
2271
2272static int fs_ratios[] = {
2273 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2274};
2275
2276static int bclk_divs[] = {
2277 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2278 640, 880, 960, 1280, 1760, 1920
2279};
2280
2281static int wm8994_hw_params(struct snd_pcm_substream *substream,
2282 struct snd_pcm_hw_params *params,
2283 struct snd_soc_dai *dai)
2284{
2285 struct snd_soc_codec *codec = dai->codec;
c4431df0 2286 struct wm8994 *control = codec->control_data;
b2c812e2 2287 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2288 int aif1_reg;
b1e43d93 2289 int aif2_reg;
9e6e96a1
MB		 2290 int bclk_reg;
2291 int lrclk_reg;
2292 int rate_reg;
2293 int aif1 = 0;
b1e43d93 2294 int aif2 = 0;
9e6e96a1
MB		 2295 int bclk = 0;
2296 int lrclk = 0;
2297 int rate_val = 0;
2298 int id = dai->id - 1;
2299
2300 int i, cur_val, best_val, bclk_rate, best;
2301
2302 switch (dai->id) {
2303 case 1:
2304 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2305 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2306 bclk_reg = WM8994_AIF1_BCLK;
2307 rate_reg = WM8994_AIF1_RATE;
2308 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2309 wm8994->lrclk_shared[0]) {
9e6e96a1 2310 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2311 } else {
9e6e96a1 2312 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2313 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2314 }
9e6e96a1
MB		 2315 break;
2316 case 2:
2317 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2318 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2319 bclk_reg = WM8994_AIF2_BCLK;
2320 rate_reg = WM8994_AIF2_RATE;
2321 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2322 wm8994->lrclk_shared[1]) {
9e6e96a1 2323 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2324 } else {
9e6e96a1 2325 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2326 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2327 }
9e6e96a1 2328 break;
c4431df0
MB		 2329 case 3:
2330 switch (control->type) {
2331 case WM8958:
2332 aif1_reg = WM8958_AIF3_CONTROL_1;
2333 break;
2334 default:
2335 return 0;
2336 }
9e6e96a1
MB		 2337 default:
2338 return -EINVAL;
2339 }
2340
2341 bclk_rate = params_rate(params) * 2;
2342 switch (params_format(params)) {
2343 case SNDRV_PCM_FORMAT_S16_LE:
2344 bclk_rate *= 16;
2345 break;
2346 case SNDRV_PCM_FORMAT_S20_3LE:
2347 bclk_rate *= 20;
2348 aif1 |= 0x20;
2349 break;
2350 case SNDRV_PCM_FORMAT_S24_LE:
2351 bclk_rate *= 24;
2352 aif1 |= 0x40;
2353 break;
2354 case SNDRV_PCM_FORMAT_S32_LE:
2355 bclk_rate *= 32;
2356 aif1 |= 0x60;
2357 break;
2358 default:
2359 return -EINVAL;
2360 }
2361
2362 /* Try to find an appropriate sample rate; look for an exact match. */
2363 for (i = 0; i < ARRAY_SIZE(srs); i++)
2364 if (srs[i].rate == params_rate(params))
2365 break;
2366 if (i == ARRAY_SIZE(srs))
2367 return -EINVAL;
2368 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2369
2370 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2371 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2372 dai->id, wm8994->aifclk[id], bclk_rate);
2373
b1e43d93
MB		 2374 if (params_channels(params) == 1 &&
2375 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2376 aif2 |= WM8994_AIF1_MONO;
2377
9e6e96a1
MB		 2378 if (wm8994->aifclk[id] == 0) {
2379 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2380 return -EINVAL;
2381 }
2382
2383 /* AIFCLK/fs ratio; look for a close match in either direction */
2384 best = 0;
2385 best_val = abs((fs_ratios[0] * params_rate(params))
2386 - wm8994->aifclk[id]);
2387 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2388 cur_val = abs((fs_ratios[i] * params_rate(params))
2389 - wm8994->aifclk[id]);
2390 if (cur_val >= best_val)
2391 continue;
2392 best = i;
2393 best_val = cur_val;
2394 }
2395 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2396 dai->id, fs_ratios[best]);
2397 rate_val |= best;
2398
2399 /* We may not get quite the right frequency if using
2400 * approximate clocks so look for the closest match that is
2401 * higher than the target (we need to ensure that there enough
2402 * BCLKs to clock out the samples).
2403 */
2404 best = 0;
2405 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2406 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2407 if (cur_val < 0) /* BCLK table is sorted */
2408 break;
2409 best = i;
2410 }
07cd8ada 2411 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2412 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2413 bclk_divs[best], bclk_rate);
2414 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2415
2416 lrclk = bclk_rate / params_rate(params);
2417 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2418 lrclk, bclk_rate / lrclk);
2419
2420 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2421 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2422 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2423 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2424 lrclk);
2425 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2426 WM8994_AIF1CLK_RATE_MASK, rate_val);
2427
2428 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2429 switch (dai->id) {
2430 case 1:
2431 wm8994->dac_rates[0] = params_rate(params);
2432 wm8994_set_retune_mobile(codec, 0);
2433 wm8994_set_retune_mobile(codec, 1);
2434 break;
2435 case 2:
2436 wm8994->dac_rates[1] = params_rate(params);
2437 wm8994_set_retune_mobile(codec, 2);
2438 break;
2439 }
2440 }
2441
2442 return 0;
2443}
2444
c4431df0
MB		 2445static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2446 struct snd_pcm_hw_params *params,
2447 struct snd_soc_dai *dai)
2448{
2449 struct snd_soc_codec *codec = dai->codec;
2450 struct wm8994 *control = codec->control_data;
2451 int aif1_reg;
2452 int aif1 = 0;
2453
2454 switch (dai->id) {
2455 case 3:
2456 switch (control->type) {
2457 case WM8958:
2458 aif1_reg = WM8958_AIF3_CONTROL_1;
2459 break;
2460 default:
2461 return 0;
2462 }
2463 default:
2464 return 0;
2465 }
2466
2467 switch (params_format(params)) {
2468 case SNDRV_PCM_FORMAT_S16_LE:
2469 break;
2470 case SNDRV_PCM_FORMAT_S20_3LE:
2471 aif1 |= 0x20;
2472 break;
2473 case SNDRV_PCM_FORMAT_S24_LE:
2474 aif1 |= 0x40;
2475 break;
2476 case SNDRV_PCM_FORMAT_S32_LE:
2477 aif1 |= 0x60;
2478 break;
2479 default:
2480 return -EINVAL;
2481 }
2482
2483 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2484}
2485
9e6e96a1
MB		 2486static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2487{
2488 struct snd_soc_codec *codec = codec_dai->codec;
2489 int mute_reg;
2490 int reg;
2491
2492 switch (codec_dai->id) {
2493 case 1:
2494 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2495 break;
2496 case 2:
2497 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2498 break;
2499 default:
2500 return -EINVAL;
2501 }
2502
2503 if (mute)
2504 reg = WM8994_AIF1DAC1_MUTE;
2505 else
2506 reg = 0;
2507
2508 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2509
2510 return 0;
2511}
2512
778a76e2
MB		 2513static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2514{
2515 struct snd_soc_codec *codec = codec_dai->codec;
2516 int reg, val, mask;
2517
2518 switch (codec_dai->id) {
2519 case 1:
2520 reg = WM8994_AIF1_MASTER_SLAVE;
2521 mask = WM8994_AIF1_TRI;
2522 break;
2523 case 2:
2524 reg = WM8994_AIF2_MASTER_SLAVE;
2525 mask = WM8994_AIF2_TRI;
2526 break;
2527 case 3:
2528 reg = WM8994_POWER_MANAGEMENT_6;
2529 mask = WM8994_AIF3_TRI;
2530 break;
2531 default:
2532 return -EINVAL;
2533 }
2534
2535 if (tristate)
2536 val = mask;
2537 else
2538 val = 0;
2539
78b3fb46 2540 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2541}
2542
9e6e96a1
MB		 2543#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2544
2545#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2546 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2547
2548static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2549 .set_sysclk = wm8994_set_dai_sysclk,
2550 .set_fmt = wm8994_set_dai_fmt,
2551 .hw_params = wm8994_hw_params,
2552 .digital_mute = wm8994_aif_mute,
2553 .set_pll = wm8994_set_fll,
778a76e2 2554 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2555};
2556
2557static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2558 .set_sysclk = wm8994_set_dai_sysclk,
2559 .set_fmt = wm8994_set_dai_fmt,
2560 .hw_params = wm8994_hw_params,
2561 .digital_mute = wm8994_aif_mute,
2562 .set_pll = wm8994_set_fll,
778a76e2
MB		 2563 .set_tristate = wm8994_set_tristate,
2564};
2565
2566static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2567 .hw_params = wm8994_aif3_hw_params,
778a76e2 2568 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2569};
2570
f0fba2ad 2571static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2572 {
f0fba2ad 2573 .name = "wm8994-aif1",
8c7f78b3 2574 .id = 1,
9e6e96a1
MB		 2575 .playback = {
2576 .stream_name = "AIF1 Playback",
b1e43d93 2577 .channels_min = 1,
9e6e96a1
MB		 2578 .channels_max = 2,
2579 .rates = WM8994_RATES,
2580 .formats = WM8994_FORMATS,
2581 },
2582 .capture = {
2583 .stream_name = "AIF1 Capture",
b1e43d93 2584 .channels_min = 1,
9e6e96a1
MB		 2585 .channels_max = 2,
2586 .rates = WM8994_RATES,
2587 .formats = WM8994_FORMATS,
2588 },
2589 .ops = &wm8994_aif1_dai_ops,
2590 },
2591 {
f0fba2ad 2592 .name = "wm8994-aif2",
8c7f78b3 2593 .id = 2,
9e6e96a1
MB		 2594 .playback = {
2595 .stream_name = "AIF2 Playback",
b1e43d93 2596 .channels_min = 1,
9e6e96a1
MB		 2597 .channels_max = 2,
2598 .rates = WM8994_RATES,
2599 .formats = WM8994_FORMATS,
2600 },
2601 .capture = {
2602 .stream_name = "AIF2 Capture",
b1e43d93 2603 .channels_min = 1,
9e6e96a1
MB		 2604 .channels_max = 2,
2605 .rates = WM8994_RATES,
2606 .formats = WM8994_FORMATS,
2607 },
2608 .ops = &wm8994_aif2_dai_ops,
2609 },
2610 {
f0fba2ad 2611 .name = "wm8994-aif3",
8c7f78b3 2612 .id = 3,
9e6e96a1
MB		 2613 .playback = {
2614 .stream_name = "AIF3 Playback",
b1e43d93 2615 .channels_min = 1,
9e6e96a1
MB		 2616 .channels_max = 2,
2617 .rates = WM8994_RATES,
2618 .formats = WM8994_FORMATS,
2619 },
a8462bde 2620 .capture = {
9e6e96a1 2621 .stream_name = "AIF3 Capture",
b1e43d93 2622 .channels_min = 1,
9e6e96a1
MB		 2623 .channels_max = 2,
2624 .rates = WM8994_RATES,
2625 .formats = WM8994_FORMATS,
2626 },
778a76e2 2627 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2628 }
2629};
9e6e96a1
MB		 2630
2631#ifdef CONFIG_PM
f0fba2ad 2632static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2633{
b2c812e2 2634 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2635 int i, ret;
2636
2637 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2638 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2639 sizeof(struct fll_config));
f0fba2ad 2640 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2641 if (ret < 0)
2642 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2643 i + 1, ret);
2644 }
2645
2646 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2647
2648 return 0;
2649}
2650
f0fba2ad 2651static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2652{
b2c812e2 2653 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2654 int i, ret;
c52fd021
DP		 2655 unsigned int val, mask;
2656
2657 if (wm8994->revision < 4) {
2658 /* force a HW read */
2659 val = wm8994_reg_read(codec->control_data,
2660 WM8994_POWER_MANAGEMENT_5);
2661
2662 /* modify the cache only */
2663 codec->cache_only = 1;
2664 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2665 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2666 val &= mask;
2667 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2668 mask, val);
2669 codec->cache_only = 0;
2670 }
9e6e96a1
MB		 2671
2672 /* Restore the registers */
ca9aef50
MB		 2673 ret = snd_soc_cache_sync(codec);
2674 if (ret != 0)
2675 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2676
2677 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2678
2679 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2680 if (!wm8994->fll_suspend[i].out)
2681 continue;
2682
f0fba2ad 2683 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2684 wm8994->fll_suspend[i].src,
2685 wm8994->fll_suspend[i].in,
2686 wm8994->fll_suspend[i].out);
2687 if (ret < 0)
2688 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2689 i + 1, ret);
2690 }
2691
2692 return 0;
2693}
2694#else
2695#define wm8994_suspend NULL
2696#define wm8994_resume NULL
2697#endif
2698
2699static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2700{
f0fba2ad 2701 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2702 struct wm8994_pdata *pdata = wm8994->pdata;
2703 struct snd_kcontrol_new controls[] = {
2704 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2705 wm8994->retune_mobile_enum,
2706 wm8994_get_retune_mobile_enum,
2707 wm8994_put_retune_mobile_enum),
2708 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2709 wm8994->retune_mobile_enum,
2710 wm8994_get_retune_mobile_enum,
2711 wm8994_put_retune_mobile_enum),
2712 SOC_ENUM_EXT("AIF2 EQ Mode",
2713 wm8994->retune_mobile_enum,
2714 wm8994_get_retune_mobile_enum,
2715 wm8994_put_retune_mobile_enum),
2716 };
2717 int ret, i, j;
2718 const char **t;
2719
2720 /* We need an array of texts for the enum API but the number
2721 * of texts is likely to be less than the number of
2722 * configurations due to the sample rate dependency of the
2723 * configurations. */
2724 wm8994->num_retune_mobile_texts = 0;
2725 wm8994->retune_mobile_texts = NULL;
2726 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2727 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2728 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2729 wm8994->retune_mobile_texts[j]) == 0)
2730 break;
2731 }
2732
2733 if (j != wm8994->num_retune_mobile_texts)
2734 continue;
2735
2736 /* Expand the array... */
2737 t = krealloc(wm8994->retune_mobile_texts,
2738 sizeof(char *) *
2739 (wm8994->num_retune_mobile_texts + 1),
2740 GFP_KERNEL);
2741 if (t == NULL)
2742 continue;
2743
2744 /* ...store the new entry... */
2745 t[wm8994->num_retune_mobile_texts] =
2746 pdata->retune_mobile_cfgs[i].name;
2747
2748 /* ...and remember the new version. */
2749 wm8994->num_retune_mobile_texts++;
2750 wm8994->retune_mobile_texts = t;
2751 }
2752
2753 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2754 wm8994->num_retune_mobile_texts);
2755
2756 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2757 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2758
f0fba2ad 2759 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2760 ARRAY_SIZE(controls));
2761 if (ret != 0)
f0fba2ad 2762 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2763 "Failed to add ReTune Mobile controls: %d\n", ret);
2764}
2765
2766static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2767{
f0fba2ad 2768 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2769 struct wm8994_pdata *pdata = wm8994->pdata;
2770 int ret, i;
2771
2772 if (!pdata)
2773 return;
2774
2775 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2776 pdata->lineout2_diff,
2777 pdata->lineout1fb,
2778 pdata->lineout2fb,
2779 pdata->jd_scthr,
2780 pdata->jd_thr,
2781 pdata->micbias1_lvl,
2782 pdata->micbias2_lvl);
2783
2784 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2785
2786 if (pdata->num_drc_cfgs) {
2787 struct snd_kcontrol_new controls[] = {
2788 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2789 wm8994_get_drc_enum, wm8994_put_drc_enum),
2790 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2791 wm8994_get_drc_enum, wm8994_put_drc_enum),
2792 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2793 wm8994_get_drc_enum, wm8994_put_drc_enum),
2794 };
2795
2796 /* We need an array of texts for the enum API */
2797 wm8994->drc_texts = kmalloc(sizeof(char *)
2798 * pdata->num_drc_cfgs, GFP_KERNEL);
2799 if (!wm8994->drc_texts) {
f0fba2ad 2800 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2801 "Failed to allocate %d DRC config texts\n",
2802 pdata->num_drc_cfgs);
2803 return;
2804 }
2805
2806 for (i = 0; i < pdata->num_drc_cfgs; i++)
2807 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2808
2809 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2810 wm8994->drc_enum.texts = wm8994->drc_texts;
2811
f0fba2ad 2812 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2813 ARRAY_SIZE(controls));
2814 if (ret != 0)
f0fba2ad 2815 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2816 "Failed to add DRC mode controls: %d\n", ret);
2817
2818 for (i = 0; i < WM8994_NUM_DRC; i++)
2819 wm8994_set_drc(codec, i);
2820 }
2821
2822 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2823 pdata->num_retune_mobile_cfgs);
2824
131d8106
MB		 2825 if (pdata->num_mbc_cfgs) {
2826 struct snd_kcontrol_new control[] = {
2827 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2828 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2829 };
2830
2831 /* We need an array of texts for the enum API */
2832 wm8994->mbc_texts = kmalloc(sizeof(char *)
2833 * pdata->num_mbc_cfgs, GFP_KERNEL);
2834 if (!wm8994->mbc_texts) {
2835 dev_err(wm8994->codec->dev,
2836 "Failed to allocate %d MBC config texts\n",
2837 pdata->num_mbc_cfgs);
2838 return;
2839 }
2840
2841 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2842 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2843
2844 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2845 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2846
2847 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2848 if (ret != 0)
2849 dev_err(wm8994->codec->dev,
2850 "Failed to add MBC mode controls: %d\n", ret);
2851 }
2852
9e6e96a1
MB		 2853 if (pdata->num_retune_mobile_cfgs)
2854 wm8994_handle_retune_mobile_pdata(wm8994);
2855 else
f0fba2ad 2856 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1
MB		 2857 ARRAY_SIZE(wm8994_eq_controls));
2858}
2859
88766984
MB		 2860/**
2861 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2862 *
2863 * @codec: WM8994 codec
2864 * @jack: jack to report detection events on
2865 * @micbias: microphone bias to detect on
2866 * @det: value to report for presence detection
2867 * @shrt: value to report for short detection
2868 *
2869 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2870 * being used to bring out signals to the processor then only platform
5ab230a7 2871 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2872 * be configured using snd_soc_jack_add_gpios() instead.
2873 *
2874 * Configuration of detection levels is available via the micbias1_lvl
2875 * and micbias2_lvl platform data members.
2876 */
2877int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2878 int micbias, int det, int shrt)
2879{
b2c812e2 2880 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2881 struct wm8994_micdet *micdet;
3a423157 2882 struct wm8994 *control = codec->control_data;
88766984
MB		 2883 int reg;
2884
3a423157
MB		 2885 if (control->type != WM8994)
2886 return -EINVAL;
2887
88766984
MB		 2888 switch (micbias) {
2889 case 1:
2890 micdet = &wm8994->micdet[0];
2891 break;
2892 case 2:
2893 micdet = &wm8994->micdet[1];
2894 break;
2895 default:
2896 return -EINVAL;
2897 }
2898
2899 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2900 micbias, det, shrt);
2901
2902 /* Store the configuration */
2903 micdet->jack = jack;
2904 micdet->det = det;
2905 micdet->shrt = shrt;
2906
2907 /* If either of the jacks is set up then enable detection */
2908 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2909 reg = WM8994_MICD_ENA;
2910 else
2911 reg = 0;
2912
2913 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2914
2915 return 0;
2916}
2917EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2918
2919static irqreturn_t wm8994_mic_irq(int irq, void *data)
2920{
2921 struct wm8994_priv *priv = data;
f0fba2ad 2922 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2923 int reg;
2924 int report;
2925
7116f452 2926#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2927 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2928#endif
2bbb5d66 2929
88766984
MB		 2930 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2931 if (reg < 0) {
2932 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2933 reg);
2934 return IRQ_HANDLED;
2935 }
2936
2937 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2938
2939 report = 0;
2940 if (reg & WM8994_MIC1_DET_STS)
2941 report |= priv->micdet[0].det;
2942 if (reg & WM8994_MIC1_SHRT_STS)
2943 report |= priv->micdet[0].shrt;
2944 snd_soc_jack_report(priv->micdet[0].jack, report,
2945 priv->micdet[0].det | priv->micdet[0].shrt);
2946
2947 report = 0;
2948 if (reg & WM8994_MIC2_DET_STS)
2949 report |= priv->micdet[1].det;
2950 if (reg & WM8994_MIC2_SHRT_STS)
2951 report |= priv->micdet[1].shrt;
2952 snd_soc_jack_report(priv->micdet[1].jack, report,
2953 priv->micdet[1].det | priv->micdet[1].shrt);
2954
2955 return IRQ_HANDLED;
2956}
2957
821edd2f
MB		 2958/* Default microphone detection handler for WM8958 - the user can
2959 * override this if they wish.
2960 */
2961static void wm8958_default_micdet(u16 status, void *data)
2962{
2963 struct snd_soc_codec *codec = data;
2964 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2965 int report = 0;
2966
2967 /* If nothing present then clear our statuses */
2968 if (!(status & WM8958_MICD_STS)) {
2969 wm8994->jack_is_video = false;
2970 wm8994->jack_is_mic = false;
2971 goto done;
2972 }
2973
2974 /* Assume anything over 475 ohms is a microphone and remember
2975 * that we've seen one (since buttons override it) */
2976 if (status & 0x600)
2977 wm8994->jack_is_mic = true;
2978 if (wm8994->jack_is_mic)
2979 report |= SND_JACK_MICROPHONE;
2980
2981 /* Video has an impedence of approximately 75 ohms; assume
2982 * this isn't used as a button and remember it since buttons
2983 * override it. */
2984 if (status & 0x40)
2985 wm8994->jack_is_video = true;
2986 if (wm8994->jack_is_video)
2987 report |= SND_JACK_VIDEOOUT;
2988
2989 /* Everything else is buttons; just assign slots */
2990 if (status & 0x4)
2991 report |= SND_JACK_BTN_0;
2992 if (status & 0x8)
2993 report |= SND_JACK_BTN_1;
2994 if (status & 0x10)
2995 report |= SND_JACK_BTN_2;
2996 if (status & 0x20)
2997 report |= SND_JACK_BTN_3;
2998 if (status & 0x80)
2999 report |= SND_JACK_BTN_4;
3000 if (status & 0x100)
3001 report |= SND_JACK_BTN_5;
3002
3003done:
406e56c9 3004 snd_soc_jack_report(wm8994->micdet[0].jack, report,
821edd2f
MB		 3005 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
3006 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
406e56c9 3007 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT);
821edd2f
MB		 3008}
3009
3010/**
3011 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3012 *
3013 * @codec: WM8958 codec
3014 * @jack: jack to report detection events on
3015 *
3016 * Enable microphone detection functionality for the WM8958. By
3017 * default simple detection which supports the detection of up to 6
3018 * buttons plus video and microphone functionality is supported.
3019 *
3020 * The WM8958 has an advanced jack detection facility which is able to
3021 * support complex accessory detection, especially when used in
3022 * conjunction with external circuitry. In order to provide maximum
3023 * flexiblity a callback is provided which allows a completely custom
3024 * detection algorithm.
3025 */
3026int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3027 wm8958_micdet_cb cb, void *cb_data)
3028{
3029 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3030 struct wm8994 *control = codec->control_data;
3031
3032 if (control->type != WM8958)
3033 return -EINVAL;
3034
3035 if (jack) {
3036 if (!cb) {
3037 dev_dbg(codec->dev, "Using default micdet callback\n");
3038 cb = wm8958_default_micdet;
3039 cb_data = codec;
3040 }
3041
3042 wm8994->micdet[0].jack = jack;
3043 wm8994->jack_cb = cb;
3044 wm8994->jack_cb_data = cb_data;
3045
3046 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3047 WM8958_MICD_ENA, WM8958_MICD_ENA);
3048 } else {
3049 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3050 WM8958_MICD_ENA, 0);
3051 }
3052
3053 return 0;
3054}
3055EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3056
3057static irqreturn_t wm8958_mic_irq(int irq, void *data)
3058{
3059 struct wm8994_priv *wm8994 = data;
3060 struct snd_soc_codec *codec = wm8994->codec;
3061 int reg;
3062
3063 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3064 if (reg < 0) {
3065 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3066 reg);
3067 return IRQ_NONE;
3068 }
3069
3070 if (!(reg & WM8958_MICD_VALID)) {
3071 dev_dbg(codec->dev, "Mic detect data not valid\n");
3072 goto out;
3073 }
3074
7116f452 3075#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3076 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3077#endif
2bbb5d66 3078
821edd2f
MB		 3079 if (wm8994->jack_cb)
3080 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3081 else
3082 dev_warn(codec->dev, "Accessory detection with no callback\n");
3083
3084out:
3085 return IRQ_HANDLED;
3086}
3087
f0fba2ad 3088static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3089{
3a423157 3090 struct wm8994 *control;
9e6e96a1 3091 struct wm8994_priv *wm8994;
ce6120cc 3092 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 3093 int ret, i;
9e6e96a1 3094
f0fba2ad 3095 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 3096 control = codec->control_data;
9e6e96a1
MB		 3097
3098 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 3099 if (wm8994 == NULL)
9e6e96a1 3100 return -ENOMEM;
b2c812e2 3101 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad
LG		 3102
3103 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3104 wm8994->codec = codec;
9e6e96a1 3105
9b7c525d
MB		 3106 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3107 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3108 else if (wm8994->pdata && wm8994->pdata->irq_base)
3109 wm8994->micdet_irq = wm8994->pdata->irq_base +
3110 WM8994_IRQ_MIC1_DET;
3111
39fb51a1
MB		 3112 pm_runtime_enable(codec->dev);
3113 pm_runtime_resume(codec->dev);
3114
ca9aef50
MB		 3115 /* Read our current status back from the chip - we don't want to
3116 * reset as this may interfere with the GPIO or LDO operation. */
3117 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
d4754ec9 3118 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
ca9aef50 3119 continue;
9e6e96a1 3120
ca9aef50
MB		 3121 ret = wm8994_reg_read(codec->control_data, i);
3122 if (ret <= 0)
3123 continue;
3124
3125 ret = snd_soc_cache_write(codec, i, ret);
3126 if (ret != 0) {
3127 dev_err(codec->dev,
3128 "Failed to initialise cache for 0x%x: %d\n",
3129 i, ret);
3130 goto err;
3131 }
3132 }
9e6e96a1
MB		 3133
3134 /* Set revision-specific configuration */
b6b05691 3135 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3136 switch (control->type) {
3137 case WM8994:
3138 switch (wm8994->revision) {
3139 case 2:
3140 case 3:
3141 wm8994->hubs.dcs_codes = -5;
3142 wm8994->hubs.hp_startup_mode = 1;
3143 wm8994->hubs.dcs_readback_mode = 1;
3144 break;
3145 default:
3146 wm8994->hubs.dcs_readback_mode = 1;
3147 break;
3148 }
3149
3150 case WM8958:
8437f700 3151 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 3152 break;
3a423157 3153
9e6e96a1
MB		 3154 default:
3155 break;
3156 }
9e6e96a1 3157
3a423157
MB		 3158 switch (control->type) {
3159 case WM8994:
9b7c525d
MB		 3160 if (wm8994->micdet_irq) {
3161 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3162 wm8994_mic_irq,
3163 IRQF_TRIGGER_RISING,
3164 "Mic1 detect",
3165 wm8994);
3166 if (ret != 0)
3167 dev_warn(codec->dev,
3168 "Failed to request Mic1 detect IRQ: %d\n",
3169 ret);
3170 }
3a423157
MB		 3171
3172 ret = wm8994_request_irq(codec->control_data,
3173 WM8994_IRQ_MIC1_SHRT,
3174 wm8994_mic_irq, "Mic 1 short",
3175 wm8994);
3176 if (ret != 0)
3177 dev_warn(codec->dev,
3178 "Failed to request Mic1 short IRQ: %d\n",
3179 ret);
3180
3181 ret = wm8994_request_irq(codec->control_data,
3182 WM8994_IRQ_MIC2_DET,
3183 wm8994_mic_irq, "Mic 2 detect",
3184 wm8994);
3185 if (ret != 0)
3186 dev_warn(codec->dev,
3187 "Failed to request Mic2 detect IRQ: %d\n",
3188 ret);
3189
3190 ret = wm8994_request_irq(codec->control_data,
3191 WM8994_IRQ_MIC2_SHRT,
3192 wm8994_mic_irq, "Mic 2 short",
3193 wm8994);
3194 if (ret != 0)
3195 dev_warn(codec->dev,
3196 "Failed to request Mic2 short IRQ: %d\n",
3197 ret);
3198 break;
821edd2f
MB		 3199
3200 case WM8958:
9b7c525d
MB		 3201 if (wm8994->micdet_irq) {
3202 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3203 wm8958_mic_irq,
3204 IRQF_TRIGGER_RISING,
3205 "Mic detect",
3206 wm8994);
3207 if (ret != 0)
3208 dev_warn(codec->dev,
3209 "Failed to request Mic detect IRQ: %d\n",
3210 ret);
3211 }
3a423157 3212 }
88766984 3213
9e6e96a1
MB		 3214 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3215 * configured on init - if a system wants to do this dynamically
3216 * at runtime we can deal with that then.
3217 */
3218 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3219 if (ret < 0) {
3220 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3221 goto err_irq;
9e6e96a1
MB		 3222 }
3223 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3224 wm8994->lrclk_shared[0] = 1;
3225 wm8994_dai[0].symmetric_rates = 1;
3226 } else {
3227 wm8994->lrclk_shared[0] = 0;
3228 }
3229
3230 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3231 if (ret < 0) {
3232 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3233 goto err_irq;
9e6e96a1
MB		 3234 }
3235 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3236 wm8994->lrclk_shared[1] = 1;
3237 wm8994_dai[1].symmetric_rates = 1;
3238 } else {
3239 wm8994->lrclk_shared[1] = 0;
3240 }
3241
9e6e96a1
MB		 3242 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3243
9e6e96a1
MB		 3244 /* Latch volume updates (right only; we always do left then right). */
3245 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3246 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3247 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3248 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3249 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3250 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3251 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3252 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3253 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3254 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3255 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3256 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3257 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3258 WM8994_DAC1_VU, WM8994_DAC1_VU);
3259 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3260 WM8994_DAC2_VU, WM8994_DAC2_VU);
3261
3262 /* Set the low bit of the 3D stereo depth so TLV matches */
3263 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3264 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3265 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3266 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3267 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3268 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3269 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3270 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3271 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3272
d1ce6b20
MB		 3273 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3274 * behaviour on idle TDM clock cycles. */
3275 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3276 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3277
9e6e96a1
MB		 3278 wm8994_update_class_w(codec);
3279
f0fba2ad 3280 wm8994_handle_pdata(wm8994);
9e6e96a1 3281
f0fba2ad
LG		 3282 wm_hubs_add_analogue_controls(codec);
3283 snd_soc_add_controls(codec, wm8994_snd_controls,
3284 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3285 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3286 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3287
3288 switch (control->type) {
3289 case WM8994:
3290 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3291 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3292 if (wm8994->revision < 4) {
173efa09
DP		 3293 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3294 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
c52fd021
DP		 3295 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3296 ARRAY_SIZE(wm8994_dac_revd_widgets));
3297 } else {
173efa09
DP		 3298 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3299 ARRAY_SIZE(wm8994_lateclk_widgets));
c52fd021
DP		 3300 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3301 ARRAY_SIZE(wm8994_dac_widgets));
3302 }
c4431df0
MB		 3303 break;
3304 case WM8958:
3305 snd_soc_add_controls(codec, wm8958_snd_controls,
3306 ARRAY_SIZE(wm8958_snd_controls));
3307 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3308 ARRAY_SIZE(wm8958_dapm_widgets));
3309 break;
3310 }
3311
3312
f0fba2ad 3313 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3314 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3315
c4431df0
MB		 3316 switch (control->type) {
3317 case WM8994:
3318 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3319 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3320
173efa09 3321 if (wm8994->revision < 4) {
6ed8f148
MB		 3322 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3323 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3324 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3325 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3326 } else {
3327 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3328 ARRAY_SIZE(wm8994_lateclk_intercon));
3329 }
c4431df0
MB		 3330 break;
3331 case WM8958:
3332 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3333 ARRAY_SIZE(wm8958_intercon));
3334 break;
3335 }
3336
9e6e96a1
MB		 3337 return 0;
3338
88766984
MB		 3339err_irq:
3340 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3341 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3342 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3343 if (wm8994->micdet_irq)
3344 free_irq(wm8994->micdet_irq, wm8994);
9e6e96a1
MB		 3345err:
3346 kfree(wm8994);
3347 return ret;
3348}
3349
f0fba2ad 3350static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3351{
f0fba2ad 3352 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 3353 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 3354
3355 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3356
39fb51a1
MB		 3357 pm_runtime_disable(codec->dev);
3358
3a423157
MB		 3359 switch (control->type) {
3360 case WM8994:
9b7c525d
MB		 3361 if (wm8994->micdet_irq)
3362 free_irq(wm8994->micdet_irq, wm8994);
3a423157
MB		 3363 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3364 wm8994);
3365 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3366 wm8994);
3367 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3368 wm8994);
3369 break;
821edd2f
MB		 3370
3371 case WM8958:
9b7c525d
MB		 3372 if (wm8994->micdet_irq)
3373 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3374 break;
3a423157 3375 }
24fb2b11
AL		 3376 kfree(wm8994->retune_mobile_texts);
3377 kfree(wm8994->drc_texts);
9e6e96a1 3378 kfree(wm8994);
9e6e96a1
MB		 3379
3380 return 0;
3381}
3382
f0fba2ad
LG		 3383static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3384 .probe = wm8994_codec_probe,
3385 .remove = wm8994_codec_remove,
3386 .suspend = wm8994_suspend,
3387 .resume = wm8994_resume,
ca9aef50
MB		 3388 .read = wm8994_read,
3389 .write = wm8994_write,
eba19fdd
MB		 3390 .readable_register = wm8994_readable,
3391 .volatile_register = wm8994_volatile,
f0fba2ad 3392 .set_bias_level = wm8994_set_bias_level,
ca9aef50
MB		 3393
3394 .reg_cache_size = WM8994_CACHE_SIZE,
3395 .reg_cache_default = wm8994_reg_defaults,
3396 .reg_word_size = 2,
2e19b0c8 3397 .compress_type = SND_SOC_RBTREE_COMPRESSION,
f0fba2ad
LG		 3398};
3399
3400static int __devinit wm8994_probe(struct platform_device *pdev)
3401{
3402 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3403 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3404}
3405
3406static int __devexit wm8994_remove(struct platform_device *pdev)
3407{
3408 snd_soc_unregister_codec(&pdev->dev);
3409 return 0;
3410}
3411
9e6e96a1
MB		 3412static struct platform_driver wm8994_codec_driver = {
3413 .driver = {
3414 .name = "wm8994-codec",
3415 .owner = THIS_MODULE,
3416 },
f0fba2ad
LG		 3417 .probe = wm8994_probe,
3418 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3419};
3420
3421static __init int wm8994_init(void)
3422{
3423 return platform_driver_register(&wm8994_codec_driver);
3424}
3425module_init(wm8994_init);
3426
3427static __exit void wm8994_exit(void)
3428{
3429 platform_driver_unregister(&wm8994_codec_driver);
3430}
3431module_exit(wm8994_exit);
3432
3433
3434MODULE_DESCRIPTION("ASoC WM8994 driver");
3435MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3436MODULE_LICENSE("GPL");
3437MODULE_ALIAS("platform:wm8994-codec");
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