]>
Commit | Line | Data |
---|---|---|
9e6e96a1 MB |
1 | /* |
2 | * wm8994.c -- WM8994 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/i2c.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/consumer.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
9e6e96a1 MB |
23 | #include <sound/core.h> |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
27 | #include <sound/soc-dapm.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/tlv.h> | |
30 | ||
31 | #include <linux/mfd/wm8994/core.h> | |
32 | #include <linux/mfd/wm8994/registers.h> | |
33 | #include <linux/mfd/wm8994/pdata.h> | |
34 | #include <linux/mfd/wm8994/gpio.h> | |
35 | ||
36 | #include "wm8994.h" | |
37 | #include "wm_hubs.h" | |
38 | ||
9e6e96a1 MB |
39 | struct fll_config { |
40 | int src; | |
41 | int in; | |
42 | int out; | |
43 | }; | |
44 | ||
45 | #define WM8994_NUM_DRC 3 | |
46 | #define WM8994_NUM_EQ 3 | |
47 | ||
48 | static int wm8994_drc_base[] = { | |
49 | WM8994_AIF1_DRC1_1, | |
50 | WM8994_AIF1_DRC2_1, | |
51 | WM8994_AIF2_DRC_1, | |
52 | }; | |
53 | ||
54 | static int wm8994_retune_mobile_base[] = { | |
55 | WM8994_AIF1_DAC1_EQ_GAINS_1, | |
56 | WM8994_AIF1_DAC2_EQ_GAINS_1, | |
57 | WM8994_AIF2_EQ_GAINS_1, | |
58 | }; | |
59 | ||
60 | #define WM8994_REG_CACHE_SIZE 0x621 | |
61 | ||
88766984 MB |
62 | struct wm8994_micdet { |
63 | struct snd_soc_jack *jack; | |
64 | int det; | |
65 | int shrt; | |
66 | }; | |
67 | ||
9e6e96a1 MB |
68 | /* codec private data */ |
69 | struct wm8994_priv { | |
70 | struct wm_hubs_data hubs; | |
f0fba2ad LG |
71 | enum snd_soc_control_type control_type; |
72 | void *control_data; | |
73 | struct snd_soc_codec *codec; | |
9e6e96a1 MB |
74 | u16 reg_cache[WM8994_REG_CACHE_SIZE + 1]; |
75 | int sysclk[2]; | |
76 | int sysclk_rate[2]; | |
77 | int mclk[2]; | |
78 | int aifclk[2]; | |
79 | struct fll_config fll[2], fll_suspend[2]; | |
80 | ||
81 | int dac_rates[2]; | |
82 | int lrclk_shared[2]; | |
83 | ||
84 | /* Platform dependant DRC configuration */ | |
85 | const char **drc_texts; | |
86 | int drc_cfg[WM8994_NUM_DRC]; | |
87 | struct soc_enum drc_enum; | |
88 | ||
89 | /* Platform dependant ReTune mobile configuration */ | |
90 | int num_retune_mobile_texts; | |
91 | const char **retune_mobile_texts; | |
92 | int retune_mobile_cfg[WM8994_NUM_EQ]; | |
93 | struct soc_enum retune_mobile_enum; | |
94 | ||
88766984 MB |
95 | struct wm8994_micdet micdet[2]; |
96 | ||
b6b05691 | 97 | int revision; |
9e6e96a1 MB |
98 | struct wm8994_pdata *pdata; |
99 | }; | |
100 | ||
c14c05c1 JP |
101 | static const struct { |
102 | unsigned short readable; /* Mask of readable bits */ | |
103 | unsigned short writable; /* Mask of writable bits */ | |
9e6e96a1 | 104 | } access_masks[] = { |
c14c05c1 JP |
105 | { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */ |
106 | { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */ | |
107 | { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */ | |
108 | { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */ | |
109 | { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */ | |
110 | { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */ | |
111 | { 0x003F, 0x003F }, /* R6 - Power Management (6) */ | |
112 | { 0x0000, 0x0000 }, /* R7 */ | |
113 | { 0x0000, 0x0000 }, /* R8 */ | |
114 | { 0x0000, 0x0000 }, /* R9 */ | |
115 | { 0x0000, 0x0000 }, /* R10 */ | |
116 | { 0x0000, 0x0000 }, /* R11 */ | |
117 | { 0x0000, 0x0000 }, /* R12 */ | |
118 | { 0x0000, 0x0000 }, /* R13 */ | |
119 | { 0x0000, 0x0000 }, /* R14 */ | |
120 | { 0x0000, 0x0000 }, /* R15 */ | |
121 | { 0x0000, 0x0000 }, /* R16 */ | |
122 | { 0x0000, 0x0000 }, /* R17 */ | |
123 | { 0x0000, 0x0000 }, /* R18 */ | |
124 | { 0x0000, 0x0000 }, /* R19 */ | |
125 | { 0x0000, 0x0000 }, /* R20 */ | |
126 | { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */ | |
127 | { 0x0000, 0x0000 }, /* R22 */ | |
128 | { 0x0000, 0x0000 }, /* R23 */ | |
129 | { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */ | |
130 | { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */ | |
131 | { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */ | |
132 | { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */ | |
133 | { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */ | |
134 | { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */ | |
135 | { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */ | |
136 | { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */ | |
137 | { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */ | |
138 | { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */ | |
139 | { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */ | |
140 | { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */ | |
141 | { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */ | |
142 | { 0x003F, 0x003F }, /* R37 - ClassD */ | |
143 | { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */ | |
144 | { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */ | |
145 | { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */ | |
146 | { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */ | |
147 | { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */ | |
148 | { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */ | |
149 | { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */ | |
150 | { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */ | |
151 | { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */ | |
152 | { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */ | |
153 | { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */ | |
154 | { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */ | |
155 | { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */ | |
156 | { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */ | |
157 | { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */ | |
158 | { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */ | |
159 | { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */ | |
160 | { 0x00C1, 0x00C1 }, /* R55 - Additional Control */ | |
161 | { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */ | |
162 | { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */ | |
163 | { 0x00FF, 0x00FF }, /* R58 - MICBIAS */ | |
164 | { 0x000F, 0x000F }, /* R59 - LDO 1 */ | |
165 | { 0x0007, 0x0007 }, /* R60 - LDO 2 */ | |
166 | { 0x0000, 0x0000 }, /* R61 */ | |
167 | { 0x0000, 0x0000 }, /* R62 */ | |
168 | { 0x0000, 0x0000 }, /* R63 */ | |
169 | { 0x0000, 0x0000 }, /* R64 */ | |
170 | { 0x0000, 0x0000 }, /* R65 */ | |
171 | { 0x0000, 0x0000 }, /* R66 */ | |
172 | { 0x0000, 0x0000 }, /* R67 */ | |
173 | { 0x0000, 0x0000 }, /* R68 */ | |
174 | { 0x0000, 0x0000 }, /* R69 */ | |
175 | { 0x0000, 0x0000 }, /* R70 */ | |
176 | { 0x0000, 0x0000 }, /* R71 */ | |
177 | { 0x0000, 0x0000 }, /* R72 */ | |
178 | { 0x0000, 0x0000 }, /* R73 */ | |
179 | { 0x0000, 0x0000 }, /* R74 */ | |
180 | { 0x0000, 0x0000 }, /* R75 */ | |
181 | { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */ | |
182 | { 0x0000, 0x0000 }, /* R77 */ | |
183 | { 0x0000, 0x0000 }, /* R78 */ | |
184 | { 0x0000, 0x0000 }, /* R79 */ | |
185 | { 0x0000, 0x0000 }, /* R80 */ | |
186 | { 0x0301, 0x0301 }, /* R81 - Class W (1) */ | |
187 | { 0x0000, 0x0000 }, /* R82 */ | |
188 | { 0x0000, 0x0000 }, /* R83 */ | |
189 | { 0x333F, 0x333F }, /* R84 - DC Servo (1) */ | |
190 | { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */ | |
191 | { 0x0000, 0x0000 }, /* R86 */ | |
192 | { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */ | |
193 | { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */ | |
194 | { 0x0000, 0x0000 }, /* R89 */ | |
195 | { 0x0000, 0x0000 }, /* R90 */ | |
196 | { 0x0000, 0x0000 }, /* R91 */ | |
197 | { 0x0000, 0x0000 }, /* R92 */ | |
198 | { 0x0000, 0x0000 }, /* R93 */ | |
199 | { 0x0000, 0x0000 }, /* R94 */ | |
200 | { 0x0000, 0x0000 }, /* R95 */ | |
201 | { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */ | |
202 | { 0x0000, 0x0000 }, /* R97 */ | |
203 | { 0x0000, 0x0000 }, /* R98 */ | |
204 | { 0x0000, 0x0000 }, /* R99 */ | |
205 | { 0x0000, 0x0000 }, /* R100 */ | |
206 | { 0x0000, 0x0000 }, /* R101 */ | |
207 | { 0x0000, 0x0000 }, /* R102 */ | |
208 | { 0x0000, 0x0000 }, /* R103 */ | |
209 | { 0x0000, 0x0000 }, /* R104 */ | |
210 | { 0x0000, 0x0000 }, /* R105 */ | |
211 | { 0x0000, 0x0000 }, /* R106 */ | |
212 | { 0x0000, 0x0000 }, /* R107 */ | |
213 | { 0x0000, 0x0000 }, /* R108 */ | |
214 | { 0x0000, 0x0000 }, /* R109 */ | |
215 | { 0x0000, 0x0000 }, /* R110 */ | |
216 | { 0x0000, 0x0000 }, /* R111 */ | |
217 | { 0x0000, 0x0000 }, /* R112 */ | |
218 | { 0x0000, 0x0000 }, /* R113 */ | |
219 | { 0x0000, 0x0000 }, /* R114 */ | |
220 | { 0x0000, 0x0000 }, /* R115 */ | |
221 | { 0x0000, 0x0000 }, /* R116 */ | |
222 | { 0x0000, 0x0000 }, /* R117 */ | |
223 | { 0x0000, 0x0000 }, /* R118 */ | |
224 | { 0x0000, 0x0000 }, /* R119 */ | |
225 | { 0x0000, 0x0000 }, /* R120 */ | |
226 | { 0x0000, 0x0000 }, /* R121 */ | |
227 | { 0x0000, 0x0000 }, /* R122 */ | |
228 | { 0x0000, 0x0000 }, /* R123 */ | |
229 | { 0x0000, 0x0000 }, /* R124 */ | |
230 | { 0x0000, 0x0000 }, /* R125 */ | |
231 | { 0x0000, 0x0000 }, /* R126 */ | |
232 | { 0x0000, 0x0000 }, /* R127 */ | |
233 | { 0x0000, 0x0000 }, /* R128 */ | |
234 | { 0x0000, 0x0000 }, /* R129 */ | |
235 | { 0x0000, 0x0000 }, /* R130 */ | |
236 | { 0x0000, 0x0000 }, /* R131 */ | |
237 | { 0x0000, 0x0000 }, /* R132 */ | |
238 | { 0x0000, 0x0000 }, /* R133 */ | |
239 | { 0x0000, 0x0000 }, /* R134 */ | |
240 | { 0x0000, 0x0000 }, /* R135 */ | |
241 | { 0x0000, 0x0000 }, /* R136 */ | |
242 | { 0x0000, 0x0000 }, /* R137 */ | |
243 | { 0x0000, 0x0000 }, /* R138 */ | |
244 | { 0x0000, 0x0000 }, /* R139 */ | |
245 | { 0x0000, 0x0000 }, /* R140 */ | |
246 | { 0x0000, 0x0000 }, /* R141 */ | |
247 | { 0x0000, 0x0000 }, /* R142 */ | |
248 | { 0x0000, 0x0000 }, /* R143 */ | |
249 | { 0x0000, 0x0000 }, /* R144 */ | |
250 | { 0x0000, 0x0000 }, /* R145 */ | |
251 | { 0x0000, 0x0000 }, /* R146 */ | |
252 | { 0x0000, 0x0000 }, /* R147 */ | |
253 | { 0x0000, 0x0000 }, /* R148 */ | |
254 | { 0x0000, 0x0000 }, /* R149 */ | |
255 | { 0x0000, 0x0000 }, /* R150 */ | |
256 | { 0x0000, 0x0000 }, /* R151 */ | |
257 | { 0x0000, 0x0000 }, /* R152 */ | |
258 | { 0x0000, 0x0000 }, /* R153 */ | |
259 | { 0x0000, 0x0000 }, /* R154 */ | |
260 | { 0x0000, 0x0000 }, /* R155 */ | |
261 | { 0x0000, 0x0000 }, /* R156 */ | |
262 | { 0x0000, 0x0000 }, /* R157 */ | |
263 | { 0x0000, 0x0000 }, /* R158 */ | |
264 | { 0x0000, 0x0000 }, /* R159 */ | |
265 | { 0x0000, 0x0000 }, /* R160 */ | |
266 | { 0x0000, 0x0000 }, /* R161 */ | |
267 | { 0x0000, 0x0000 }, /* R162 */ | |
268 | { 0x0000, 0x0000 }, /* R163 */ | |
269 | { 0x0000, 0x0000 }, /* R164 */ | |
270 | { 0x0000, 0x0000 }, /* R165 */ | |
271 | { 0x0000, 0x0000 }, /* R166 */ | |
272 | { 0x0000, 0x0000 }, /* R167 */ | |
273 | { 0x0000, 0x0000 }, /* R168 */ | |
274 | { 0x0000, 0x0000 }, /* R169 */ | |
275 | { 0x0000, 0x0000 }, /* R170 */ | |
276 | { 0x0000, 0x0000 }, /* R171 */ | |
277 | { 0x0000, 0x0000 }, /* R172 */ | |
278 | { 0x0000, 0x0000 }, /* R173 */ | |
279 | { 0x0000, 0x0000 }, /* R174 */ | |
280 | { 0x0000, 0x0000 }, /* R175 */ | |
281 | { 0x0000, 0x0000 }, /* R176 */ | |
282 | { 0x0000, 0x0000 }, /* R177 */ | |
283 | { 0x0000, 0x0000 }, /* R178 */ | |
284 | { 0x0000, 0x0000 }, /* R179 */ | |
285 | { 0x0000, 0x0000 }, /* R180 */ | |
286 | { 0x0000, 0x0000 }, /* R181 */ | |
287 | { 0x0000, 0x0000 }, /* R182 */ | |
288 | { 0x0000, 0x0000 }, /* R183 */ | |
289 | { 0x0000, 0x0000 }, /* R184 */ | |
290 | { 0x0000, 0x0000 }, /* R185 */ | |
291 | { 0x0000, 0x0000 }, /* R186 */ | |
292 | { 0x0000, 0x0000 }, /* R187 */ | |
293 | { 0x0000, 0x0000 }, /* R188 */ | |
294 | { 0x0000, 0x0000 }, /* R189 */ | |
295 | { 0x0000, 0x0000 }, /* R190 */ | |
296 | { 0x0000, 0x0000 }, /* R191 */ | |
297 | { 0x0000, 0x0000 }, /* R192 */ | |
298 | { 0x0000, 0x0000 }, /* R193 */ | |
299 | { 0x0000, 0x0000 }, /* R194 */ | |
300 | { 0x0000, 0x0000 }, /* R195 */ | |
301 | { 0x0000, 0x0000 }, /* R196 */ | |
302 | { 0x0000, 0x0000 }, /* R197 */ | |
303 | { 0x0000, 0x0000 }, /* R198 */ | |
304 | { 0x0000, 0x0000 }, /* R199 */ | |
305 | { 0x0000, 0x0000 }, /* R200 */ | |
306 | { 0x0000, 0x0000 }, /* R201 */ | |
307 | { 0x0000, 0x0000 }, /* R202 */ | |
308 | { 0x0000, 0x0000 }, /* R203 */ | |
309 | { 0x0000, 0x0000 }, /* R204 */ | |
310 | { 0x0000, 0x0000 }, /* R205 */ | |
311 | { 0x0000, 0x0000 }, /* R206 */ | |
312 | { 0x0000, 0x0000 }, /* R207 */ | |
313 | { 0x0000, 0x0000 }, /* R208 */ | |
314 | { 0x0000, 0x0000 }, /* R209 */ | |
315 | { 0x0000, 0x0000 }, /* R210 */ | |
316 | { 0x0000, 0x0000 }, /* R211 */ | |
317 | { 0x0000, 0x0000 }, /* R212 */ | |
318 | { 0x0000, 0x0000 }, /* R213 */ | |
319 | { 0x0000, 0x0000 }, /* R214 */ | |
320 | { 0x0000, 0x0000 }, /* R215 */ | |
321 | { 0x0000, 0x0000 }, /* R216 */ | |
322 | { 0x0000, 0x0000 }, /* R217 */ | |
323 | { 0x0000, 0x0000 }, /* R218 */ | |
324 | { 0x0000, 0x0000 }, /* R219 */ | |
325 | { 0x0000, 0x0000 }, /* R220 */ | |
326 | { 0x0000, 0x0000 }, /* R221 */ | |
327 | { 0x0000, 0x0000 }, /* R222 */ | |
328 | { 0x0000, 0x0000 }, /* R223 */ | |
329 | { 0x0000, 0x0000 }, /* R224 */ | |
330 | { 0x0000, 0x0000 }, /* R225 */ | |
331 | { 0x0000, 0x0000 }, /* R226 */ | |
332 | { 0x0000, 0x0000 }, /* R227 */ | |
333 | { 0x0000, 0x0000 }, /* R228 */ | |
334 | { 0x0000, 0x0000 }, /* R229 */ | |
335 | { 0x0000, 0x0000 }, /* R230 */ | |
336 | { 0x0000, 0x0000 }, /* R231 */ | |
337 | { 0x0000, 0x0000 }, /* R232 */ | |
338 | { 0x0000, 0x0000 }, /* R233 */ | |
339 | { 0x0000, 0x0000 }, /* R234 */ | |
340 | { 0x0000, 0x0000 }, /* R235 */ | |
341 | { 0x0000, 0x0000 }, /* R236 */ | |
342 | { 0x0000, 0x0000 }, /* R237 */ | |
343 | { 0x0000, 0x0000 }, /* R238 */ | |
344 | { 0x0000, 0x0000 }, /* R239 */ | |
345 | { 0x0000, 0x0000 }, /* R240 */ | |
346 | { 0x0000, 0x0000 }, /* R241 */ | |
347 | { 0x0000, 0x0000 }, /* R242 */ | |
348 | { 0x0000, 0x0000 }, /* R243 */ | |
349 | { 0x0000, 0x0000 }, /* R244 */ | |
350 | { 0x0000, 0x0000 }, /* R245 */ | |
351 | { 0x0000, 0x0000 }, /* R246 */ | |
352 | { 0x0000, 0x0000 }, /* R247 */ | |
353 | { 0x0000, 0x0000 }, /* R248 */ | |
354 | { 0x0000, 0x0000 }, /* R249 */ | |
355 | { 0x0000, 0x0000 }, /* R250 */ | |
356 | { 0x0000, 0x0000 }, /* R251 */ | |
357 | { 0x0000, 0x0000 }, /* R252 */ | |
358 | { 0x0000, 0x0000 }, /* R253 */ | |
359 | { 0x0000, 0x0000 }, /* R254 */ | |
360 | { 0x0000, 0x0000 }, /* R255 */ | |
361 | { 0x000F, 0x0000 }, /* R256 - Chip Revision */ | |
362 | { 0x0074, 0x0074 }, /* R257 - Control Interface */ | |
363 | { 0x0000, 0x0000 }, /* R258 */ | |
364 | { 0x0000, 0x0000 }, /* R259 */ | |
365 | { 0x0000, 0x0000 }, /* R260 */ | |
366 | { 0x0000, 0x0000 }, /* R261 */ | |
367 | { 0x0000, 0x0000 }, /* R262 */ | |
368 | { 0x0000, 0x0000 }, /* R263 */ | |
369 | { 0x0000, 0x0000 }, /* R264 */ | |
370 | { 0x0000, 0x0000 }, /* R265 */ | |
371 | { 0x0000, 0x0000 }, /* R266 */ | |
372 | { 0x0000, 0x0000 }, /* R267 */ | |
373 | { 0x0000, 0x0000 }, /* R268 */ | |
374 | { 0x0000, 0x0000 }, /* R269 */ | |
375 | { 0x0000, 0x0000 }, /* R270 */ | |
376 | { 0x0000, 0x0000 }, /* R271 */ | |
377 | { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */ | |
378 | { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ | |
379 | { 0x0000, 0x0000 }, /* R274 */ | |
380 | { 0x0000, 0x0000 }, /* R275 */ | |
381 | { 0x0000, 0x0000 }, /* R276 */ | |
382 | { 0x0000, 0x0000 }, /* R277 */ | |
383 | { 0x0000, 0x0000 }, /* R278 */ | |
384 | { 0x0000, 0x0000 }, /* R279 */ | |
385 | { 0x0000, 0x0000 }, /* R280 */ | |
386 | { 0x0000, 0x0000 }, /* R281 */ | |
387 | { 0x0000, 0x0000 }, /* R282 */ | |
388 | { 0x0000, 0x0000 }, /* R283 */ | |
389 | { 0x0000, 0x0000 }, /* R284 */ | |
390 | { 0x0000, 0x0000 }, /* R285 */ | |
391 | { 0x0000, 0x0000 }, /* R286 */ | |
392 | { 0x0000, 0x0000 }, /* R287 */ | |
393 | { 0x0000, 0x0000 }, /* R288 */ | |
394 | { 0x0000, 0x0000 }, /* R289 */ | |
395 | { 0x0000, 0x0000 }, /* R290 */ | |
396 | { 0x0000, 0x0000 }, /* R291 */ | |
397 | { 0x0000, 0x0000 }, /* R292 */ | |
398 | { 0x0000, 0x0000 }, /* R293 */ | |
399 | { 0x0000, 0x0000 }, /* R294 */ | |
400 | { 0x0000, 0x0000 }, /* R295 */ | |
401 | { 0x0000, 0x0000 }, /* R296 */ | |
402 | { 0x0000, 0x0000 }, /* R297 */ | |
403 | { 0x0000, 0x0000 }, /* R298 */ | |
404 | { 0x0000, 0x0000 }, /* R299 */ | |
405 | { 0x0000, 0x0000 }, /* R300 */ | |
406 | { 0x0000, 0x0000 }, /* R301 */ | |
407 | { 0x0000, 0x0000 }, /* R302 */ | |
408 | { 0x0000, 0x0000 }, /* R303 */ | |
409 | { 0x0000, 0x0000 }, /* R304 */ | |
410 | { 0x0000, 0x0000 }, /* R305 */ | |
411 | { 0x0000, 0x0000 }, /* R306 */ | |
412 | { 0x0000, 0x0000 }, /* R307 */ | |
413 | { 0x0000, 0x0000 }, /* R308 */ | |
414 | { 0x0000, 0x0000 }, /* R309 */ | |
415 | { 0x0000, 0x0000 }, /* R310 */ | |
416 | { 0x0000, 0x0000 }, /* R311 */ | |
417 | { 0x0000, 0x0000 }, /* R312 */ | |
418 | { 0x0000, 0x0000 }, /* R313 */ | |
419 | { 0x0000, 0x0000 }, /* R314 */ | |
420 | { 0x0000, 0x0000 }, /* R315 */ | |
421 | { 0x0000, 0x0000 }, /* R316 */ | |
422 | { 0x0000, 0x0000 }, /* R317 */ | |
423 | { 0x0000, 0x0000 }, /* R318 */ | |
424 | { 0x0000, 0x0000 }, /* R319 */ | |
425 | { 0x0000, 0x0000 }, /* R320 */ | |
426 | { 0x0000, 0x0000 }, /* R321 */ | |
427 | { 0x0000, 0x0000 }, /* R322 */ | |
428 | { 0x0000, 0x0000 }, /* R323 */ | |
429 | { 0x0000, 0x0000 }, /* R324 */ | |
430 | { 0x0000, 0x0000 }, /* R325 */ | |
431 | { 0x0000, 0x0000 }, /* R326 */ | |
432 | { 0x0000, 0x0000 }, /* R327 */ | |
433 | { 0x0000, 0x0000 }, /* R328 */ | |
434 | { 0x0000, 0x0000 }, /* R329 */ | |
435 | { 0x0000, 0x0000 }, /* R330 */ | |
436 | { 0x0000, 0x0000 }, /* R331 */ | |
437 | { 0x0000, 0x0000 }, /* R332 */ | |
438 | { 0x0000, 0x0000 }, /* R333 */ | |
439 | { 0x0000, 0x0000 }, /* R334 */ | |
440 | { 0x0000, 0x0000 }, /* R335 */ | |
441 | { 0x0000, 0x0000 }, /* R336 */ | |
442 | { 0x0000, 0x0000 }, /* R337 */ | |
443 | { 0x0000, 0x0000 }, /* R338 */ | |
444 | { 0x0000, 0x0000 }, /* R339 */ | |
445 | { 0x0000, 0x0000 }, /* R340 */ | |
446 | { 0x0000, 0x0000 }, /* R341 */ | |
447 | { 0x0000, 0x0000 }, /* R342 */ | |
448 | { 0x0000, 0x0000 }, /* R343 */ | |
449 | { 0x0000, 0x0000 }, /* R344 */ | |
450 | { 0x0000, 0x0000 }, /* R345 */ | |
451 | { 0x0000, 0x0000 }, /* R346 */ | |
452 | { 0x0000, 0x0000 }, /* R347 */ | |
453 | { 0x0000, 0x0000 }, /* R348 */ | |
454 | { 0x0000, 0x0000 }, /* R349 */ | |
455 | { 0x0000, 0x0000 }, /* R350 */ | |
456 | { 0x0000, 0x0000 }, /* R351 */ | |
457 | { 0x0000, 0x0000 }, /* R352 */ | |
458 | { 0x0000, 0x0000 }, /* R353 */ | |
459 | { 0x0000, 0x0000 }, /* R354 */ | |
460 | { 0x0000, 0x0000 }, /* R355 */ | |
461 | { 0x0000, 0x0000 }, /* R356 */ | |
462 | { 0x0000, 0x0000 }, /* R357 */ | |
463 | { 0x0000, 0x0000 }, /* R358 */ | |
464 | { 0x0000, 0x0000 }, /* R359 */ | |
465 | { 0x0000, 0x0000 }, /* R360 */ | |
466 | { 0x0000, 0x0000 }, /* R361 */ | |
467 | { 0x0000, 0x0000 }, /* R362 */ | |
468 | { 0x0000, 0x0000 }, /* R363 */ | |
469 | { 0x0000, 0x0000 }, /* R364 */ | |
470 | { 0x0000, 0x0000 }, /* R365 */ | |
471 | { 0x0000, 0x0000 }, /* R366 */ | |
472 | { 0x0000, 0x0000 }, /* R367 */ | |
473 | { 0x0000, 0x0000 }, /* R368 */ | |
474 | { 0x0000, 0x0000 }, /* R369 */ | |
475 | { 0x0000, 0x0000 }, /* R370 */ | |
476 | { 0x0000, 0x0000 }, /* R371 */ | |
477 | { 0x0000, 0x0000 }, /* R372 */ | |
478 | { 0x0000, 0x0000 }, /* R373 */ | |
479 | { 0x0000, 0x0000 }, /* R374 */ | |
480 | { 0x0000, 0x0000 }, /* R375 */ | |
481 | { 0x0000, 0x0000 }, /* R376 */ | |
482 | { 0x0000, 0x0000 }, /* R377 */ | |
483 | { 0x0000, 0x0000 }, /* R378 */ | |
484 | { 0x0000, 0x0000 }, /* R379 */ | |
485 | { 0x0000, 0x0000 }, /* R380 */ | |
486 | { 0x0000, 0x0000 }, /* R381 */ | |
487 | { 0x0000, 0x0000 }, /* R382 */ | |
488 | { 0x0000, 0x0000 }, /* R383 */ | |
489 | { 0x0000, 0x0000 }, /* R384 */ | |
490 | { 0x0000, 0x0000 }, /* R385 */ | |
491 | { 0x0000, 0x0000 }, /* R386 */ | |
492 | { 0x0000, 0x0000 }, /* R387 */ | |
493 | { 0x0000, 0x0000 }, /* R388 */ | |
494 | { 0x0000, 0x0000 }, /* R389 */ | |
495 | { 0x0000, 0x0000 }, /* R390 */ | |
496 | { 0x0000, 0x0000 }, /* R391 */ | |
497 | { 0x0000, 0x0000 }, /* R392 */ | |
498 | { 0x0000, 0x0000 }, /* R393 */ | |
499 | { 0x0000, 0x0000 }, /* R394 */ | |
500 | { 0x0000, 0x0000 }, /* R395 */ | |
501 | { 0x0000, 0x0000 }, /* R396 */ | |
502 | { 0x0000, 0x0000 }, /* R397 */ | |
503 | { 0x0000, 0x0000 }, /* R398 */ | |
504 | { 0x0000, 0x0000 }, /* R399 */ | |
505 | { 0x0000, 0x0000 }, /* R400 */ | |
506 | { 0x0000, 0x0000 }, /* R401 */ | |
507 | { 0x0000, 0x0000 }, /* R402 */ | |
508 | { 0x0000, 0x0000 }, /* R403 */ | |
509 | { 0x0000, 0x0000 }, /* R404 */ | |
510 | { 0x0000, 0x0000 }, /* R405 */ | |
511 | { 0x0000, 0x0000 }, /* R406 */ | |
512 | { 0x0000, 0x0000 }, /* R407 */ | |
513 | { 0x0000, 0x0000 }, /* R408 */ | |
514 | { 0x0000, 0x0000 }, /* R409 */ | |
515 | { 0x0000, 0x0000 }, /* R410 */ | |
516 | { 0x0000, 0x0000 }, /* R411 */ | |
517 | { 0x0000, 0x0000 }, /* R412 */ | |
518 | { 0x0000, 0x0000 }, /* R413 */ | |
519 | { 0x0000, 0x0000 }, /* R414 */ | |
520 | { 0x0000, 0x0000 }, /* R415 */ | |
521 | { 0x0000, 0x0000 }, /* R416 */ | |
522 | { 0x0000, 0x0000 }, /* R417 */ | |
523 | { 0x0000, 0x0000 }, /* R418 */ | |
524 | { 0x0000, 0x0000 }, /* R419 */ | |
525 | { 0x0000, 0x0000 }, /* R420 */ | |
526 | { 0x0000, 0x0000 }, /* R421 */ | |
527 | { 0x0000, 0x0000 }, /* R422 */ | |
528 | { 0x0000, 0x0000 }, /* R423 */ | |
529 | { 0x0000, 0x0000 }, /* R424 */ | |
530 | { 0x0000, 0x0000 }, /* R425 */ | |
531 | { 0x0000, 0x0000 }, /* R426 */ | |
532 | { 0x0000, 0x0000 }, /* R427 */ | |
533 | { 0x0000, 0x0000 }, /* R428 */ | |
534 | { 0x0000, 0x0000 }, /* R429 */ | |
535 | { 0x0000, 0x0000 }, /* R430 */ | |
536 | { 0x0000, 0x0000 }, /* R431 */ | |
537 | { 0x0000, 0x0000 }, /* R432 */ | |
538 | { 0x0000, 0x0000 }, /* R433 */ | |
539 | { 0x0000, 0x0000 }, /* R434 */ | |
540 | { 0x0000, 0x0000 }, /* R435 */ | |
541 | { 0x0000, 0x0000 }, /* R436 */ | |
542 | { 0x0000, 0x0000 }, /* R437 */ | |
543 | { 0x0000, 0x0000 }, /* R438 */ | |
544 | { 0x0000, 0x0000 }, /* R439 */ | |
545 | { 0x0000, 0x0000 }, /* R440 */ | |
546 | { 0x0000, 0x0000 }, /* R441 */ | |
547 | { 0x0000, 0x0000 }, /* R442 */ | |
548 | { 0x0000, 0x0000 }, /* R443 */ | |
549 | { 0x0000, 0x0000 }, /* R444 */ | |
550 | { 0x0000, 0x0000 }, /* R445 */ | |
551 | { 0x0000, 0x0000 }, /* R446 */ | |
552 | { 0x0000, 0x0000 }, /* R447 */ | |
553 | { 0x0000, 0x0000 }, /* R448 */ | |
554 | { 0x0000, 0x0000 }, /* R449 */ | |
555 | { 0x0000, 0x0000 }, /* R450 */ | |
556 | { 0x0000, 0x0000 }, /* R451 */ | |
557 | { 0x0000, 0x0000 }, /* R452 */ | |
558 | { 0x0000, 0x0000 }, /* R453 */ | |
559 | { 0x0000, 0x0000 }, /* R454 */ | |
560 | { 0x0000, 0x0000 }, /* R455 */ | |
561 | { 0x0000, 0x0000 }, /* R456 */ | |
562 | { 0x0000, 0x0000 }, /* R457 */ | |
563 | { 0x0000, 0x0000 }, /* R458 */ | |
564 | { 0x0000, 0x0000 }, /* R459 */ | |
565 | { 0x0000, 0x0000 }, /* R460 */ | |
566 | { 0x0000, 0x0000 }, /* R461 */ | |
567 | { 0x0000, 0x0000 }, /* R462 */ | |
568 | { 0x0000, 0x0000 }, /* R463 */ | |
569 | { 0x0000, 0x0000 }, /* R464 */ | |
570 | { 0x0000, 0x0000 }, /* R465 */ | |
571 | { 0x0000, 0x0000 }, /* R466 */ | |
572 | { 0x0000, 0x0000 }, /* R467 */ | |
573 | { 0x0000, 0x0000 }, /* R468 */ | |
574 | { 0x0000, 0x0000 }, /* R469 */ | |
575 | { 0x0000, 0x0000 }, /* R470 */ | |
576 | { 0x0000, 0x0000 }, /* R471 */ | |
577 | { 0x0000, 0x0000 }, /* R472 */ | |
578 | { 0x0000, 0x0000 }, /* R473 */ | |
579 | { 0x0000, 0x0000 }, /* R474 */ | |
580 | { 0x0000, 0x0000 }, /* R475 */ | |
581 | { 0x0000, 0x0000 }, /* R476 */ | |
582 | { 0x0000, 0x0000 }, /* R477 */ | |
583 | { 0x0000, 0x0000 }, /* R478 */ | |
584 | { 0x0000, 0x0000 }, /* R479 */ | |
585 | { 0x0000, 0x0000 }, /* R480 */ | |
586 | { 0x0000, 0x0000 }, /* R481 */ | |
587 | { 0x0000, 0x0000 }, /* R482 */ | |
588 | { 0x0000, 0x0000 }, /* R483 */ | |
589 | { 0x0000, 0x0000 }, /* R484 */ | |
590 | { 0x0000, 0x0000 }, /* R485 */ | |
591 | { 0x0000, 0x0000 }, /* R486 */ | |
592 | { 0x0000, 0x0000 }, /* R487 */ | |
593 | { 0x0000, 0x0000 }, /* R488 */ | |
594 | { 0x0000, 0x0000 }, /* R489 */ | |
595 | { 0x0000, 0x0000 }, /* R490 */ | |
596 | { 0x0000, 0x0000 }, /* R491 */ | |
597 | { 0x0000, 0x0000 }, /* R492 */ | |
598 | { 0x0000, 0x0000 }, /* R493 */ | |
599 | { 0x0000, 0x0000 }, /* R494 */ | |
600 | { 0x0000, 0x0000 }, /* R495 */ | |
601 | { 0x0000, 0x0000 }, /* R496 */ | |
602 | { 0x0000, 0x0000 }, /* R497 */ | |
603 | { 0x0000, 0x0000 }, /* R498 */ | |
604 | { 0x0000, 0x0000 }, /* R499 */ | |
605 | { 0x0000, 0x0000 }, /* R500 */ | |
606 | { 0x0000, 0x0000 }, /* R501 */ | |
607 | { 0x0000, 0x0000 }, /* R502 */ | |
608 | { 0x0000, 0x0000 }, /* R503 */ | |
609 | { 0x0000, 0x0000 }, /* R504 */ | |
610 | { 0x0000, 0x0000 }, /* R505 */ | |
611 | { 0x0000, 0x0000 }, /* R506 */ | |
612 | { 0x0000, 0x0000 }, /* R507 */ | |
613 | { 0x0000, 0x0000 }, /* R508 */ | |
614 | { 0x0000, 0x0000 }, /* R509 */ | |
615 | { 0x0000, 0x0000 }, /* R510 */ | |
616 | { 0x0000, 0x0000 }, /* R511 */ | |
617 | { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */ | |
618 | { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */ | |
619 | { 0x0000, 0x0000 }, /* R514 */ | |
620 | { 0x0000, 0x0000 }, /* R515 */ | |
621 | { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */ | |
622 | { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */ | |
623 | { 0x0000, 0x0000 }, /* R518 */ | |
624 | { 0x0000, 0x0000 }, /* R519 */ | |
625 | { 0x001F, 0x001F }, /* R520 - Clocking (1) */ | |
626 | { 0x0777, 0x0777 }, /* R521 - Clocking (2) */ | |
627 | { 0x0000, 0x0000 }, /* R522 */ | |
628 | { 0x0000, 0x0000 }, /* R523 */ | |
629 | { 0x0000, 0x0000 }, /* R524 */ | |
630 | { 0x0000, 0x0000 }, /* R525 */ | |
631 | { 0x0000, 0x0000 }, /* R526 */ | |
632 | { 0x0000, 0x0000 }, /* R527 */ | |
633 | { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */ | |
634 | { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */ | |
635 | { 0x000F, 0x0000 }, /* R530 - Rate Status */ | |
636 | { 0x0000, 0x0000 }, /* R531 */ | |
637 | { 0x0000, 0x0000 }, /* R532 */ | |
638 | { 0x0000, 0x0000 }, /* R533 */ | |
639 | { 0x0000, 0x0000 }, /* R534 */ | |
640 | { 0x0000, 0x0000 }, /* R535 */ | |
641 | { 0x0000, 0x0000 }, /* R536 */ | |
642 | { 0x0000, 0x0000 }, /* R537 */ | |
643 | { 0x0000, 0x0000 }, /* R538 */ | |
644 | { 0x0000, 0x0000 }, /* R539 */ | |
645 | { 0x0000, 0x0000 }, /* R540 */ | |
646 | { 0x0000, 0x0000 }, /* R541 */ | |
647 | { 0x0000, 0x0000 }, /* R542 */ | |
648 | { 0x0000, 0x0000 }, /* R543 */ | |
649 | { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */ | |
650 | { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */ | |
651 | { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */ | |
652 | { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */ | |
653 | { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */ | |
654 | { 0x0000, 0x0000 }, /* R549 */ | |
655 | { 0x0000, 0x0000 }, /* R550 */ | |
656 | { 0x0000, 0x0000 }, /* R551 */ | |
657 | { 0x0000, 0x0000 }, /* R552 */ | |
658 | { 0x0000, 0x0000 }, /* R553 */ | |
659 | { 0x0000, 0x0000 }, /* R554 */ | |
660 | { 0x0000, 0x0000 }, /* R555 */ | |
661 | { 0x0000, 0x0000 }, /* R556 */ | |
662 | { 0x0000, 0x0000 }, /* R557 */ | |
663 | { 0x0000, 0x0000 }, /* R558 */ | |
664 | { 0x0000, 0x0000 }, /* R559 */ | |
665 | { 0x0000, 0x0000 }, /* R560 */ | |
666 | { 0x0000, 0x0000 }, /* R561 */ | |
667 | { 0x0000, 0x0000 }, /* R562 */ | |
668 | { 0x0000, 0x0000 }, /* R563 */ | |
669 | { 0x0000, 0x0000 }, /* R564 */ | |
670 | { 0x0000, 0x0000 }, /* R565 */ | |
671 | { 0x0000, 0x0000 }, /* R566 */ | |
672 | { 0x0000, 0x0000 }, /* R567 */ | |
673 | { 0x0000, 0x0000 }, /* R568 */ | |
674 | { 0x0000, 0x0000 }, /* R569 */ | |
675 | { 0x0000, 0x0000 }, /* R570 */ | |
676 | { 0x0000, 0x0000 }, /* R571 */ | |
677 | { 0x0000, 0x0000 }, /* R572 */ | |
678 | { 0x0000, 0x0000 }, /* R573 */ | |
679 | { 0x0000, 0x0000 }, /* R574 */ | |
680 | { 0x0000, 0x0000 }, /* R575 */ | |
681 | { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */ | |
682 | { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */ | |
683 | { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */ | |
684 | { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */ | |
685 | { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */ | |
686 | { 0x0000, 0x0000 }, /* R581 */ | |
687 | { 0x0000, 0x0000 }, /* R582 */ | |
688 | { 0x0000, 0x0000 }, /* R583 */ | |
689 | { 0x0000, 0x0000 }, /* R584 */ | |
690 | { 0x0000, 0x0000 }, /* R585 */ | |
691 | { 0x0000, 0x0000 }, /* R586 */ | |
692 | { 0x0000, 0x0000 }, /* R587 */ | |
693 | { 0x0000, 0x0000 }, /* R588 */ | |
694 | { 0x0000, 0x0000 }, /* R589 */ | |
695 | { 0x0000, 0x0000 }, /* R590 */ | |
696 | { 0x0000, 0x0000 }, /* R591 */ | |
697 | { 0x0000, 0x0000 }, /* R592 */ | |
698 | { 0x0000, 0x0000 }, /* R593 */ | |
699 | { 0x0000, 0x0000 }, /* R594 */ | |
700 | { 0x0000, 0x0000 }, /* R595 */ | |
701 | { 0x0000, 0x0000 }, /* R596 */ | |
702 | { 0x0000, 0x0000 }, /* R597 */ | |
703 | { 0x0000, 0x0000 }, /* R598 */ | |
704 | { 0x0000, 0x0000 }, /* R599 */ | |
705 | { 0x0000, 0x0000 }, /* R600 */ | |
706 | { 0x0000, 0x0000 }, /* R601 */ | |
707 | { 0x0000, 0x0000 }, /* R602 */ | |
708 | { 0x0000, 0x0000 }, /* R603 */ | |
709 | { 0x0000, 0x0000 }, /* R604 */ | |
710 | { 0x0000, 0x0000 }, /* R605 */ | |
711 | { 0x0000, 0x0000 }, /* R606 */ | |
712 | { 0x0000, 0x0000 }, /* R607 */ | |
713 | { 0x0000, 0x0000 }, /* R608 */ | |
714 | { 0x0000, 0x0000 }, /* R609 */ | |
715 | { 0x0000, 0x0000 }, /* R610 */ | |
716 | { 0x0000, 0x0000 }, /* R611 */ | |
717 | { 0x0000, 0x0000 }, /* R612 */ | |
718 | { 0x0000, 0x0000 }, /* R613 */ | |
719 | { 0x0000, 0x0000 }, /* R614 */ | |
720 | { 0x0000, 0x0000 }, /* R615 */ | |
721 | { 0x0000, 0x0000 }, /* R616 */ | |
722 | { 0x0000, 0x0000 }, /* R617 */ | |
723 | { 0x0000, 0x0000 }, /* R618 */ | |
724 | { 0x0000, 0x0000 }, /* R619 */ | |
725 | { 0x0000, 0x0000 }, /* R620 */ | |
726 | { 0x0000, 0x0000 }, /* R621 */ | |
727 | { 0x0000, 0x0000 }, /* R622 */ | |
728 | { 0x0000, 0x0000 }, /* R623 */ | |
729 | { 0x0000, 0x0000 }, /* R624 */ | |
730 | { 0x0000, 0x0000 }, /* R625 */ | |
731 | { 0x0000, 0x0000 }, /* R626 */ | |
732 | { 0x0000, 0x0000 }, /* R627 */ | |
733 | { 0x0000, 0x0000 }, /* R628 */ | |
734 | { 0x0000, 0x0000 }, /* R629 */ | |
735 | { 0x0000, 0x0000 }, /* R630 */ | |
736 | { 0x0000, 0x0000 }, /* R631 */ | |
737 | { 0x0000, 0x0000 }, /* R632 */ | |
738 | { 0x0000, 0x0000 }, /* R633 */ | |
739 | { 0x0000, 0x0000 }, /* R634 */ | |
740 | { 0x0000, 0x0000 }, /* R635 */ | |
741 | { 0x0000, 0x0000 }, /* R636 */ | |
742 | { 0x0000, 0x0000 }, /* R637 */ | |
743 | { 0x0000, 0x0000 }, /* R638 */ | |
744 | { 0x0000, 0x0000 }, /* R639 */ | |
745 | { 0x0000, 0x0000 }, /* R640 */ | |
746 | { 0x0000, 0x0000 }, /* R641 */ | |
747 | { 0x0000, 0x0000 }, /* R642 */ | |
748 | { 0x0000, 0x0000 }, /* R643 */ | |
749 | { 0x0000, 0x0000 }, /* R644 */ | |
750 | { 0x0000, 0x0000 }, /* R645 */ | |
751 | { 0x0000, 0x0000 }, /* R646 */ | |
752 | { 0x0000, 0x0000 }, /* R647 */ | |
753 | { 0x0000, 0x0000 }, /* R648 */ | |
754 | { 0x0000, 0x0000 }, /* R649 */ | |
755 | { 0x0000, 0x0000 }, /* R650 */ | |
756 | { 0x0000, 0x0000 }, /* R651 */ | |
757 | { 0x0000, 0x0000 }, /* R652 */ | |
758 | { 0x0000, 0x0000 }, /* R653 */ | |
759 | { 0x0000, 0x0000 }, /* R654 */ | |
760 | { 0x0000, 0x0000 }, /* R655 */ | |
761 | { 0x0000, 0x0000 }, /* R656 */ | |
762 | { 0x0000, 0x0000 }, /* R657 */ | |
763 | { 0x0000, 0x0000 }, /* R658 */ | |
764 | { 0x0000, 0x0000 }, /* R659 */ | |
765 | { 0x0000, 0x0000 }, /* R660 */ | |
766 | { 0x0000, 0x0000 }, /* R661 */ | |
767 | { 0x0000, 0x0000 }, /* R662 */ | |
768 | { 0x0000, 0x0000 }, /* R663 */ | |
769 | { 0x0000, 0x0000 }, /* R664 */ | |
770 | { 0x0000, 0x0000 }, /* R665 */ | |
771 | { 0x0000, 0x0000 }, /* R666 */ | |
772 | { 0x0000, 0x0000 }, /* R667 */ | |
773 | { 0x0000, 0x0000 }, /* R668 */ | |
774 | { 0x0000, 0x0000 }, /* R669 */ | |
775 | { 0x0000, 0x0000 }, /* R670 */ | |
776 | { 0x0000, 0x0000 }, /* R671 */ | |
777 | { 0x0000, 0x0000 }, /* R672 */ | |
778 | { 0x0000, 0x0000 }, /* R673 */ | |
779 | { 0x0000, 0x0000 }, /* R674 */ | |
780 | { 0x0000, 0x0000 }, /* R675 */ | |
781 | { 0x0000, 0x0000 }, /* R676 */ | |
782 | { 0x0000, 0x0000 }, /* R677 */ | |
783 | { 0x0000, 0x0000 }, /* R678 */ | |
784 | { 0x0000, 0x0000 }, /* R679 */ | |
785 | { 0x0000, 0x0000 }, /* R680 */ | |
786 | { 0x0000, 0x0000 }, /* R681 */ | |
787 | { 0x0000, 0x0000 }, /* R682 */ | |
788 | { 0x0000, 0x0000 }, /* R683 */ | |
789 | { 0x0000, 0x0000 }, /* R684 */ | |
790 | { 0x0000, 0x0000 }, /* R685 */ | |
791 | { 0x0000, 0x0000 }, /* R686 */ | |
792 | { 0x0000, 0x0000 }, /* R687 */ | |
793 | { 0x0000, 0x0000 }, /* R688 */ | |
794 | { 0x0000, 0x0000 }, /* R689 */ | |
795 | { 0x0000, 0x0000 }, /* R690 */ | |
796 | { 0x0000, 0x0000 }, /* R691 */ | |
797 | { 0x0000, 0x0000 }, /* R692 */ | |
798 | { 0x0000, 0x0000 }, /* R693 */ | |
799 | { 0x0000, 0x0000 }, /* R694 */ | |
800 | { 0x0000, 0x0000 }, /* R695 */ | |
801 | { 0x0000, 0x0000 }, /* R696 */ | |
802 | { 0x0000, 0x0000 }, /* R697 */ | |
803 | { 0x0000, 0x0000 }, /* R698 */ | |
804 | { 0x0000, 0x0000 }, /* R699 */ | |
805 | { 0x0000, 0x0000 }, /* R700 */ | |
806 | { 0x0000, 0x0000 }, /* R701 */ | |
807 | { 0x0000, 0x0000 }, /* R702 */ | |
808 | { 0x0000, 0x0000 }, /* R703 */ | |
809 | { 0x0000, 0x0000 }, /* R704 */ | |
810 | { 0x0000, 0x0000 }, /* R705 */ | |
811 | { 0x0000, 0x0000 }, /* R706 */ | |
812 | { 0x0000, 0x0000 }, /* R707 */ | |
813 | { 0x0000, 0x0000 }, /* R708 */ | |
814 | { 0x0000, 0x0000 }, /* R709 */ | |
815 | { 0x0000, 0x0000 }, /* R710 */ | |
816 | { 0x0000, 0x0000 }, /* R711 */ | |
817 | { 0x0000, 0x0000 }, /* R712 */ | |
818 | { 0x0000, 0x0000 }, /* R713 */ | |
819 | { 0x0000, 0x0000 }, /* R714 */ | |
820 | { 0x0000, 0x0000 }, /* R715 */ | |
821 | { 0x0000, 0x0000 }, /* R716 */ | |
822 | { 0x0000, 0x0000 }, /* R717 */ | |
823 | { 0x0000, 0x0000 }, /* R718 */ | |
824 | { 0x0000, 0x0000 }, /* R719 */ | |
825 | { 0x0000, 0x0000 }, /* R720 */ | |
826 | { 0x0000, 0x0000 }, /* R721 */ | |
827 | { 0x0000, 0x0000 }, /* R722 */ | |
828 | { 0x0000, 0x0000 }, /* R723 */ | |
829 | { 0x0000, 0x0000 }, /* R724 */ | |
830 | { 0x0000, 0x0000 }, /* R725 */ | |
831 | { 0x0000, 0x0000 }, /* R726 */ | |
832 | { 0x0000, 0x0000 }, /* R727 */ | |
833 | { 0x0000, 0x0000 }, /* R728 */ | |
834 | { 0x0000, 0x0000 }, /* R729 */ | |
835 | { 0x0000, 0x0000 }, /* R730 */ | |
836 | { 0x0000, 0x0000 }, /* R731 */ | |
837 | { 0x0000, 0x0000 }, /* R732 */ | |
838 | { 0x0000, 0x0000 }, /* R733 */ | |
839 | { 0x0000, 0x0000 }, /* R734 */ | |
840 | { 0x0000, 0x0000 }, /* R735 */ | |
841 | { 0x0000, 0x0000 }, /* R736 */ | |
842 | { 0x0000, 0x0000 }, /* R737 */ | |
843 | { 0x0000, 0x0000 }, /* R738 */ | |
844 | { 0x0000, 0x0000 }, /* R739 */ | |
845 | { 0x0000, 0x0000 }, /* R740 */ | |
846 | { 0x0000, 0x0000 }, /* R741 */ | |
847 | { 0x0000, 0x0000 }, /* R742 */ | |
848 | { 0x0000, 0x0000 }, /* R743 */ | |
849 | { 0x0000, 0x0000 }, /* R744 */ | |
850 | { 0x0000, 0x0000 }, /* R745 */ | |
851 | { 0x0000, 0x0000 }, /* R746 */ | |
852 | { 0x0000, 0x0000 }, /* R747 */ | |
853 | { 0x0000, 0x0000 }, /* R748 */ | |
854 | { 0x0000, 0x0000 }, /* R749 */ | |
855 | { 0x0000, 0x0000 }, /* R750 */ | |
856 | { 0x0000, 0x0000 }, /* R751 */ | |
857 | { 0x0000, 0x0000 }, /* R752 */ | |
858 | { 0x0000, 0x0000 }, /* R753 */ | |
859 | { 0x0000, 0x0000 }, /* R754 */ | |
860 | { 0x0000, 0x0000 }, /* R755 */ | |
861 | { 0x0000, 0x0000 }, /* R756 */ | |
862 | { 0x0000, 0x0000 }, /* R757 */ | |
863 | { 0x0000, 0x0000 }, /* R758 */ | |
864 | { 0x0000, 0x0000 }, /* R759 */ | |
865 | { 0x0000, 0x0000 }, /* R760 */ | |
866 | { 0x0000, 0x0000 }, /* R761 */ | |
867 | { 0x0000, 0x0000 }, /* R762 */ | |
868 | { 0x0000, 0x0000 }, /* R763 */ | |
869 | { 0x0000, 0x0000 }, /* R764 */ | |
870 | { 0x0000, 0x0000 }, /* R765 */ | |
871 | { 0x0000, 0x0000 }, /* R766 */ | |
872 | { 0x0000, 0x0000 }, /* R767 */ | |
873 | { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */ | |
874 | { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */ | |
875 | { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */ | |
876 | { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */ | |
877 | { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */ | |
878 | { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */ | |
879 | { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */ | |
880 | { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */ | |
881 | { 0x0000, 0x0000 }, /* R776 */ | |
882 | { 0x0000, 0x0000 }, /* R777 */ | |
883 | { 0x0000, 0x0000 }, /* R778 */ | |
884 | { 0x0000, 0x0000 }, /* R779 */ | |
885 | { 0x0000, 0x0000 }, /* R780 */ | |
886 | { 0x0000, 0x0000 }, /* R781 */ | |
887 | { 0x0000, 0x0000 }, /* R782 */ | |
888 | { 0x0000, 0x0000 }, /* R783 */ | |
889 | { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */ | |
890 | { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */ | |
891 | { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */ | |
892 | { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */ | |
893 | { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */ | |
894 | { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */ | |
895 | { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */ | |
896 | { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */ | |
897 | { 0x0000, 0x0000 }, /* R792 */ | |
898 | { 0x0000, 0x0000 }, /* R793 */ | |
899 | { 0x0000, 0x0000 }, /* R794 */ | |
900 | { 0x0000, 0x0000 }, /* R795 */ | |
901 | { 0x0000, 0x0000 }, /* R796 */ | |
902 | { 0x0000, 0x0000 }, /* R797 */ | |
903 | { 0x0000, 0x0000 }, /* R798 */ | |
904 | { 0x0000, 0x0000 }, /* R799 */ | |
905 | { 0x0000, 0x0000 }, /* R800 */ | |
906 | { 0x0000, 0x0000 }, /* R801 */ | |
907 | { 0x0000, 0x0000 }, /* R802 */ | |
908 | { 0x0000, 0x0000 }, /* R803 */ | |
909 | { 0x0000, 0x0000 }, /* R804 */ | |
910 | { 0x0000, 0x0000 }, /* R805 */ | |
911 | { 0x0000, 0x0000 }, /* R806 */ | |
912 | { 0x0000, 0x0000 }, /* R807 */ | |
913 | { 0x0000, 0x0000 }, /* R808 */ | |
914 | { 0x0000, 0x0000 }, /* R809 */ | |
915 | { 0x0000, 0x0000 }, /* R810 */ | |
916 | { 0x0000, 0x0000 }, /* R811 */ | |
917 | { 0x0000, 0x0000 }, /* R812 */ | |
918 | { 0x0000, 0x0000 }, /* R813 */ | |
919 | { 0x0000, 0x0000 }, /* R814 */ | |
920 | { 0x0000, 0x0000 }, /* R815 */ | |
921 | { 0x0000, 0x0000 }, /* R816 */ | |
922 | { 0x0000, 0x0000 }, /* R817 */ | |
923 | { 0x0000, 0x0000 }, /* R818 */ | |
924 | { 0x0000, 0x0000 }, /* R819 */ | |
925 | { 0x0000, 0x0000 }, /* R820 */ | |
926 | { 0x0000, 0x0000 }, /* R821 */ | |
927 | { 0x0000, 0x0000 }, /* R822 */ | |
928 | { 0x0000, 0x0000 }, /* R823 */ | |
929 | { 0x0000, 0x0000 }, /* R824 */ | |
930 | { 0x0000, 0x0000 }, /* R825 */ | |
931 | { 0x0000, 0x0000 }, /* R826 */ | |
932 | { 0x0000, 0x0000 }, /* R827 */ | |
933 | { 0x0000, 0x0000 }, /* R828 */ | |
934 | { 0x0000, 0x0000 }, /* R829 */ | |
935 | { 0x0000, 0x0000 }, /* R830 */ | |
936 | { 0x0000, 0x0000 }, /* R831 */ | |
937 | { 0x0000, 0x0000 }, /* R832 */ | |
938 | { 0x0000, 0x0000 }, /* R833 */ | |
939 | { 0x0000, 0x0000 }, /* R834 */ | |
940 | { 0x0000, 0x0000 }, /* R835 */ | |
941 | { 0x0000, 0x0000 }, /* R836 */ | |
942 | { 0x0000, 0x0000 }, /* R837 */ | |
943 | { 0x0000, 0x0000 }, /* R838 */ | |
944 | { 0x0000, 0x0000 }, /* R839 */ | |
945 | { 0x0000, 0x0000 }, /* R840 */ | |
946 | { 0x0000, 0x0000 }, /* R841 */ | |
947 | { 0x0000, 0x0000 }, /* R842 */ | |
948 | { 0x0000, 0x0000 }, /* R843 */ | |
949 | { 0x0000, 0x0000 }, /* R844 */ | |
950 | { 0x0000, 0x0000 }, /* R845 */ | |
951 | { 0x0000, 0x0000 }, /* R846 */ | |
952 | { 0x0000, 0x0000 }, /* R847 */ | |
953 | { 0x0000, 0x0000 }, /* R848 */ | |
954 | { 0x0000, 0x0000 }, /* R849 */ | |
955 | { 0x0000, 0x0000 }, /* R850 */ | |
956 | { 0x0000, 0x0000 }, /* R851 */ | |
957 | { 0x0000, 0x0000 }, /* R852 */ | |
958 | { 0x0000, 0x0000 }, /* R853 */ | |
959 | { 0x0000, 0x0000 }, /* R854 */ | |
960 | { 0x0000, 0x0000 }, /* R855 */ | |
961 | { 0x0000, 0x0000 }, /* R856 */ | |
962 | { 0x0000, 0x0000 }, /* R857 */ | |
963 | { 0x0000, 0x0000 }, /* R858 */ | |
964 | { 0x0000, 0x0000 }, /* R859 */ | |
965 | { 0x0000, 0x0000 }, /* R860 */ | |
966 | { 0x0000, 0x0000 }, /* R861 */ | |
967 | { 0x0000, 0x0000 }, /* R862 */ | |
968 | { 0x0000, 0x0000 }, /* R863 */ | |
969 | { 0x0000, 0x0000 }, /* R864 */ | |
970 | { 0x0000, 0x0000 }, /* R865 */ | |
971 | { 0x0000, 0x0000 }, /* R866 */ | |
972 | { 0x0000, 0x0000 }, /* R867 */ | |
973 | { 0x0000, 0x0000 }, /* R868 */ | |
974 | { 0x0000, 0x0000 }, /* R869 */ | |
975 | { 0x0000, 0x0000 }, /* R870 */ | |
976 | { 0x0000, 0x0000 }, /* R871 */ | |
977 | { 0x0000, 0x0000 }, /* R872 */ | |
978 | { 0x0000, 0x0000 }, /* R873 */ | |
979 | { 0x0000, 0x0000 }, /* R874 */ | |
980 | { 0x0000, 0x0000 }, /* R875 */ | |
981 | { 0x0000, 0x0000 }, /* R876 */ | |
982 | { 0x0000, 0x0000 }, /* R877 */ | |
983 | { 0x0000, 0x0000 }, /* R878 */ | |
984 | { 0x0000, 0x0000 }, /* R879 */ | |
985 | { 0x0000, 0x0000 }, /* R880 */ | |
986 | { 0x0000, 0x0000 }, /* R881 */ | |
987 | { 0x0000, 0x0000 }, /* R882 */ | |
988 | { 0x0000, 0x0000 }, /* R883 */ | |
989 | { 0x0000, 0x0000 }, /* R884 */ | |
990 | { 0x0000, 0x0000 }, /* R885 */ | |
991 | { 0x0000, 0x0000 }, /* R886 */ | |
992 | { 0x0000, 0x0000 }, /* R887 */ | |
993 | { 0x0000, 0x0000 }, /* R888 */ | |
994 | { 0x0000, 0x0000 }, /* R889 */ | |
995 | { 0x0000, 0x0000 }, /* R890 */ | |
996 | { 0x0000, 0x0000 }, /* R891 */ | |
997 | { 0x0000, 0x0000 }, /* R892 */ | |
998 | { 0x0000, 0x0000 }, /* R893 */ | |
999 | { 0x0000, 0x0000 }, /* R894 */ | |
1000 | { 0x0000, 0x0000 }, /* R895 */ | |
1001 | { 0x0000, 0x0000 }, /* R896 */ | |
1002 | { 0x0000, 0x0000 }, /* R897 */ | |
1003 | { 0x0000, 0x0000 }, /* R898 */ | |
1004 | { 0x0000, 0x0000 }, /* R899 */ | |
1005 | { 0x0000, 0x0000 }, /* R900 */ | |
1006 | { 0x0000, 0x0000 }, /* R901 */ | |
1007 | { 0x0000, 0x0000 }, /* R902 */ | |
1008 | { 0x0000, 0x0000 }, /* R903 */ | |
1009 | { 0x0000, 0x0000 }, /* R904 */ | |
1010 | { 0x0000, 0x0000 }, /* R905 */ | |
1011 | { 0x0000, 0x0000 }, /* R906 */ | |
1012 | { 0x0000, 0x0000 }, /* R907 */ | |
1013 | { 0x0000, 0x0000 }, /* R908 */ | |
1014 | { 0x0000, 0x0000 }, /* R909 */ | |
1015 | { 0x0000, 0x0000 }, /* R910 */ | |
1016 | { 0x0000, 0x0000 }, /* R911 */ | |
1017 | { 0x0000, 0x0000 }, /* R912 */ | |
1018 | { 0x0000, 0x0000 }, /* R913 */ | |
1019 | { 0x0000, 0x0000 }, /* R914 */ | |
1020 | { 0x0000, 0x0000 }, /* R915 */ | |
1021 | { 0x0000, 0x0000 }, /* R916 */ | |
1022 | { 0x0000, 0x0000 }, /* R917 */ | |
1023 | { 0x0000, 0x0000 }, /* R918 */ | |
1024 | { 0x0000, 0x0000 }, /* R919 */ | |
1025 | { 0x0000, 0x0000 }, /* R920 */ | |
1026 | { 0x0000, 0x0000 }, /* R921 */ | |
1027 | { 0x0000, 0x0000 }, /* R922 */ | |
1028 | { 0x0000, 0x0000 }, /* R923 */ | |
1029 | { 0x0000, 0x0000 }, /* R924 */ | |
1030 | { 0x0000, 0x0000 }, /* R925 */ | |
1031 | { 0x0000, 0x0000 }, /* R926 */ | |
1032 | { 0x0000, 0x0000 }, /* R927 */ | |
1033 | { 0x0000, 0x0000 }, /* R928 */ | |
1034 | { 0x0000, 0x0000 }, /* R929 */ | |
1035 | { 0x0000, 0x0000 }, /* R930 */ | |
1036 | { 0x0000, 0x0000 }, /* R931 */ | |
1037 | { 0x0000, 0x0000 }, /* R932 */ | |
1038 | { 0x0000, 0x0000 }, /* R933 */ | |
1039 | { 0x0000, 0x0000 }, /* R934 */ | |
1040 | { 0x0000, 0x0000 }, /* R935 */ | |
1041 | { 0x0000, 0x0000 }, /* R936 */ | |
1042 | { 0x0000, 0x0000 }, /* R937 */ | |
1043 | { 0x0000, 0x0000 }, /* R938 */ | |
1044 | { 0x0000, 0x0000 }, /* R939 */ | |
1045 | { 0x0000, 0x0000 }, /* R940 */ | |
1046 | { 0x0000, 0x0000 }, /* R941 */ | |
1047 | { 0x0000, 0x0000 }, /* R942 */ | |
1048 | { 0x0000, 0x0000 }, /* R943 */ | |
1049 | { 0x0000, 0x0000 }, /* R944 */ | |
1050 | { 0x0000, 0x0000 }, /* R945 */ | |
1051 | { 0x0000, 0x0000 }, /* R946 */ | |
1052 | { 0x0000, 0x0000 }, /* R947 */ | |
1053 | { 0x0000, 0x0000 }, /* R948 */ | |
1054 | { 0x0000, 0x0000 }, /* R949 */ | |
1055 | { 0x0000, 0x0000 }, /* R950 */ | |
1056 | { 0x0000, 0x0000 }, /* R951 */ | |
1057 | { 0x0000, 0x0000 }, /* R952 */ | |
1058 | { 0x0000, 0x0000 }, /* R953 */ | |
1059 | { 0x0000, 0x0000 }, /* R954 */ | |
1060 | { 0x0000, 0x0000 }, /* R955 */ | |
1061 | { 0x0000, 0x0000 }, /* R956 */ | |
1062 | { 0x0000, 0x0000 }, /* R957 */ | |
1063 | { 0x0000, 0x0000 }, /* R958 */ | |
1064 | { 0x0000, 0x0000 }, /* R959 */ | |
1065 | { 0x0000, 0x0000 }, /* R960 */ | |
1066 | { 0x0000, 0x0000 }, /* R961 */ | |
1067 | { 0x0000, 0x0000 }, /* R962 */ | |
1068 | { 0x0000, 0x0000 }, /* R963 */ | |
1069 | { 0x0000, 0x0000 }, /* R964 */ | |
1070 | { 0x0000, 0x0000 }, /* R965 */ | |
1071 | { 0x0000, 0x0000 }, /* R966 */ | |
1072 | { 0x0000, 0x0000 }, /* R967 */ | |
1073 | { 0x0000, 0x0000 }, /* R968 */ | |
1074 | { 0x0000, 0x0000 }, /* R969 */ | |
1075 | { 0x0000, 0x0000 }, /* R970 */ | |
1076 | { 0x0000, 0x0000 }, /* R971 */ | |
1077 | { 0x0000, 0x0000 }, /* R972 */ | |
1078 | { 0x0000, 0x0000 }, /* R973 */ | |
1079 | { 0x0000, 0x0000 }, /* R974 */ | |
1080 | { 0x0000, 0x0000 }, /* R975 */ | |
1081 | { 0x0000, 0x0000 }, /* R976 */ | |
1082 | { 0x0000, 0x0000 }, /* R977 */ | |
1083 | { 0x0000, 0x0000 }, /* R978 */ | |
1084 | { 0x0000, 0x0000 }, /* R979 */ | |
1085 | { 0x0000, 0x0000 }, /* R980 */ | |
1086 | { 0x0000, 0x0000 }, /* R981 */ | |
1087 | { 0x0000, 0x0000 }, /* R982 */ | |
1088 | { 0x0000, 0x0000 }, /* R983 */ | |
1089 | { 0x0000, 0x0000 }, /* R984 */ | |
1090 | { 0x0000, 0x0000 }, /* R985 */ | |
1091 | { 0x0000, 0x0000 }, /* R986 */ | |
1092 | { 0x0000, 0x0000 }, /* R987 */ | |
1093 | { 0x0000, 0x0000 }, /* R988 */ | |
1094 | { 0x0000, 0x0000 }, /* R989 */ | |
1095 | { 0x0000, 0x0000 }, /* R990 */ | |
1096 | { 0x0000, 0x0000 }, /* R991 */ | |
1097 | { 0x0000, 0x0000 }, /* R992 */ | |
1098 | { 0x0000, 0x0000 }, /* R993 */ | |
1099 | { 0x0000, 0x0000 }, /* R994 */ | |
1100 | { 0x0000, 0x0000 }, /* R995 */ | |
1101 | { 0x0000, 0x0000 }, /* R996 */ | |
1102 | { 0x0000, 0x0000 }, /* R997 */ | |
1103 | { 0x0000, 0x0000 }, /* R998 */ | |
1104 | { 0x0000, 0x0000 }, /* R999 */ | |
1105 | { 0x0000, 0x0000 }, /* R1000 */ | |
1106 | { 0x0000, 0x0000 }, /* R1001 */ | |
1107 | { 0x0000, 0x0000 }, /* R1002 */ | |
1108 | { 0x0000, 0x0000 }, /* R1003 */ | |
1109 | { 0x0000, 0x0000 }, /* R1004 */ | |
1110 | { 0x0000, 0x0000 }, /* R1005 */ | |
1111 | { 0x0000, 0x0000 }, /* R1006 */ | |
1112 | { 0x0000, 0x0000 }, /* R1007 */ | |
1113 | { 0x0000, 0x0000 }, /* R1008 */ | |
1114 | { 0x0000, 0x0000 }, /* R1009 */ | |
1115 | { 0x0000, 0x0000 }, /* R1010 */ | |
1116 | { 0x0000, 0x0000 }, /* R1011 */ | |
1117 | { 0x0000, 0x0000 }, /* R1012 */ | |
1118 | { 0x0000, 0x0000 }, /* R1013 */ | |
1119 | { 0x0000, 0x0000 }, /* R1014 */ | |
1120 | { 0x0000, 0x0000 }, /* R1015 */ | |
1121 | { 0x0000, 0x0000 }, /* R1016 */ | |
1122 | { 0x0000, 0x0000 }, /* R1017 */ | |
1123 | { 0x0000, 0x0000 }, /* R1018 */ | |
1124 | { 0x0000, 0x0000 }, /* R1019 */ | |
1125 | { 0x0000, 0x0000 }, /* R1020 */ | |
1126 | { 0x0000, 0x0000 }, /* R1021 */ | |
1127 | { 0x0000, 0x0000 }, /* R1022 */ | |
1128 | { 0x0000, 0x0000 }, /* R1023 */ | |
1129 | { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */ | |
1130 | { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */ | |
1131 | { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */ | |
1132 | { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */ | |
1133 | { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */ | |
1134 | { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */ | |
1135 | { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */ | |
1136 | { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */ | |
1137 | { 0x0000, 0x0000 }, /* R1032 */ | |
1138 | { 0x0000, 0x0000 }, /* R1033 */ | |
1139 | { 0x0000, 0x0000 }, /* R1034 */ | |
1140 | { 0x0000, 0x0000 }, /* R1035 */ | |
1141 | { 0x0000, 0x0000 }, /* R1036 */ | |
1142 | { 0x0000, 0x0000 }, /* R1037 */ | |
1143 | { 0x0000, 0x0000 }, /* R1038 */ | |
1144 | { 0x0000, 0x0000 }, /* R1039 */ | |
1145 | { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */ | |
1146 | { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */ | |
1147 | { 0x0000, 0x0000 }, /* R1042 */ | |
1148 | { 0x0000, 0x0000 }, /* R1043 */ | |
1149 | { 0x0000, 0x0000 }, /* R1044 */ | |
1150 | { 0x0000, 0x0000 }, /* R1045 */ | |
1151 | { 0x0000, 0x0000 }, /* R1046 */ | |
1152 | { 0x0000, 0x0000 }, /* R1047 */ | |
1153 | { 0x0000, 0x0000 }, /* R1048 */ | |
1154 | { 0x0000, 0x0000 }, /* R1049 */ | |
1155 | { 0x0000, 0x0000 }, /* R1050 */ | |
1156 | { 0x0000, 0x0000 }, /* R1051 */ | |
1157 | { 0x0000, 0x0000 }, /* R1052 */ | |
1158 | { 0x0000, 0x0000 }, /* R1053 */ | |
1159 | { 0x0000, 0x0000 }, /* R1054 */ | |
1160 | { 0x0000, 0x0000 }, /* R1055 */ | |
1161 | { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */ | |
1162 | { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */ | |
1163 | { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */ | |
1164 | { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */ | |
1165 | { 0x0000, 0x0000 }, /* R1060 */ | |
1166 | { 0x0000, 0x0000 }, /* R1061 */ | |
1167 | { 0x0000, 0x0000 }, /* R1062 */ | |
1168 | { 0x0000, 0x0000 }, /* R1063 */ | |
1169 | { 0x0000, 0x0000 }, /* R1064 */ | |
1170 | { 0x0000, 0x0000 }, /* R1065 */ | |
1171 | { 0x0000, 0x0000 }, /* R1066 */ | |
1172 | { 0x0000, 0x0000 }, /* R1067 */ | |
1173 | { 0x0000, 0x0000 }, /* R1068 */ | |
1174 | { 0x0000, 0x0000 }, /* R1069 */ | |
1175 | { 0x0000, 0x0000 }, /* R1070 */ | |
1176 | { 0x0000, 0x0000 }, /* R1071 */ | |
1177 | { 0x0000, 0x0000 }, /* R1072 */ | |
1178 | { 0x0000, 0x0000 }, /* R1073 */ | |
1179 | { 0x0000, 0x0000 }, /* R1074 */ | |
1180 | { 0x0000, 0x0000 }, /* R1075 */ | |
1181 | { 0x0000, 0x0000 }, /* R1076 */ | |
1182 | { 0x0000, 0x0000 }, /* R1077 */ | |
1183 | { 0x0000, 0x0000 }, /* R1078 */ | |
1184 | { 0x0000, 0x0000 }, /* R1079 */ | |
1185 | { 0x0000, 0x0000 }, /* R1080 */ | |
1186 | { 0x0000, 0x0000 }, /* R1081 */ | |
1187 | { 0x0000, 0x0000 }, /* R1082 */ | |
1188 | { 0x0000, 0x0000 }, /* R1083 */ | |
1189 | { 0x0000, 0x0000 }, /* R1084 */ | |
1190 | { 0x0000, 0x0000 }, /* R1085 */ | |
1191 | { 0x0000, 0x0000 }, /* R1086 */ | |
1192 | { 0x0000, 0x0000 }, /* R1087 */ | |
1193 | { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */ | |
1194 | { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */ | |
1195 | { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */ | |
1196 | { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */ | |
1197 | { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */ | |
1198 | { 0x0000, 0x0000 }, /* R1093 */ | |
1199 | { 0x0000, 0x0000 }, /* R1094 */ | |
1200 | { 0x0000, 0x0000 }, /* R1095 */ | |
1201 | { 0x0000, 0x0000 }, /* R1096 */ | |
1202 | { 0x0000, 0x0000 }, /* R1097 */ | |
1203 | { 0x0000, 0x0000 }, /* R1098 */ | |
1204 | { 0x0000, 0x0000 }, /* R1099 */ | |
1205 | { 0x0000, 0x0000 }, /* R1100 */ | |
1206 | { 0x0000, 0x0000 }, /* R1101 */ | |
1207 | { 0x0000, 0x0000 }, /* R1102 */ | |
1208 | { 0x0000, 0x0000 }, /* R1103 */ | |
1209 | { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */ | |
1210 | { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */ | |
1211 | { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */ | |
1212 | { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */ | |
1213 | { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */ | |
1214 | { 0x0000, 0x0000 }, /* R1109 */ | |
1215 | { 0x0000, 0x0000 }, /* R1110 */ | |
1216 | { 0x0000, 0x0000 }, /* R1111 */ | |
1217 | { 0x0000, 0x0000 }, /* R1112 */ | |
1218 | { 0x0000, 0x0000 }, /* R1113 */ | |
1219 | { 0x0000, 0x0000 }, /* R1114 */ | |
1220 | { 0x0000, 0x0000 }, /* R1115 */ | |
1221 | { 0x0000, 0x0000 }, /* R1116 */ | |
1222 | { 0x0000, 0x0000 }, /* R1117 */ | |
1223 | { 0x0000, 0x0000 }, /* R1118 */ | |
1224 | { 0x0000, 0x0000 }, /* R1119 */ | |
1225 | { 0x0000, 0x0000 }, /* R1120 */ | |
1226 | { 0x0000, 0x0000 }, /* R1121 */ | |
1227 | { 0x0000, 0x0000 }, /* R1122 */ | |
1228 | { 0x0000, 0x0000 }, /* R1123 */ | |
1229 | { 0x0000, 0x0000 }, /* R1124 */ | |
1230 | { 0x0000, 0x0000 }, /* R1125 */ | |
1231 | { 0x0000, 0x0000 }, /* R1126 */ | |
1232 | { 0x0000, 0x0000 }, /* R1127 */ | |
1233 | { 0x0000, 0x0000 }, /* R1128 */ | |
1234 | { 0x0000, 0x0000 }, /* R1129 */ | |
1235 | { 0x0000, 0x0000 }, /* R1130 */ | |
1236 | { 0x0000, 0x0000 }, /* R1131 */ | |
1237 | { 0x0000, 0x0000 }, /* R1132 */ | |
1238 | { 0x0000, 0x0000 }, /* R1133 */ | |
1239 | { 0x0000, 0x0000 }, /* R1134 */ | |
1240 | { 0x0000, 0x0000 }, /* R1135 */ | |
1241 | { 0x0000, 0x0000 }, /* R1136 */ | |
1242 | { 0x0000, 0x0000 }, /* R1137 */ | |
1243 | { 0x0000, 0x0000 }, /* R1138 */ | |
1244 | { 0x0000, 0x0000 }, /* R1139 */ | |
1245 | { 0x0000, 0x0000 }, /* R1140 */ | |
1246 | { 0x0000, 0x0000 }, /* R1141 */ | |
1247 | { 0x0000, 0x0000 }, /* R1142 */ | |
1248 | { 0x0000, 0x0000 }, /* R1143 */ | |
1249 | { 0x0000, 0x0000 }, /* R1144 */ | |
1250 | { 0x0000, 0x0000 }, /* R1145 */ | |
1251 | { 0x0000, 0x0000 }, /* R1146 */ | |
1252 | { 0x0000, 0x0000 }, /* R1147 */ | |
1253 | { 0x0000, 0x0000 }, /* R1148 */ | |
1254 | { 0x0000, 0x0000 }, /* R1149 */ | |
1255 | { 0x0000, 0x0000 }, /* R1150 */ | |
1256 | { 0x0000, 0x0000 }, /* R1151 */ | |
1257 | { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ | |
1258 | { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ | |
1259 | { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ | |
1260 | { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ | |
1261 | { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ | |
1262 | { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ | |
1263 | { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ | |
1264 | { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ | |
1265 | { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ | |
1266 | { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ | |
1267 | { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ | |
1268 | { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ | |
1269 | { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ | |
1270 | { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ | |
1271 | { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ | |
1272 | { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ | |
1273 | { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ | |
1274 | { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ | |
1275 | { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ | |
1276 | { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ | |
1277 | { 0x0000, 0x0000 }, /* R1172 */ | |
1278 | { 0x0000, 0x0000 }, /* R1173 */ | |
1279 | { 0x0000, 0x0000 }, /* R1174 */ | |
1280 | { 0x0000, 0x0000 }, /* R1175 */ | |
1281 | { 0x0000, 0x0000 }, /* R1176 */ | |
1282 | { 0x0000, 0x0000 }, /* R1177 */ | |
1283 | { 0x0000, 0x0000 }, /* R1178 */ | |
1284 | { 0x0000, 0x0000 }, /* R1179 */ | |
1285 | { 0x0000, 0x0000 }, /* R1180 */ | |
1286 | { 0x0000, 0x0000 }, /* R1181 */ | |
1287 | { 0x0000, 0x0000 }, /* R1182 */ | |
1288 | { 0x0000, 0x0000 }, /* R1183 */ | |
1289 | { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ | |
1290 | { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ | |
1291 | { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ | |
1292 | { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ | |
1293 | { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ | |
1294 | { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ | |
1295 | { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ | |
1296 | { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ | |
1297 | { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ | |
1298 | { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ | |
1299 | { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ | |
1300 | { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ | |
1301 | { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ | |
1302 | { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ | |
1303 | { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ | |
1304 | { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ | |
1305 | { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ | |
1306 | { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ | |
1307 | { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ | |
1308 | { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ | |
1309 | { 0x0000, 0x0000 }, /* R1204 */ | |
1310 | { 0x0000, 0x0000 }, /* R1205 */ | |
1311 | { 0x0000, 0x0000 }, /* R1206 */ | |
1312 | { 0x0000, 0x0000 }, /* R1207 */ | |
1313 | { 0x0000, 0x0000 }, /* R1208 */ | |
1314 | { 0x0000, 0x0000 }, /* R1209 */ | |
1315 | { 0x0000, 0x0000 }, /* R1210 */ | |
1316 | { 0x0000, 0x0000 }, /* R1211 */ | |
1317 | { 0x0000, 0x0000 }, /* R1212 */ | |
1318 | { 0x0000, 0x0000 }, /* R1213 */ | |
1319 | { 0x0000, 0x0000 }, /* R1214 */ | |
1320 | { 0x0000, 0x0000 }, /* R1215 */ | |
1321 | { 0x0000, 0x0000 }, /* R1216 */ | |
1322 | { 0x0000, 0x0000 }, /* R1217 */ | |
1323 | { 0x0000, 0x0000 }, /* R1218 */ | |
1324 | { 0x0000, 0x0000 }, /* R1219 */ | |
1325 | { 0x0000, 0x0000 }, /* R1220 */ | |
1326 | { 0x0000, 0x0000 }, /* R1221 */ | |
1327 | { 0x0000, 0x0000 }, /* R1222 */ | |
1328 | { 0x0000, 0x0000 }, /* R1223 */ | |
1329 | { 0x0000, 0x0000 }, /* R1224 */ | |
1330 | { 0x0000, 0x0000 }, /* R1225 */ | |
1331 | { 0x0000, 0x0000 }, /* R1226 */ | |
1332 | { 0x0000, 0x0000 }, /* R1227 */ | |
1333 | { 0x0000, 0x0000 }, /* R1228 */ | |
1334 | { 0x0000, 0x0000 }, /* R1229 */ | |
1335 | { 0x0000, 0x0000 }, /* R1230 */ | |
1336 | { 0x0000, 0x0000 }, /* R1231 */ | |
1337 | { 0x0000, 0x0000 }, /* R1232 */ | |
1338 | { 0x0000, 0x0000 }, /* R1233 */ | |
1339 | { 0x0000, 0x0000 }, /* R1234 */ | |
1340 | { 0x0000, 0x0000 }, /* R1235 */ | |
1341 | { 0x0000, 0x0000 }, /* R1236 */ | |
1342 | { 0x0000, 0x0000 }, /* R1237 */ | |
1343 | { 0x0000, 0x0000 }, /* R1238 */ | |
1344 | { 0x0000, 0x0000 }, /* R1239 */ | |
1345 | { 0x0000, 0x0000 }, /* R1240 */ | |
1346 | { 0x0000, 0x0000 }, /* R1241 */ | |
1347 | { 0x0000, 0x0000 }, /* R1242 */ | |
1348 | { 0x0000, 0x0000 }, /* R1243 */ | |
1349 | { 0x0000, 0x0000 }, /* R1244 */ | |
1350 | { 0x0000, 0x0000 }, /* R1245 */ | |
1351 | { 0x0000, 0x0000 }, /* R1246 */ | |
1352 | { 0x0000, 0x0000 }, /* R1247 */ | |
1353 | { 0x0000, 0x0000 }, /* R1248 */ | |
1354 | { 0x0000, 0x0000 }, /* R1249 */ | |
1355 | { 0x0000, 0x0000 }, /* R1250 */ | |
1356 | { 0x0000, 0x0000 }, /* R1251 */ | |
1357 | { 0x0000, 0x0000 }, /* R1252 */ | |
1358 | { 0x0000, 0x0000 }, /* R1253 */ | |
1359 | { 0x0000, 0x0000 }, /* R1254 */ | |
1360 | { 0x0000, 0x0000 }, /* R1255 */ | |
1361 | { 0x0000, 0x0000 }, /* R1256 */ | |
1362 | { 0x0000, 0x0000 }, /* R1257 */ | |
1363 | { 0x0000, 0x0000 }, /* R1258 */ | |
1364 | { 0x0000, 0x0000 }, /* R1259 */ | |
1365 | { 0x0000, 0x0000 }, /* R1260 */ | |
1366 | { 0x0000, 0x0000 }, /* R1261 */ | |
1367 | { 0x0000, 0x0000 }, /* R1262 */ | |
1368 | { 0x0000, 0x0000 }, /* R1263 */ | |
1369 | { 0x0000, 0x0000 }, /* R1264 */ | |
1370 | { 0x0000, 0x0000 }, /* R1265 */ | |
1371 | { 0x0000, 0x0000 }, /* R1266 */ | |
1372 | { 0x0000, 0x0000 }, /* R1267 */ | |
1373 | { 0x0000, 0x0000 }, /* R1268 */ | |
1374 | { 0x0000, 0x0000 }, /* R1269 */ | |
1375 | { 0x0000, 0x0000 }, /* R1270 */ | |
1376 | { 0x0000, 0x0000 }, /* R1271 */ | |
1377 | { 0x0000, 0x0000 }, /* R1272 */ | |
1378 | { 0x0000, 0x0000 }, /* R1273 */ | |
1379 | { 0x0000, 0x0000 }, /* R1274 */ | |
1380 | { 0x0000, 0x0000 }, /* R1275 */ | |
1381 | { 0x0000, 0x0000 }, /* R1276 */ | |
1382 | { 0x0000, 0x0000 }, /* R1277 */ | |
1383 | { 0x0000, 0x0000 }, /* R1278 */ | |
1384 | { 0x0000, 0x0000 }, /* R1279 */ | |
1385 | { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */ | |
1386 | { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */ | |
1387 | { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */ | |
1388 | { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */ | |
1389 | { 0x0000, 0x0000 }, /* R1284 */ | |
1390 | { 0x0000, 0x0000 }, /* R1285 */ | |
1391 | { 0x0000, 0x0000 }, /* R1286 */ | |
1392 | { 0x0000, 0x0000 }, /* R1287 */ | |
1393 | { 0x0000, 0x0000 }, /* R1288 */ | |
1394 | { 0x0000, 0x0000 }, /* R1289 */ | |
1395 | { 0x0000, 0x0000 }, /* R1290 */ | |
1396 | { 0x0000, 0x0000 }, /* R1291 */ | |
1397 | { 0x0000, 0x0000 }, /* R1292 */ | |
1398 | { 0x0000, 0x0000 }, /* R1293 */ | |
1399 | { 0x0000, 0x0000 }, /* R1294 */ | |
1400 | { 0x0000, 0x0000 }, /* R1295 */ | |
1401 | { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */ | |
1402 | { 0x0000, 0x0000 }, /* R1297 */ | |
1403 | { 0x0000, 0x0000 }, /* R1298 */ | |
1404 | { 0x0000, 0x0000 }, /* R1299 */ | |
1405 | { 0x0000, 0x0000 }, /* R1300 */ | |
1406 | { 0x0000, 0x0000 }, /* R1301 */ | |
1407 | { 0x0000, 0x0000 }, /* R1302 */ | |
1408 | { 0x0000, 0x0000 }, /* R1303 */ | |
1409 | { 0x0000, 0x0000 }, /* R1304 */ | |
1410 | { 0x0000, 0x0000 }, /* R1305 */ | |
1411 | { 0x0000, 0x0000 }, /* R1306 */ | |
1412 | { 0x0000, 0x0000 }, /* R1307 */ | |
1413 | { 0x0000, 0x0000 }, /* R1308 */ | |
1414 | { 0x0000, 0x0000 }, /* R1309 */ | |
1415 | { 0x0000, 0x0000 }, /* R1310 */ | |
1416 | { 0x0000, 0x0000 }, /* R1311 */ | |
1417 | { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */ | |
1418 | { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */ | |
1419 | { 0x0000, 0x0000 }, /* R1314 */ | |
1420 | { 0x0000, 0x0000 }, /* R1315 */ | |
1421 | { 0x0000, 0x0000 }, /* R1316 */ | |
1422 | { 0x0000, 0x0000 }, /* R1317 */ | |
1423 | { 0x0000, 0x0000 }, /* R1318 */ | |
1424 | { 0x0000, 0x0000 }, /* R1319 */ | |
1425 | { 0x0000, 0x0000 }, /* R1320 */ | |
1426 | { 0x0000, 0x0000 }, /* R1321 */ | |
1427 | { 0x0000, 0x0000 }, /* R1322 */ | |
1428 | { 0x0000, 0x0000 }, /* R1323 */ | |
1429 | { 0x0000, 0x0000 }, /* R1324 */ | |
1430 | { 0x0000, 0x0000 }, /* R1325 */ | |
1431 | { 0x0000, 0x0000 }, /* R1326 */ | |
1432 | { 0x0000, 0x0000 }, /* R1327 */ | |
1433 | { 0x0000, 0x0000 }, /* R1328 */ | |
1434 | { 0x0000, 0x0000 }, /* R1329 */ | |
1435 | { 0x0000, 0x0000 }, /* R1330 */ | |
1436 | { 0x0000, 0x0000 }, /* R1331 */ | |
1437 | { 0x0000, 0x0000 }, /* R1332 */ | |
1438 | { 0x0000, 0x0000 }, /* R1333 */ | |
1439 | { 0x0000, 0x0000 }, /* R1334 */ | |
1440 | { 0x0000, 0x0000 }, /* R1335 */ | |
1441 | { 0x0000, 0x0000 }, /* R1336 */ | |
1442 | { 0x0000, 0x0000 }, /* R1337 */ | |
1443 | { 0x0000, 0x0000 }, /* R1338 */ | |
1444 | { 0x0000, 0x0000 }, /* R1339 */ | |
1445 | { 0x0000, 0x0000 }, /* R1340 */ | |
1446 | { 0x0000, 0x0000 }, /* R1341 */ | |
1447 | { 0x0000, 0x0000 }, /* R1342 */ | |
1448 | { 0x0000, 0x0000 }, /* R1343 */ | |
1449 | { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */ | |
1450 | { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */ | |
1451 | { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */ | |
1452 | { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */ | |
1453 | { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */ | |
1454 | { 0x0000, 0x0000 }, /* R1349 */ | |
1455 | { 0x0000, 0x0000 }, /* R1350 */ | |
1456 | { 0x0000, 0x0000 }, /* R1351 */ | |
1457 | { 0x0000, 0x0000 }, /* R1352 */ | |
1458 | { 0x0000, 0x0000 }, /* R1353 */ | |
1459 | { 0x0000, 0x0000 }, /* R1354 */ | |
1460 | { 0x0000, 0x0000 }, /* R1355 */ | |
1461 | { 0x0000, 0x0000 }, /* R1356 */ | |
1462 | { 0x0000, 0x0000 }, /* R1357 */ | |
1463 | { 0x0000, 0x0000 }, /* R1358 */ | |
1464 | { 0x0000, 0x0000 }, /* R1359 */ | |
1465 | { 0x0000, 0x0000 }, /* R1360 */ | |
1466 | { 0x0000, 0x0000 }, /* R1361 */ | |
1467 | { 0x0000, 0x0000 }, /* R1362 */ | |
1468 | { 0x0000, 0x0000 }, /* R1363 */ | |
1469 | { 0x0000, 0x0000 }, /* R1364 */ | |
1470 | { 0x0000, 0x0000 }, /* R1365 */ | |
1471 | { 0x0000, 0x0000 }, /* R1366 */ | |
1472 | { 0x0000, 0x0000 }, /* R1367 */ | |
1473 | { 0x0000, 0x0000 }, /* R1368 */ | |
1474 | { 0x0000, 0x0000 }, /* R1369 */ | |
1475 | { 0x0000, 0x0000 }, /* R1370 */ | |
1476 | { 0x0000, 0x0000 }, /* R1371 */ | |
1477 | { 0x0000, 0x0000 }, /* R1372 */ | |
1478 | { 0x0000, 0x0000 }, /* R1373 */ | |
1479 | { 0x0000, 0x0000 }, /* R1374 */ | |
1480 | { 0x0000, 0x0000 }, /* R1375 */ | |
1481 | { 0x0000, 0x0000 }, /* R1376 */ | |
1482 | { 0x0000, 0x0000 }, /* R1377 */ | |
1483 | { 0x0000, 0x0000 }, /* R1378 */ | |
1484 | { 0x0000, 0x0000 }, /* R1379 */ | |
1485 | { 0x0000, 0x0000 }, /* R1380 */ | |
1486 | { 0x0000, 0x0000 }, /* R1381 */ | |
1487 | { 0x0000, 0x0000 }, /* R1382 */ | |
1488 | { 0x0000, 0x0000 }, /* R1383 */ | |
1489 | { 0x0000, 0x0000 }, /* R1384 */ | |
1490 | { 0x0000, 0x0000 }, /* R1385 */ | |
1491 | { 0x0000, 0x0000 }, /* R1386 */ | |
1492 | { 0x0000, 0x0000 }, /* R1387 */ | |
1493 | { 0x0000, 0x0000 }, /* R1388 */ | |
1494 | { 0x0000, 0x0000 }, /* R1389 */ | |
1495 | { 0x0000, 0x0000 }, /* R1390 */ | |
1496 | { 0x0000, 0x0000 }, /* R1391 */ | |
1497 | { 0x0000, 0x0000 }, /* R1392 */ | |
1498 | { 0x0000, 0x0000 }, /* R1393 */ | |
1499 | { 0x0000, 0x0000 }, /* R1394 */ | |
1500 | { 0x0000, 0x0000 }, /* R1395 */ | |
1501 | { 0x0000, 0x0000 }, /* R1396 */ | |
1502 | { 0x0000, 0x0000 }, /* R1397 */ | |
1503 | { 0x0000, 0x0000 }, /* R1398 */ | |
1504 | { 0x0000, 0x0000 }, /* R1399 */ | |
1505 | { 0x0000, 0x0000 }, /* R1400 */ | |
1506 | { 0x0000, 0x0000 }, /* R1401 */ | |
1507 | { 0x0000, 0x0000 }, /* R1402 */ | |
1508 | { 0x0000, 0x0000 }, /* R1403 */ | |
1509 | { 0x0000, 0x0000 }, /* R1404 */ | |
1510 | { 0x0000, 0x0000 }, /* R1405 */ | |
1511 | { 0x0000, 0x0000 }, /* R1406 */ | |
1512 | { 0x0000, 0x0000 }, /* R1407 */ | |
1513 | { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */ | |
1514 | { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */ | |
1515 | { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */ | |
1516 | { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */ | |
1517 | { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */ | |
1518 | { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */ | |
1519 | { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */ | |
1520 | { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */ | |
1521 | { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */ | |
1522 | { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */ | |
1523 | { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */ | |
1524 | { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */ | |
1525 | { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */ | |
1526 | { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */ | |
1527 | { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */ | |
1528 | { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */ | |
1529 | { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */ | |
1530 | { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */ | |
1531 | { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */ | |
1532 | { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */ | |
1533 | { 0x0000, 0x0000 }, /* R1428 */ | |
1534 | { 0x0000, 0x0000 }, /* R1429 */ | |
1535 | { 0x0000, 0x0000 }, /* R1430 */ | |
1536 | { 0x0000, 0x0000 }, /* R1431 */ | |
1537 | { 0x0000, 0x0000 }, /* R1432 */ | |
1538 | { 0x0000, 0x0000 }, /* R1433 */ | |
1539 | { 0x0000, 0x0000 }, /* R1434 */ | |
1540 | { 0x0000, 0x0000 }, /* R1435 */ | |
1541 | { 0x0000, 0x0000 }, /* R1436 */ | |
1542 | { 0x0000, 0x0000 }, /* R1437 */ | |
1543 | { 0x0000, 0x0000 }, /* R1438 */ | |
1544 | { 0x0000, 0x0000 }, /* R1439 */ | |
1545 | { 0x0000, 0x0000 }, /* R1440 */ | |
1546 | { 0x0000, 0x0000 }, /* R1441 */ | |
1547 | { 0x0000, 0x0000 }, /* R1442 */ | |
1548 | { 0x0000, 0x0000 }, /* R1443 */ | |
1549 | { 0x0000, 0x0000 }, /* R1444 */ | |
1550 | { 0x0000, 0x0000 }, /* R1445 */ | |
1551 | { 0x0000, 0x0000 }, /* R1446 */ | |
1552 | { 0x0000, 0x0000 }, /* R1447 */ | |
1553 | { 0x0000, 0x0000 }, /* R1448 */ | |
1554 | { 0x0000, 0x0000 }, /* R1449 */ | |
1555 | { 0x0000, 0x0000 }, /* R1450 */ | |
1556 | { 0x0000, 0x0000 }, /* R1451 */ | |
1557 | { 0x0000, 0x0000 }, /* R1452 */ | |
1558 | { 0x0000, 0x0000 }, /* R1453 */ | |
1559 | { 0x0000, 0x0000 }, /* R1454 */ | |
1560 | { 0x0000, 0x0000 }, /* R1455 */ | |
1561 | { 0x0000, 0x0000 }, /* R1456 */ | |
1562 | { 0x0000, 0x0000 }, /* R1457 */ | |
1563 | { 0x0000, 0x0000 }, /* R1458 */ | |
1564 | { 0x0000, 0x0000 }, /* R1459 */ | |
1565 | { 0x0000, 0x0000 }, /* R1460 */ | |
1566 | { 0x0000, 0x0000 }, /* R1461 */ | |
1567 | { 0x0000, 0x0000 }, /* R1462 */ | |
1568 | { 0x0000, 0x0000 }, /* R1463 */ | |
1569 | { 0x0000, 0x0000 }, /* R1464 */ | |
1570 | { 0x0000, 0x0000 }, /* R1465 */ | |
1571 | { 0x0000, 0x0000 }, /* R1466 */ | |
1572 | { 0x0000, 0x0000 }, /* R1467 */ | |
1573 | { 0x0000, 0x0000 }, /* R1468 */ | |
1574 | { 0x0000, 0x0000 }, /* R1469 */ | |
1575 | { 0x0000, 0x0000 }, /* R1470 */ | |
1576 | { 0x0000, 0x0000 }, /* R1471 */ | |
1577 | { 0x0000, 0x0000 }, /* R1472 */ | |
1578 | { 0x0000, 0x0000 }, /* R1473 */ | |
1579 | { 0x0000, 0x0000 }, /* R1474 */ | |
1580 | { 0x0000, 0x0000 }, /* R1475 */ | |
1581 | { 0x0000, 0x0000 }, /* R1476 */ | |
1582 | { 0x0000, 0x0000 }, /* R1477 */ | |
1583 | { 0x0000, 0x0000 }, /* R1478 */ | |
1584 | { 0x0000, 0x0000 }, /* R1479 */ | |
1585 | { 0x0000, 0x0000 }, /* R1480 */ | |
1586 | { 0x0000, 0x0000 }, /* R1481 */ | |
1587 | { 0x0000, 0x0000 }, /* R1482 */ | |
1588 | { 0x0000, 0x0000 }, /* R1483 */ | |
1589 | { 0x0000, 0x0000 }, /* R1484 */ | |
1590 | { 0x0000, 0x0000 }, /* R1485 */ | |
1591 | { 0x0000, 0x0000 }, /* R1486 */ | |
1592 | { 0x0000, 0x0000 }, /* R1487 */ | |
1593 | { 0x0000, 0x0000 }, /* R1488 */ | |
1594 | { 0x0000, 0x0000 }, /* R1489 */ | |
1595 | { 0x0000, 0x0000 }, /* R1490 */ | |
1596 | { 0x0000, 0x0000 }, /* R1491 */ | |
1597 | { 0x0000, 0x0000 }, /* R1492 */ | |
1598 | { 0x0000, 0x0000 }, /* R1493 */ | |
1599 | { 0x0000, 0x0000 }, /* R1494 */ | |
1600 | { 0x0000, 0x0000 }, /* R1495 */ | |
1601 | { 0x0000, 0x0000 }, /* R1496 */ | |
1602 | { 0x0000, 0x0000 }, /* R1497 */ | |
1603 | { 0x0000, 0x0000 }, /* R1498 */ | |
1604 | { 0x0000, 0x0000 }, /* R1499 */ | |
1605 | { 0x0000, 0x0000 }, /* R1500 */ | |
1606 | { 0x0000, 0x0000 }, /* R1501 */ | |
1607 | { 0x0000, 0x0000 }, /* R1502 */ | |
1608 | { 0x0000, 0x0000 }, /* R1503 */ | |
1609 | { 0x0000, 0x0000 }, /* R1504 */ | |
1610 | { 0x0000, 0x0000 }, /* R1505 */ | |
1611 | { 0x0000, 0x0000 }, /* R1506 */ | |
1612 | { 0x0000, 0x0000 }, /* R1507 */ | |
1613 | { 0x0000, 0x0000 }, /* R1508 */ | |
1614 | { 0x0000, 0x0000 }, /* R1509 */ | |
1615 | { 0x0000, 0x0000 }, /* R1510 */ | |
1616 | { 0x0000, 0x0000 }, /* R1511 */ | |
1617 | { 0x0000, 0x0000 }, /* R1512 */ | |
1618 | { 0x0000, 0x0000 }, /* R1513 */ | |
1619 | { 0x0000, 0x0000 }, /* R1514 */ | |
1620 | { 0x0000, 0x0000 }, /* R1515 */ | |
1621 | { 0x0000, 0x0000 }, /* R1516 */ | |
1622 | { 0x0000, 0x0000 }, /* R1517 */ | |
1623 | { 0x0000, 0x0000 }, /* R1518 */ | |
1624 | { 0x0000, 0x0000 }, /* R1519 */ | |
1625 | { 0x0000, 0x0000 }, /* R1520 */ | |
1626 | { 0x0000, 0x0000 }, /* R1521 */ | |
1627 | { 0x0000, 0x0000 }, /* R1522 */ | |
1628 | { 0x0000, 0x0000 }, /* R1523 */ | |
1629 | { 0x0000, 0x0000 }, /* R1524 */ | |
1630 | { 0x0000, 0x0000 }, /* R1525 */ | |
1631 | { 0x0000, 0x0000 }, /* R1526 */ | |
1632 | { 0x0000, 0x0000 }, /* R1527 */ | |
1633 | { 0x0000, 0x0000 }, /* R1528 */ | |
1634 | { 0x0000, 0x0000 }, /* R1529 */ | |
1635 | { 0x0000, 0x0000 }, /* R1530 */ | |
1636 | { 0x0000, 0x0000 }, /* R1531 */ | |
1637 | { 0x0000, 0x0000 }, /* R1532 */ | |
1638 | { 0x0000, 0x0000 }, /* R1533 */ | |
1639 | { 0x0000, 0x0000 }, /* R1534 */ | |
1640 | { 0x0000, 0x0000 }, /* R1535 */ | |
1641 | { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */ | |
1642 | { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */ | |
1643 | { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */ | |
1644 | { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */ | |
1645 | { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */ | |
1646 | { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */ | |
1647 | { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ | |
1648 | { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ | |
1649 | { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ | |
1650 | { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */ | |
1651 | { 0x0000, 0x0000 }, /* R1546 */ | |
1652 | { 0x0000, 0x0000 }, /* R1547 */ | |
1653 | { 0x0000, 0x0000 }, /* R1548 */ | |
1654 | { 0x0000, 0x0000 }, /* R1549 */ | |
1655 | { 0x0000, 0x0000 }, /* R1550 */ | |
1656 | { 0x0000, 0x0000 }, /* R1551 */ | |
1657 | { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */ | |
1658 | { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */ | |
1659 | { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */ | |
1660 | { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */ | |
1661 | { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */ | |
1662 | { 0x0000, 0x0000 }, /* R1557 */ | |
1663 | { 0x0000, 0x0000 }, /* R1558 */ | |
1664 | { 0x0000, 0x0000 }, /* R1559 */ | |
1665 | { 0x0000, 0x0000 }, /* R1560 */ | |
1666 | { 0x0000, 0x0000 }, /* R1561 */ | |
1667 | { 0x0000, 0x0000 }, /* R1562 */ | |
1668 | { 0x0000, 0x0000 }, /* R1563 */ | |
1669 | { 0x0000, 0x0000 }, /* R1564 */ | |
1670 | { 0x0000, 0x0000 }, /* R1565 */ | |
1671 | { 0x0000, 0x0000 }, /* R1566 */ | |
1672 | { 0x0000, 0x0000 }, /* R1567 */ | |
1673 | { 0x0003, 0x0003 }, /* R1568 - Oversampling */ | |
1674 | { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */ | |
9e6e96a1 MB |
1675 | }; |
1676 | ||
1677 | static int wm8994_readable(unsigned int reg) | |
1678 | { | |
e88ff1e6 MB |
1679 | switch (reg) { |
1680 | case WM8994_GPIO_1: | |
1681 | case WM8994_GPIO_2: | |
1682 | case WM8994_GPIO_3: | |
1683 | case WM8994_GPIO_4: | |
1684 | case WM8994_GPIO_5: | |
1685 | case WM8994_GPIO_6: | |
1686 | case WM8994_GPIO_7: | |
1687 | case WM8994_GPIO_8: | |
1688 | case WM8994_GPIO_9: | |
1689 | case WM8994_GPIO_10: | |
1690 | case WM8994_GPIO_11: | |
1691 | case WM8994_INTERRUPT_STATUS_1: | |
1692 | case WM8994_INTERRUPT_STATUS_2: | |
1693 | case WM8994_INTERRUPT_RAW_STATUS_2: | |
1694 | return 1; | |
1695 | default: | |
1696 | break; | |
1697 | } | |
1698 | ||
9e6e96a1 MB |
1699 | if (reg >= ARRAY_SIZE(access_masks)) |
1700 | return 0; | |
1701 | return access_masks[reg].readable != 0; | |
1702 | } | |
1703 | ||
1704 | static int wm8994_volatile(unsigned int reg) | |
1705 | { | |
1706 | if (reg >= WM8994_REG_CACHE_SIZE) | |
1707 | return 1; | |
1708 | ||
1709 | switch (reg) { | |
1710 | case WM8994_SOFTWARE_RESET: | |
1711 | case WM8994_CHIP_REVISION: | |
1712 | case WM8994_DC_SERVO_1: | |
1713 | case WM8994_DC_SERVO_READBACK: | |
1714 | case WM8994_RATE_STATUS: | |
1715 | case WM8994_LDO_1: | |
1716 | case WM8994_LDO_2: | |
1717 | return 1; | |
1718 | default: | |
1719 | return 0; | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, | |
1724 | unsigned int value) | |
1725 | { | |
b2c812e2 | 1726 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
1727 | |
1728 | BUG_ON(reg > WM8994_MAX_REGISTER); | |
1729 | ||
1730 | if (!wm8994_volatile(reg)) | |
1731 | wm8994->reg_cache[reg] = value; | |
1732 | ||
fd5722e5 MB |
1733 | dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value); |
1734 | ||
9e6e96a1 MB |
1735 | return wm8994_reg_write(codec->control_data, reg, value); |
1736 | } | |
1737 | ||
1738 | static unsigned int wm8994_read(struct snd_soc_codec *codec, | |
1739 | unsigned int reg) | |
1740 | { | |
1741 | u16 *reg_cache = codec->reg_cache; | |
1742 | ||
1743 | BUG_ON(reg > WM8994_MAX_REGISTER); | |
1744 | ||
1745 | if (wm8994_volatile(reg)) | |
1746 | return wm8994_reg_read(codec->control_data, reg); | |
1747 | else | |
1748 | return reg_cache[reg]; | |
1749 | } | |
1750 | ||
1751 | static int configure_aif_clock(struct snd_soc_codec *codec, int aif) | |
1752 | { | |
b2c812e2 | 1753 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
1754 | int rate; |
1755 | int reg1 = 0; | |
1756 | int offset; | |
1757 | ||
1758 | if (aif) | |
1759 | offset = 4; | |
1760 | else | |
1761 | offset = 0; | |
1762 | ||
1763 | switch (wm8994->sysclk[aif]) { | |
1764 | case WM8994_SYSCLK_MCLK1: | |
1765 | rate = wm8994->mclk[0]; | |
1766 | break; | |
1767 | ||
1768 | case WM8994_SYSCLK_MCLK2: | |
1769 | reg1 |= 0x8; | |
1770 | rate = wm8994->mclk[1]; | |
1771 | break; | |
1772 | ||
1773 | case WM8994_SYSCLK_FLL1: | |
1774 | reg1 |= 0x10; | |
1775 | rate = wm8994->fll[0].out; | |
1776 | break; | |
1777 | ||
1778 | case WM8994_SYSCLK_FLL2: | |
1779 | reg1 |= 0x18; | |
1780 | rate = wm8994->fll[1].out; | |
1781 | break; | |
1782 | ||
1783 | default: | |
1784 | return -EINVAL; | |
1785 | } | |
1786 | ||
1787 | if (rate >= 13500000) { | |
1788 | rate /= 2; | |
1789 | reg1 |= WM8994_AIF1CLK_DIV; | |
1790 | ||
1791 | dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", | |
1792 | aif + 1, rate); | |
1793 | } | |
5e5e2bef MB |
1794 | |
1795 | if (rate && rate < 3000000) | |
1796 | dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n", | |
1797 | aif + 1, rate); | |
1798 | ||
9e6e96a1 MB |
1799 | wm8994->aifclk[aif] = rate; |
1800 | ||
1801 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, | |
1802 | WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, | |
1803 | reg1); | |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | static int configure_clock(struct snd_soc_codec *codec) | |
1809 | { | |
b2c812e2 | 1810 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
1811 | int old, new; |
1812 | ||
1813 | /* Bring up the AIF clocks first */ | |
1814 | configure_aif_clock(codec, 0); | |
1815 | configure_aif_clock(codec, 1); | |
1816 | ||
1817 | /* Then switch CLK_SYS over to the higher of them; a change | |
1818 | * can only happen as a result of a clocking change which can | |
1819 | * only be made outside of DAPM so we can safely redo the | |
1820 | * clocking. | |
1821 | */ | |
1822 | ||
1823 | /* If they're equal it doesn't matter which is used */ | |
1824 | if (wm8994->aifclk[0] == wm8994->aifclk[1]) | |
1825 | return 0; | |
1826 | ||
1827 | if (wm8994->aifclk[0] < wm8994->aifclk[1]) | |
1828 | new = WM8994_SYSCLK_SRC; | |
1829 | else | |
1830 | new = 0; | |
1831 | ||
1832 | old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC; | |
1833 | ||
1834 | /* If there's no change then we're done. */ | |
1835 | if (old == new) | |
1836 | return 0; | |
1837 | ||
1838 | snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); | |
1839 | ||
1840 | snd_soc_dapm_sync(codec); | |
1841 | ||
1842 | return 0; | |
1843 | } | |
1844 | ||
1845 | static int check_clk_sys(struct snd_soc_dapm_widget *source, | |
1846 | struct snd_soc_dapm_widget *sink) | |
1847 | { | |
1848 | int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); | |
1849 | const char *clk; | |
1850 | ||
1851 | /* Check what we're currently using for CLK_SYS */ | |
1852 | if (reg & WM8994_SYSCLK_SRC) | |
1853 | clk = "AIF2CLK"; | |
1854 | else | |
1855 | clk = "AIF1CLK"; | |
1856 | ||
1857 | return strcmp(source->name, clk) == 0; | |
1858 | } | |
1859 | ||
1860 | static const char *sidetone_hpf_text[] = { | |
1861 | "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" | |
1862 | }; | |
1863 | ||
1864 | static const struct soc_enum sidetone_hpf = | |
1865 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); | |
1866 | ||
1867 | static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); | |
1868 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
1869 | static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); | |
1870 | static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); | |
1871 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
1872 | ||
1873 | #define WM8994_DRC_SWITCH(xname, reg, shift) \ | |
1874 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1875 | .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ | |
1876 | .put = wm8994_put_drc_sw, \ | |
1877 | .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } | |
1878 | ||
1879 | static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, | |
1880 | struct snd_ctl_elem_value *ucontrol) | |
1881 | { | |
1882 | struct soc_mixer_control *mc = | |
1883 | (struct soc_mixer_control *)kcontrol->private_value; | |
1884 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1885 | int mask, ret; | |
1886 | ||
1887 | /* Can't enable both ADC and DAC paths simultaneously */ | |
1888 | if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) | |
1889 | mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | | |
1890 | WM8994_AIF1ADC1R_DRC_ENA_MASK; | |
1891 | else | |
1892 | mask = WM8994_AIF1DAC1_DRC_ENA_MASK; | |
1893 | ||
1894 | ret = snd_soc_read(codec, mc->reg); | |
1895 | if (ret < 0) | |
1896 | return ret; | |
1897 | if (ret & mask) | |
1898 | return -EINVAL; | |
1899 | ||
1900 | return snd_soc_put_volsw(kcontrol, ucontrol); | |
1901 | } | |
1902 | ||
9e6e96a1 MB |
1903 | static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) |
1904 | { | |
b2c812e2 | 1905 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
1906 | struct wm8994_pdata *pdata = wm8994->pdata; |
1907 | int base = wm8994_drc_base[drc]; | |
1908 | int cfg = wm8994->drc_cfg[drc]; | |
1909 | int save, i; | |
1910 | ||
1911 | /* Save any enables; the configuration should clear them. */ | |
1912 | save = snd_soc_read(codec, base); | |
1913 | save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | | |
1914 | WM8994_AIF1ADC1R_DRC_ENA; | |
1915 | ||
1916 | for (i = 0; i < WM8994_DRC_REGS; i++) | |
1917 | snd_soc_update_bits(codec, base + i, 0xffff, | |
1918 | pdata->drc_cfgs[cfg].regs[i]); | |
1919 | ||
1920 | snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | | |
1921 | WM8994_AIF1ADC1L_DRC_ENA | | |
1922 | WM8994_AIF1ADC1R_DRC_ENA, save); | |
1923 | } | |
1924 | ||
1925 | /* Icky as hell but saves code duplication */ | |
1926 | static int wm8994_get_drc(const char *name) | |
1927 | { | |
1928 | if (strcmp(name, "AIF1DRC1 Mode") == 0) | |
1929 | return 0; | |
1930 | if (strcmp(name, "AIF1DRC2 Mode") == 0) | |
1931 | return 1; | |
1932 | if (strcmp(name, "AIF2DRC Mode") == 0) | |
1933 | return 2; | |
1934 | return -EINVAL; | |
1935 | } | |
1936 | ||
1937 | static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, | |
1938 | struct snd_ctl_elem_value *ucontrol) | |
1939 | { | |
1940 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 1941 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
1942 | struct wm8994_pdata *pdata = wm8994->pdata; |
1943 | int drc = wm8994_get_drc(kcontrol->id.name); | |
1944 | int value = ucontrol->value.integer.value[0]; | |
1945 | ||
1946 | if (drc < 0) | |
1947 | return drc; | |
1948 | ||
1949 | if (value >= pdata->num_drc_cfgs) | |
1950 | return -EINVAL; | |
1951 | ||
1952 | wm8994->drc_cfg[drc] = value; | |
1953 | ||
1954 | wm8994_set_drc(codec, drc); | |
1955 | ||
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, | |
1960 | struct snd_ctl_elem_value *ucontrol) | |
1961 | { | |
1962 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 1963 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
1964 | int drc = wm8994_get_drc(kcontrol->id.name); |
1965 | ||
1966 | ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; | |
1967 | ||
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) | |
1972 | { | |
b2c812e2 | 1973 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
1974 | struct wm8994_pdata *pdata = wm8994->pdata; |
1975 | int base = wm8994_retune_mobile_base[block]; | |
1976 | int iface, best, best_val, save, i, cfg; | |
1977 | ||
1978 | if (!pdata || !wm8994->num_retune_mobile_texts) | |
1979 | return; | |
1980 | ||
1981 | switch (block) { | |
1982 | case 0: | |
1983 | case 1: | |
1984 | iface = 0; | |
1985 | break; | |
1986 | case 2: | |
1987 | iface = 1; | |
1988 | break; | |
1989 | default: | |
1990 | return; | |
1991 | } | |
1992 | ||
1993 | /* Find the version of the currently selected configuration | |
1994 | * with the nearest sample rate. */ | |
1995 | cfg = wm8994->retune_mobile_cfg[block]; | |
1996 | best = 0; | |
1997 | best_val = INT_MAX; | |
1998 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
1999 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
2000 | wm8994->retune_mobile_texts[cfg]) == 0 && | |
2001 | abs(pdata->retune_mobile_cfgs[i].rate | |
2002 | - wm8994->dac_rates[iface]) < best_val) { | |
2003 | best = i; | |
2004 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
2005 | - wm8994->dac_rates[iface]); | |
2006 | } | |
2007 | } | |
2008 | ||
2009 | dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", | |
2010 | block, | |
2011 | pdata->retune_mobile_cfgs[best].name, | |
2012 | pdata->retune_mobile_cfgs[best].rate, | |
2013 | wm8994->dac_rates[iface]); | |
2014 | ||
2015 | /* The EQ will be disabled while reconfiguring it, remember the | |
2016 | * current configuration. | |
2017 | */ | |
2018 | save = snd_soc_read(codec, base); | |
2019 | save &= WM8994_AIF1DAC1_EQ_ENA; | |
2020 | ||
2021 | for (i = 0; i < WM8994_EQ_REGS; i++) | |
2022 | snd_soc_update_bits(codec, base + i, 0xffff, | |
2023 | pdata->retune_mobile_cfgs[best].regs[i]); | |
2024 | ||
2025 | snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); | |
2026 | } | |
2027 | ||
2028 | /* Icky as hell but saves code duplication */ | |
2029 | static int wm8994_get_retune_mobile_block(const char *name) | |
2030 | { | |
2031 | if (strcmp(name, "AIF1.1 EQ Mode") == 0) | |
2032 | return 0; | |
2033 | if (strcmp(name, "AIF1.2 EQ Mode") == 0) | |
2034 | return 1; | |
2035 | if (strcmp(name, "AIF2 EQ Mode") == 0) | |
2036 | return 2; | |
2037 | return -EINVAL; | |
2038 | } | |
2039 | ||
2040 | static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
2041 | struct snd_ctl_elem_value *ucontrol) | |
2042 | { | |
2043 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 2044 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
2045 | struct wm8994_pdata *pdata = wm8994->pdata; |
2046 | int block = wm8994_get_retune_mobile_block(kcontrol->id.name); | |
2047 | int value = ucontrol->value.integer.value[0]; | |
2048 | ||
2049 | if (block < 0) | |
2050 | return block; | |
2051 | ||
2052 | if (value >= pdata->num_retune_mobile_cfgs) | |
2053 | return -EINVAL; | |
2054 | ||
2055 | wm8994->retune_mobile_cfg[block] = value; | |
2056 | ||
2057 | wm8994_set_retune_mobile(codec, block); | |
2058 | ||
2059 | return 0; | |
2060 | } | |
2061 | ||
2062 | static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
2063 | struct snd_ctl_elem_value *ucontrol) | |
2064 | { | |
2065 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 2066 | struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
2067 | int block = wm8994_get_retune_mobile_block(kcontrol->id.name); |
2068 | ||
2069 | ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; | |
2070 | ||
2071 | return 0; | |
2072 | } | |
2073 | ||
f554885f MB |
2074 | static const char *aifdac_src_text[] = { |
2075 | "Left", "Right" | |
2076 | }; | |
2077 | ||
2078 | static const struct soc_enum aif1dacl_src = | |
2079 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aifdac_src_text); | |
2080 | ||
2081 | static const struct soc_enum aif1dacr_src = | |
2082 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aifdac_src_text); | |
2083 | ||
2084 | static const struct soc_enum aif2dacl_src = | |
2085 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aifdac_src_text); | |
2086 | ||
2087 | static const struct soc_enum aif2dacr_src = | |
2088 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aifdac_src_text); | |
2089 | ||
9e6e96a1 MB |
2090 | static const struct snd_kcontrol_new wm8994_snd_controls[] = { |
2091 | SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, | |
2092 | WM8994_AIF1_ADC1_RIGHT_VOLUME, | |
2093 | 1, 119, 0, digital_tlv), | |
2094 | SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, | |
2095 | WM8994_AIF1_ADC2_RIGHT_VOLUME, | |
2096 | 1, 119, 0, digital_tlv), | |
2097 | SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, | |
2098 | WM8994_AIF2_ADC_RIGHT_VOLUME, | |
2099 | 1, 119, 0, digital_tlv), | |
2100 | ||
f554885f MB |
2101 | SOC_ENUM("AIF1DACL Source", aif1dacl_src), |
2102 | SOC_ENUM("AIF1DACR Source", aif1dacr_src), | |
2103 | SOC_ENUM("AIF2DACL Source", aif1dacl_src), | |
2104 | SOC_ENUM("AIF2DACR Source", aif1dacr_src), | |
2105 | ||
9e6e96a1 MB |
2106 | SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, |
2107 | WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
2108 | SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, | |
2109 | WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
2110 | SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, | |
2111 | WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
2112 | ||
2113 | SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), | |
2114 | SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), | |
2115 | ||
2116 | SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), | |
2117 | SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), | |
2118 | SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), | |
2119 | ||
2120 | WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), | |
2121 | WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), | |
2122 | WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), | |
2123 | ||
2124 | WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), | |
2125 | WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), | |
2126 | WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), | |
2127 | ||
2128 | WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), | |
2129 | WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), | |
2130 | WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), | |
2131 | ||
2132 | SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, | |
2133 | 5, 12, 0, st_tlv), | |
2134 | SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, | |
2135 | 0, 12, 0, st_tlv), | |
2136 | SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, | |
2137 | 5, 12, 0, st_tlv), | |
2138 | SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, | |
2139 | 0, 12, 0, st_tlv), | |
2140 | SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), | |
2141 | SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), | |
2142 | ||
2143 | SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, | |
2144 | WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
2145 | SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, | |
2146 | WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), | |
2147 | ||
2148 | SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, | |
2149 | WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
2150 | SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, | |
2151 | WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), | |
2152 | ||
2153 | SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, | |
2154 | 6, 1, 1, wm_hubs_spkmix_tlv), | |
2155 | SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, | |
2156 | 2, 1, 1, wm_hubs_spkmix_tlv), | |
2157 | ||
2158 | SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, | |
2159 | 6, 1, 1, wm_hubs_spkmix_tlv), | |
2160 | SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, | |
2161 | 2, 1, 1, wm_hubs_spkmix_tlv), | |
2162 | ||
2163 | SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, | |
2164 | 10, 15, 0, wm8994_3d_tlv), | |
2165 | SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, | |
2166 | 8, 1, 0), | |
2167 | SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, | |
2168 | 10, 15, 0, wm8994_3d_tlv), | |
2169 | SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, | |
2170 | 8, 1, 0), | |
2171 | SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, | |
2172 | 10, 15, 0, wm8994_3d_tlv), | |
2173 | SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, | |
2174 | 8, 1, 0), | |
2175 | }; | |
2176 | ||
2177 | static const struct snd_kcontrol_new wm8994_eq_controls[] = { | |
2178 | SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, | |
2179 | eq_tlv), | |
2180 | SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, | |
2181 | eq_tlv), | |
2182 | SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, | |
2183 | eq_tlv), | |
2184 | SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, | |
2185 | eq_tlv), | |
2186 | SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, | |
2187 | eq_tlv), | |
2188 | ||
2189 | SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, | |
2190 | eq_tlv), | |
2191 | SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, | |
2192 | eq_tlv), | |
2193 | SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, | |
2194 | eq_tlv), | |
2195 | SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, | |
2196 | eq_tlv), | |
2197 | SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, | |
2198 | eq_tlv), | |
2199 | ||
2200 | SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, | |
2201 | eq_tlv), | |
2202 | SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, | |
2203 | eq_tlv), | |
2204 | SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, | |
2205 | eq_tlv), | |
2206 | SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, | |
2207 | eq_tlv), | |
2208 | SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, | |
2209 | eq_tlv), | |
2210 | }; | |
2211 | ||
2212 | static int clk_sys_event(struct snd_soc_dapm_widget *w, | |
2213 | struct snd_kcontrol *kcontrol, int event) | |
2214 | { | |
2215 | struct snd_soc_codec *codec = w->codec; | |
2216 | ||
2217 | switch (event) { | |
2218 | case SND_SOC_DAPM_PRE_PMU: | |
2219 | return configure_clock(codec); | |
2220 | ||
2221 | case SND_SOC_DAPM_POST_PMD: | |
2222 | configure_clock(codec); | |
2223 | break; | |
2224 | } | |
2225 | ||
2226 | return 0; | |
2227 | } | |
2228 | ||
2229 | static void wm8994_update_class_w(struct snd_soc_codec *codec) | |
2230 | { | |
2231 | int enable = 1; | |
2232 | int source = 0; /* GCC flow analysis can't track enable */ | |
2233 | int reg, reg_r; | |
2234 | ||
2235 | /* Only support direct DAC->headphone paths */ | |
2236 | reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1); | |
2237 | if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) { | |
ee839a21 | 2238 | dev_vdbg(codec->dev, "HPL connected to output mixer\n"); |
9e6e96a1 MB |
2239 | enable = 0; |
2240 | } | |
2241 | ||
2242 | reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2); | |
2243 | if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) { | |
ee839a21 | 2244 | dev_vdbg(codec->dev, "HPR connected to output mixer\n"); |
9e6e96a1 MB |
2245 | enable = 0; |
2246 | } | |
2247 | ||
2248 | /* We also need the same setting for L/R and only one path */ | |
2249 | reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); | |
2250 | switch (reg) { | |
2251 | case WM8994_AIF2DACL_TO_DAC1L: | |
ee839a21 | 2252 | dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); |
9e6e96a1 MB |
2253 | source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
2254 | break; | |
2255 | case WM8994_AIF1DAC2L_TO_DAC1L: | |
ee839a21 | 2256 | dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); |
9e6e96a1 MB |
2257 | source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
2258 | break; | |
2259 | case WM8994_AIF1DAC1L_TO_DAC1L: | |
ee839a21 | 2260 | dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); |
9e6e96a1 MB |
2261 | source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
2262 | break; | |
2263 | default: | |
ee839a21 | 2264 | dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); |
9e6e96a1 MB |
2265 | enable = 0; |
2266 | break; | |
2267 | } | |
2268 | ||
2269 | reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); | |
2270 | if (reg_r != reg) { | |
ee839a21 | 2271 | dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); |
9e6e96a1 MB |
2272 | enable = 0; |
2273 | } | |
2274 | ||
2275 | if (enable) { | |
2276 | dev_dbg(codec->dev, "Class W enabled\n"); | |
2277 | snd_soc_update_bits(codec, WM8994_CLASS_W_1, | |
2278 | WM8994_CP_DYN_PWR | | |
2279 | WM8994_CP_DYN_SRC_SEL_MASK, | |
2280 | source | WM8994_CP_DYN_PWR); | |
2281 | ||
2282 | } else { | |
2283 | dev_dbg(codec->dev, "Class W disabled\n"); | |
2284 | snd_soc_update_bits(codec, WM8994_CLASS_W_1, | |
2285 | WM8994_CP_DYN_PWR, 0); | |
2286 | } | |
2287 | } | |
2288 | ||
2289 | static const char *hp_mux_text[] = { | |
2290 | "Mixer", | |
2291 | "DAC", | |
2292 | }; | |
2293 | ||
2294 | #define WM8994_HP_ENUM(xname, xenum) \ | |
2295 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2296 | .info = snd_soc_info_enum_double, \ | |
2297 | .get = snd_soc_dapm_get_enum_double, \ | |
2298 | .put = wm8994_put_hp_enum, \ | |
2299 | .private_value = (unsigned long)&xenum } | |
2300 | ||
2301 | static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol, | |
2302 | struct snd_ctl_elem_value *ucontrol) | |
2303 | { | |
2304 | struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); | |
2305 | struct snd_soc_codec *codec = w->codec; | |
2306 | int ret; | |
2307 | ||
2308 | ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); | |
2309 | ||
2310 | wm8994_update_class_w(codec); | |
2311 | ||
2312 | return ret; | |
2313 | } | |
2314 | ||
2315 | static const struct soc_enum hpl_enum = | |
2316 | SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text); | |
2317 | ||
2318 | static const struct snd_kcontrol_new hpl_mux = | |
2319 | WM8994_HP_ENUM("Left Headphone Mux", hpl_enum); | |
2320 | ||
2321 | static const struct soc_enum hpr_enum = | |
2322 | SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text); | |
2323 | ||
2324 | static const struct snd_kcontrol_new hpr_mux = | |
2325 | WM8994_HP_ENUM("Right Headphone Mux", hpr_enum); | |
2326 | ||
2327 | static const char *adc_mux_text[] = { | |
2328 | "ADC", | |
2329 | "DMIC", | |
2330 | }; | |
2331 | ||
2332 | static const struct soc_enum adc_enum = | |
2333 | SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); | |
2334 | ||
2335 | static const struct snd_kcontrol_new adcl_mux = | |
2336 | SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); | |
2337 | ||
2338 | static const struct snd_kcontrol_new adcr_mux = | |
2339 | SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); | |
2340 | ||
2341 | static const struct snd_kcontrol_new left_speaker_mixer[] = { | |
2342 | SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), | |
2343 | SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), | |
2344 | SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), | |
2345 | SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), | |
2346 | SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), | |
2347 | }; | |
2348 | ||
2349 | static const struct snd_kcontrol_new right_speaker_mixer[] = { | |
2350 | SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), | |
2351 | SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), | |
2352 | SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), | |
2353 | SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), | |
2354 | SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), | |
2355 | }; | |
2356 | ||
2357 | /* Debugging; dump chip status after DAPM transitions */ | |
2358 | static int post_ev(struct snd_soc_dapm_widget *w, | |
2359 | struct snd_kcontrol *kcontrol, int event) | |
2360 | { | |
2361 | struct snd_soc_codec *codec = w->codec; | |
2362 | dev_dbg(codec->dev, "SRC status: %x\n", | |
2363 | snd_soc_read(codec, | |
2364 | WM8994_RATE_STATUS)); | |
2365 | return 0; | |
2366 | } | |
2367 | ||
2368 | static const struct snd_kcontrol_new aif1adc1l_mix[] = { | |
2369 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
2370 | 1, 1, 0), | |
2371 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
2372 | 0, 1, 0), | |
2373 | }; | |
2374 | ||
2375 | static const struct snd_kcontrol_new aif1adc1r_mix[] = { | |
2376 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
2377 | 1, 1, 0), | |
2378 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
2379 | 0, 1, 0), | |
2380 | }; | |
2381 | ||
a3257ba8 MB |
2382 | static const struct snd_kcontrol_new aif1adc2l_mix[] = { |
2383 | SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
2384 | 1, 1, 0), | |
2385 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
2386 | 0, 1, 0), | |
2387 | }; | |
2388 | ||
2389 | static const struct snd_kcontrol_new aif1adc2r_mix[] = { | |
2390 | SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
2391 | 1, 1, 0), | |
2392 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
2393 | 0, 1, 0), | |
2394 | }; | |
2395 | ||
9e6e96a1 MB |
2396 | static const struct snd_kcontrol_new aif2dac2l_mix[] = { |
2397 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
2398 | 5, 1, 0), | |
2399 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
2400 | 4, 1, 0), | |
2401 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
2402 | 2, 1, 0), | |
2403 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
2404 | 1, 1, 0), | |
2405 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
2406 | 0, 1, 0), | |
2407 | }; | |
2408 | ||
2409 | static const struct snd_kcontrol_new aif2dac2r_mix[] = { | |
2410 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
2411 | 5, 1, 0), | |
2412 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
2413 | 4, 1, 0), | |
2414 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
2415 | 2, 1, 0), | |
2416 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
2417 | 1, 1, 0), | |
2418 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
2419 | 0, 1, 0), | |
2420 | }; | |
2421 | ||
2422 | #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ | |
2423 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2424 | .info = snd_soc_info_volsw, \ | |
2425 | .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ | |
2426 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } | |
2427 | ||
2428 | static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, | |
2429 | struct snd_ctl_elem_value *ucontrol) | |
2430 | { | |
2431 | struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); | |
2432 | struct snd_soc_codec *codec = w->codec; | |
2433 | int ret; | |
2434 | ||
2435 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); | |
2436 | ||
2437 | wm8994_update_class_w(codec); | |
2438 | ||
2439 | return ret; | |
2440 | } | |
2441 | ||
2442 | static const struct snd_kcontrol_new dac1l_mix[] = { | |
2443 | WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
2444 | 5, 1, 0), | |
2445 | WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
2446 | 4, 1, 0), | |
2447 | WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
2448 | 2, 1, 0), | |
2449 | WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
2450 | 1, 1, 0), | |
2451 | WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
2452 | 0, 1, 0), | |
2453 | }; | |
2454 | ||
2455 | static const struct snd_kcontrol_new dac1r_mix[] = { | |
2456 | WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
2457 | 5, 1, 0), | |
2458 | WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
2459 | 4, 1, 0), | |
2460 | WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
2461 | 2, 1, 0), | |
2462 | WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
2463 | 1, 1, 0), | |
2464 | WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
2465 | 0, 1, 0), | |
2466 | }; | |
2467 | ||
2468 | static const char *sidetone_text[] = { | |
2469 | "ADC/DMIC1", "DMIC2", | |
2470 | }; | |
2471 | ||
2472 | static const struct soc_enum sidetone1_enum = | |
2473 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); | |
2474 | ||
2475 | static const struct snd_kcontrol_new sidetone1_mux = | |
2476 | SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); | |
2477 | ||
2478 | static const struct soc_enum sidetone2_enum = | |
2479 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); | |
2480 | ||
2481 | static const struct snd_kcontrol_new sidetone2_mux = | |
2482 | SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); | |
2483 | ||
2484 | static const char *aif1dac_text[] = { | |
2485 | "AIF1DACDAT", "AIF3DACDAT", | |
2486 | }; | |
2487 | ||
2488 | static const struct soc_enum aif1dac_enum = | |
2489 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); | |
2490 | ||
2491 | static const struct snd_kcontrol_new aif1dac_mux = | |
2492 | SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); | |
2493 | ||
2494 | static const char *aif2dac_text[] = { | |
2495 | "AIF2DACDAT", "AIF3DACDAT", | |
2496 | }; | |
2497 | ||
2498 | static const struct soc_enum aif2dac_enum = | |
2499 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); | |
2500 | ||
2501 | static const struct snd_kcontrol_new aif2dac_mux = | |
2502 | SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); | |
2503 | ||
2504 | static const char *aif2adc_text[] = { | |
2505 | "AIF2ADCDAT", "AIF3DACDAT", | |
2506 | }; | |
2507 | ||
2508 | static const struct soc_enum aif2adc_enum = | |
2509 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); | |
2510 | ||
2511 | static const struct snd_kcontrol_new aif2adc_mux = | |
2512 | SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); | |
2513 | ||
2514 | static const char *aif3adc_text[] = { | |
2515 | "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", | |
2516 | }; | |
2517 | ||
2518 | static const struct soc_enum aif3adc_enum = | |
2519 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); | |
2520 | ||
2521 | static const struct snd_kcontrol_new aif3adc_mux = | |
2522 | SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum); | |
2523 | ||
2524 | static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { | |
2525 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
2526 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
66b47fdb | 2527 | SND_SOC_DAPM_INPUT("Clock"), |
9e6e96a1 MB |
2528 | |
2529 | SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, | |
2530 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
2531 | ||
2532 | SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0), | |
2533 | SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0), | |
2534 | SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0), | |
2535 | ||
2536 | SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0), | |
2537 | SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0), | |
2538 | ||
2539 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", | |
2540 | 0, WM8994_POWER_MANAGEMENT_4, 9, 0), | |
2541 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", | |
2542 | 0, WM8994_POWER_MANAGEMENT_4, 8, 0), | |
2543 | SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, | |
2544 | WM8994_POWER_MANAGEMENT_5, 9, 0), | |
2545 | SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, | |
2546 | WM8994_POWER_MANAGEMENT_5, 8, 0), | |
2547 | ||
2548 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", | |
2549 | 0, WM8994_POWER_MANAGEMENT_4, 11, 0), | |
2550 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", | |
2551 | 0, WM8994_POWER_MANAGEMENT_4, 10, 0), | |
2552 | SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, | |
2553 | WM8994_POWER_MANAGEMENT_5, 11, 0), | |
2554 | SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, | |
2555 | WM8994_POWER_MANAGEMENT_5, 10, 0), | |
2556 | ||
2557 | SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, | |
2558 | aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), | |
2559 | SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, | |
2560 | aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), | |
2561 | ||
a3257ba8 MB |
2562 | SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, |
2563 | aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), | |
2564 | SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, | |
2565 | aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), | |
2566 | ||
9e6e96a1 MB |
2567 | SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, |
2568 | aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), | |
2569 | SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, | |
2570 | aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), | |
2571 | ||
2572 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), | |
2573 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), | |
2574 | ||
2575 | SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, | |
2576 | dac1l_mix, ARRAY_SIZE(dac1l_mix)), | |
2577 | SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, | |
2578 | dac1r_mix, ARRAY_SIZE(dac1r_mix)), | |
2579 | ||
2580 | SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, | |
2581 | WM8994_POWER_MANAGEMENT_4, 13, 0), | |
2582 | SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, | |
2583 | WM8994_POWER_MANAGEMENT_4, 12, 0), | |
2584 | SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0, | |
2585 | WM8994_POWER_MANAGEMENT_5, 13, 0), | |
2586 | SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0, | |
2587 | WM8994_POWER_MANAGEMENT_5, 12, 0), | |
2588 | ||
2589 | SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2590 | SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2591 | SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
2592 | ||
2593 | SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), | |
2594 | SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), | |
2595 | SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), | |
2596 | SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux), | |
2597 | ||
2598 | SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2599 | SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), | |
2600 | ||
2601 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), | |
2602 | ||
2603 | SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), | |
2604 | SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), | |
2605 | SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), | |
2606 | SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), | |
2607 | ||
2608 | /* Power is done with the muxes since the ADC power also controls the | |
2609 | * downsampling chain, the chip will automatically manage the analogue | |
2610 | * specific portions. | |
2611 | */ | |
2612 | SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), | |
2613 | SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), | |
2614 | ||
2615 | SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), | |
2616 | SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), | |
2617 | ||
2618 | SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), | |
2619 | SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), | |
2620 | SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), | |
2621 | SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), | |
2622 | ||
2623 | SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), | |
2624 | SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), | |
2625 | ||
2626 | SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, | |
2627 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), | |
2628 | SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, | |
2629 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), | |
2630 | ||
2631 | SND_SOC_DAPM_POST("Debug log", post_ev), | |
2632 | }; | |
2633 | ||
2634 | static const struct snd_soc_dapm_route intercon[] = { | |
2635 | ||
2636 | { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, | |
2637 | { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, | |
2638 | ||
2639 | { "DSP1CLK", NULL, "CLK_SYS" }, | |
2640 | { "DSP2CLK", NULL, "CLK_SYS" }, | |
2641 | { "DSPINTCLK", NULL, "CLK_SYS" }, | |
2642 | ||
2643 | { "AIF1ADC1L", NULL, "AIF1CLK" }, | |
2644 | { "AIF1ADC1L", NULL, "DSP1CLK" }, | |
2645 | { "AIF1ADC1R", NULL, "AIF1CLK" }, | |
2646 | { "AIF1ADC1R", NULL, "DSP1CLK" }, | |
2647 | { "AIF1ADC1R", NULL, "DSPINTCLK" }, | |
2648 | ||
2649 | { "AIF1DAC1L", NULL, "AIF1CLK" }, | |
2650 | { "AIF1DAC1L", NULL, "DSP1CLK" }, | |
2651 | { "AIF1DAC1R", NULL, "AIF1CLK" }, | |
2652 | { "AIF1DAC1R", NULL, "DSP1CLK" }, | |
2653 | { "AIF1DAC1R", NULL, "DSPINTCLK" }, | |
2654 | ||
2655 | { "AIF1ADC2L", NULL, "AIF1CLK" }, | |
2656 | { "AIF1ADC2L", NULL, "DSP1CLK" }, | |
2657 | { "AIF1ADC2R", NULL, "AIF1CLK" }, | |
2658 | { "AIF1ADC2R", NULL, "DSP1CLK" }, | |
2659 | { "AIF1ADC2R", NULL, "DSPINTCLK" }, | |
2660 | ||
2661 | { "AIF1DAC2L", NULL, "AIF1CLK" }, | |
2662 | { "AIF1DAC2L", NULL, "DSP1CLK" }, | |
2663 | { "AIF1DAC2R", NULL, "AIF1CLK" }, | |
2664 | { "AIF1DAC2R", NULL, "DSP1CLK" }, | |
2665 | { "AIF1DAC2R", NULL, "DSPINTCLK" }, | |
2666 | ||
2667 | { "AIF2ADCL", NULL, "AIF2CLK" }, | |
2668 | { "AIF2ADCL", NULL, "DSP2CLK" }, | |
2669 | { "AIF2ADCR", NULL, "AIF2CLK" }, | |
2670 | { "AIF2ADCR", NULL, "DSP2CLK" }, | |
2671 | { "AIF2ADCR", NULL, "DSPINTCLK" }, | |
2672 | ||
2673 | { "AIF2DACL", NULL, "AIF2CLK" }, | |
2674 | { "AIF2DACL", NULL, "DSP2CLK" }, | |
2675 | { "AIF2DACR", NULL, "AIF2CLK" }, | |
2676 | { "AIF2DACR", NULL, "DSP2CLK" }, | |
2677 | { "AIF2DACR", NULL, "DSPINTCLK" }, | |
2678 | ||
2679 | { "DMIC1L", NULL, "DMIC1DAT" }, | |
2680 | { "DMIC1L", NULL, "CLK_SYS" }, | |
2681 | { "DMIC1R", NULL, "DMIC1DAT" }, | |
2682 | { "DMIC1R", NULL, "CLK_SYS" }, | |
2683 | { "DMIC2L", NULL, "DMIC2DAT" }, | |
2684 | { "DMIC2L", NULL, "CLK_SYS" }, | |
2685 | { "DMIC2R", NULL, "DMIC2DAT" }, | |
2686 | { "DMIC2R", NULL, "CLK_SYS" }, | |
2687 | ||
2688 | { "ADCL", NULL, "AIF1CLK" }, | |
2689 | { "ADCL", NULL, "DSP1CLK" }, | |
2690 | { "ADCL", NULL, "DSPINTCLK" }, | |
2691 | ||
2692 | { "ADCR", NULL, "AIF1CLK" }, | |
2693 | { "ADCR", NULL, "DSP1CLK" }, | |
2694 | { "ADCR", NULL, "DSPINTCLK" }, | |
2695 | ||
2696 | { "ADCL Mux", "ADC", "ADCL" }, | |
2697 | { "ADCL Mux", "DMIC", "DMIC1L" }, | |
2698 | { "ADCR Mux", "ADC", "ADCR" }, | |
2699 | { "ADCR Mux", "DMIC", "DMIC1R" }, | |
2700 | ||
2701 | { "DAC1L", NULL, "AIF1CLK" }, | |
2702 | { "DAC1L", NULL, "DSP1CLK" }, | |
2703 | { "DAC1L", NULL, "DSPINTCLK" }, | |
2704 | ||
2705 | { "DAC1R", NULL, "AIF1CLK" }, | |
2706 | { "DAC1R", NULL, "DSP1CLK" }, | |
2707 | { "DAC1R", NULL, "DSPINTCLK" }, | |
2708 | ||
2709 | { "DAC2L", NULL, "AIF2CLK" }, | |
2710 | { "DAC2L", NULL, "DSP2CLK" }, | |
2711 | { "DAC2L", NULL, "DSPINTCLK" }, | |
2712 | ||
2713 | { "DAC2R", NULL, "AIF2DACR" }, | |
2714 | { "DAC2R", NULL, "AIF2CLK" }, | |
2715 | { "DAC2R", NULL, "DSP2CLK" }, | |
2716 | { "DAC2R", NULL, "DSPINTCLK" }, | |
2717 | ||
2718 | { "TOCLK", NULL, "CLK_SYS" }, | |
2719 | ||
2720 | /* AIF1 outputs */ | |
2721 | { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, | |
2722 | { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, | |
2723 | { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, | |
2724 | ||
2725 | { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, | |
2726 | { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, | |
2727 | { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, | |
2728 | ||
a3257ba8 MB |
2729 | { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, |
2730 | { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, | |
2731 | { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, | |
2732 | ||
2733 | { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, | |
2734 | { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, | |
2735 | { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, | |
2736 | ||
9e6e96a1 MB |
2737 | /* Pin level routing for AIF3 */ |
2738 | { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, | |
2739 | { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, | |
2740 | { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, | |
2741 | { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, | |
2742 | ||
2743 | { "AIF2DACL", NULL, "AIF2DAC Mux" }, | |
2744 | { "AIF2DACR", NULL, "AIF2DAC Mux" }, | |
2745 | ||
2746 | { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, | |
2747 | { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, | |
2748 | { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, | |
2749 | { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, | |
2750 | { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, | |
2751 | { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, | |
2752 | { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, | |
2753 | ||
2754 | /* DAC1 inputs */ | |
2755 | { "DAC1L", NULL, "DAC1L Mixer" }, | |
2756 | { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, | |
2757 | { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
2758 | { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
2759 | { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
2760 | { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
2761 | ||
2762 | { "DAC1R", NULL, "DAC1R Mixer" }, | |
2763 | { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, | |
2764 | { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
2765 | { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
2766 | { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
2767 | { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
2768 | ||
2769 | /* DAC2/AIF2 outputs */ | |
2770 | { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, | |
2771 | { "DAC2L", NULL, "AIF2DAC2L Mixer" }, | |
2772 | { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, | |
2773 | { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
2774 | { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
2775 | { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
2776 | { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
2777 | ||
2778 | { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, | |
2779 | { "DAC2R", NULL, "AIF2DAC2R Mixer" }, | |
2780 | { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, | |
2781 | { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
2782 | { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
2783 | { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
2784 | { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
2785 | ||
2786 | { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, | |
2787 | ||
2788 | /* AIF3 output */ | |
2789 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, | |
2790 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, | |
2791 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, | |
2792 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, | |
2793 | { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, | |
2794 | { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, | |
2795 | { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, | |
2796 | { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, | |
2797 | ||
2798 | /* Sidetone */ | |
2799 | { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, | |
2800 | { "Left Sidetone", "DMIC2", "DMIC2L" }, | |
2801 | { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, | |
2802 | { "Right Sidetone", "DMIC2", "DMIC2R" }, | |
2803 | ||
2804 | /* Output stages */ | |
2805 | { "Left Output Mixer", "DAC Switch", "DAC1L" }, | |
2806 | { "Right Output Mixer", "DAC Switch", "DAC1R" }, | |
2807 | ||
2808 | { "SPKL", "DAC1 Switch", "DAC1L" }, | |
2809 | { "SPKL", "DAC2 Switch", "DAC2L" }, | |
2810 | ||
2811 | { "SPKR", "DAC1 Switch", "DAC1R" }, | |
2812 | { "SPKR", "DAC2 Switch", "DAC2R" }, | |
2813 | ||
2814 | { "Left Headphone Mux", "DAC", "DAC1L" }, | |
2815 | { "Right Headphone Mux", "DAC", "DAC1R" }, | |
2816 | }; | |
2817 | ||
2818 | /* The size in bits of the FLL divide multiplied by 10 | |
2819 | * to allow rounding later */ | |
2820 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
2821 | ||
2822 | struct fll_div { | |
2823 | u16 outdiv; | |
2824 | u16 n; | |
2825 | u16 k; | |
2826 | u16 clk_ref_div; | |
2827 | u16 fll_fratio; | |
2828 | }; | |
2829 | ||
2830 | static int wm8994_get_fll_config(struct fll_div *fll, | |
2831 | int freq_in, int freq_out) | |
2832 | { | |
2833 | u64 Kpart; | |
2834 | unsigned int K, Ndiv, Nmod; | |
2835 | ||
2836 | pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); | |
2837 | ||
2838 | /* Scale the input frequency down to <= 13.5MHz */ | |
2839 | fll->clk_ref_div = 0; | |
2840 | while (freq_in > 13500000) { | |
2841 | fll->clk_ref_div++; | |
2842 | freq_in /= 2; | |
2843 | ||
2844 | if (fll->clk_ref_div > 3) | |
2845 | return -EINVAL; | |
2846 | } | |
2847 | pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); | |
2848 | ||
2849 | /* Scale the output to give 90MHz<=Fvco<=100MHz */ | |
2850 | fll->outdiv = 3; | |
2851 | while (freq_out * (fll->outdiv + 1) < 90000000) { | |
2852 | fll->outdiv++; | |
2853 | if (fll->outdiv > 63) | |
2854 | return -EINVAL; | |
2855 | } | |
2856 | freq_out *= fll->outdiv + 1; | |
2857 | pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); | |
2858 | ||
2859 | if (freq_in > 1000000) { | |
2860 | fll->fll_fratio = 0; | |
7d48a6ac MB |
2861 | } else if (freq_in > 256000) { |
2862 | fll->fll_fratio = 1; | |
2863 | freq_in *= 2; | |
2864 | } else if (freq_in > 128000) { | |
2865 | fll->fll_fratio = 2; | |
2866 | freq_in *= 4; | |
2867 | } else if (freq_in > 64000) { | |
9e6e96a1 MB |
2868 | fll->fll_fratio = 3; |
2869 | freq_in *= 8; | |
7d48a6ac MB |
2870 | } else { |
2871 | fll->fll_fratio = 4; | |
2872 | freq_in *= 16; | |
9e6e96a1 MB |
2873 | } |
2874 | pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); | |
2875 | ||
2876 | /* Now, calculate N.K */ | |
2877 | Ndiv = freq_out / freq_in; | |
2878 | ||
2879 | fll->n = Ndiv; | |
2880 | Nmod = freq_out % freq_in; | |
2881 | pr_debug("Nmod=%d\n", Nmod); | |
2882 | ||
2883 | /* Calculate fractional part - scale up so we can round. */ | |
2884 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
2885 | ||
2886 | do_div(Kpart, freq_in); | |
2887 | ||
2888 | K = Kpart & 0xFFFFFFFF; | |
2889 | ||
2890 | if ((K % 10) >= 5) | |
2891 | K += 5; | |
2892 | ||
2893 | /* Move down to proper range now rounding is done */ | |
2894 | fll->k = K / 10; | |
2895 | ||
2896 | pr_debug("N=%x K=%x\n", fll->n, fll->k); | |
2897 | ||
2898 | return 0; | |
2899 | } | |
2900 | ||
f0fba2ad | 2901 | static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, |
9e6e96a1 MB |
2902 | unsigned int freq_in, unsigned int freq_out) |
2903 | { | |
b2c812e2 | 2904 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
2905 | int reg_offset, ret; |
2906 | struct fll_div fll; | |
2907 | u16 reg, aif1, aif2; | |
2908 | ||
2909 | aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1) | |
2910 | & WM8994_AIF1CLK_ENA; | |
2911 | ||
2912 | aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1) | |
2913 | & WM8994_AIF2CLK_ENA; | |
2914 | ||
2915 | switch (id) { | |
2916 | case WM8994_FLL1: | |
2917 | reg_offset = 0; | |
2918 | id = 0; | |
2919 | break; | |
2920 | case WM8994_FLL2: | |
2921 | reg_offset = 0x20; | |
2922 | id = 1; | |
2923 | break; | |
2924 | default: | |
2925 | return -EINVAL; | |
2926 | } | |
2927 | ||
136ff2a2 | 2928 | switch (src) { |
7add84aa MB |
2929 | case 0: |
2930 | /* Allow no source specification when stopping */ | |
2931 | if (freq_out) | |
2932 | return -EINVAL; | |
2933 | break; | |
136ff2a2 MB |
2934 | case WM8994_FLL_SRC_MCLK1: |
2935 | case WM8994_FLL_SRC_MCLK2: | |
2936 | case WM8994_FLL_SRC_LRCLK: | |
2937 | case WM8994_FLL_SRC_BCLK: | |
2938 | break; | |
2939 | default: | |
2940 | return -EINVAL; | |
2941 | } | |
2942 | ||
9e6e96a1 MB |
2943 | /* Are we changing anything? */ |
2944 | if (wm8994->fll[id].src == src && | |
2945 | wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) | |
2946 | return 0; | |
2947 | ||
2948 | /* If we're stopping the FLL redo the old config - no | |
2949 | * registers will actually be written but we avoid GCC flow | |
2950 | * analysis bugs spewing warnings. | |
2951 | */ | |
2952 | if (freq_out) | |
2953 | ret = wm8994_get_fll_config(&fll, freq_in, freq_out); | |
2954 | else | |
2955 | ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, | |
2956 | wm8994->fll[id].out); | |
2957 | if (ret < 0) | |
2958 | return ret; | |
2959 | ||
2960 | /* Gate the AIF clocks while we reclock */ | |
2961 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, | |
2962 | WM8994_AIF1CLK_ENA, 0); | |
2963 | snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, | |
2964 | WM8994_AIF2CLK_ENA, 0); | |
2965 | ||
2966 | /* We always need to disable the FLL while reconfiguring */ | |
2967 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, | |
2968 | WM8994_FLL1_ENA, 0); | |
2969 | ||
2970 | reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | | |
2971 | (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); | |
2972 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, | |
2973 | WM8994_FLL1_OUTDIV_MASK | | |
2974 | WM8994_FLL1_FRATIO_MASK, reg); | |
2975 | ||
2976 | snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k); | |
2977 | ||
2978 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, | |
2979 | WM8994_FLL1_N_MASK, | |
2980 | fll.n << WM8994_FLL1_N_SHIFT); | |
2981 | ||
2982 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, | |
136ff2a2 MB |
2983 | WM8994_FLL1_REFCLK_DIV_MASK | |
2984 | WM8994_FLL1_REFCLK_SRC_MASK, | |
2985 | (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | | |
2986 | (src - 1)); | |
9e6e96a1 MB |
2987 | |
2988 | /* Enable (with fractional mode if required) */ | |
2989 | if (freq_out) { | |
2990 | if (fll.k) | |
2991 | reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC; | |
2992 | else | |
2993 | reg = WM8994_FLL1_ENA; | |
2994 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, | |
2995 | WM8994_FLL1_ENA | WM8994_FLL1_FRAC, | |
2996 | reg); | |
2997 | } | |
2998 | ||
2999 | wm8994->fll[id].in = freq_in; | |
3000 | wm8994->fll[id].out = freq_out; | |
136ff2a2 | 3001 | wm8994->fll[id].src = src; |
9e6e96a1 MB |
3002 | |
3003 | /* Enable any gated AIF clocks */ | |
3004 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, | |
3005 | WM8994_AIF1CLK_ENA, aif1); | |
3006 | snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, | |
3007 | WM8994_AIF2CLK_ENA, aif2); | |
3008 | ||
3009 | configure_clock(codec); | |
3010 | ||
3011 | return 0; | |
3012 | } | |
3013 | ||
f0fba2ad | 3014 | |
66b47fdb MB |
3015 | static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; |
3016 | ||
f0fba2ad LG |
3017 | static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, |
3018 | unsigned int freq_in, unsigned int freq_out) | |
3019 | { | |
3020 | return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); | |
3021 | } | |
3022 | ||
9e6e96a1 MB |
3023 | static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, |
3024 | int clk_id, unsigned int freq, int dir) | |
3025 | { | |
3026 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 3027 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
66b47fdb | 3028 | int i; |
9e6e96a1 MB |
3029 | |
3030 | switch (dai->id) { | |
3031 | case 1: | |
3032 | case 2: | |
3033 | break; | |
3034 | ||
3035 | default: | |
3036 | /* AIF3 shares clocking with AIF1/2 */ | |
3037 | return -EINVAL; | |
3038 | } | |
3039 | ||
3040 | switch (clk_id) { | |
3041 | case WM8994_SYSCLK_MCLK1: | |
3042 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; | |
3043 | wm8994->mclk[0] = freq; | |
3044 | dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", | |
3045 | dai->id, freq); | |
3046 | break; | |
3047 | ||
3048 | case WM8994_SYSCLK_MCLK2: | |
3049 | /* TODO: Set GPIO AF */ | |
3050 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; | |
3051 | wm8994->mclk[1] = freq; | |
3052 | dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", | |
3053 | dai->id, freq); | |
3054 | break; | |
3055 | ||
3056 | case WM8994_SYSCLK_FLL1: | |
3057 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; | |
3058 | dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); | |
3059 | break; | |
3060 | ||
3061 | case WM8994_SYSCLK_FLL2: | |
3062 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; | |
3063 | dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); | |
3064 | break; | |
3065 | ||
66b47fdb MB |
3066 | case WM8994_SYSCLK_OPCLK: |
3067 | /* Special case - a division (times 10) is given and | |
3068 | * no effect on main clocking. | |
3069 | */ | |
3070 | if (freq) { | |
3071 | for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) | |
3072 | if (opclk_divs[i] == freq) | |
3073 | break; | |
3074 | if (i == ARRAY_SIZE(opclk_divs)) | |
3075 | return -EINVAL; | |
3076 | snd_soc_update_bits(codec, WM8994_CLOCKING_2, | |
3077 | WM8994_OPCLK_DIV_MASK, i); | |
3078 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, | |
3079 | WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); | |
3080 | } else { | |
3081 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, | |
3082 | WM8994_OPCLK_ENA, 0); | |
3083 | } | |
3084 | ||
9e6e96a1 MB |
3085 | default: |
3086 | return -EINVAL; | |
3087 | } | |
3088 | ||
3089 | configure_clock(codec); | |
3090 | ||
3091 | return 0; | |
3092 | } | |
3093 | ||
3094 | static int wm8994_set_bias_level(struct snd_soc_codec *codec, | |
3095 | enum snd_soc_bias_level level) | |
3096 | { | |
b6b05691 MB |
3097 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
3098 | ||
9e6e96a1 MB |
3099 | switch (level) { |
3100 | case SND_SOC_BIAS_ON: | |
3101 | break; | |
3102 | ||
3103 | case SND_SOC_BIAS_PREPARE: | |
3104 | /* VMID=2x40k */ | |
3105 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
3106 | WM8994_VMID_SEL_MASK, 0x2); | |
3107 | break; | |
3108 | ||
3109 | case SND_SOC_BIAS_STANDBY: | |
3110 | if (codec->bias_level == SND_SOC_BIAS_OFF) { | |
0c17b393 MB |
3111 | /* Tweak DC servo and DSP configuration for |
3112 | * improved performance. */ | |
b6b05691 MB |
3113 | if (wm8994->revision < 4) { |
3114 | /* Tweak DC servo and DSP configuration for | |
3115 | * improved performance. */ | |
3116 | snd_soc_write(codec, 0x102, 0x3); | |
3117 | snd_soc_write(codec, 0x56, 0x3); | |
3118 | snd_soc_write(codec, 0x817, 0); | |
3119 | snd_soc_write(codec, 0x102, 0); | |
3120 | } | |
9e6e96a1 MB |
3121 | |
3122 | /* Discharge LINEOUT1 & 2 */ | |
3123 | snd_soc_update_bits(codec, WM8994_ANTIPOP_1, | |
3124 | WM8994_LINEOUT1_DISCH | | |
3125 | WM8994_LINEOUT2_DISCH, | |
3126 | WM8994_LINEOUT1_DISCH | | |
3127 | WM8994_LINEOUT2_DISCH); | |
3128 | ||
3129 | /* Startup bias, VMID ramp & buffer */ | |
3130 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
3131 | WM8994_STARTUP_BIAS_ENA | | |
3132 | WM8994_VMID_BUF_ENA | | |
3133 | WM8994_VMID_RAMP_MASK, | |
3134 | WM8994_STARTUP_BIAS_ENA | | |
3135 | WM8994_VMID_BUF_ENA | | |
3136 | (0x11 << WM8994_VMID_RAMP_SHIFT)); | |
3137 | ||
3138 | /* Main bias enable, VMID=2x40k */ | |
3139 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
3140 | WM8994_BIAS_ENA | | |
3141 | WM8994_VMID_SEL_MASK, | |
3142 | WM8994_BIAS_ENA | 0x2); | |
3143 | ||
3144 | msleep(20); | |
3145 | } | |
3146 | ||
3147 | /* VMID=2x500k */ | |
3148 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
3149 | WM8994_VMID_SEL_MASK, 0x4); | |
3150 | ||
3151 | break; | |
3152 | ||
3153 | case SND_SOC_BIAS_OFF: | |
d522ffbf MB |
3154 | if (codec->bias_level == SND_SOC_BIAS_STANDBY) { |
3155 | /* Switch over to startup biases */ | |
3156 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
3157 | WM8994_BIAS_SRC | | |
3158 | WM8994_STARTUP_BIAS_ENA | | |
3159 | WM8994_VMID_BUF_ENA | | |
3160 | WM8994_VMID_RAMP_MASK, | |
3161 | WM8994_BIAS_SRC | | |
3162 | WM8994_STARTUP_BIAS_ENA | | |
3163 | WM8994_VMID_BUF_ENA | | |
3164 | (1 << WM8994_VMID_RAMP_SHIFT)); | |
9e6e96a1 | 3165 | |
d522ffbf MB |
3166 | /* Disable main biases */ |
3167 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
3168 | WM8994_BIAS_ENA | | |
3169 | WM8994_VMID_SEL_MASK, 0); | |
9e6e96a1 | 3170 | |
d522ffbf MB |
3171 | /* Discharge line */ |
3172 | snd_soc_update_bits(codec, WM8994_ANTIPOP_1, | |
3173 | WM8994_LINEOUT1_DISCH | | |
3174 | WM8994_LINEOUT2_DISCH, | |
3175 | WM8994_LINEOUT1_DISCH | | |
3176 | WM8994_LINEOUT2_DISCH); | |
9e6e96a1 | 3177 | |
d522ffbf | 3178 | msleep(5); |
9e6e96a1 | 3179 | |
d522ffbf MB |
3180 | /* Switch off startup biases */ |
3181 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
3182 | WM8994_BIAS_SRC | | |
3183 | WM8994_STARTUP_BIAS_ENA | | |
3184 | WM8994_VMID_BUF_ENA | | |
3185 | WM8994_VMID_RAMP_MASK, 0); | |
3186 | } | |
9e6e96a1 MB |
3187 | break; |
3188 | } | |
3189 | codec->bias_level = level; | |
3190 | return 0; | |
3191 | } | |
3192 | ||
3193 | static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
3194 | { | |
3195 | struct snd_soc_codec *codec = dai->codec; | |
3196 | int ms_reg; | |
3197 | int aif1_reg; | |
3198 | int ms = 0; | |
3199 | int aif1 = 0; | |
3200 | ||
3201 | switch (dai->id) { | |
3202 | case 1: | |
3203 | ms_reg = WM8994_AIF1_MASTER_SLAVE; | |
3204 | aif1_reg = WM8994_AIF1_CONTROL_1; | |
3205 | break; | |
3206 | case 2: | |
3207 | ms_reg = WM8994_AIF2_MASTER_SLAVE; | |
3208 | aif1_reg = WM8994_AIF2_CONTROL_1; | |
3209 | break; | |
3210 | default: | |
3211 | return -EINVAL; | |
3212 | } | |
3213 | ||
3214 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
3215 | case SND_SOC_DAIFMT_CBS_CFS: | |
3216 | break; | |
3217 | case SND_SOC_DAIFMT_CBM_CFM: | |
3218 | ms = WM8994_AIF1_MSTR; | |
3219 | break; | |
3220 | default: | |
3221 | return -EINVAL; | |
3222 | } | |
3223 | ||
3224 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
3225 | case SND_SOC_DAIFMT_DSP_B: | |
3226 | aif1 |= WM8994_AIF1_LRCLK_INV; | |
3227 | case SND_SOC_DAIFMT_DSP_A: | |
3228 | aif1 |= 0x18; | |
3229 | break; | |
3230 | case SND_SOC_DAIFMT_I2S: | |
3231 | aif1 |= 0x10; | |
3232 | break; | |
3233 | case SND_SOC_DAIFMT_RIGHT_J: | |
3234 | break; | |
3235 | case SND_SOC_DAIFMT_LEFT_J: | |
3236 | aif1 |= 0x8; | |
3237 | break; | |
3238 | default: | |
3239 | return -EINVAL; | |
3240 | } | |
3241 | ||
3242 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
3243 | case SND_SOC_DAIFMT_DSP_A: | |
3244 | case SND_SOC_DAIFMT_DSP_B: | |
3245 | /* frame inversion not valid for DSP modes */ | |
3246 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
3247 | case SND_SOC_DAIFMT_NB_NF: | |
3248 | break; | |
3249 | case SND_SOC_DAIFMT_IB_NF: | |
3250 | aif1 |= WM8994_AIF1_BCLK_INV; | |
3251 | break; | |
3252 | default: | |
3253 | return -EINVAL; | |
3254 | } | |
3255 | break; | |
3256 | ||
3257 | case SND_SOC_DAIFMT_I2S: | |
3258 | case SND_SOC_DAIFMT_RIGHT_J: | |
3259 | case SND_SOC_DAIFMT_LEFT_J: | |
3260 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
3261 | case SND_SOC_DAIFMT_NB_NF: | |
3262 | break; | |
3263 | case SND_SOC_DAIFMT_IB_IF: | |
3264 | aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; | |
3265 | break; | |
3266 | case SND_SOC_DAIFMT_IB_NF: | |
3267 | aif1 |= WM8994_AIF1_BCLK_INV; | |
3268 | break; | |
3269 | case SND_SOC_DAIFMT_NB_IF: | |
3270 | aif1 |= WM8994_AIF1_LRCLK_INV; | |
3271 | break; | |
3272 | default: | |
3273 | return -EINVAL; | |
3274 | } | |
3275 | break; | |
3276 | default: | |
3277 | return -EINVAL; | |
3278 | } | |
3279 | ||
3280 | snd_soc_update_bits(codec, aif1_reg, | |
3281 | WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | | |
3282 | WM8994_AIF1_FMT_MASK, | |
3283 | aif1); | |
3284 | snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, | |
3285 | ms); | |
3286 | ||
3287 | return 0; | |
3288 | } | |
3289 | ||
3290 | static struct { | |
3291 | int val, rate; | |
3292 | } srs[] = { | |
3293 | { 0, 8000 }, | |
3294 | { 1, 11025 }, | |
3295 | { 2, 12000 }, | |
3296 | { 3, 16000 }, | |
3297 | { 4, 22050 }, | |
3298 | { 5, 24000 }, | |
3299 | { 6, 32000 }, | |
3300 | { 7, 44100 }, | |
3301 | { 8, 48000 }, | |
3302 | { 9, 88200 }, | |
3303 | { 10, 96000 }, | |
3304 | }; | |
3305 | ||
3306 | static int fs_ratios[] = { | |
3307 | 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 | |
3308 | }; | |
3309 | ||
3310 | static int bclk_divs[] = { | |
3311 | 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, | |
3312 | 640, 880, 960, 1280, 1760, 1920 | |
3313 | }; | |
3314 | ||
3315 | static int wm8994_hw_params(struct snd_pcm_substream *substream, | |
3316 | struct snd_pcm_hw_params *params, | |
3317 | struct snd_soc_dai *dai) | |
3318 | { | |
3319 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 3320 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
3321 | int aif1_reg; |
3322 | int bclk_reg; | |
3323 | int lrclk_reg; | |
3324 | int rate_reg; | |
3325 | int aif1 = 0; | |
3326 | int bclk = 0; | |
3327 | int lrclk = 0; | |
3328 | int rate_val = 0; | |
3329 | int id = dai->id - 1; | |
3330 | ||
3331 | int i, cur_val, best_val, bclk_rate, best; | |
3332 | ||
3333 | switch (dai->id) { | |
3334 | case 1: | |
3335 | aif1_reg = WM8994_AIF1_CONTROL_1; | |
3336 | bclk_reg = WM8994_AIF1_BCLK; | |
3337 | rate_reg = WM8994_AIF1_RATE; | |
3338 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
7d83d213 | 3339 | wm8994->lrclk_shared[0]) { |
9e6e96a1 | 3340 | lrclk_reg = WM8994_AIF1DAC_LRCLK; |
7d83d213 | 3341 | } else { |
9e6e96a1 | 3342 | lrclk_reg = WM8994_AIF1ADC_LRCLK; |
7d83d213 MB |
3343 | dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); |
3344 | } | |
9e6e96a1 MB |
3345 | break; |
3346 | case 2: | |
3347 | aif1_reg = WM8994_AIF2_CONTROL_1; | |
3348 | bclk_reg = WM8994_AIF2_BCLK; | |
3349 | rate_reg = WM8994_AIF2_RATE; | |
3350 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
7d83d213 | 3351 | wm8994->lrclk_shared[1]) { |
9e6e96a1 | 3352 | lrclk_reg = WM8994_AIF2DAC_LRCLK; |
7d83d213 | 3353 | } else { |
9e6e96a1 | 3354 | lrclk_reg = WM8994_AIF2ADC_LRCLK; |
7d83d213 MB |
3355 | dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); |
3356 | } | |
9e6e96a1 MB |
3357 | break; |
3358 | default: | |
3359 | return -EINVAL; | |
3360 | } | |
3361 | ||
3362 | bclk_rate = params_rate(params) * 2; | |
3363 | switch (params_format(params)) { | |
3364 | case SNDRV_PCM_FORMAT_S16_LE: | |
3365 | bclk_rate *= 16; | |
3366 | break; | |
3367 | case SNDRV_PCM_FORMAT_S20_3LE: | |
3368 | bclk_rate *= 20; | |
3369 | aif1 |= 0x20; | |
3370 | break; | |
3371 | case SNDRV_PCM_FORMAT_S24_LE: | |
3372 | bclk_rate *= 24; | |
3373 | aif1 |= 0x40; | |
3374 | break; | |
3375 | case SNDRV_PCM_FORMAT_S32_LE: | |
3376 | bclk_rate *= 32; | |
3377 | aif1 |= 0x60; | |
3378 | break; | |
3379 | default: | |
3380 | return -EINVAL; | |
3381 | } | |
3382 | ||
3383 | /* Try to find an appropriate sample rate; look for an exact match. */ | |
3384 | for (i = 0; i < ARRAY_SIZE(srs); i++) | |
3385 | if (srs[i].rate == params_rate(params)) | |
3386 | break; | |
3387 | if (i == ARRAY_SIZE(srs)) | |
3388 | return -EINVAL; | |
3389 | rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; | |
3390 | ||
3391 | dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); | |
3392 | dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", | |
3393 | dai->id, wm8994->aifclk[id], bclk_rate); | |
3394 | ||
3395 | if (wm8994->aifclk[id] == 0) { | |
3396 | dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); | |
3397 | return -EINVAL; | |
3398 | } | |
3399 | ||
3400 | /* AIFCLK/fs ratio; look for a close match in either direction */ | |
3401 | best = 0; | |
3402 | best_val = abs((fs_ratios[0] * params_rate(params)) | |
3403 | - wm8994->aifclk[id]); | |
3404 | for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { | |
3405 | cur_val = abs((fs_ratios[i] * params_rate(params)) | |
3406 | - wm8994->aifclk[id]); | |
3407 | if (cur_val >= best_val) | |
3408 | continue; | |
3409 | best = i; | |
3410 | best_val = cur_val; | |
3411 | } | |
3412 | dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", | |
3413 | dai->id, fs_ratios[best]); | |
3414 | rate_val |= best; | |
3415 | ||
3416 | /* We may not get quite the right frequency if using | |
3417 | * approximate clocks so look for the closest match that is | |
3418 | * higher than the target (we need to ensure that there enough | |
3419 | * BCLKs to clock out the samples). | |
3420 | */ | |
3421 | best = 0; | |
3422 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
07cd8ada | 3423 | cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; |
9e6e96a1 MB |
3424 | if (cur_val < 0) /* BCLK table is sorted */ |
3425 | break; | |
3426 | best = i; | |
3427 | } | |
07cd8ada | 3428 | bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; |
9e6e96a1 MB |
3429 | dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", |
3430 | bclk_divs[best], bclk_rate); | |
3431 | bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; | |
3432 | ||
3433 | lrclk = bclk_rate / params_rate(params); | |
3434 | dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", | |
3435 | lrclk, bclk_rate / lrclk); | |
3436 | ||
3437 | snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); | |
3438 | snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); | |
3439 | snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, | |
3440 | lrclk); | |
3441 | snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | | |
3442 | WM8994_AIF1CLK_RATE_MASK, rate_val); | |
3443 | ||
3444 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
3445 | switch (dai->id) { | |
3446 | case 1: | |
3447 | wm8994->dac_rates[0] = params_rate(params); | |
3448 | wm8994_set_retune_mobile(codec, 0); | |
3449 | wm8994_set_retune_mobile(codec, 1); | |
3450 | break; | |
3451 | case 2: | |
3452 | wm8994->dac_rates[1] = params_rate(params); | |
3453 | wm8994_set_retune_mobile(codec, 2); | |
3454 | break; | |
3455 | } | |
3456 | } | |
3457 | ||
3458 | return 0; | |
3459 | } | |
3460 | ||
3461 | static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) | |
3462 | { | |
3463 | struct snd_soc_codec *codec = codec_dai->codec; | |
3464 | int mute_reg; | |
3465 | int reg; | |
3466 | ||
3467 | switch (codec_dai->id) { | |
3468 | case 1: | |
3469 | mute_reg = WM8994_AIF1_DAC1_FILTERS_1; | |
3470 | break; | |
3471 | case 2: | |
3472 | mute_reg = WM8994_AIF2_DAC_FILTERS_1; | |
3473 | break; | |
3474 | default: | |
3475 | return -EINVAL; | |
3476 | } | |
3477 | ||
3478 | if (mute) | |
3479 | reg = WM8994_AIF1DAC1_MUTE; | |
3480 | else | |
3481 | reg = 0; | |
3482 | ||
3483 | snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); | |
3484 | ||
3485 | return 0; | |
3486 | } | |
3487 | ||
778a76e2 MB |
3488 | static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) |
3489 | { | |
3490 | struct snd_soc_codec *codec = codec_dai->codec; | |
3491 | int reg, val, mask; | |
3492 | ||
3493 | switch (codec_dai->id) { | |
3494 | case 1: | |
3495 | reg = WM8994_AIF1_MASTER_SLAVE; | |
3496 | mask = WM8994_AIF1_TRI; | |
3497 | break; | |
3498 | case 2: | |
3499 | reg = WM8994_AIF2_MASTER_SLAVE; | |
3500 | mask = WM8994_AIF2_TRI; | |
3501 | break; | |
3502 | case 3: | |
3503 | reg = WM8994_POWER_MANAGEMENT_6; | |
3504 | mask = WM8994_AIF3_TRI; | |
3505 | break; | |
3506 | default: | |
3507 | return -EINVAL; | |
3508 | } | |
3509 | ||
3510 | if (tristate) | |
3511 | val = mask; | |
3512 | else | |
3513 | val = 0; | |
3514 | ||
3515 | return snd_soc_update_bits(codec, reg, mask, reg); | |
3516 | } | |
3517 | ||
9e6e96a1 MB |
3518 | #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 |
3519 | ||
3520 | #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
3079aed5 | 3521 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
9e6e96a1 MB |
3522 | |
3523 | static struct snd_soc_dai_ops wm8994_aif1_dai_ops = { | |
3524 | .set_sysclk = wm8994_set_dai_sysclk, | |
3525 | .set_fmt = wm8994_set_dai_fmt, | |
3526 | .hw_params = wm8994_hw_params, | |
3527 | .digital_mute = wm8994_aif_mute, | |
3528 | .set_pll = wm8994_set_fll, | |
778a76e2 | 3529 | .set_tristate = wm8994_set_tristate, |
9e6e96a1 MB |
3530 | }; |
3531 | ||
3532 | static struct snd_soc_dai_ops wm8994_aif2_dai_ops = { | |
3533 | .set_sysclk = wm8994_set_dai_sysclk, | |
3534 | .set_fmt = wm8994_set_dai_fmt, | |
3535 | .hw_params = wm8994_hw_params, | |
3536 | .digital_mute = wm8994_aif_mute, | |
3537 | .set_pll = wm8994_set_fll, | |
778a76e2 MB |
3538 | .set_tristate = wm8994_set_tristate, |
3539 | }; | |
3540 | ||
3541 | static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { | |
3542 | .set_tristate = wm8994_set_tristate, | |
9e6e96a1 MB |
3543 | }; |
3544 | ||
f0fba2ad | 3545 | static struct snd_soc_dai_driver wm8994_dai[] = { |
9e6e96a1 | 3546 | { |
f0fba2ad | 3547 | .name = "wm8994-aif1", |
8c7f78b3 | 3548 | .id = 1, |
9e6e96a1 MB |
3549 | .playback = { |
3550 | .stream_name = "AIF1 Playback", | |
3551 | .channels_min = 2, | |
3552 | .channels_max = 2, | |
3553 | .rates = WM8994_RATES, | |
3554 | .formats = WM8994_FORMATS, | |
3555 | }, | |
3556 | .capture = { | |
3557 | .stream_name = "AIF1 Capture", | |
3558 | .channels_min = 2, | |
3559 | .channels_max = 2, | |
3560 | .rates = WM8994_RATES, | |
3561 | .formats = WM8994_FORMATS, | |
3562 | }, | |
3563 | .ops = &wm8994_aif1_dai_ops, | |
3564 | }, | |
3565 | { | |
f0fba2ad | 3566 | .name = "wm8994-aif2", |
8c7f78b3 | 3567 | .id = 2, |
9e6e96a1 MB |
3568 | .playback = { |
3569 | .stream_name = "AIF2 Playback", | |
3570 | .channels_min = 2, | |
3571 | .channels_max = 2, | |
3572 | .rates = WM8994_RATES, | |
3573 | .formats = WM8994_FORMATS, | |
3574 | }, | |
3575 | .capture = { | |
3576 | .stream_name = "AIF2 Capture", | |
3577 | .channels_min = 2, | |
3578 | .channels_max = 2, | |
3579 | .rates = WM8994_RATES, | |
3580 | .formats = WM8994_FORMATS, | |
3581 | }, | |
3582 | .ops = &wm8994_aif2_dai_ops, | |
3583 | }, | |
3584 | { | |
f0fba2ad | 3585 | .name = "wm8994-aif3", |
8c7f78b3 | 3586 | .id = 3, |
9e6e96a1 MB |
3587 | .playback = { |
3588 | .stream_name = "AIF3 Playback", | |
3589 | .channels_min = 2, | |
3590 | .channels_max = 2, | |
3591 | .rates = WM8994_RATES, | |
3592 | .formats = WM8994_FORMATS, | |
3593 | }, | |
a8462bde | 3594 | .capture = { |
9e6e96a1 MB |
3595 | .stream_name = "AIF3 Capture", |
3596 | .channels_min = 2, | |
3597 | .channels_max = 2, | |
3598 | .rates = WM8994_RATES, | |
3599 | .formats = WM8994_FORMATS, | |
3600 | }, | |
778a76e2 | 3601 | .ops = &wm8994_aif3_dai_ops, |
9e6e96a1 MB |
3602 | } |
3603 | }; | |
9e6e96a1 MB |
3604 | |
3605 | #ifdef CONFIG_PM | |
f0fba2ad | 3606 | static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state) |
9e6e96a1 | 3607 | { |
b2c812e2 | 3608 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
3609 | int i, ret; |
3610 | ||
3611 | for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { | |
3612 | memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], | |
3613 | sizeof(struct fll_config)); | |
f0fba2ad | 3614 | ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); |
9e6e96a1 MB |
3615 | if (ret < 0) |
3616 | dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", | |
3617 | i + 1, ret); | |
3618 | } | |
3619 | ||
3620 | wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
3621 | ||
3622 | return 0; | |
3623 | } | |
3624 | ||
f0fba2ad | 3625 | static int wm8994_resume(struct snd_soc_codec *codec) |
9e6e96a1 | 3626 | { |
b2c812e2 | 3627 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
3628 | u16 *reg_cache = codec->reg_cache; |
3629 | int i, ret; | |
3630 | ||
3631 | /* Restore the registers */ | |
3632 | for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) { | |
3633 | switch (i) { | |
3634 | case WM8994_LDO_1: | |
3635 | case WM8994_LDO_2: | |
3636 | case WM8994_SOFTWARE_RESET: | |
3637 | /* Handled by other MFD drivers */ | |
3638 | continue; | |
3639 | default: | |
3640 | break; | |
3641 | } | |
3642 | ||
3643 | if (!access_masks[i].writable) | |
3644 | continue; | |
3645 | ||
3646 | wm8994_reg_write(codec->control_data, i, reg_cache[i]); | |
3647 | } | |
3648 | ||
3649 | wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
3650 | ||
3651 | for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { | |
6a2f1ee1 MB |
3652 | if (!wm8994->fll_suspend[i].out) |
3653 | continue; | |
3654 | ||
f0fba2ad | 3655 | ret = _wm8994_set_fll(codec, i + 1, |
9e6e96a1 MB |
3656 | wm8994->fll_suspend[i].src, |
3657 | wm8994->fll_suspend[i].in, | |
3658 | wm8994->fll_suspend[i].out); | |
3659 | if (ret < 0) | |
3660 | dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", | |
3661 | i + 1, ret); | |
3662 | } | |
3663 | ||
3664 | return 0; | |
3665 | } | |
3666 | #else | |
3667 | #define wm8994_suspend NULL | |
3668 | #define wm8994_resume NULL | |
3669 | #endif | |
3670 | ||
3671 | static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) | |
3672 | { | |
f0fba2ad | 3673 | struct snd_soc_codec *codec = wm8994->codec; |
9e6e96a1 MB |
3674 | struct wm8994_pdata *pdata = wm8994->pdata; |
3675 | struct snd_kcontrol_new controls[] = { | |
3676 | SOC_ENUM_EXT("AIF1.1 EQ Mode", | |
3677 | wm8994->retune_mobile_enum, | |
3678 | wm8994_get_retune_mobile_enum, | |
3679 | wm8994_put_retune_mobile_enum), | |
3680 | SOC_ENUM_EXT("AIF1.2 EQ Mode", | |
3681 | wm8994->retune_mobile_enum, | |
3682 | wm8994_get_retune_mobile_enum, | |
3683 | wm8994_put_retune_mobile_enum), | |
3684 | SOC_ENUM_EXT("AIF2 EQ Mode", | |
3685 | wm8994->retune_mobile_enum, | |
3686 | wm8994_get_retune_mobile_enum, | |
3687 | wm8994_put_retune_mobile_enum), | |
3688 | }; | |
3689 | int ret, i, j; | |
3690 | const char **t; | |
3691 | ||
3692 | /* We need an array of texts for the enum API but the number | |
3693 | * of texts is likely to be less than the number of | |
3694 | * configurations due to the sample rate dependency of the | |
3695 | * configurations. */ | |
3696 | wm8994->num_retune_mobile_texts = 0; | |
3697 | wm8994->retune_mobile_texts = NULL; | |
3698 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
3699 | for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { | |
3700 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
3701 | wm8994->retune_mobile_texts[j]) == 0) | |
3702 | break; | |
3703 | } | |
3704 | ||
3705 | if (j != wm8994->num_retune_mobile_texts) | |
3706 | continue; | |
3707 | ||
3708 | /* Expand the array... */ | |
3709 | t = krealloc(wm8994->retune_mobile_texts, | |
3710 | sizeof(char *) * | |
3711 | (wm8994->num_retune_mobile_texts + 1), | |
3712 | GFP_KERNEL); | |
3713 | if (t == NULL) | |
3714 | continue; | |
3715 | ||
3716 | /* ...store the new entry... */ | |
3717 | t[wm8994->num_retune_mobile_texts] = | |
3718 | pdata->retune_mobile_cfgs[i].name; | |
3719 | ||
3720 | /* ...and remember the new version. */ | |
3721 | wm8994->num_retune_mobile_texts++; | |
3722 | wm8994->retune_mobile_texts = t; | |
3723 | } | |
3724 | ||
3725 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
3726 | wm8994->num_retune_mobile_texts); | |
3727 | ||
3728 | wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; | |
3729 | wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; | |
3730 | ||
f0fba2ad | 3731 | ret = snd_soc_add_controls(wm8994->codec, controls, |
9e6e96a1 MB |
3732 | ARRAY_SIZE(controls)); |
3733 | if (ret != 0) | |
f0fba2ad | 3734 | dev_err(wm8994->codec->dev, |
9e6e96a1 MB |
3735 | "Failed to add ReTune Mobile controls: %d\n", ret); |
3736 | } | |
3737 | ||
3738 | static void wm8994_handle_pdata(struct wm8994_priv *wm8994) | |
3739 | { | |
f0fba2ad | 3740 | struct snd_soc_codec *codec = wm8994->codec; |
9e6e96a1 MB |
3741 | struct wm8994_pdata *pdata = wm8994->pdata; |
3742 | int ret, i; | |
3743 | ||
3744 | if (!pdata) | |
3745 | return; | |
3746 | ||
3747 | wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, | |
3748 | pdata->lineout2_diff, | |
3749 | pdata->lineout1fb, | |
3750 | pdata->lineout2fb, | |
3751 | pdata->jd_scthr, | |
3752 | pdata->jd_thr, | |
3753 | pdata->micbias1_lvl, | |
3754 | pdata->micbias2_lvl); | |
3755 | ||
3756 | dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); | |
3757 | ||
3758 | if (pdata->num_drc_cfgs) { | |
3759 | struct snd_kcontrol_new controls[] = { | |
3760 | SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, | |
3761 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
3762 | SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, | |
3763 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
3764 | SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, | |
3765 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
3766 | }; | |
3767 | ||
3768 | /* We need an array of texts for the enum API */ | |
3769 | wm8994->drc_texts = kmalloc(sizeof(char *) | |
3770 | * pdata->num_drc_cfgs, GFP_KERNEL); | |
3771 | if (!wm8994->drc_texts) { | |
f0fba2ad | 3772 | dev_err(wm8994->codec->dev, |
9e6e96a1 MB |
3773 | "Failed to allocate %d DRC config texts\n", |
3774 | pdata->num_drc_cfgs); | |
3775 | return; | |
3776 | } | |
3777 | ||
3778 | for (i = 0; i < pdata->num_drc_cfgs; i++) | |
3779 | wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; | |
3780 | ||
3781 | wm8994->drc_enum.max = pdata->num_drc_cfgs; | |
3782 | wm8994->drc_enum.texts = wm8994->drc_texts; | |
3783 | ||
f0fba2ad | 3784 | ret = snd_soc_add_controls(wm8994->codec, controls, |
9e6e96a1 MB |
3785 | ARRAY_SIZE(controls)); |
3786 | if (ret != 0) | |
f0fba2ad | 3787 | dev_err(wm8994->codec->dev, |
9e6e96a1 MB |
3788 | "Failed to add DRC mode controls: %d\n", ret); |
3789 | ||
3790 | for (i = 0; i < WM8994_NUM_DRC; i++) | |
3791 | wm8994_set_drc(codec, i); | |
3792 | } | |
3793 | ||
3794 | dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", | |
3795 | pdata->num_retune_mobile_cfgs); | |
3796 | ||
3797 | if (pdata->num_retune_mobile_cfgs) | |
3798 | wm8994_handle_retune_mobile_pdata(wm8994); | |
3799 | else | |
f0fba2ad | 3800 | snd_soc_add_controls(wm8994->codec, wm8994_eq_controls, |
9e6e96a1 MB |
3801 | ARRAY_SIZE(wm8994_eq_controls)); |
3802 | } | |
3803 | ||
88766984 MB |
3804 | /** |
3805 | * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ | |
3806 | * | |
3807 | * @codec: WM8994 codec | |
3808 | * @jack: jack to report detection events on | |
3809 | * @micbias: microphone bias to detect on | |
3810 | * @det: value to report for presence detection | |
3811 | * @shrt: value to report for short detection | |
3812 | * | |
3813 | * Enable microphone detection via IRQ on the WM8994. If GPIOs are | |
3814 | * being used to bring out signals to the processor then only platform | |
5ab230a7 | 3815 | * data configuration is needed for WM8994 and processor GPIOs should |
88766984 MB |
3816 | * be configured using snd_soc_jack_add_gpios() instead. |
3817 | * | |
3818 | * Configuration of detection levels is available via the micbias1_lvl | |
3819 | * and micbias2_lvl platform data members. | |
3820 | */ | |
3821 | int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
3822 | int micbias, int det, int shrt) | |
3823 | { | |
b2c812e2 | 3824 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
88766984 MB |
3825 | struct wm8994_micdet *micdet; |
3826 | int reg; | |
3827 | ||
3828 | switch (micbias) { | |
3829 | case 1: | |
3830 | micdet = &wm8994->micdet[0]; | |
3831 | break; | |
3832 | case 2: | |
3833 | micdet = &wm8994->micdet[1]; | |
3834 | break; | |
3835 | default: | |
3836 | return -EINVAL; | |
3837 | } | |
3838 | ||
3839 | dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n", | |
3840 | micbias, det, shrt); | |
3841 | ||
3842 | /* Store the configuration */ | |
3843 | micdet->jack = jack; | |
3844 | micdet->det = det; | |
3845 | micdet->shrt = shrt; | |
3846 | ||
3847 | /* If either of the jacks is set up then enable detection */ | |
3848 | if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) | |
3849 | reg = WM8994_MICD_ENA; | |
3850 | else | |
3851 | reg = 0; | |
3852 | ||
3853 | snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); | |
3854 | ||
3855 | return 0; | |
3856 | } | |
3857 | EXPORT_SYMBOL_GPL(wm8994_mic_detect); | |
3858 | ||
3859 | static irqreturn_t wm8994_mic_irq(int irq, void *data) | |
3860 | { | |
3861 | struct wm8994_priv *priv = data; | |
f0fba2ad | 3862 | struct snd_soc_codec *codec = priv->codec; |
88766984 MB |
3863 | int reg; |
3864 | int report; | |
3865 | ||
3866 | reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); | |
3867 | if (reg < 0) { | |
3868 | dev_err(codec->dev, "Failed to read microphone status: %d\n", | |
3869 | reg); | |
3870 | return IRQ_HANDLED; | |
3871 | } | |
3872 | ||
3873 | dev_dbg(codec->dev, "Microphone status: %x\n", reg); | |
3874 | ||
3875 | report = 0; | |
3876 | if (reg & WM8994_MIC1_DET_STS) | |
3877 | report |= priv->micdet[0].det; | |
3878 | if (reg & WM8994_MIC1_SHRT_STS) | |
3879 | report |= priv->micdet[0].shrt; | |
3880 | snd_soc_jack_report(priv->micdet[0].jack, report, | |
3881 | priv->micdet[0].det | priv->micdet[0].shrt); | |
3882 | ||
3883 | report = 0; | |
3884 | if (reg & WM8994_MIC2_DET_STS) | |
3885 | report |= priv->micdet[1].det; | |
3886 | if (reg & WM8994_MIC2_SHRT_STS) | |
3887 | report |= priv->micdet[1].shrt; | |
3888 | snd_soc_jack_report(priv->micdet[1].jack, report, | |
3889 | priv->micdet[1].det | priv->micdet[1].shrt); | |
3890 | ||
3891 | return IRQ_HANDLED; | |
3892 | } | |
3893 | ||
f0fba2ad | 3894 | static int wm8994_codec_probe(struct snd_soc_codec *codec) |
9e6e96a1 | 3895 | { |
9e6e96a1 | 3896 | struct wm8994_priv *wm8994; |
ec62dbd7 | 3897 | int ret, i; |
9e6e96a1 | 3898 | |
f0fba2ad | 3899 | codec->control_data = dev_get_drvdata(codec->dev->parent); |
9e6e96a1 MB |
3900 | |
3901 | wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); | |
f0fba2ad | 3902 | if (wm8994 == NULL) |
9e6e96a1 | 3903 | return -ENOMEM; |
b2c812e2 | 3904 | snd_soc_codec_set_drvdata(codec, wm8994); |
f0fba2ad LG |
3905 | |
3906 | wm8994->pdata = dev_get_platdata(codec->dev->parent); | |
3907 | wm8994->codec = codec; | |
9e6e96a1 MB |
3908 | |
3909 | /* Fill the cache with physical values we inherited; don't reset */ | |
3910 | ret = wm8994_bulk_read(codec->control_data, 0, | |
3911 | ARRAY_SIZE(wm8994->reg_cache) - 1, | |
3912 | codec->reg_cache); | |
3913 | if (ret < 0) { | |
3914 | dev_err(codec->dev, "Failed to fill register cache: %d\n", | |
3915 | ret); | |
3916 | goto err; | |
3917 | } | |
3918 | ||
3919 | /* Clear the cached values for unreadable/volatile registers to | |
3920 | * avoid potential confusion. | |
3921 | */ | |
3922 | for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++) | |
3923 | if (wm8994_volatile(i) || !wm8994_readable(i)) | |
3924 | wm8994->reg_cache[i] = 0; | |
3925 | ||
3926 | /* Set revision-specific configuration */ | |
b6b05691 MB |
3927 | wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); |
3928 | switch (wm8994->revision) { | |
9e6e96a1 MB |
3929 | case 2: |
3930 | case 3: | |
3931 | wm8994->hubs.dcs_codes = -5; | |
3932 | wm8994->hubs.hp_startup_mode = 1; | |
8437f700 | 3933 | wm8994->hubs.dcs_readback_mode = 1; |
9e6e96a1 MB |
3934 | break; |
3935 | default: | |
8437f700 | 3936 | wm8994->hubs.dcs_readback_mode = 1; |
9e6e96a1 MB |
3937 | break; |
3938 | } | |
9e6e96a1 | 3939 | |
88766984 MB |
3940 | ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET, |
3941 | wm8994_mic_irq, "Mic 1 detect", wm8994); | |
3942 | if (ret != 0) | |
f0fba2ad | 3943 | dev_warn(codec->dev, |
88766984 MB |
3944 | "Failed to request Mic1 detect IRQ: %d\n", ret); |
3945 | ||
3946 | ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, | |
3947 | wm8994_mic_irq, "Mic 1 short", wm8994); | |
3948 | if (ret != 0) | |
f0fba2ad | 3949 | dev_warn(codec->dev, |
88766984 MB |
3950 | "Failed to request Mic1 short IRQ: %d\n", ret); |
3951 | ||
3952 | ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET, | |
3953 | wm8994_mic_irq, "Mic 2 detect", wm8994); | |
3954 | if (ret != 0) | |
f0fba2ad | 3955 | dev_warn(codec->dev, |
88766984 MB |
3956 | "Failed to request Mic2 detect IRQ: %d\n", ret); |
3957 | ||
3958 | ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, | |
3959 | wm8994_mic_irq, "Mic 2 short", wm8994); | |
3960 | if (ret != 0) | |
f0fba2ad | 3961 | dev_warn(codec->dev, |
88766984 MB |
3962 | "Failed to request Mic2 short IRQ: %d\n", ret); |
3963 | ||
9e6e96a1 MB |
3964 | /* Remember if AIFnLRCLK is configured as a GPIO. This should be |
3965 | * configured on init - if a system wants to do this dynamically | |
3966 | * at runtime we can deal with that then. | |
3967 | */ | |
3968 | ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1); | |
3969 | if (ret < 0) { | |
3970 | dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); | |
88766984 | 3971 | goto err_irq; |
9e6e96a1 MB |
3972 | } |
3973 | if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { | |
3974 | wm8994->lrclk_shared[0] = 1; | |
3975 | wm8994_dai[0].symmetric_rates = 1; | |
3976 | } else { | |
3977 | wm8994->lrclk_shared[0] = 0; | |
3978 | } | |
3979 | ||
3980 | ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6); | |
3981 | if (ret < 0) { | |
3982 | dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); | |
88766984 | 3983 | goto err_irq; |
9e6e96a1 MB |
3984 | } |
3985 | if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { | |
3986 | wm8994->lrclk_shared[1] = 1; | |
3987 | wm8994_dai[1].symmetric_rates = 1; | |
3988 | } else { | |
3989 | wm8994->lrclk_shared[1] = 0; | |
3990 | } | |
3991 | ||
9e6e96a1 MB |
3992 | wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
3993 | ||
9e6e96a1 MB |
3994 | /* Latch volume updates (right only; we always do left then right). */ |
3995 | snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME, | |
3996 | WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); | |
3997 | snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME, | |
3998 | WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); | |
3999 | snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME, | |
4000 | WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); | |
4001 | snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME, | |
4002 | WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); | |
4003 | snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME, | |
4004 | WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); | |
4005 | snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME, | |
4006 | WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); | |
4007 | snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME, | |
4008 | WM8994_DAC1_VU, WM8994_DAC1_VU); | |
4009 | snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME, | |
4010 | WM8994_DAC2_VU, WM8994_DAC2_VU); | |
4011 | ||
4012 | /* Set the low bit of the 3D stereo depth so TLV matches */ | |
4013 | snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, | |
4014 | 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, | |
4015 | 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); | |
4016 | snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, | |
4017 | 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, | |
4018 | 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); | |
4019 | snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, | |
4020 | 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, | |
4021 | 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); | |
4022 | ||
d1ce6b20 MB |
4023 | /* Unconditionally enable AIF1 ADC TDM mode; it only affects |
4024 | * behaviour on idle TDM clock cycles. */ | |
4025 | snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, | |
4026 | WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); | |
4027 | ||
9e6e96a1 MB |
4028 | wm8994_update_class_w(codec); |
4029 | ||
f0fba2ad | 4030 | wm8994_handle_pdata(wm8994); |
9e6e96a1 | 4031 | |
f0fba2ad LG |
4032 | wm_hubs_add_analogue_controls(codec); |
4033 | snd_soc_add_controls(codec, wm8994_snd_controls, | |
4034 | ARRAY_SIZE(wm8994_snd_controls)); | |
4035 | snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets, | |
4036 | ARRAY_SIZE(wm8994_dapm_widgets)); | |
4037 | wm_hubs_add_analogue_routes(codec, 0, 0); | |
4038 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
9e6e96a1 MB |
4039 | |
4040 | return 0; | |
4041 | ||
88766984 MB |
4042 | err_irq: |
4043 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); | |
4044 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); | |
4045 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); | |
4046 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); | |
9e6e96a1 MB |
4047 | err: |
4048 | kfree(wm8994); | |
4049 | return ret; | |
4050 | } | |
4051 | ||
f0fba2ad | 4052 | static int wm8994_codec_remove(struct snd_soc_codec *codec) |
9e6e96a1 | 4053 | { |
f0fba2ad | 4054 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
4055 | |
4056 | wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
f0fba2ad | 4057 | |
88766984 MB |
4058 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); |
4059 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); | |
4060 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); | |
4061 | wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); | |
9e6e96a1 | 4062 | kfree(wm8994); |
9e6e96a1 MB |
4063 | |
4064 | return 0; | |
4065 | } | |
4066 | ||
f0fba2ad LG |
4067 | static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { |
4068 | .probe = wm8994_codec_probe, | |
4069 | .remove = wm8994_codec_remove, | |
4070 | .suspend = wm8994_suspend, | |
4071 | .resume = wm8994_resume, | |
4072 | .read = wm8994_read, | |
4073 | .write = wm8994_write, | |
4074 | .set_bias_level = wm8994_set_bias_level, | |
4075 | }; | |
4076 | ||
4077 | static int __devinit wm8994_probe(struct platform_device *pdev) | |
4078 | { | |
4079 | return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, | |
4080 | wm8994_dai, ARRAY_SIZE(wm8994_dai)); | |
4081 | } | |
4082 | ||
4083 | static int __devexit wm8994_remove(struct platform_device *pdev) | |
4084 | { | |
4085 | snd_soc_unregister_codec(&pdev->dev); | |
4086 | return 0; | |
4087 | } | |
4088 | ||
9e6e96a1 MB |
4089 | static struct platform_driver wm8994_codec_driver = { |
4090 | .driver = { | |
4091 | .name = "wm8994-codec", | |
4092 | .owner = THIS_MODULE, | |
4093 | }, | |
f0fba2ad LG |
4094 | .probe = wm8994_probe, |
4095 | .remove = __devexit_p(wm8994_remove), | |
9e6e96a1 MB |
4096 | }; |
4097 | ||
4098 | static __init int wm8994_init(void) | |
4099 | { | |
4100 | return platform_driver_register(&wm8994_codec_driver); | |
4101 | } | |
4102 | module_init(wm8994_init); | |
4103 | ||
4104 | static __exit void wm8994_exit(void) | |
4105 | { | |
4106 | platform_driver_unregister(&wm8994_codec_driver); | |
4107 | } | |
4108 | module_exit(wm8994_exit); | |
4109 | ||
4110 | ||
4111 | MODULE_DESCRIPTION("ASoC WM8994 driver"); | |
4112 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
4113 | MODULE_LICENSE("GPL"); | |
4114 | MODULE_ALIAS("platform:wm8994-codec"); |