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6a504a75 DP |
1 | /* |
2 | * wm8995.c -- WM8995 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2010 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * Based on wm8994.c and wm_hubs.c by Mark Brown | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/moduleparam.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/pm.h> | |
20 | #include <linux/i2c.h> | |
21 | #include <linux/spi/spi.h> | |
219d8df8 | 22 | #include <linux/regulator/consumer.h> |
6a504a75 DP |
23 | #include <linux/slab.h> |
24 | #include <sound/core.h> | |
25 | #include <sound/pcm.h> | |
26 | #include <sound/pcm_params.h> | |
27 | #include <sound/soc.h> | |
28 | #include <sound/soc-dapm.h> | |
29 | #include <sound/initval.h> | |
30 | #include <sound/tlv.h> | |
31 | ||
32 | #include "wm8995.h" | |
33 | ||
219d8df8 DP |
34 | #define WM8995_NUM_SUPPLIES 8 |
35 | static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = { | |
36 | "DCVDD", | |
37 | "DBVDD1", | |
38 | "DBVDD2", | |
39 | "DBVDD3", | |
40 | "AVDD1", | |
41 | "AVDD2", | |
42 | "CPVDD", | |
43 | "MICVDD" | |
44 | }; | |
45 | ||
03cfbdf9 | 46 | static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] = { |
6a504a75 DP |
47 | [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b, |
48 | [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0, | |
49 | [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003, | |
50 | [41] = 0x0013, [48] = 0x0004, [56] = 0x09f8, [64] = 0x1f25, | |
51 | [69] = 0x0004, [82] = 0xaaaa, [84] = 0x2a2a, [146] = 0x0060, | |
52 | [256] = 0x0002, [257] = 0x8004, [520] = 0x0010, [528] = 0x0083, | |
53 | [529] = 0x0083, [548] = 0x0c80, [580] = 0x0c80, [768] = 0x4050, | |
54 | [769] = 0x4000, [771] = 0x0040, [772] = 0x0040, [773] = 0x0040, | |
55 | [774] = 0x0004, [775] = 0x0100, [784] = 0x4050, [785] = 0x4000, | |
56 | [787] = 0x0040, [788] = 0x0040, [789] = 0x0040, [1024] = 0x00c0, | |
57 | [1025] = 0x00c0, [1026] = 0x00c0, [1027] = 0x00c0, [1028] = 0x00c0, | |
58 | [1029] = 0x00c0, [1030] = 0x00c0, [1031] = 0x00c0, [1056] = 0x0200, | |
59 | [1057] = 0x0010, [1058] = 0x0200, [1059] = 0x0010, [1088] = 0x0098, | |
60 | [1089] = 0x0845, [1104] = 0x0098, [1105] = 0x0845, [1152] = 0x6318, | |
61 | [1153] = 0x6300, [1154] = 0x0fca, [1155] = 0x0400, [1156] = 0x00d8, | |
62 | [1157] = 0x1eb5, [1158] = 0xf145, [1159] = 0x0b75, [1160] = 0x01c5, | |
63 | [1161] = 0x1c58, [1162] = 0xf373, [1163] = 0x0a54, [1164] = 0x0558, | |
64 | [1165] = 0x168e, [1166] = 0xf829, [1167] = 0x07ad, [1168] = 0x1103, | |
65 | [1169] = 0x0564, [1170] = 0x0559, [1171] = 0x4000, [1184] = 0x6318, | |
66 | [1185] = 0x6300, [1186] = 0x0fca, [1187] = 0x0400, [1188] = 0x00d8, | |
67 | [1189] = 0x1eb5, [1190] = 0xf145, [1191] = 0x0b75, [1192] = 0x01c5, | |
68 | [1193] = 0x1c58, [1194] = 0xf373, [1195] = 0x0a54, [1196] = 0x0558, | |
69 | [1197] = 0x168e, [1198] = 0xf829, [1199] = 0x07ad, [1200] = 0x1103, | |
70 | [1201] = 0x0564, [1202] = 0x0559, [1203] = 0x4000, [1280] = 0x00c0, | |
71 | [1281] = 0x00c0, [1282] = 0x00c0, [1283] = 0x00c0, [1312] = 0x0200, | |
72 | [1313] = 0x0010, [1344] = 0x0098, [1345] = 0x0845, [1408] = 0x6318, | |
73 | [1409] = 0x6300, [1410] = 0x0fca, [1411] = 0x0400, [1412] = 0x00d8, | |
74 | [1413] = 0x1eb5, [1414] = 0xf145, [1415] = 0x0b75, [1416] = 0x01c5, | |
75 | [1417] = 0x1c58, [1418] = 0xf373, [1419] = 0x0a54, [1420] = 0x0558, | |
76 | [1421] = 0x168e, [1422] = 0xf829, [1423] = 0x07ad, [1424] = 0x1103, | |
77 | [1425] = 0x0564, [1426] = 0x0559, [1427] = 0x4000, [1568] = 0x0002, | |
78 | [1792] = 0xa100, [1793] = 0xa101, [1794] = 0xa101, [1795] = 0xa101, | |
79 | [1796] = 0xa101, [1797] = 0xa101, [1798] = 0xa101, [1799] = 0xa101, | |
80 | [1800] = 0xa101, [1801] = 0xa101, [1802] = 0xa101, [1803] = 0xa101, | |
81 | [1804] = 0xa101, [1805] = 0xa101, [1825] = 0x0055, [1848] = 0x3fff, | |
82 | [1849] = 0x1fff, [2049] = 0x0001, [2050] = 0x0069, [2056] = 0x0002, | |
83 | [2057] = 0x0003, [2058] = 0x0069, [12288] = 0x0001, [12289] = 0x0001, | |
84 | [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f, | |
85 | [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104, | |
86 | [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050, | |
87 | [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003, | |
88 | [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b, | |
89 | [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff, | |
90 | [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff, | |
91 | [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001, | |
92 | [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001, | |
93 | [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003, | |
94 | [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401, | |
95 | [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060, | |
96 | [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff, | |
97 | [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff, | |
98 | [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff, | |
99 | [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006, | |
100 | [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006, | |
101 | [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061, | |
102 | [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003, | |
103 | [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106, | |
104 | [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502, | |
105 | [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff, | |
106 | [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff, | |
107 | [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001, | |
108 | [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f, | |
109 | [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106, | |
110 | [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050, | |
111 | [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b, | |
112 | [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff, | |
113 | [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff, | |
114 | [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff, | |
115 | [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100, | |
116 | [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff, | |
117 | [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff, | |
118 | [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff, | |
119 | [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff, | |
120 | [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102, | |
121 | [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff, | |
122 | [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff, | |
123 | [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff, | |
124 | [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff, | |
125 | [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601, | |
126 | [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304, | |
127 | [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100 | |
128 | }; | |
129 | ||
130 | struct fll_config { | |
131 | int src; | |
132 | int in; | |
133 | int out; | |
134 | }; | |
135 | ||
136 | struct wm8995_priv { | |
137 | enum snd_soc_control_type control_type; | |
138 | int sysclk[2]; | |
139 | int mclk[2]; | |
140 | int aifclk[2]; | |
141 | struct fll_config fll[2], fll_suspend[2]; | |
219d8df8 DP |
142 | struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES]; |
143 | struct notifier_block disable_nb[WM8995_NUM_SUPPLIES]; | |
144 | struct snd_soc_codec *codec; | |
6a504a75 DP |
145 | }; |
146 | ||
219d8df8 DP |
147 | /* |
148 | * We can't use the same notifier block for more than one supply and | |
149 | * there's no way I can see to get from a callback to the caller | |
150 | * except container_of(). | |
151 | */ | |
152 | #define WM8995_REGULATOR_EVENT(n) \ | |
153 | static int wm8995_regulator_event_##n(struct notifier_block *nb, \ | |
154 | unsigned long event, void *data) \ | |
155 | { \ | |
156 | struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \ | |
157 | disable_nb[n]); \ | |
158 | if (event & REGULATOR_EVENT_DISABLE) { \ | |
159 | wm8995->codec->cache_sync = 1; \ | |
160 | } \ | |
161 | return 0; \ | |
162 | } | |
163 | ||
164 | WM8995_REGULATOR_EVENT(0) | |
165 | WM8995_REGULATOR_EVENT(1) | |
166 | WM8995_REGULATOR_EVENT(2) | |
167 | WM8995_REGULATOR_EVENT(3) | |
168 | WM8995_REGULATOR_EVENT(4) | |
169 | WM8995_REGULATOR_EVENT(5) | |
170 | WM8995_REGULATOR_EVENT(6) | |
171 | WM8995_REGULATOR_EVENT(7) | |
172 | ||
6a504a75 DP |
173 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); |
174 | static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); | |
175 | static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); | |
176 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); | |
177 | ||
178 | static const char *in1l_text[] = { | |
179 | "Differential", "Single-ended IN1LN", "Single-ended IN1LP" | |
180 | }; | |
181 | ||
182 | static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, | |
183 | 2, in1l_text); | |
184 | ||
185 | static const char *in1r_text[] = { | |
186 | "Differential", "Single-ended IN1RN", "Single-ended IN1RP" | |
187 | }; | |
188 | ||
189 | static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, | |
190 | 0, in1r_text); | |
191 | ||
192 | static const char *dmic_src_text[] = { | |
193 | "DMICDAT1", "DMICDAT2", "DMICDAT3" | |
194 | }; | |
195 | ||
196 | static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, | |
197 | 8, dmic_src_text); | |
198 | static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, | |
199 | 6, dmic_src_text); | |
200 | ||
201 | static const struct snd_kcontrol_new wm8995_snd_controls[] = { | |
202 | SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, | |
203 | WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
204 | SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, | |
205 | WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), | |
206 | ||
207 | SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, | |
208 | WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
209 | SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, | |
210 | WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), | |
211 | ||
212 | SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, | |
213 | WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
214 | SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, | |
215 | WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
216 | SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, | |
217 | WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
218 | ||
219 | SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, | |
220 | WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), | |
221 | ||
222 | SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, | |
223 | 4, 3, 0, in1l_boost_tlv), | |
224 | ||
225 | SOC_ENUM("IN1L Mode", in1l_enum), | |
226 | SOC_ENUM("IN1R Mode", in1r_enum), | |
227 | ||
228 | SOC_ENUM("DMIC1 SRC", dmic_src1_enum), | |
229 | SOC_ENUM("DMIC2 SRC", dmic_src2_enum), | |
230 | ||
231 | SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, | |
232 | 24, 0, sidetone_tlv), | |
233 | SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, | |
234 | 24, 0, sidetone_tlv), | |
235 | ||
236 | SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, | |
237 | WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
238 | SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, | |
239 | WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
240 | SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, | |
241 | WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) | |
242 | }; | |
243 | ||
244 | static void wm8995_update_class_w(struct snd_soc_codec *codec) | |
245 | { | |
246 | int enable = 1; | |
247 | int source = 0; /* GCC flow analysis can't track enable */ | |
248 | int reg, reg_r; | |
249 | ||
250 | /* We also need the same setting for L/R and only one path */ | |
251 | reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING); | |
252 | switch (reg) { | |
253 | case WM8995_AIF2DACL_TO_DAC1L: | |
254 | dev_dbg(codec->dev, "Class W source AIF2DAC\n"); | |
255 | source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; | |
256 | break; | |
257 | case WM8995_AIF1DAC2L_TO_DAC1L: | |
258 | dev_dbg(codec->dev, "Class W source AIF1DAC2\n"); | |
259 | source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; | |
260 | break; | |
261 | case WM8995_AIF1DAC1L_TO_DAC1L: | |
262 | dev_dbg(codec->dev, "Class W source AIF1DAC1\n"); | |
263 | source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; | |
264 | break; | |
265 | default: | |
266 | dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg); | |
267 | enable = 0; | |
268 | break; | |
269 | } | |
270 | ||
271 | reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING); | |
272 | if (reg_r != reg) { | |
273 | dev_dbg(codec->dev, "Left and right DAC mixers different\n"); | |
274 | enable = 0; | |
275 | } | |
276 | ||
277 | if (enable) { | |
278 | dev_dbg(codec->dev, "Class W enabled\n"); | |
279 | snd_soc_update_bits(codec, WM8995_CLASS_W_1, | |
280 | WM8995_CP_DYN_PWR_MASK | | |
281 | WM8995_CP_DYN_SRC_SEL_MASK, | |
282 | source | WM8995_CP_DYN_PWR); | |
283 | } else { | |
284 | dev_dbg(codec->dev, "Class W disabled\n"); | |
285 | snd_soc_update_bits(codec, WM8995_CLASS_W_1, | |
286 | WM8995_CP_DYN_PWR_MASK, 0); | |
287 | } | |
288 | } | |
289 | ||
290 | static int check_clk_sys(struct snd_soc_dapm_widget *source, | |
291 | struct snd_soc_dapm_widget *sink) | |
292 | { | |
293 | unsigned int reg; | |
294 | const char *clk; | |
295 | ||
296 | reg = snd_soc_read(source->codec, WM8995_CLOCKING_1); | |
297 | /* Check what we're currently using for CLK_SYS */ | |
298 | if (reg & WM8995_SYSCLK_SRC) | |
299 | clk = "AIF2CLK"; | |
300 | else | |
301 | clk = "AIF1CLK"; | |
302 | return !strcmp(source->name, clk); | |
303 | } | |
304 | ||
305 | static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, | |
306 | struct snd_ctl_elem_value *ucontrol) | |
307 | { | |
9d03545d JN |
308 | struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); |
309 | struct snd_soc_dapm_widget *w = wlist->widgets[0]; | |
6a504a75 DP |
310 | struct snd_soc_codec *codec; |
311 | int ret; | |
312 | ||
6a504a75 DP |
313 | codec = w->codec; |
314 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); | |
315 | wm8995_update_class_w(codec); | |
316 | return ret; | |
317 | } | |
318 | ||
319 | static int hp_supply_event(struct snd_soc_dapm_widget *w, | |
320 | struct snd_kcontrol *kcontrol, int event) | |
321 | { | |
322 | struct snd_soc_codec *codec; | |
323 | struct wm8995_priv *wm8995; | |
324 | ||
325 | codec = w->codec; | |
326 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
327 | ||
328 | switch (event) { | |
329 | case SND_SOC_DAPM_PRE_PMU: | |
330 | /* Enable the headphone amp */ | |
331 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
332 | WM8995_HPOUT1L_ENA_MASK | | |
333 | WM8995_HPOUT1R_ENA_MASK, | |
334 | WM8995_HPOUT1L_ENA | | |
335 | WM8995_HPOUT1R_ENA); | |
336 | ||
337 | /* Enable the second stage */ | |
338 | snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, | |
339 | WM8995_HPOUT1L_DLY_MASK | | |
340 | WM8995_HPOUT1R_DLY_MASK, | |
341 | WM8995_HPOUT1L_DLY | | |
342 | WM8995_HPOUT1R_DLY); | |
343 | break; | |
344 | case SND_SOC_DAPM_PRE_PMD: | |
345 | snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, | |
346 | WM8995_CP_ENA_MASK, 0); | |
347 | break; | |
348 | } | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static void dc_servo_cmd(struct snd_soc_codec *codec, | |
354 | unsigned int reg, unsigned int val, unsigned int mask) | |
355 | { | |
356 | int timeout = 10; | |
357 | ||
358 | dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", | |
359 | __func__, reg, val, mask); | |
360 | ||
361 | snd_soc_write(codec, reg, val); | |
362 | while (timeout--) { | |
363 | msleep(10); | |
364 | val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0); | |
365 | if ((val & mask) == mask) | |
366 | return; | |
367 | } | |
368 | ||
369 | dev_err(codec->dev, "Timed out waiting for DC Servo\n"); | |
370 | } | |
371 | ||
372 | static int hp_event(struct snd_soc_dapm_widget *w, | |
373 | struct snd_kcontrol *kcontrol, int event) | |
374 | { | |
375 | struct snd_soc_codec *codec; | |
376 | unsigned int reg; | |
377 | ||
378 | codec = w->codec; | |
379 | reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1); | |
380 | ||
381 | switch (event) { | |
382 | case SND_SOC_DAPM_POST_PMU: | |
383 | snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, | |
384 | WM8995_CP_ENA_MASK, WM8995_CP_ENA); | |
385 | ||
386 | msleep(5); | |
387 | ||
388 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
389 | WM8995_HPOUT1L_ENA_MASK | | |
390 | WM8995_HPOUT1R_ENA_MASK, | |
391 | WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); | |
392 | ||
393 | udelay(20); | |
394 | ||
395 | reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; | |
396 | snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); | |
397 | ||
398 | snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | | |
399 | WM8995_DCS_ENA_CHAN_1); | |
400 | ||
401 | dc_servo_cmd(codec, WM8995_DC_SERVO_2, | |
402 | WM8995_DCS_TRIG_STARTUP_0 | | |
403 | WM8995_DCS_TRIG_STARTUP_1, | |
404 | WM8995_DCS_TRIG_DAC_WR_0 | | |
405 | WM8995_DCS_TRIG_DAC_WR_1); | |
406 | ||
407 | reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | | |
408 | WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; | |
409 | snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); | |
410 | ||
411 | break; | |
412 | case SND_SOC_DAPM_PRE_PMD: | |
413 | snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, | |
414 | WM8995_HPOUT1L_OUTP_MASK | | |
415 | WM8995_HPOUT1R_OUTP_MASK | | |
416 | WM8995_HPOUT1L_RMV_SHORT_MASK | | |
417 | WM8995_HPOUT1R_RMV_SHORT_MASK, 0); | |
418 | ||
419 | snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, | |
420 | WM8995_HPOUT1L_DLY_MASK | | |
421 | WM8995_HPOUT1R_DLY_MASK, 0); | |
422 | ||
423 | snd_soc_write(codec, WM8995_DC_SERVO_1, 0); | |
424 | ||
425 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
426 | WM8995_HPOUT1L_ENA_MASK | | |
427 | WM8995_HPOUT1R_ENA_MASK, | |
428 | 0); | |
429 | break; | |
430 | } | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
435 | static int configure_aif_clock(struct snd_soc_codec *codec, int aif) | |
436 | { | |
437 | struct wm8995_priv *wm8995; | |
438 | int rate; | |
439 | int reg1 = 0; | |
440 | int offset; | |
441 | ||
442 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
443 | ||
444 | if (aif) | |
445 | offset = 4; | |
446 | else | |
447 | offset = 0; | |
448 | ||
449 | switch (wm8995->sysclk[aif]) { | |
450 | case WM8995_SYSCLK_MCLK1: | |
451 | rate = wm8995->mclk[0]; | |
452 | break; | |
453 | case WM8995_SYSCLK_MCLK2: | |
454 | reg1 |= 0x8; | |
455 | rate = wm8995->mclk[1]; | |
456 | break; | |
457 | case WM8995_SYSCLK_FLL1: | |
458 | reg1 |= 0x10; | |
459 | rate = wm8995->fll[0].out; | |
460 | break; | |
461 | case WM8995_SYSCLK_FLL2: | |
462 | reg1 |= 0x18; | |
463 | rate = wm8995->fll[1].out; | |
464 | break; | |
465 | default: | |
466 | return -EINVAL; | |
467 | } | |
468 | ||
469 | if (rate >= 13500000) { | |
470 | rate /= 2; | |
471 | reg1 |= WM8995_AIF1CLK_DIV; | |
472 | ||
473 | dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", | |
474 | aif + 1, rate); | |
475 | } | |
476 | ||
477 | wm8995->aifclk[aif] = rate; | |
478 | ||
479 | snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset, | |
480 | WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, | |
481 | reg1); | |
482 | return 0; | |
483 | } | |
484 | ||
485 | static int configure_clock(struct snd_soc_codec *codec) | |
486 | { | |
487 | struct wm8995_priv *wm8995; | |
73478755 | 488 | int change, new; |
6a504a75 DP |
489 | |
490 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
491 | ||
492 | /* Bring up the AIF clocks first */ | |
493 | configure_aif_clock(codec, 0); | |
494 | configure_aif_clock(codec, 1); | |
495 | ||
496 | /* | |
497 | * Then switch CLK_SYS over to the higher of them; a change | |
498 | * can only happen as a result of a clocking change which can | |
499 | * only be made outside of DAPM so we can safely redo the | |
500 | * clocking. | |
501 | */ | |
502 | ||
503 | /* If they're equal it doesn't matter which is used */ | |
504 | if (wm8995->aifclk[0] == wm8995->aifclk[1]) | |
505 | return 0; | |
506 | ||
507 | if (wm8995->aifclk[0] < wm8995->aifclk[1]) | |
508 | new = WM8995_SYSCLK_SRC; | |
509 | else | |
510 | new = 0; | |
511 | ||
73478755 AL |
512 | change = snd_soc_update_bits(codec, WM8995_CLOCKING_1, |
513 | WM8995_SYSCLK_SRC_MASK, new); | |
514 | if (!change) | |
6a504a75 DP |
515 | return 0; |
516 | ||
6a504a75 DP |
517 | snd_soc_dapm_sync(&codec->dapm); |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static int clk_sys_event(struct snd_soc_dapm_widget *w, | |
523 | struct snd_kcontrol *kcontrol, int event) | |
524 | { | |
525 | struct snd_soc_codec *codec; | |
526 | ||
527 | codec = w->codec; | |
528 | ||
529 | switch (event) { | |
530 | case SND_SOC_DAPM_PRE_PMU: | |
531 | return configure_clock(codec); | |
532 | ||
533 | case SND_SOC_DAPM_POST_PMD: | |
534 | configure_clock(codec); | |
535 | break; | |
536 | } | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | static const char *sidetone_text[] = { | |
542 | "ADC/DMIC1", "DMIC2", | |
543 | }; | |
544 | ||
545 | static const struct soc_enum sidetone1_enum = | |
546 | SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text); | |
547 | ||
548 | static const struct snd_kcontrol_new sidetone1_mux = | |
549 | SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); | |
550 | ||
551 | static const struct soc_enum sidetone2_enum = | |
552 | SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text); | |
553 | ||
554 | static const struct snd_kcontrol_new sidetone2_mux = | |
555 | SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); | |
556 | ||
557 | static const struct snd_kcontrol_new aif1adc1l_mix[] = { | |
558 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
559 | 1, 1, 0), | |
560 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
561 | 0, 1, 0), | |
562 | }; | |
563 | ||
564 | static const struct snd_kcontrol_new aif1adc1r_mix[] = { | |
565 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
566 | 1, 1, 0), | |
567 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
568 | 0, 1, 0), | |
569 | }; | |
570 | ||
571 | static const struct snd_kcontrol_new aif1adc2l_mix[] = { | |
572 | SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
573 | 1, 1, 0), | |
574 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
575 | 0, 1, 0), | |
576 | }; | |
577 | ||
578 | static const struct snd_kcontrol_new aif1adc2r_mix[] = { | |
579 | SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
580 | 1, 1, 0), | |
581 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
582 | 0, 1, 0), | |
583 | }; | |
584 | ||
585 | static const struct snd_kcontrol_new dac1l_mix[] = { | |
586 | WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
587 | 5, 1, 0), | |
588 | WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
589 | 4, 1, 0), | |
590 | WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
591 | 2, 1, 0), | |
592 | WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
593 | 1, 1, 0), | |
594 | WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
595 | 0, 1, 0), | |
596 | }; | |
597 | ||
598 | static const struct snd_kcontrol_new dac1r_mix[] = { | |
599 | WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
600 | 5, 1, 0), | |
601 | WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
602 | 4, 1, 0), | |
603 | WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
604 | 2, 1, 0), | |
605 | WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
606 | 1, 1, 0), | |
607 | WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
608 | 0, 1, 0), | |
609 | }; | |
610 | ||
611 | static const struct snd_kcontrol_new aif2dac2l_mix[] = { | |
612 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
613 | 5, 1, 0), | |
614 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
615 | 4, 1, 0), | |
616 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
617 | 2, 1, 0), | |
618 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
619 | 1, 1, 0), | |
620 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
621 | 0, 1, 0), | |
622 | }; | |
623 | ||
624 | static const struct snd_kcontrol_new aif2dac2r_mix[] = { | |
625 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
626 | 5, 1, 0), | |
627 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
628 | 4, 1, 0), | |
629 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
630 | 2, 1, 0), | |
631 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
632 | 1, 1, 0), | |
633 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
634 | 0, 1, 0), | |
635 | }; | |
636 | ||
637 | static const struct snd_kcontrol_new in1l_pga = | |
638 | SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); | |
639 | ||
640 | static const struct snd_kcontrol_new in1r_pga = | |
641 | SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); | |
642 | ||
643 | static const char *adc_mux_text[] = { | |
644 | "ADC", | |
645 | "DMIC", | |
646 | }; | |
647 | ||
648 | static const struct soc_enum adc_enum = | |
649 | SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); | |
650 | ||
651 | static const struct snd_kcontrol_new adcl_mux = | |
652 | SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); | |
653 | ||
654 | static const struct snd_kcontrol_new adcr_mux = | |
655 | SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); | |
656 | ||
657 | static const char *spk_src_text[] = { | |
658 | "DAC1L", "DAC1R", "DAC2L", "DAC2R" | |
659 | }; | |
660 | ||
661 | static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, | |
662 | 0, spk_src_text); | |
663 | static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, | |
664 | 0, spk_src_text); | |
665 | static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, | |
666 | 0, spk_src_text); | |
667 | static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, | |
668 | 0, spk_src_text); | |
669 | ||
670 | static const struct snd_kcontrol_new spk1l_mux = | |
671 | SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); | |
672 | static const struct snd_kcontrol_new spk1r_mux = | |
673 | SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); | |
674 | static const struct snd_kcontrol_new spk2l_mux = | |
675 | SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); | |
676 | static const struct snd_kcontrol_new spk2r_mux = | |
677 | SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); | |
678 | ||
679 | static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { | |
680 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
681 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
682 | ||
683 | SND_SOC_DAPM_INPUT("IN1L"), | |
684 | SND_SOC_DAPM_INPUT("IN1R"), | |
685 | ||
686 | SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, | |
687 | &in1l_pga, 1), | |
688 | SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, | |
689 | &in1r_pga, 1), | |
690 | ||
9ce31623 MB |
691 | SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0, |
692 | NULL, 0), | |
693 | SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0, | |
694 | NULL, 0), | |
6a504a75 DP |
695 | |
696 | SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), | |
697 | SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), | |
698 | SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), | |
699 | SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), | |
700 | SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), | |
701 | SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, | |
702 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
703 | ||
704 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, | |
705 | WM8995_POWER_MANAGEMENT_3, 9, 0), | |
706 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, | |
707 | WM8995_POWER_MANAGEMENT_3, 8, 0), | |
708 | SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, | |
709 | SND_SOC_NOPM, 0, 0), | |
710 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", | |
711 | 0, WM8995_POWER_MANAGEMENT_3, 11, 0), | |
712 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", | |
713 | 0, WM8995_POWER_MANAGEMENT_3, 10, 0), | |
714 | ||
715 | SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, | |
716 | &adcl_mux), | |
717 | SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, | |
718 | &adcr_mux), | |
719 | ||
720 | SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), | |
721 | SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), | |
722 | SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), | |
723 | SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), | |
724 | ||
725 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), | |
726 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), | |
727 | ||
728 | SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, | |
729 | aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), | |
730 | SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, | |
731 | aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), | |
732 | SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, | |
733 | aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), | |
734 | SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, | |
735 | aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), | |
736 | ||
737 | SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
738 | 9, 0), | |
739 | SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
740 | 8, 0), | |
741 | SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, | |
742 | 0, 0), | |
743 | ||
744 | SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
745 | 11, 0), | |
746 | SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
747 | 10, 0), | |
748 | ||
749 | SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, | |
750 | aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), | |
751 | SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, | |
752 | aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), | |
753 | ||
754 | SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), | |
755 | SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), | |
756 | SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), | |
757 | SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), | |
758 | ||
759 | SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, | |
760 | ARRAY_SIZE(dac1l_mix)), | |
761 | SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, | |
762 | ARRAY_SIZE(dac1r_mix)), | |
763 | ||
764 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), | |
765 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), | |
766 | ||
767 | SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
768 | hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
769 | ||
770 | SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, | |
771 | hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
772 | ||
773 | SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, | |
774 | 4, 0, &spk1l_mux), | |
775 | SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, | |
776 | 4, 0, &spk1r_mux), | |
777 | SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, | |
778 | 4, 0, &spk2l_mux), | |
779 | SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, | |
780 | 4, 0, &spk2r_mux), | |
781 | ||
782 | SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), | |
783 | ||
784 | SND_SOC_DAPM_OUTPUT("HP1L"), | |
785 | SND_SOC_DAPM_OUTPUT("HP1R"), | |
786 | SND_SOC_DAPM_OUTPUT("SPK1L"), | |
787 | SND_SOC_DAPM_OUTPUT("SPK1R"), | |
788 | SND_SOC_DAPM_OUTPUT("SPK2L"), | |
789 | SND_SOC_DAPM_OUTPUT("SPK2R") | |
790 | }; | |
791 | ||
792 | static const struct snd_soc_dapm_route wm8995_intercon[] = { | |
793 | { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, | |
794 | { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, | |
795 | ||
796 | { "DSP1CLK", NULL, "CLK_SYS" }, | |
797 | { "DSP2CLK", NULL, "CLK_SYS" }, | |
798 | { "SYSDSPCLK", NULL, "CLK_SYS" }, | |
799 | ||
800 | { "AIF1ADC1L", NULL, "AIF1CLK" }, | |
801 | { "AIF1ADC1L", NULL, "DSP1CLK" }, | |
802 | { "AIF1ADC1R", NULL, "AIF1CLK" }, | |
803 | { "AIF1ADC1R", NULL, "DSP1CLK" }, | |
804 | { "AIF1ADC1R", NULL, "SYSDSPCLK" }, | |
805 | ||
806 | { "AIF1ADC2L", NULL, "AIF1CLK" }, | |
807 | { "AIF1ADC2L", NULL, "DSP1CLK" }, | |
808 | { "AIF1ADC2R", NULL, "AIF1CLK" }, | |
809 | { "AIF1ADC2R", NULL, "DSP1CLK" }, | |
810 | { "AIF1ADC2R", NULL, "SYSDSPCLK" }, | |
811 | ||
812 | { "DMIC1L", NULL, "DMIC1DAT" }, | |
813 | { "DMIC1L", NULL, "CLK_SYS" }, | |
814 | { "DMIC1R", NULL, "DMIC1DAT" }, | |
815 | { "DMIC1R", NULL, "CLK_SYS" }, | |
816 | { "DMIC2L", NULL, "DMIC2DAT" }, | |
817 | { "DMIC2L", NULL, "CLK_SYS" }, | |
818 | { "DMIC2R", NULL, "DMIC2DAT" }, | |
819 | { "DMIC2R", NULL, "CLK_SYS" }, | |
820 | ||
821 | { "ADCL", NULL, "AIF1CLK" }, | |
822 | { "ADCL", NULL, "DSP1CLK" }, | |
823 | { "ADCL", NULL, "SYSDSPCLK" }, | |
824 | ||
825 | { "ADCR", NULL, "AIF1CLK" }, | |
826 | { "ADCR", NULL, "DSP1CLK" }, | |
827 | { "ADCR", NULL, "SYSDSPCLK" }, | |
828 | ||
829 | { "IN1L PGA", "IN1L Switch", "IN1L" }, | |
830 | { "IN1R PGA", "IN1R Switch", "IN1R" }, | |
831 | { "IN1L PGA", NULL, "LDO2" }, | |
832 | { "IN1R PGA", NULL, "LDO2" }, | |
833 | ||
834 | { "ADCL", NULL, "IN1L PGA" }, | |
835 | { "ADCR", NULL, "IN1R PGA" }, | |
836 | ||
837 | { "ADCL Mux", "ADC", "ADCL" }, | |
838 | { "ADCL Mux", "DMIC", "DMIC1L" }, | |
839 | { "ADCR Mux", "ADC", "ADCR" }, | |
840 | { "ADCR Mux", "DMIC", "DMIC1R" }, | |
841 | ||
842 | /* AIF1 outputs */ | |
843 | { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, | |
844 | { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, | |
845 | ||
846 | { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, | |
847 | { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, | |
848 | ||
849 | { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, | |
850 | { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, | |
851 | ||
852 | { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, | |
853 | { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, | |
854 | ||
855 | /* Sidetone */ | |
856 | { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, | |
857 | { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, | |
858 | { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, | |
859 | { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, | |
860 | ||
861 | { "AIF1DAC1L", NULL, "AIF1CLK" }, | |
862 | { "AIF1DAC1L", NULL, "DSP1CLK" }, | |
863 | { "AIF1DAC1R", NULL, "AIF1CLK" }, | |
864 | { "AIF1DAC1R", NULL, "DSP1CLK" }, | |
865 | { "AIF1DAC1R", NULL, "SYSDSPCLK" }, | |
866 | ||
867 | { "AIF1DAC2L", NULL, "AIF1CLK" }, | |
868 | { "AIF1DAC2L", NULL, "DSP1CLK" }, | |
869 | { "AIF1DAC2R", NULL, "AIF1CLK" }, | |
870 | { "AIF1DAC2R", NULL, "DSP1CLK" }, | |
871 | { "AIF1DAC2R", NULL, "SYSDSPCLK" }, | |
872 | ||
873 | { "DAC1L", NULL, "AIF1CLK" }, | |
874 | { "DAC1L", NULL, "DSP1CLK" }, | |
875 | { "DAC1L", NULL, "SYSDSPCLK" }, | |
876 | ||
877 | { "DAC1R", NULL, "AIF1CLK" }, | |
878 | { "DAC1R", NULL, "DSP1CLK" }, | |
879 | { "DAC1R", NULL, "SYSDSPCLK" }, | |
880 | ||
881 | { "AIF1DAC1L", NULL, "AIF1DACDAT" }, | |
882 | { "AIF1DAC1R", NULL, "AIF1DACDAT" }, | |
883 | { "AIF1DAC2L", NULL, "AIF1DACDAT" }, | |
884 | { "AIF1DAC2R", NULL, "AIF1DACDAT" }, | |
885 | ||
886 | /* DAC1 inputs */ | |
887 | { "DAC1L", NULL, "DAC1L Mixer" }, | |
888 | { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
889 | { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
890 | { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
891 | { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
892 | ||
893 | { "DAC1R", NULL, "DAC1R Mixer" }, | |
894 | { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
895 | { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
896 | { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
897 | { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
898 | ||
899 | /* DAC2/AIF2 outputs */ | |
900 | { "DAC2L", NULL, "AIF2DAC2L Mixer" }, | |
901 | { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
902 | { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
903 | ||
904 | { "DAC2R", NULL, "AIF2DAC2R Mixer" }, | |
905 | { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
906 | { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
907 | ||
908 | /* Output stages */ | |
909 | { "Headphone PGA", NULL, "DAC1L" }, | |
910 | { "Headphone PGA", NULL, "DAC1R" }, | |
911 | ||
912 | { "Headphone PGA", NULL, "DAC2L" }, | |
913 | { "Headphone PGA", NULL, "DAC2R" }, | |
914 | ||
915 | { "Headphone PGA", NULL, "Headphone Supply" }, | |
916 | { "Headphone PGA", NULL, "CLK_SYS" }, | |
917 | { "Headphone PGA", NULL, "LDO2" }, | |
918 | ||
919 | { "HP1L", NULL, "Headphone PGA" }, | |
920 | { "HP1R", NULL, "Headphone PGA" }, | |
921 | ||
922 | { "SPK1L Driver", "DAC1L", "DAC1L" }, | |
923 | { "SPK1L Driver", "DAC1R", "DAC1R" }, | |
924 | { "SPK1L Driver", "DAC2L", "DAC2L" }, | |
925 | { "SPK1L Driver", "DAC2R", "DAC2R" }, | |
926 | { "SPK1L Driver", NULL, "CLK_SYS" }, | |
927 | ||
928 | { "SPK1R Driver", "DAC1L", "DAC1L" }, | |
929 | { "SPK1R Driver", "DAC1R", "DAC1R" }, | |
930 | { "SPK1R Driver", "DAC2L", "DAC2L" }, | |
931 | { "SPK1R Driver", "DAC2R", "DAC2R" }, | |
932 | { "SPK1R Driver", NULL, "CLK_SYS" }, | |
933 | ||
934 | { "SPK2L Driver", "DAC1L", "DAC1L" }, | |
935 | { "SPK2L Driver", "DAC1R", "DAC1R" }, | |
936 | { "SPK2L Driver", "DAC2L", "DAC2L" }, | |
937 | { "SPK2L Driver", "DAC2R", "DAC2R" }, | |
938 | { "SPK2L Driver", NULL, "CLK_SYS" }, | |
939 | ||
940 | { "SPK2R Driver", "DAC1L", "DAC1L" }, | |
941 | { "SPK2R Driver", "DAC1R", "DAC1R" }, | |
942 | { "SPK2R Driver", "DAC2L", "DAC2L" }, | |
943 | { "SPK2R Driver", "DAC2R", "DAC2R" }, | |
944 | { "SPK2R Driver", NULL, "CLK_SYS" }, | |
945 | ||
946 | { "SPK1L", NULL, "SPK1L Driver" }, | |
947 | { "SPK1R", NULL, "SPK1R Driver" }, | |
948 | { "SPK2L", NULL, "SPK2L Driver" }, | |
949 | { "SPK2R", NULL, "SPK2R Driver" } | |
950 | }; | |
951 | ||
d4754ec9 | 952 | static int wm8995_volatile(struct snd_soc_codec *codec, unsigned int reg) |
6a504a75 DP |
953 | { |
954 | /* out of bounds registers are generally considered | |
955 | * volatile to support register banks that are partially | |
956 | * owned by something else for e.g. a DSP | |
957 | */ | |
958 | if (reg > WM8995_MAX_CACHED_REGISTER) | |
959 | return 1; | |
960 | ||
961 | switch (reg) { | |
962 | case WM8995_SOFTWARE_RESET: | |
963 | case WM8995_DC_SERVO_READBACK_0: | |
964 | case WM8995_INTERRUPT_STATUS_1: | |
965 | case WM8995_INTERRUPT_STATUS_2: | |
966 | case WM8995_INTERRUPT_STATUS_1_MASK: | |
967 | case WM8995_INTERRUPT_STATUS_2_MASK: | |
968 | case WM8995_INTERRUPT_CONTROL: | |
969 | case WM8995_ACCESSORY_DETECT_MODE1: | |
970 | case WM8995_ACCESSORY_DETECT_MODE2: | |
971 | case WM8995_HEADPHONE_DETECT1: | |
972 | case WM8995_HEADPHONE_DETECT2: | |
973 | return 1; | |
974 | } | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
979 | static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) | |
980 | { | |
981 | struct snd_soc_codec *codec = dai->codec; | |
982 | int mute_reg; | |
983 | ||
984 | switch (dai->id) { | |
985 | case 0: | |
986 | mute_reg = WM8995_AIF1_DAC1_FILTERS_1; | |
987 | break; | |
988 | case 1: | |
989 | mute_reg = WM8995_AIF2_DAC_FILTERS_1; | |
990 | break; | |
991 | default: | |
992 | return -EINVAL; | |
993 | } | |
994 | ||
995 | snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, | |
996 | !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); | |
997 | return 0; | |
998 | } | |
999 | ||
1000 | static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1001 | { | |
1002 | struct snd_soc_codec *codec; | |
1003 | int master; | |
1004 | int aif; | |
1005 | ||
1006 | codec = dai->codec; | |
1007 | ||
1008 | master = 0; | |
1009 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1010 | case SND_SOC_DAIFMT_CBS_CFS: | |
1011 | break; | |
1012 | case SND_SOC_DAIFMT_CBM_CFM: | |
1013 | master = WM8995_AIF1_MSTR; | |
1014 | break; | |
1015 | default: | |
1016 | dev_err(dai->dev, "Unknown master/slave configuration\n"); | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | ||
1020 | aif = 0; | |
1021 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1022 | case SND_SOC_DAIFMT_DSP_B: | |
1023 | aif |= WM8995_AIF1_LRCLK_INV; | |
1024 | case SND_SOC_DAIFMT_DSP_A: | |
1025 | aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); | |
1026 | break; | |
1027 | case SND_SOC_DAIFMT_I2S: | |
1028 | aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); | |
1029 | break; | |
1030 | case SND_SOC_DAIFMT_RIGHT_J: | |
1031 | break; | |
1032 | case SND_SOC_DAIFMT_LEFT_J: | |
1033 | aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); | |
1034 | break; | |
1035 | default: | |
1036 | dev_err(dai->dev, "Unknown dai format\n"); | |
1037 | return -EINVAL; | |
1038 | } | |
1039 | ||
1040 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1041 | case SND_SOC_DAIFMT_DSP_A: | |
1042 | case SND_SOC_DAIFMT_DSP_B: | |
1043 | /* frame inversion not valid for DSP modes */ | |
1044 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1045 | case SND_SOC_DAIFMT_NB_NF: | |
1046 | break; | |
1047 | case SND_SOC_DAIFMT_IB_NF: | |
1048 | aif |= WM8995_AIF1_BCLK_INV; | |
1049 | break; | |
1050 | default: | |
1051 | return -EINVAL; | |
1052 | } | |
1053 | break; | |
1054 | ||
1055 | case SND_SOC_DAIFMT_I2S: | |
1056 | case SND_SOC_DAIFMT_RIGHT_J: | |
1057 | case SND_SOC_DAIFMT_LEFT_J: | |
1058 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1059 | case SND_SOC_DAIFMT_NB_NF: | |
1060 | break; | |
1061 | case SND_SOC_DAIFMT_IB_IF: | |
1062 | aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; | |
1063 | break; | |
1064 | case SND_SOC_DAIFMT_IB_NF: | |
1065 | aif |= WM8995_AIF1_BCLK_INV; | |
1066 | break; | |
1067 | case SND_SOC_DAIFMT_NB_IF: | |
1068 | aif |= WM8995_AIF1_LRCLK_INV; | |
1069 | break; | |
1070 | default: | |
1071 | return -EINVAL; | |
1072 | } | |
1073 | break; | |
1074 | default: | |
1075 | return -EINVAL; | |
1076 | } | |
1077 | ||
1078 | snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1, | |
1079 | WM8995_AIF1_BCLK_INV_MASK | | |
1080 | WM8995_AIF1_LRCLK_INV_MASK | | |
1081 | WM8995_AIF1_FMT_MASK, aif); | |
1082 | snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE, | |
1083 | WM8995_AIF1_MSTR_MASK, master); | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static const int srs[] = { | |
1088 | 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, | |
1089 | 48000, 88200, 96000 | |
1090 | }; | |
1091 | ||
1092 | static const int fs_ratios[] = { | |
1093 | -1 /* reserved */, | |
1094 | 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 | |
1095 | }; | |
1096 | ||
1097 | static const int bclk_divs[] = { | |
1098 | 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 | |
1099 | }; | |
1100 | ||
1101 | static int wm8995_hw_params(struct snd_pcm_substream *substream, | |
1102 | struct snd_pcm_hw_params *params, | |
1103 | struct snd_soc_dai *dai) | |
1104 | { | |
1105 | struct snd_soc_codec *codec; | |
1106 | struct wm8995_priv *wm8995; | |
1107 | int aif1_reg; | |
1108 | int bclk_reg; | |
1109 | int lrclk_reg; | |
1110 | int rate_reg; | |
1111 | int bclk_rate; | |
1112 | int aif1; | |
1113 | int lrclk, bclk; | |
1114 | int i, rate_val, best, best_val, cur_val; | |
1115 | ||
1116 | codec = dai->codec; | |
1117 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1118 | ||
1119 | switch (dai->id) { | |
1120 | case 0: | |
1121 | aif1_reg = WM8995_AIF1_CONTROL_1; | |
1122 | bclk_reg = WM8995_AIF1_BCLK; | |
1123 | rate_reg = WM8995_AIF1_RATE; | |
1124 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || | |
1125 | wm8995->lrclk_shared[0] */) { | |
1126 | lrclk_reg = WM8995_AIF1DAC_LRCLK; | |
1127 | } else { | |
1128 | lrclk_reg = WM8995_AIF1ADC_LRCLK; | |
1129 | dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); | |
1130 | } | |
1131 | break; | |
1132 | case 1: | |
1133 | aif1_reg = WM8995_AIF2_CONTROL_1; | |
1134 | bclk_reg = WM8995_AIF2_BCLK; | |
1135 | rate_reg = WM8995_AIF2_RATE; | |
1136 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || | |
1137 | wm8995->lrclk_shared[1] */) { | |
1138 | lrclk_reg = WM8995_AIF2DAC_LRCLK; | |
1139 | } else { | |
1140 | lrclk_reg = WM8995_AIF2ADC_LRCLK; | |
1141 | dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); | |
1142 | } | |
1143 | break; | |
1144 | default: | |
1145 | return -EINVAL; | |
1146 | } | |
1147 | ||
1148 | bclk_rate = snd_soc_params_to_bclk(params); | |
1149 | if (bclk_rate < 0) | |
1150 | return bclk_rate; | |
1151 | ||
1152 | aif1 = 0; | |
1153 | switch (params_format(params)) { | |
1154 | case SNDRV_PCM_FORMAT_S16_LE: | |
1155 | break; | |
1156 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1157 | aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); | |
1158 | break; | |
1159 | case SNDRV_PCM_FORMAT_S24_LE: | |
1160 | aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); | |
1161 | break; | |
1162 | case SNDRV_PCM_FORMAT_S32_LE: | |
1163 | aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); | |
1164 | break; | |
1165 | default: | |
1166 | dev_err(dai->dev, "Unsupported word length %u\n", | |
1167 | params_format(params)); | |
1168 | return -EINVAL; | |
1169 | } | |
1170 | ||
1171 | /* try to find a suitable sample rate */ | |
1172 | for (i = 0; i < ARRAY_SIZE(srs); ++i) | |
1173 | if (srs[i] == params_rate(params)) | |
1174 | break; | |
1175 | if (i == ARRAY_SIZE(srs)) { | |
1176 | dev_err(dai->dev, "Sample rate %d is not supported\n", | |
1177 | params_rate(params)); | |
1178 | return -EINVAL; | |
1179 | } | |
1180 | rate_val = i << WM8995_AIF1_SR_SHIFT; | |
1181 | ||
1182 | dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); | |
1183 | dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", | |
1184 | dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); | |
1185 | ||
1186 | /* AIFCLK/fs ratio; look for a close match in either direction */ | |
1187 | best = 1; | |
1188 | best_val = abs((fs_ratios[1] * params_rate(params)) | |
1189 | - wm8995->aifclk[dai->id]); | |
1190 | for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { | |
1191 | cur_val = abs((fs_ratios[i] * params_rate(params)) | |
1192 | - wm8995->aifclk[dai->id]); | |
1193 | if (cur_val >= best_val) | |
1194 | continue; | |
1195 | best = i; | |
1196 | best_val = cur_val; | |
1197 | } | |
1198 | rate_val |= best; | |
1199 | ||
1200 | dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", | |
1201 | dai->id + 1, fs_ratios[best]); | |
1202 | ||
1203 | /* | |
1204 | * We may not get quite the right frequency if using | |
1205 | * approximate clocks so look for the closest match that is | |
1206 | * higher than the target (we need to ensure that there enough | |
1207 | * BCLKs to clock out the samples). | |
1208 | */ | |
1209 | best = 0; | |
1210 | bclk = 0; | |
1211 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1212 | cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate; | |
1213 | if (cur_val < 0) /* BCLK table is sorted */ | |
1214 | break; | |
1215 | best = i; | |
1216 | } | |
1217 | bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; | |
1218 | ||
1219 | bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; | |
1220 | dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", | |
1221 | bclk_divs[best], bclk_rate); | |
1222 | ||
1223 | lrclk = bclk_rate / params_rate(params); | |
1224 | dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", | |
1225 | lrclk, bclk_rate / lrclk); | |
1226 | ||
1227 | snd_soc_update_bits(codec, aif1_reg, | |
1228 | WM8995_AIF1_WL_MASK, aif1); | |
1229 | snd_soc_update_bits(codec, bclk_reg, | |
1230 | WM8995_AIF1_BCLK_DIV_MASK, bclk); | |
1231 | snd_soc_update_bits(codec, lrclk_reg, | |
1232 | WM8995_AIF1DAC_RATE_MASK, lrclk); | |
1233 | snd_soc_update_bits(codec, rate_reg, | |
1234 | WM8995_AIF1_SR_MASK | | |
1235 | WM8995_AIF1CLK_RATE_MASK, rate_val); | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) | |
1240 | { | |
1241 | struct snd_soc_codec *codec = codec_dai->codec; | |
1242 | int reg, val, mask; | |
1243 | ||
1244 | switch (codec_dai->id) { | |
1245 | case 0: | |
1246 | reg = WM8995_AIF1_MASTER_SLAVE; | |
1247 | mask = WM8995_AIF1_TRI; | |
1248 | break; | |
1249 | case 1: | |
1250 | reg = WM8995_AIF2_MASTER_SLAVE; | |
1251 | mask = WM8995_AIF2_TRI; | |
1252 | break; | |
1253 | case 2: | |
1254 | reg = WM8995_POWER_MANAGEMENT_5; | |
1255 | mask = WM8995_AIF3_TRI; | |
1256 | break; | |
1257 | default: | |
1258 | return -EINVAL; | |
1259 | } | |
1260 | ||
1261 | if (tristate) | |
1262 | val = mask; | |
1263 | else | |
1264 | val = 0; | |
1265 | ||
a2828792 | 1266 | return snd_soc_update_bits(codec, reg, mask, val); |
6a504a75 DP |
1267 | } |
1268 | ||
1269 | /* The size in bits of the FLL divide multiplied by 10 | |
1270 | * to allow rounding later */ | |
1271 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1272 | ||
1273 | struct fll_div { | |
1274 | u16 outdiv; | |
1275 | u16 n; | |
1276 | u16 k; | |
1277 | u16 clk_ref_div; | |
1278 | u16 fll_fratio; | |
1279 | }; | |
1280 | ||
1281 | static int wm8995_get_fll_config(struct fll_div *fll, | |
1282 | int freq_in, int freq_out) | |
1283 | { | |
1284 | u64 Kpart; | |
1285 | unsigned int K, Ndiv, Nmod; | |
1286 | ||
1287 | pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); | |
1288 | ||
1289 | /* Scale the input frequency down to <= 13.5MHz */ | |
1290 | fll->clk_ref_div = 0; | |
1291 | while (freq_in > 13500000) { | |
1292 | fll->clk_ref_div++; | |
1293 | freq_in /= 2; | |
1294 | ||
1295 | if (fll->clk_ref_div > 3) | |
1296 | return -EINVAL; | |
1297 | } | |
1298 | pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); | |
1299 | ||
1300 | /* Scale the output to give 90MHz<=Fvco<=100MHz */ | |
1301 | fll->outdiv = 3; | |
1302 | while (freq_out * (fll->outdiv + 1) < 90000000) { | |
1303 | fll->outdiv++; | |
1304 | if (fll->outdiv > 63) | |
1305 | return -EINVAL; | |
1306 | } | |
1307 | freq_out *= fll->outdiv + 1; | |
1308 | pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); | |
1309 | ||
1310 | if (freq_in > 1000000) { | |
1311 | fll->fll_fratio = 0; | |
1312 | } else if (freq_in > 256000) { | |
1313 | fll->fll_fratio = 1; | |
1314 | freq_in *= 2; | |
1315 | } else if (freq_in > 128000) { | |
1316 | fll->fll_fratio = 2; | |
1317 | freq_in *= 4; | |
1318 | } else if (freq_in > 64000) { | |
1319 | fll->fll_fratio = 3; | |
1320 | freq_in *= 8; | |
1321 | } else { | |
1322 | fll->fll_fratio = 4; | |
1323 | freq_in *= 16; | |
1324 | } | |
1325 | pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); | |
1326 | ||
1327 | /* Now, calculate N.K */ | |
1328 | Ndiv = freq_out / freq_in; | |
1329 | ||
1330 | fll->n = Ndiv; | |
1331 | Nmod = freq_out % freq_in; | |
1332 | pr_debug("Nmod=%d\n", Nmod); | |
1333 | ||
1334 | /* Calculate fractional part - scale up so we can round. */ | |
1335 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1336 | ||
1337 | do_div(Kpart, freq_in); | |
1338 | ||
1339 | K = Kpart & 0xFFFFFFFF; | |
1340 | ||
1341 | if ((K % 10) >= 5) | |
1342 | K += 5; | |
1343 | ||
1344 | /* Move down to proper range now rounding is done */ | |
1345 | fll->k = K / 10; | |
1346 | ||
1347 | pr_debug("N=%x K=%x\n", fll->n, fll->k); | |
1348 | ||
1349 | return 0; | |
1350 | } | |
1351 | ||
1352 | static int wm8995_set_fll(struct snd_soc_dai *dai, int id, | |
1353 | int src, unsigned int freq_in, | |
1354 | unsigned int freq_out) | |
1355 | { | |
1356 | struct snd_soc_codec *codec; | |
1357 | struct wm8995_priv *wm8995; | |
1358 | int reg_offset, ret; | |
1359 | struct fll_div fll; | |
1360 | u16 reg, aif1, aif2; | |
1361 | ||
1362 | codec = dai->codec; | |
1363 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1364 | ||
1365 | aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1) | |
1366 | & WM8995_AIF1CLK_ENA; | |
1367 | ||
1368 | aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1) | |
1369 | & WM8995_AIF2CLK_ENA; | |
1370 | ||
1371 | switch (id) { | |
1372 | case WM8995_FLL1: | |
1373 | reg_offset = 0; | |
1374 | id = 0; | |
1375 | break; | |
1376 | case WM8995_FLL2: | |
1377 | reg_offset = 0x20; | |
1378 | id = 1; | |
1379 | break; | |
1380 | default: | |
1381 | return -EINVAL; | |
1382 | } | |
1383 | ||
1384 | switch (src) { | |
1385 | case 0: | |
1386 | /* Allow no source specification when stopping */ | |
1387 | if (freq_out) | |
1388 | return -EINVAL; | |
1389 | break; | |
1390 | case WM8995_FLL_SRC_MCLK1: | |
1391 | case WM8995_FLL_SRC_MCLK2: | |
1392 | case WM8995_FLL_SRC_LRCLK: | |
1393 | case WM8995_FLL_SRC_BCLK: | |
1394 | break; | |
1395 | default: | |
1396 | return -EINVAL; | |
1397 | } | |
1398 | ||
1399 | /* Are we changing anything? */ | |
1400 | if (wm8995->fll[id].src == src && | |
1401 | wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) | |
1402 | return 0; | |
1403 | ||
1404 | /* If we're stopping the FLL redo the old config - no | |
1405 | * registers will actually be written but we avoid GCC flow | |
1406 | * analysis bugs spewing warnings. | |
1407 | */ | |
1408 | if (freq_out) | |
1409 | ret = wm8995_get_fll_config(&fll, freq_in, freq_out); | |
1410 | else | |
1411 | ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, | |
1412 | wm8995->fll[id].out); | |
1413 | if (ret < 0) | |
1414 | return ret; | |
1415 | ||
1416 | /* Gate the AIF clocks while we reclock */ | |
1417 | snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, | |
1418 | WM8995_AIF1CLK_ENA_MASK, 0); | |
1419 | snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, | |
1420 | WM8995_AIF2CLK_ENA_MASK, 0); | |
1421 | ||
1422 | /* We always need to disable the FLL while reconfiguring */ | |
1423 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, | |
1424 | WM8995_FLL1_ENA_MASK, 0); | |
1425 | ||
1426 | reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | | |
1427 | (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); | |
1428 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, | |
1429 | WM8995_FLL1_OUTDIV_MASK | | |
1430 | WM8995_FLL1_FRATIO_MASK, reg); | |
1431 | ||
1432 | snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); | |
1433 | ||
1434 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, | |
1435 | WM8995_FLL1_N_MASK, | |
1436 | fll.n << WM8995_FLL1_N_SHIFT); | |
1437 | ||
1438 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, | |
1439 | WM8995_FLL1_REFCLK_DIV_MASK | | |
1440 | WM8995_FLL1_REFCLK_SRC_MASK, | |
1441 | (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | | |
1442 | (src - 1)); | |
1443 | ||
1444 | if (freq_out) | |
1445 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, | |
1446 | WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); | |
1447 | ||
1448 | wm8995->fll[id].in = freq_in; | |
1449 | wm8995->fll[id].out = freq_out; | |
1450 | wm8995->fll[id].src = src; | |
1451 | ||
1452 | /* Enable any gated AIF clocks */ | |
1453 | snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, | |
1454 | WM8995_AIF1CLK_ENA_MASK, aif1); | |
1455 | snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, | |
1456 | WM8995_AIF2CLK_ENA_MASK, aif2); | |
1457 | ||
1458 | configure_clock(codec); | |
1459 | ||
1460 | return 0; | |
1461 | } | |
1462 | ||
1463 | static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, | |
1464 | int clk_id, unsigned int freq, int dir) | |
1465 | { | |
1466 | struct snd_soc_codec *codec; | |
1467 | struct wm8995_priv *wm8995; | |
1468 | ||
1469 | codec = dai->codec; | |
1470 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1471 | ||
1472 | switch (dai->id) { | |
1473 | case 0: | |
1474 | case 1: | |
1475 | break; | |
1476 | default: | |
1477 | /* AIF3 shares clocking with AIF1/2 */ | |
1478 | return -EINVAL; | |
1479 | } | |
1480 | ||
1481 | switch (clk_id) { | |
1482 | case WM8995_SYSCLK_MCLK1: | |
1483 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; | |
1484 | wm8995->mclk[0] = freq; | |
1485 | dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", | |
1486 | dai->id + 1, freq); | |
1487 | break; | |
1488 | case WM8995_SYSCLK_MCLK2: | |
1489 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; | |
1490 | wm8995->mclk[1] = freq; | |
1491 | dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", | |
1492 | dai->id + 1, freq); | |
1493 | break; | |
1494 | case WM8995_SYSCLK_FLL1: | |
1495 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; | |
1496 | dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); | |
1497 | break; | |
1498 | case WM8995_SYSCLK_FLL2: | |
1499 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; | |
1500 | dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); | |
1501 | break; | |
1502 | case WM8995_SYSCLK_OPCLK: | |
1503 | default: | |
1504 | dev_err(dai->dev, "Unknown clock source %d\n", clk_id); | |
1505 | return -EINVAL; | |
1506 | } | |
1507 | ||
1508 | configure_clock(codec); | |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
1513 | static int wm8995_set_bias_level(struct snd_soc_codec *codec, | |
1514 | enum snd_soc_bias_level level) | |
1515 | { | |
1516 | struct wm8995_priv *wm8995; | |
1517 | int ret; | |
1518 | ||
1519 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1520 | switch (level) { | |
1521 | case SND_SOC_BIAS_ON: | |
1522 | case SND_SOC_BIAS_PREPARE: | |
1523 | break; | |
1524 | case SND_SOC_BIAS_STANDBY: | |
1525 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
219d8df8 DP |
1526 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), |
1527 | wm8995->supplies); | |
1528 | if (ret) | |
1529 | return ret; | |
1530 | ||
6a504a75 DP |
1531 | ret = snd_soc_cache_sync(codec); |
1532 | if (ret) { | |
1533 | dev_err(codec->dev, | |
1534 | "Failed to sync cache: %d\n", ret); | |
1535 | return ret; | |
1536 | } | |
1537 | ||
1538 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
1539 | WM8995_BG_ENA_MASK, WM8995_BG_ENA); | |
6a504a75 DP |
1540 | } |
1541 | break; | |
1542 | case SND_SOC_BIAS_OFF: | |
1543 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
1544 | WM8995_BG_ENA_MASK, 0); | |
219d8df8 DP |
1545 | regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), |
1546 | wm8995->supplies); | |
6a504a75 DP |
1547 | break; |
1548 | } | |
1549 | ||
1550 | codec->dapm.bias_level = level; | |
1551 | return 0; | |
1552 | } | |
1553 | ||
1554 | #ifdef CONFIG_PM | |
1555 | static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state) | |
1556 | { | |
1557 | wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | static int wm8995_resume(struct snd_soc_codec *codec) | |
1562 | { | |
1563 | wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1564 | return 0; | |
1565 | } | |
1566 | #else | |
1567 | #define wm8995_suspend NULL | |
1568 | #define wm8995_resume NULL | |
1569 | #endif | |
1570 | ||
1571 | static int wm8995_remove(struct snd_soc_codec *codec) | |
1572 | { | |
1573 | struct wm8995_priv *wm8995; | |
5992c587 | 1574 | int i; |
6a504a75 | 1575 | |
6a504a75 DP |
1576 | wm8995 = snd_soc_codec_get_drvdata(codec); |
1577 | wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
5992c587 AL |
1578 | |
1579 | for (i = 0; i < ARRAY_SIZE(wm8995->supplies); ++i) | |
1580 | regulator_unregister_notifier(wm8995->supplies[i].consumer, | |
1581 | &wm8995->disable_nb[i]); | |
1582 | ||
1583 | regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); | |
6a504a75 DP |
1584 | return 0; |
1585 | } | |
1586 | ||
1587 | static int wm8995_probe(struct snd_soc_codec *codec) | |
1588 | { | |
1589 | struct wm8995_priv *wm8995; | |
219d8df8 | 1590 | int i; |
6a504a75 DP |
1591 | int ret; |
1592 | ||
1593 | codec->dapm.idle_bias_off = 1; | |
1594 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
219d8df8 | 1595 | wm8995->codec = codec; |
6a504a75 DP |
1596 | |
1597 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type); | |
1598 | if (ret < 0) { | |
1599 | dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); | |
1600 | return ret; | |
1601 | } | |
1602 | ||
219d8df8 DP |
1603 | for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) |
1604 | wm8995->supplies[i].supply = wm8995_supply_names[i]; | |
1605 | ||
1606 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8995->supplies), | |
1607 | wm8995->supplies); | |
1608 | if (ret) { | |
1609 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
1610 | return ret; | |
1611 | } | |
1612 | ||
1613 | wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0; | |
1614 | wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1; | |
1615 | wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2; | |
1616 | wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3; | |
1617 | wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4; | |
1618 | wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5; | |
1619 | wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6; | |
1620 | wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7; | |
1621 | ||
1622 | /* This should really be moved into the regulator core */ | |
1623 | for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) { | |
1624 | ret = regulator_register_notifier(wm8995->supplies[i].consumer, | |
1625 | &wm8995->disable_nb[i]); | |
1626 | if (ret) { | |
1627 | dev_err(codec->dev, | |
1628 | "Failed to register regulator notifier: %d\n", | |
1629 | ret); | |
1630 | } | |
1631 | } | |
1632 | ||
1633 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), | |
1634 | wm8995->supplies); | |
1635 | if (ret) { | |
1636 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
1637 | goto err_reg_get; | |
1638 | } | |
1639 | ||
6a504a75 DP |
1640 | ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET); |
1641 | if (ret < 0) { | |
1642 | dev_err(codec->dev, "Failed to read device ID: %d\n", ret); | |
219d8df8 | 1643 | goto err_reg_enable; |
6a504a75 DP |
1644 | } |
1645 | ||
1646 | if (ret != 0x8995) { | |
1647 | dev_err(codec->dev, "Invalid device ID: %#x\n", ret); | |
6fa0c25b | 1648 | ret = -EINVAL; |
219d8df8 | 1649 | goto err_reg_enable; |
6a504a75 DP |
1650 | } |
1651 | ||
1652 | ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0); | |
1653 | if (ret < 0) { | |
1654 | dev_err(codec->dev, "Failed to issue reset: %d\n", ret); | |
219d8df8 | 1655 | goto err_reg_enable; |
6a504a75 DP |
1656 | } |
1657 | ||
1658 | wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1659 | ||
1660 | /* Latch volume updates (right only; we always do left then right). */ | |
1661 | snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME, | |
1662 | WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); | |
1663 | snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME, | |
1664 | WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); | |
1665 | snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME, | |
1666 | WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); | |
1667 | snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME, | |
1668 | WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); | |
1669 | snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME, | |
1670 | WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); | |
1671 | snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME, | |
1672 | WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); | |
1673 | snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME, | |
1674 | WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); | |
1675 | snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME, | |
1676 | WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); | |
1677 | snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME, | |
1678 | WM8995_IN1_VU_MASK, WM8995_IN1_VU); | |
1679 | ||
1680 | wm8995_update_class_w(codec); | |
1681 | ||
1682 | snd_soc_add_controls(codec, wm8995_snd_controls, | |
1683 | ARRAY_SIZE(wm8995_snd_controls)); | |
1684 | snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets, | |
1685 | ARRAY_SIZE(wm8995_dapm_widgets)); | |
1686 | snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon, | |
1687 | ARRAY_SIZE(wm8995_intercon)); | |
1688 | ||
1689 | return 0; | |
219d8df8 DP |
1690 | |
1691 | err_reg_enable: | |
1692 | regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); | |
1693 | err_reg_get: | |
1694 | regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); | |
1695 | return ret; | |
6a504a75 DP |
1696 | } |
1697 | ||
1698 | #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1699 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1700 | ||
1701 | static struct snd_soc_dai_ops wm8995_aif1_dai_ops = { | |
1702 | .set_sysclk = wm8995_set_dai_sysclk, | |
1703 | .set_fmt = wm8995_set_dai_fmt, | |
1704 | .hw_params = wm8995_hw_params, | |
1705 | .digital_mute = wm8995_aif_mute, | |
1706 | .set_pll = wm8995_set_fll, | |
1707 | .set_tristate = wm8995_set_tristate, | |
1708 | }; | |
1709 | ||
1710 | static struct snd_soc_dai_ops wm8995_aif2_dai_ops = { | |
1711 | .set_sysclk = wm8995_set_dai_sysclk, | |
1712 | .set_fmt = wm8995_set_dai_fmt, | |
1713 | .hw_params = wm8995_hw_params, | |
1714 | .digital_mute = wm8995_aif_mute, | |
1715 | .set_pll = wm8995_set_fll, | |
1716 | .set_tristate = wm8995_set_tristate, | |
1717 | }; | |
1718 | ||
1719 | static struct snd_soc_dai_ops wm8995_aif3_dai_ops = { | |
1720 | .set_tristate = wm8995_set_tristate, | |
1721 | }; | |
1722 | ||
1723 | static struct snd_soc_dai_driver wm8995_dai[] = { | |
1724 | { | |
1725 | .name = "wm8995-aif1", | |
1726 | .playback = { | |
1727 | .stream_name = "AIF1 Playback", | |
1728 | .channels_min = 2, | |
1729 | .channels_max = 2, | |
1730 | .rates = SNDRV_PCM_RATE_8000_96000, | |
1731 | .formats = WM8995_FORMATS | |
1732 | }, | |
1733 | .capture = { | |
1734 | .stream_name = "AIF1 Capture", | |
1735 | .channels_min = 2, | |
1736 | .channels_max = 2, | |
1737 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1738 | .formats = WM8995_FORMATS | |
1739 | }, | |
1740 | .ops = &wm8995_aif1_dai_ops | |
1741 | }, | |
1742 | { | |
1743 | .name = "wm8995-aif2", | |
1744 | .playback = { | |
1745 | .stream_name = "AIF2 Playback", | |
1746 | .channels_min = 2, | |
1747 | .channels_max = 2, | |
1748 | .rates = SNDRV_PCM_RATE_8000_96000, | |
1749 | .formats = WM8995_FORMATS | |
1750 | }, | |
1751 | .capture = { | |
1752 | .stream_name = "AIF2 Capture", | |
1753 | .channels_min = 2, | |
1754 | .channels_max = 2, | |
1755 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1756 | .formats = WM8995_FORMATS | |
1757 | }, | |
1758 | .ops = &wm8995_aif2_dai_ops | |
1759 | }, | |
1760 | { | |
1761 | .name = "wm8995-aif3", | |
1762 | .playback = { | |
1763 | .stream_name = "AIF3 Playback", | |
1764 | .channels_min = 2, | |
1765 | .channels_max = 2, | |
1766 | .rates = SNDRV_PCM_RATE_8000_96000, | |
1767 | .formats = WM8995_FORMATS | |
1768 | }, | |
1769 | .capture = { | |
1770 | .stream_name = "AIF3 Capture", | |
1771 | .channels_min = 2, | |
1772 | .channels_max = 2, | |
1773 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1774 | .formats = WM8995_FORMATS | |
1775 | }, | |
1776 | .ops = &wm8995_aif3_dai_ops | |
1777 | } | |
1778 | }; | |
1779 | ||
1780 | static struct snd_soc_codec_driver soc_codec_dev_wm8995 = { | |
1781 | .probe = wm8995_probe, | |
1782 | .remove = wm8995_remove, | |
1783 | .suspend = wm8995_suspend, | |
1784 | .resume = wm8995_resume, | |
1785 | .set_bias_level = wm8995_set_bias_level, | |
1786 | .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs), | |
1787 | .reg_word_size = sizeof(u16), | |
1788 | .reg_cache_default = wm8995_reg_defs, | |
1789 | .volatile_register = wm8995_volatile, | |
1790 | .compress_type = SND_SOC_RBTREE_COMPRESSION | |
1791 | }; | |
1792 | ||
1793 | #if defined(CONFIG_SPI_MASTER) | |
1794 | static int __devinit wm8995_spi_probe(struct spi_device *spi) | |
1795 | { | |
1796 | struct wm8995_priv *wm8995; | |
1797 | int ret; | |
1798 | ||
1799 | wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); | |
1800 | if (!wm8995) | |
1801 | return -ENOMEM; | |
1802 | ||
1803 | wm8995->control_type = SND_SOC_SPI; | |
1804 | spi_set_drvdata(spi, wm8995); | |
1805 | ||
1806 | ret = snd_soc_register_codec(&spi->dev, | |
1807 | &soc_codec_dev_wm8995, wm8995_dai, | |
1808 | ARRAY_SIZE(wm8995_dai)); | |
1809 | if (ret < 0) | |
1810 | kfree(wm8995); | |
1811 | return ret; | |
1812 | } | |
1813 | ||
1814 | static int __devexit wm8995_spi_remove(struct spi_device *spi) | |
1815 | { | |
1816 | snd_soc_unregister_codec(&spi->dev); | |
1817 | kfree(spi_get_drvdata(spi)); | |
1818 | return 0; | |
1819 | } | |
1820 | ||
1821 | static struct spi_driver wm8995_spi_driver = { | |
1822 | .driver = { | |
1823 | .name = "wm8995", | |
1824 | .owner = THIS_MODULE, | |
1825 | }, | |
1826 | .probe = wm8995_spi_probe, | |
1827 | .remove = __devexit_p(wm8995_spi_remove) | |
1828 | }; | |
1829 | #endif | |
1830 | ||
1831 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1832 | static __devinit int wm8995_i2c_probe(struct i2c_client *i2c, | |
1833 | const struct i2c_device_id *id) | |
1834 | { | |
1835 | struct wm8995_priv *wm8995; | |
1836 | int ret; | |
1837 | ||
1838 | wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); | |
1839 | if (!wm8995) | |
1840 | return -ENOMEM; | |
1841 | ||
1842 | wm8995->control_type = SND_SOC_I2C; | |
1843 | i2c_set_clientdata(i2c, wm8995); | |
1844 | ||
1845 | ret = snd_soc_register_codec(&i2c->dev, | |
1846 | &soc_codec_dev_wm8995, wm8995_dai, | |
1847 | ARRAY_SIZE(wm8995_dai)); | |
1848 | if (ret < 0) | |
1849 | kfree(wm8995); | |
1850 | return ret; | |
1851 | } | |
1852 | ||
1853 | static __devexit int wm8995_i2c_remove(struct i2c_client *client) | |
1854 | { | |
1855 | snd_soc_unregister_codec(&client->dev); | |
1856 | kfree(i2c_get_clientdata(client)); | |
1857 | return 0; | |
1858 | } | |
1859 | ||
1860 | static const struct i2c_device_id wm8995_i2c_id[] = { | |
1861 | {"wm8995", 0}, | |
1862 | {} | |
1863 | }; | |
1864 | ||
1865 | MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); | |
1866 | ||
1867 | static struct i2c_driver wm8995_i2c_driver = { | |
1868 | .driver = { | |
1869 | .name = "wm8995", | |
1870 | .owner = THIS_MODULE, | |
1871 | }, | |
1872 | .probe = wm8995_i2c_probe, | |
1873 | .remove = __devexit_p(wm8995_i2c_remove), | |
1874 | .id_table = wm8995_i2c_id | |
1875 | }; | |
1876 | #endif | |
1877 | ||
1878 | static int __init wm8995_modinit(void) | |
1879 | { | |
1880 | int ret = 0; | |
1881 | ||
1882 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1883 | ret = i2c_add_driver(&wm8995_i2c_driver); | |
1884 | if (ret) { | |
1885 | printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", | |
1886 | ret); | |
1887 | } | |
1888 | #endif | |
1889 | #if defined(CONFIG_SPI_MASTER) | |
1890 | ret = spi_register_driver(&wm8995_spi_driver); | |
1891 | if (ret) { | |
1892 | printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", | |
1893 | ret); | |
1894 | } | |
1895 | #endif | |
1896 | return ret; | |
1897 | } | |
1898 | ||
1899 | module_init(wm8995_modinit); | |
1900 | ||
1901 | static void __exit wm8995_exit(void) | |
1902 | { | |
1903 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1904 | i2c_del_driver(&wm8995_i2c_driver); | |
1905 | #endif | |
1906 | #if defined(CONFIG_SPI_MASTER) | |
1907 | spi_unregister_driver(&wm8995_spi_driver); | |
1908 | #endif | |
1909 | } | |
1910 | ||
1911 | module_exit(wm8995_exit); | |
1912 | ||
1913 | MODULE_DESCRIPTION("ASoC WM8995 driver"); | |
1914 | MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); | |
1915 | MODULE_LICENSE("GPL"); |