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1 | /* |
2 | * wm8996.c - WM8996 audio codec interface | |
3 | * | |
4 | * Copyright 2011 Wolfson Microelectronics PLC. | |
5 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/completion.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/gcd.h> | |
20 | #include <linux/gpio.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/regulator/consumer.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/workqueue.h> | |
25 | #include <sound/core.h> | |
26 | #include <sound/jack.h> | |
27 | #include <sound/pcm.h> | |
28 | #include <sound/pcm_params.h> | |
29 | #include <sound/soc.h> | |
30 | #include <sound/initval.h> | |
31 | #include <sound/tlv.h> | |
32 | #include <trace/events/asoc.h> | |
33 | ||
34 | #include <sound/wm8996.h> | |
35 | #include "wm8996.h" | |
36 | ||
37 | #define WM8996_AIFS 2 | |
38 | ||
39 | #define HPOUT1L 1 | |
40 | #define HPOUT1R 2 | |
41 | #define HPOUT2L 4 | |
42 | #define HPOUT2R 8 | |
43 | ||
c83495af | 44 | #define WM8996_NUM_SUPPLIES 3 |
a9ba6151 MB |
45 | static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = { |
46 | "DBVDD", | |
47 | "AVDD1", | |
48 | "AVDD2", | |
a9ba6151 MB |
49 | }; |
50 | ||
51 | struct wm8996_priv { | |
52 | struct snd_soc_codec *codec; | |
53 | ||
54 | int ldo1ena; | |
55 | ||
56 | int sysclk; | |
57 | int sysclk_src; | |
58 | ||
59 | int fll_src; | |
60 | int fll_fref; | |
61 | int fll_fout; | |
62 | ||
63 | struct completion fll_lock; | |
64 | ||
65 | u16 dcs_pending; | |
66 | struct completion dcs_done; | |
67 | ||
68 | u16 hpout_ena; | |
69 | u16 hpout_pending; | |
70 | ||
71 | struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES]; | |
72 | struct notifier_block disable_nb[WM8996_NUM_SUPPLIES]; | |
c83495af | 73 | struct regulator *cpvdd; |
a9ba6151 MB |
74 | |
75 | struct wm8996_pdata pdata; | |
76 | ||
77 | int rx_rate[WM8996_AIFS]; | |
78 | int bclk_rate[WM8996_AIFS]; | |
79 | ||
80 | /* Platform dependant ReTune mobile configuration */ | |
81 | int num_retune_mobile_texts; | |
82 | const char **retune_mobile_texts; | |
83 | int retune_mobile_cfg[2]; | |
84 | struct soc_enum retune_mobile_enum; | |
85 | ||
86 | struct snd_soc_jack *jack; | |
87 | bool detecting; | |
88 | bool jack_mic; | |
89 | wm8996_polarity_fn polarity_cb; | |
90 | ||
91 | #ifdef CONFIG_GPIOLIB | |
92 | struct gpio_chip gpio_chip; | |
93 | #endif | |
94 | }; | |
95 | ||
96 | /* We can't use the same notifier block for more than one supply and | |
97 | * there's no way I can see to get from a callback to the caller | |
98 | * except container_of(). | |
99 | */ | |
100 | #define WM8996_REGULATOR_EVENT(n) \ | |
101 | static int wm8996_regulator_event_##n(struct notifier_block *nb, \ | |
102 | unsigned long event, void *data) \ | |
103 | { \ | |
104 | struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \ | |
105 | disable_nb[n]); \ | |
106 | if (event & REGULATOR_EVENT_DISABLE) { \ | |
107 | wm8996->codec->cache_sync = 1; \ | |
108 | } \ | |
109 | return 0; \ | |
110 | } | |
111 | ||
112 | WM8996_REGULATOR_EVENT(0) | |
113 | WM8996_REGULATOR_EVENT(1) | |
114 | WM8996_REGULATOR_EVENT(2) | |
a9ba6151 MB |
115 | |
116 | static const u16 wm8996_reg[WM8996_MAX_REGISTER] = { | |
117 | [WM8996_SOFTWARE_RESET] = 0x8996, | |
118 | [WM8996_POWER_MANAGEMENT_7] = 0x10, | |
119 | [WM8996_DAC1_HPOUT1_VOLUME] = 0x88, | |
120 | [WM8996_DAC2_HPOUT2_VOLUME] = 0x88, | |
121 | [WM8996_DAC1_LEFT_VOLUME] = 0x2c0, | |
122 | [WM8996_DAC1_RIGHT_VOLUME] = 0x2c0, | |
123 | [WM8996_DAC2_LEFT_VOLUME] = 0x2c0, | |
124 | [WM8996_DAC2_RIGHT_VOLUME] = 0x2c0, | |
125 | [WM8996_OUTPUT1_LEFT_VOLUME] = 0x80, | |
126 | [WM8996_OUTPUT1_RIGHT_VOLUME] = 0x80, | |
127 | [WM8996_OUTPUT2_LEFT_VOLUME] = 0x80, | |
128 | [WM8996_OUTPUT2_RIGHT_VOLUME] = 0x80, | |
129 | [WM8996_MICBIAS_1] = 0x39, | |
130 | [WM8996_MICBIAS_2] = 0x39, | |
131 | [WM8996_LDO_1] = 0x3, | |
132 | [WM8996_LDO_2] = 0x13, | |
133 | [WM8996_ACCESSORY_DETECT_MODE_1] = 0x4, | |
134 | [WM8996_HEADPHONE_DETECT_1] = 0x20, | |
135 | [WM8996_MIC_DETECT_1] = 0x7600, | |
136 | [WM8996_MIC_DETECT_2] = 0xbf, | |
137 | [WM8996_CHARGE_PUMP_1] = 0x1f25, | |
138 | [WM8996_CHARGE_PUMP_2] = 0xab19, | |
139 | [WM8996_DC_SERVO_5] = 0x2a2a, | |
140 | [WM8996_CONTROL_INTERFACE_1] = 0x8004, | |
141 | [WM8996_CLOCKING_1] = 0x10, | |
142 | [WM8996_AIF_RATE] = 0x83, | |
143 | [WM8996_FLL_CONTROL_4] = 0x5dc0, | |
144 | [WM8996_FLL_CONTROL_5] = 0xc84, | |
145 | [WM8996_FLL_EFS_2] = 0x2, | |
146 | [WM8996_AIF1_TX_LRCLK_1] = 0x80, | |
147 | [WM8996_AIF1_TX_LRCLK_2] = 0x8, | |
148 | [WM8996_AIF1_RX_LRCLK_1] = 0x80, | |
149 | [WM8996_AIF1TX_DATA_CONFIGURATION_1] = 0x1818, | |
150 | [WM8996_AIF1RX_DATA_CONFIGURATION] = 0x1818, | |
151 | [WM8996_AIF1TX_TEST] = 0x7, | |
152 | [WM8996_AIF2_TX_LRCLK_1] = 0x80, | |
153 | [WM8996_AIF2_TX_LRCLK_2] = 0x8, | |
154 | [WM8996_AIF2_RX_LRCLK_1] = 0x80, | |
155 | [WM8996_AIF2TX_DATA_CONFIGURATION_1] = 0x1818, | |
156 | [WM8996_AIF2RX_DATA_CONFIGURATION] = 0x1818, | |
157 | [WM8996_AIF2TX_TEST] = 0x1, | |
158 | [WM8996_DSP1_TX_LEFT_VOLUME] = 0xc0, | |
159 | [WM8996_DSP1_TX_RIGHT_VOLUME] = 0xc0, | |
160 | [WM8996_DSP1_RX_LEFT_VOLUME] = 0xc0, | |
161 | [WM8996_DSP1_RX_RIGHT_VOLUME] = 0xc0, | |
162 | [WM8996_DSP1_TX_FILTERS] = 0x2000, | |
163 | [WM8996_DSP1_RX_FILTERS_1] = 0x200, | |
164 | [WM8996_DSP1_RX_FILTERS_2] = 0x10, | |
165 | [WM8996_DSP1_DRC_1] = 0x98, | |
166 | [WM8996_DSP1_DRC_2] = 0x845, | |
167 | [WM8996_DSP1_RX_EQ_GAINS_1] = 0x6318, | |
168 | [WM8996_DSP1_RX_EQ_GAINS_2] = 0x6300, | |
169 | [WM8996_DSP1_RX_EQ_BAND_1_A] = 0xfca, | |
170 | [WM8996_DSP1_RX_EQ_BAND_1_B] = 0x400, | |
171 | [WM8996_DSP1_RX_EQ_BAND_1_PG] = 0xd8, | |
172 | [WM8996_DSP1_RX_EQ_BAND_2_A] = 0x1eb5, | |
173 | [WM8996_DSP1_RX_EQ_BAND_2_B] = 0xf145, | |
174 | [WM8996_DSP1_RX_EQ_BAND_2_C] = 0xb75, | |
175 | [WM8996_DSP1_RX_EQ_BAND_2_PG] = 0x1c5, | |
176 | [WM8996_DSP1_RX_EQ_BAND_3_A] = 0x1c58, | |
177 | [WM8996_DSP1_RX_EQ_BAND_3_B] = 0xf373, | |
178 | [WM8996_DSP1_RX_EQ_BAND_3_C] = 0xa54, | |
179 | [WM8996_DSP1_RX_EQ_BAND_3_PG] = 0x558, | |
180 | [WM8996_DSP1_RX_EQ_BAND_4_A] = 0x168e, | |
181 | [WM8996_DSP1_RX_EQ_BAND_4_B] = 0xf829, | |
182 | [WM8996_DSP1_RX_EQ_BAND_4_C] = 0x7ad, | |
183 | [WM8996_DSP1_RX_EQ_BAND_4_PG] = 0x1103, | |
184 | [WM8996_DSP1_RX_EQ_BAND_5_A] = 0x564, | |
185 | [WM8996_DSP1_RX_EQ_BAND_5_B] = 0x559, | |
186 | [WM8996_DSP1_RX_EQ_BAND_5_PG] = 0x4000, | |
187 | [WM8996_DSP2_TX_LEFT_VOLUME] = 0xc0, | |
188 | [WM8996_DSP2_TX_RIGHT_VOLUME] = 0xc0, | |
189 | [WM8996_DSP2_RX_LEFT_VOLUME] = 0xc0, | |
190 | [WM8996_DSP2_RX_RIGHT_VOLUME] = 0xc0, | |
191 | [WM8996_DSP2_TX_FILTERS] = 0x2000, | |
192 | [WM8996_DSP2_RX_FILTERS_1] = 0x200, | |
193 | [WM8996_DSP2_RX_FILTERS_2] = 0x10, | |
194 | [WM8996_DSP2_DRC_1] = 0x98, | |
195 | [WM8996_DSP2_DRC_2] = 0x845, | |
196 | [WM8996_DSP2_RX_EQ_GAINS_1] = 0x6318, | |
197 | [WM8996_DSP2_RX_EQ_GAINS_2] = 0x6300, | |
198 | [WM8996_DSP2_RX_EQ_BAND_1_A] = 0xfca, | |
199 | [WM8996_DSP2_RX_EQ_BAND_1_B] = 0x400, | |
200 | [WM8996_DSP2_RX_EQ_BAND_1_PG] = 0xd8, | |
201 | [WM8996_DSP2_RX_EQ_BAND_2_A] = 0x1eb5, | |
202 | [WM8996_DSP2_RX_EQ_BAND_2_B] = 0xf145, | |
203 | [WM8996_DSP2_RX_EQ_BAND_2_C] = 0xb75, | |
204 | [WM8996_DSP2_RX_EQ_BAND_2_PG] = 0x1c5, | |
205 | [WM8996_DSP2_RX_EQ_BAND_3_A] = 0x1c58, | |
206 | [WM8996_DSP2_RX_EQ_BAND_3_B] = 0xf373, | |
207 | [WM8996_DSP2_RX_EQ_BAND_3_C] = 0xa54, | |
208 | [WM8996_DSP2_RX_EQ_BAND_3_PG] = 0x558, | |
209 | [WM8996_DSP2_RX_EQ_BAND_4_A] = 0x168e, | |
210 | [WM8996_DSP2_RX_EQ_BAND_4_B] = 0xf829, | |
211 | [WM8996_DSP2_RX_EQ_BAND_4_C] = 0x7ad, | |
212 | [WM8996_DSP2_RX_EQ_BAND_4_PG] = 0x1103, | |
213 | [WM8996_DSP2_RX_EQ_BAND_5_A] = 0x564, | |
214 | [WM8996_DSP2_RX_EQ_BAND_5_B] = 0x559, | |
215 | [WM8996_DSP2_RX_EQ_BAND_5_PG] = 0x4000, | |
216 | [WM8996_OVERSAMPLING] = 0xd, | |
217 | [WM8996_SIDETONE] = 0x1040, | |
218 | [WM8996_GPIO_1] = 0xa101, | |
219 | [WM8996_GPIO_2] = 0xa101, | |
220 | [WM8996_GPIO_3] = 0xa101, | |
221 | [WM8996_GPIO_4] = 0xa101, | |
222 | [WM8996_GPIO_5] = 0xa101, | |
223 | [WM8996_PULL_CONTROL_2] = 0x140, | |
224 | [WM8996_INTERRUPT_STATUS_1_MASK] = 0x1f, | |
225 | [WM8996_INTERRUPT_STATUS_2_MASK] = 0x1ecf, | |
226 | [WM8996_RIGHT_PDM_SPEAKER] = 0x1, | |
227 | [WM8996_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69, | |
228 | [WM8996_PDM_SPEAKER_VOLUME] = 0x66, | |
229 | [WM8996_WRITE_SEQUENCER_0] = 0x1, | |
230 | [WM8996_WRITE_SEQUENCER_1] = 0x1, | |
231 | [WM8996_WRITE_SEQUENCER_3] = 0x6, | |
232 | [WM8996_WRITE_SEQUENCER_4] = 0x40, | |
233 | [WM8996_WRITE_SEQUENCER_5] = 0x1, | |
234 | [WM8996_WRITE_SEQUENCER_6] = 0xf, | |
235 | [WM8996_WRITE_SEQUENCER_7] = 0x6, | |
236 | [WM8996_WRITE_SEQUENCER_8] = 0x1, | |
237 | [WM8996_WRITE_SEQUENCER_9] = 0x3, | |
238 | [WM8996_WRITE_SEQUENCER_10] = 0x104, | |
239 | [WM8996_WRITE_SEQUENCER_12] = 0x60, | |
240 | [WM8996_WRITE_SEQUENCER_13] = 0x11, | |
241 | [WM8996_WRITE_SEQUENCER_14] = 0x401, | |
242 | [WM8996_WRITE_SEQUENCER_16] = 0x50, | |
243 | [WM8996_WRITE_SEQUENCER_17] = 0x3, | |
244 | [WM8996_WRITE_SEQUENCER_18] = 0x100, | |
245 | [WM8996_WRITE_SEQUENCER_20] = 0x51, | |
246 | [WM8996_WRITE_SEQUENCER_21] = 0x3, | |
247 | [WM8996_WRITE_SEQUENCER_22] = 0x104, | |
248 | [WM8996_WRITE_SEQUENCER_23] = 0xa, | |
249 | [WM8996_WRITE_SEQUENCER_24] = 0x60, | |
250 | [WM8996_WRITE_SEQUENCER_25] = 0x3b, | |
251 | [WM8996_WRITE_SEQUENCER_26] = 0x502, | |
252 | [WM8996_WRITE_SEQUENCER_27] = 0x100, | |
253 | [WM8996_WRITE_SEQUENCER_28] = 0x2fff, | |
254 | [WM8996_WRITE_SEQUENCER_32] = 0x2fff, | |
255 | [WM8996_WRITE_SEQUENCER_36] = 0x2fff, | |
256 | [WM8996_WRITE_SEQUENCER_40] = 0x2fff, | |
257 | [WM8996_WRITE_SEQUENCER_44] = 0x2fff, | |
258 | [WM8996_WRITE_SEQUENCER_48] = 0x2fff, | |
259 | [WM8996_WRITE_SEQUENCER_52] = 0x2fff, | |
260 | [WM8996_WRITE_SEQUENCER_56] = 0x2fff, | |
261 | [WM8996_WRITE_SEQUENCER_60] = 0x2fff, | |
262 | [WM8996_WRITE_SEQUENCER_64] = 0x1, | |
263 | [WM8996_WRITE_SEQUENCER_65] = 0x1, | |
264 | [WM8996_WRITE_SEQUENCER_67] = 0x6, | |
265 | [WM8996_WRITE_SEQUENCER_68] = 0x40, | |
266 | [WM8996_WRITE_SEQUENCER_69] = 0x1, | |
267 | [WM8996_WRITE_SEQUENCER_70] = 0xf, | |
268 | [WM8996_WRITE_SEQUENCER_71] = 0x6, | |
269 | [WM8996_WRITE_SEQUENCER_72] = 0x1, | |
270 | [WM8996_WRITE_SEQUENCER_73] = 0x3, | |
271 | [WM8996_WRITE_SEQUENCER_74] = 0x104, | |
272 | [WM8996_WRITE_SEQUENCER_76] = 0x60, | |
273 | [WM8996_WRITE_SEQUENCER_77] = 0x11, | |
274 | [WM8996_WRITE_SEQUENCER_78] = 0x401, | |
275 | [WM8996_WRITE_SEQUENCER_80] = 0x50, | |
276 | [WM8996_WRITE_SEQUENCER_81] = 0x3, | |
277 | [WM8996_WRITE_SEQUENCER_82] = 0x100, | |
278 | [WM8996_WRITE_SEQUENCER_84] = 0x60, | |
279 | [WM8996_WRITE_SEQUENCER_85] = 0x3b, | |
280 | [WM8996_WRITE_SEQUENCER_86] = 0x502, | |
281 | [WM8996_WRITE_SEQUENCER_87] = 0x100, | |
282 | [WM8996_WRITE_SEQUENCER_88] = 0x2fff, | |
283 | [WM8996_WRITE_SEQUENCER_92] = 0x2fff, | |
284 | [WM8996_WRITE_SEQUENCER_96] = 0x2fff, | |
285 | [WM8996_WRITE_SEQUENCER_100] = 0x2fff, | |
286 | [WM8996_WRITE_SEQUENCER_104] = 0x2fff, | |
287 | [WM8996_WRITE_SEQUENCER_108] = 0x2fff, | |
288 | [WM8996_WRITE_SEQUENCER_112] = 0x2fff, | |
289 | [WM8996_WRITE_SEQUENCER_116] = 0x2fff, | |
290 | [WM8996_WRITE_SEQUENCER_120] = 0x2fff, | |
291 | [WM8996_WRITE_SEQUENCER_124] = 0x2fff, | |
292 | [WM8996_WRITE_SEQUENCER_128] = 0x1, | |
293 | [WM8996_WRITE_SEQUENCER_129] = 0x1, | |
294 | [WM8996_WRITE_SEQUENCER_131] = 0x6, | |
295 | [WM8996_WRITE_SEQUENCER_132] = 0x40, | |
296 | [WM8996_WRITE_SEQUENCER_133] = 0x1, | |
297 | [WM8996_WRITE_SEQUENCER_134] = 0xf, | |
298 | [WM8996_WRITE_SEQUENCER_135] = 0x6, | |
299 | [WM8996_WRITE_SEQUENCER_136] = 0x1, | |
300 | [WM8996_WRITE_SEQUENCER_137] = 0x3, | |
301 | [WM8996_WRITE_SEQUENCER_138] = 0x106, | |
302 | [WM8996_WRITE_SEQUENCER_140] = 0x61, | |
303 | [WM8996_WRITE_SEQUENCER_141] = 0x11, | |
304 | [WM8996_WRITE_SEQUENCER_142] = 0x401, | |
305 | [WM8996_WRITE_SEQUENCER_144] = 0x50, | |
306 | [WM8996_WRITE_SEQUENCER_145] = 0x3, | |
307 | [WM8996_WRITE_SEQUENCER_146] = 0x102, | |
308 | [WM8996_WRITE_SEQUENCER_148] = 0x51, | |
309 | [WM8996_WRITE_SEQUENCER_149] = 0x3, | |
310 | [WM8996_WRITE_SEQUENCER_150] = 0x106, | |
311 | [WM8996_WRITE_SEQUENCER_151] = 0xa, | |
312 | [WM8996_WRITE_SEQUENCER_152] = 0x61, | |
313 | [WM8996_WRITE_SEQUENCER_153] = 0x3b, | |
314 | [WM8996_WRITE_SEQUENCER_154] = 0x502, | |
315 | [WM8996_WRITE_SEQUENCER_155] = 0x100, | |
316 | [WM8996_WRITE_SEQUENCER_156] = 0x2fff, | |
317 | [WM8996_WRITE_SEQUENCER_160] = 0x2fff, | |
318 | [WM8996_WRITE_SEQUENCER_164] = 0x2fff, | |
319 | [WM8996_WRITE_SEQUENCER_168] = 0x2fff, | |
320 | [WM8996_WRITE_SEQUENCER_172] = 0x2fff, | |
321 | [WM8996_WRITE_SEQUENCER_176] = 0x2fff, | |
322 | [WM8996_WRITE_SEQUENCER_180] = 0x2fff, | |
323 | [WM8996_WRITE_SEQUENCER_184] = 0x2fff, | |
324 | [WM8996_WRITE_SEQUENCER_188] = 0x2fff, | |
325 | [WM8996_WRITE_SEQUENCER_192] = 0x1, | |
326 | [WM8996_WRITE_SEQUENCER_193] = 0x1, | |
327 | [WM8996_WRITE_SEQUENCER_195] = 0x6, | |
328 | [WM8996_WRITE_SEQUENCER_196] = 0x40, | |
329 | [WM8996_WRITE_SEQUENCER_197] = 0x1, | |
330 | [WM8996_WRITE_SEQUENCER_198] = 0xf, | |
331 | [WM8996_WRITE_SEQUENCER_199] = 0x6, | |
332 | [WM8996_WRITE_SEQUENCER_200] = 0x1, | |
333 | [WM8996_WRITE_SEQUENCER_201] = 0x3, | |
334 | [WM8996_WRITE_SEQUENCER_202] = 0x106, | |
335 | [WM8996_WRITE_SEQUENCER_204] = 0x61, | |
336 | [WM8996_WRITE_SEQUENCER_205] = 0x11, | |
337 | [WM8996_WRITE_SEQUENCER_206] = 0x401, | |
338 | [WM8996_WRITE_SEQUENCER_208] = 0x50, | |
339 | [WM8996_WRITE_SEQUENCER_209] = 0x3, | |
340 | [WM8996_WRITE_SEQUENCER_210] = 0x102, | |
341 | [WM8996_WRITE_SEQUENCER_212] = 0x61, | |
342 | [WM8996_WRITE_SEQUENCER_213] = 0x3b, | |
343 | [WM8996_WRITE_SEQUENCER_214] = 0x502, | |
344 | [WM8996_WRITE_SEQUENCER_215] = 0x100, | |
345 | [WM8996_WRITE_SEQUENCER_216] = 0x2fff, | |
346 | [WM8996_WRITE_SEQUENCER_220] = 0x2fff, | |
347 | [WM8996_WRITE_SEQUENCER_224] = 0x2fff, | |
348 | [WM8996_WRITE_SEQUENCER_228] = 0x2fff, | |
349 | [WM8996_WRITE_SEQUENCER_232] = 0x2fff, | |
350 | [WM8996_WRITE_SEQUENCER_236] = 0x2fff, | |
351 | [WM8996_WRITE_SEQUENCER_240] = 0x2fff, | |
352 | [WM8996_WRITE_SEQUENCER_244] = 0x2fff, | |
353 | [WM8996_WRITE_SEQUENCER_248] = 0x2fff, | |
354 | [WM8996_WRITE_SEQUENCER_252] = 0x2fff, | |
355 | [WM8996_WRITE_SEQUENCER_256] = 0x60, | |
356 | [WM8996_WRITE_SEQUENCER_258] = 0x601, | |
357 | [WM8996_WRITE_SEQUENCER_260] = 0x50, | |
358 | [WM8996_WRITE_SEQUENCER_262] = 0x100, | |
359 | [WM8996_WRITE_SEQUENCER_264] = 0x1, | |
360 | [WM8996_WRITE_SEQUENCER_266] = 0x104, | |
361 | [WM8996_WRITE_SEQUENCER_267] = 0x100, | |
362 | [WM8996_WRITE_SEQUENCER_268] = 0x2fff, | |
363 | [WM8996_WRITE_SEQUENCER_272] = 0x2fff, | |
364 | [WM8996_WRITE_SEQUENCER_276] = 0x2fff, | |
365 | [WM8996_WRITE_SEQUENCER_280] = 0x2fff, | |
366 | [WM8996_WRITE_SEQUENCER_284] = 0x2fff, | |
367 | [WM8996_WRITE_SEQUENCER_288] = 0x2fff, | |
368 | [WM8996_WRITE_SEQUENCER_292] = 0x2fff, | |
369 | [WM8996_WRITE_SEQUENCER_296] = 0x2fff, | |
370 | [WM8996_WRITE_SEQUENCER_300] = 0x2fff, | |
371 | [WM8996_WRITE_SEQUENCER_304] = 0x2fff, | |
372 | [WM8996_WRITE_SEQUENCER_308] = 0x2fff, | |
373 | [WM8996_WRITE_SEQUENCER_312] = 0x2fff, | |
374 | [WM8996_WRITE_SEQUENCER_316] = 0x2fff, | |
375 | [WM8996_WRITE_SEQUENCER_320] = 0x61, | |
376 | [WM8996_WRITE_SEQUENCER_322] = 0x601, | |
377 | [WM8996_WRITE_SEQUENCER_324] = 0x50, | |
378 | [WM8996_WRITE_SEQUENCER_326] = 0x102, | |
379 | [WM8996_WRITE_SEQUENCER_328] = 0x1, | |
380 | [WM8996_WRITE_SEQUENCER_330] = 0x106, | |
381 | [WM8996_WRITE_SEQUENCER_331] = 0x100, | |
382 | [WM8996_WRITE_SEQUENCER_332] = 0x2fff, | |
383 | [WM8996_WRITE_SEQUENCER_336] = 0x2fff, | |
384 | [WM8996_WRITE_SEQUENCER_340] = 0x2fff, | |
385 | [WM8996_WRITE_SEQUENCER_344] = 0x2fff, | |
386 | [WM8996_WRITE_SEQUENCER_348] = 0x2fff, | |
387 | [WM8996_WRITE_SEQUENCER_352] = 0x2fff, | |
388 | [WM8996_WRITE_SEQUENCER_356] = 0x2fff, | |
389 | [WM8996_WRITE_SEQUENCER_360] = 0x2fff, | |
390 | [WM8996_WRITE_SEQUENCER_364] = 0x2fff, | |
391 | [WM8996_WRITE_SEQUENCER_368] = 0x2fff, | |
392 | [WM8996_WRITE_SEQUENCER_372] = 0x2fff, | |
393 | [WM8996_WRITE_SEQUENCER_376] = 0x2fff, | |
394 | [WM8996_WRITE_SEQUENCER_380] = 0x2fff, | |
395 | [WM8996_WRITE_SEQUENCER_384] = 0x60, | |
396 | [WM8996_WRITE_SEQUENCER_386] = 0x601, | |
397 | [WM8996_WRITE_SEQUENCER_388] = 0x61, | |
398 | [WM8996_WRITE_SEQUENCER_390] = 0x601, | |
399 | [WM8996_WRITE_SEQUENCER_392] = 0x50, | |
400 | [WM8996_WRITE_SEQUENCER_394] = 0x300, | |
401 | [WM8996_WRITE_SEQUENCER_396] = 0x1, | |
402 | [WM8996_WRITE_SEQUENCER_398] = 0x304, | |
403 | [WM8996_WRITE_SEQUENCER_400] = 0x40, | |
404 | [WM8996_WRITE_SEQUENCER_402] = 0xf, | |
405 | [WM8996_WRITE_SEQUENCER_404] = 0x1, | |
406 | [WM8996_WRITE_SEQUENCER_407] = 0x100, | |
407 | }; | |
408 | ||
409 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); | |
410 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); | |
411 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
412 | static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); | |
413 | static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); | |
414 | static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); | |
415 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
18a4eef3 | 416 | static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1); |
a9ba6151 MB |
417 | |
418 | static const char *sidetone_hpf_text[] = { | |
419 | "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" | |
420 | }; | |
421 | ||
422 | static const struct soc_enum sidetone_hpf = | |
18036b58 | 423 | SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text); |
a9ba6151 MB |
424 | |
425 | static const char *hpf_mode_text[] = { | |
426 | "HiFi", "Custom", "Voice" | |
427 | }; | |
428 | ||
429 | static const struct soc_enum dsp1tx_hpf_mode = | |
430 | SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text); | |
431 | ||
432 | static const struct soc_enum dsp2tx_hpf_mode = | |
433 | SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text); | |
434 | ||
435 | static const char *hpf_cutoff_text[] = { | |
436 | "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" | |
437 | }; | |
438 | ||
439 | static const struct soc_enum dsp1tx_hpf_cutoff = | |
440 | SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text); | |
441 | ||
442 | static const struct soc_enum dsp2tx_hpf_cutoff = | |
443 | SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text); | |
444 | ||
445 | static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block) | |
446 | { | |
447 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
448 | struct wm8996_pdata *pdata = &wm8996->pdata; | |
449 | int base, best, best_val, save, i, cfg, iface; | |
450 | ||
451 | if (!wm8996->num_retune_mobile_texts) | |
452 | return; | |
453 | ||
454 | switch (block) { | |
455 | case 0: | |
456 | base = WM8996_DSP1_RX_EQ_GAINS_1; | |
457 | if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & | |
458 | WM8996_DSP1RX_SRC) | |
459 | iface = 1; | |
460 | else | |
461 | iface = 0; | |
462 | break; | |
463 | case 1: | |
464 | base = WM8996_DSP1_RX_EQ_GAINS_2; | |
465 | if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & | |
466 | WM8996_DSP2RX_SRC) | |
467 | iface = 1; | |
468 | else | |
469 | iface = 0; | |
470 | break; | |
471 | default: | |
472 | return; | |
473 | } | |
474 | ||
475 | /* Find the version of the currently selected configuration | |
476 | * with the nearest sample rate. */ | |
477 | cfg = wm8996->retune_mobile_cfg[block]; | |
478 | best = 0; | |
479 | best_val = INT_MAX; | |
480 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
481 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
482 | wm8996->retune_mobile_texts[cfg]) == 0 && | |
483 | abs(pdata->retune_mobile_cfgs[i].rate | |
484 | - wm8996->rx_rate[iface]) < best_val) { | |
485 | best = i; | |
486 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
487 | - wm8996->rx_rate[iface]); | |
488 | } | |
489 | } | |
490 | ||
491 | dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", | |
492 | block, | |
493 | pdata->retune_mobile_cfgs[best].name, | |
494 | pdata->retune_mobile_cfgs[best].rate, | |
495 | wm8996->rx_rate[iface]); | |
496 | ||
497 | /* The EQ will be disabled while reconfiguring it, remember the | |
498 | * current configuration. | |
499 | */ | |
500 | save = snd_soc_read(codec, base); | |
501 | save &= WM8996_DSP1RX_EQ_ENA; | |
502 | ||
503 | for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) | |
504 | snd_soc_update_bits(codec, base + i, 0xffff, | |
505 | pdata->retune_mobile_cfgs[best].regs[i]); | |
506 | ||
507 | snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save); | |
508 | } | |
509 | ||
510 | /* Icky as hell but saves code duplication */ | |
511 | static int wm8996_get_retune_mobile_block(const char *name) | |
512 | { | |
513 | if (strcmp(name, "DSP1 EQ Mode") == 0) | |
514 | return 0; | |
515 | if (strcmp(name, "DSP2 EQ Mode") == 0) | |
516 | return 1; | |
517 | return -EINVAL; | |
518 | } | |
519 | ||
520 | static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
521 | struct snd_ctl_elem_value *ucontrol) | |
522 | { | |
523 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
524 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
525 | struct wm8996_pdata *pdata = &wm8996->pdata; | |
526 | int block = wm8996_get_retune_mobile_block(kcontrol->id.name); | |
527 | int value = ucontrol->value.integer.value[0]; | |
528 | ||
529 | if (block < 0) | |
530 | return block; | |
531 | ||
532 | if (value >= pdata->num_retune_mobile_cfgs) | |
533 | return -EINVAL; | |
534 | ||
535 | wm8996->retune_mobile_cfg[block] = value; | |
536 | ||
537 | wm8996_set_retune_mobile(codec, block); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
543 | struct snd_ctl_elem_value *ucontrol) | |
544 | { | |
545 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
546 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
547 | int block = wm8996_get_retune_mobile_block(kcontrol->id.name); | |
548 | ||
549 | ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block]; | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | static const struct snd_kcontrol_new wm8996_snd_controls[] = { | |
555 | SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME, | |
556 | WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), | |
557 | SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME, | |
558 | WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), | |
559 | ||
560 | SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES, | |
561 | 0, 5, 24, 0, sidetone_tlv), | |
562 | SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES, | |
563 | 0, 5, 24, 0, sidetone_tlv), | |
564 | SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0), | |
565 | SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), | |
566 | SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0), | |
567 | ||
568 | SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME, | |
569 | WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
570 | SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME, | |
571 | WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
572 | ||
573 | SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS, | |
574 | 13, 1, 0), | |
575 | SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0), | |
576 | SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), | |
577 | SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), | |
578 | ||
579 | SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS, | |
580 | 13, 1, 0), | |
581 | SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0), | |
582 | SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), | |
583 | SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), | |
584 | ||
585 | SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME, | |
586 | WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), | |
587 | SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1), | |
588 | ||
589 | SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME, | |
590 | WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), | |
591 | SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1), | |
592 | ||
593 | SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME, | |
594 | WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), | |
595 | SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME, | |
596 | WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1), | |
597 | ||
598 | SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME, | |
599 | WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), | |
600 | SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME, | |
601 | WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1), | |
602 | ||
603 | SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0), | |
604 | SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0), | |
605 | SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0), | |
606 | SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0), | |
607 | ||
608 | SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0), | |
609 | SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0), | |
610 | ||
18a4eef3 | 611 | SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0), |
612 | SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0), | |
613 | ||
614 | SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15, | |
615 | 0, threedstereo_tlv), | |
616 | SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15, | |
617 | 0, threedstereo_tlv), | |
618 | ||
a9ba6151 MB |
619 | SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4, |
620 | 8, 0, out_digital_tlv), | |
621 | SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4, | |
622 | 8, 0, out_digital_tlv), | |
623 | ||
624 | SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME, | |
625 | WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), | |
626 | SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME, | |
627 | WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), | |
628 | ||
629 | SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME, | |
630 | WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), | |
631 | SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME, | |
632 | WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), | |
633 | ||
634 | SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, | |
635 | spk_tlv), | |
636 | SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER, | |
637 | WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1), | |
638 | SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER, | |
639 | WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0), | |
640 | ||
641 | SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0), | |
642 | SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0), | |
643 | }; | |
644 | ||
645 | static const struct snd_kcontrol_new wm8996_eq_controls[] = { | |
646 | SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0, | |
647 | eq_tlv), | |
648 | SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0, | |
649 | eq_tlv), | |
650 | SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0, | |
651 | eq_tlv), | |
652 | SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0, | |
653 | eq_tlv), | |
654 | SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0, | |
655 | eq_tlv), | |
656 | ||
657 | SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0, | |
658 | eq_tlv), | |
659 | SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0, | |
660 | eq_tlv), | |
661 | SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0, | |
662 | eq_tlv), | |
663 | SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0, | |
664 | eq_tlv), | |
665 | SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0, | |
666 | eq_tlv), | |
667 | }; | |
668 | ||
669 | static int cp_event(struct snd_soc_dapm_widget *w, | |
670 | struct snd_kcontrol *kcontrol, int event) | |
671 | { | |
c83495af MB |
672 | struct snd_soc_codec *codec = w->codec; |
673 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
674 | int ret = 0; | |
675 | ||
a9ba6151 | 676 | switch (event) { |
c83495af MB |
677 | case SND_SOC_DAPM_PRE_PMU: |
678 | ret = regulator_enable(wm8996->cpvdd); | |
679 | if (ret != 0) | |
680 | dev_err(codec->dev, "Failed to enable CPVDD: %d\n", | |
681 | ret); | |
682 | break; | |
a9ba6151 MB |
683 | case SND_SOC_DAPM_POST_PMU: |
684 | msleep(5); | |
685 | break; | |
c83495af MB |
686 | case SND_SOC_DAPM_POST_PMD: |
687 | regulator_disable_deferred(wm8996->cpvdd, 20); | |
688 | break; | |
a9ba6151 MB |
689 | default: |
690 | BUG(); | |
c83495af | 691 | ret = -EINVAL; |
a9ba6151 MB |
692 | } |
693 | ||
c83495af | 694 | return ret; |
a9ba6151 MB |
695 | } |
696 | ||
697 | static int rmv_short_event(struct snd_soc_dapm_widget *w, | |
698 | struct snd_kcontrol *kcontrol, int event) | |
699 | { | |
700 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); | |
701 | ||
702 | /* Record which outputs we enabled */ | |
703 | switch (event) { | |
704 | case SND_SOC_DAPM_PRE_PMD: | |
705 | wm8996->hpout_pending &= ~w->shift; | |
706 | break; | |
707 | case SND_SOC_DAPM_PRE_PMU: | |
708 | wm8996->hpout_pending |= w->shift; | |
709 | break; | |
710 | default: | |
711 | BUG(); | |
712 | return -EINVAL; | |
713 | } | |
714 | ||
715 | return 0; | |
716 | } | |
717 | ||
718 | static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask) | |
719 | { | |
720 | struct i2c_client *i2c = to_i2c_client(codec->dev); | |
721 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
722 | int i, ret; | |
723 | unsigned long timeout = 200; | |
724 | ||
725 | snd_soc_write(codec, WM8996_DC_SERVO_2, mask); | |
726 | ||
727 | /* Use the interrupt if possible */ | |
728 | do { | |
729 | if (i2c->irq) { | |
730 | timeout = wait_for_completion_timeout(&wm8996->dcs_done, | |
731 | msecs_to_jiffies(200)); | |
732 | if (timeout == 0) | |
733 | dev_err(codec->dev, "DC servo timed out\n"); | |
734 | ||
735 | } else { | |
736 | msleep(1); | |
737 | if (--i) { | |
738 | timeout = 0; | |
739 | break; | |
740 | } | |
741 | } | |
742 | ||
743 | ret = snd_soc_read(codec, WM8996_DC_SERVO_2); | |
744 | dev_dbg(codec->dev, "DC servo state: %x\n", ret); | |
745 | } while (ret & mask); | |
746 | ||
747 | if (timeout == 0) | |
748 | dev_err(codec->dev, "DC servo timed out for %x\n", mask); | |
749 | else | |
750 | dev_dbg(codec->dev, "DC servo complete for %x\n", mask); | |
751 | } | |
752 | ||
753 | static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm, | |
754 | enum snd_soc_dapm_type event, int subseq) | |
755 | { | |
756 | struct snd_soc_codec *codec = container_of(dapm, | |
757 | struct snd_soc_codec, dapm); | |
758 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
759 | u16 val, mask; | |
760 | ||
761 | /* Complete any pending DC servo starts */ | |
762 | if (wm8996->dcs_pending) { | |
763 | dev_dbg(codec->dev, "Starting DC servo for %x\n", | |
764 | wm8996->dcs_pending); | |
765 | ||
766 | /* Trigger a startup sequence */ | |
767 | wait_for_dc_servo(codec, wm8996->dcs_pending | |
768 | << WM8996_DCS_TRIG_STARTUP_0_SHIFT); | |
769 | ||
770 | wm8996->dcs_pending = 0; | |
771 | } | |
772 | ||
773 | if (wm8996->hpout_pending != wm8996->hpout_ena) { | |
774 | dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n", | |
775 | wm8996->hpout_ena, wm8996->hpout_pending); | |
776 | ||
777 | val = 0; | |
778 | mask = 0; | |
779 | if (wm8996->hpout_pending & HPOUT1L) { | |
780 | val |= WM8996_HPOUT1L_RMV_SHORT; | |
781 | mask |= WM8996_HPOUT1L_RMV_SHORT; | |
782 | } else { | |
783 | mask |= WM8996_HPOUT1L_RMV_SHORT | | |
784 | WM8996_HPOUT1L_OUTP | | |
785 | WM8996_HPOUT1L_DLY; | |
786 | } | |
787 | ||
788 | if (wm8996->hpout_pending & HPOUT1R) { | |
789 | val |= WM8996_HPOUT1R_RMV_SHORT; | |
790 | mask |= WM8996_HPOUT1R_RMV_SHORT; | |
791 | } else { | |
792 | mask |= WM8996_HPOUT1R_RMV_SHORT | | |
793 | WM8996_HPOUT1R_OUTP | | |
794 | WM8996_HPOUT1R_DLY; | |
795 | } | |
796 | ||
797 | snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val); | |
798 | ||
799 | val = 0; | |
800 | mask = 0; | |
801 | if (wm8996->hpout_pending & HPOUT2L) { | |
802 | val |= WM8996_HPOUT2L_RMV_SHORT; | |
803 | mask |= WM8996_HPOUT2L_RMV_SHORT; | |
804 | } else { | |
805 | mask |= WM8996_HPOUT2L_RMV_SHORT | | |
806 | WM8996_HPOUT2L_OUTP | | |
807 | WM8996_HPOUT2L_DLY; | |
808 | } | |
809 | ||
810 | if (wm8996->hpout_pending & HPOUT2R) { | |
811 | val |= WM8996_HPOUT2R_RMV_SHORT; | |
812 | mask |= WM8996_HPOUT2R_RMV_SHORT; | |
813 | } else { | |
814 | mask |= WM8996_HPOUT2R_RMV_SHORT | | |
815 | WM8996_HPOUT2R_OUTP | | |
816 | WM8996_HPOUT2R_DLY; | |
817 | } | |
818 | ||
819 | snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val); | |
820 | ||
821 | wm8996->hpout_ena = wm8996->hpout_pending; | |
822 | } | |
823 | } | |
824 | ||
825 | static int dcs_start(struct snd_soc_dapm_widget *w, | |
826 | struct snd_kcontrol *kcontrol, int event) | |
827 | { | |
828 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); | |
829 | ||
830 | switch (event) { | |
831 | case SND_SOC_DAPM_POST_PMU: | |
832 | wm8996->dcs_pending |= 1 << w->shift; | |
833 | break; | |
834 | default: | |
835 | BUG(); | |
836 | return -EINVAL; | |
837 | } | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
842 | static const char *sidetone_text[] = { | |
843 | "IN1", "IN2", | |
844 | }; | |
845 | ||
846 | static const struct soc_enum left_sidetone_enum = | |
847 | SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text); | |
848 | ||
849 | static const struct snd_kcontrol_new left_sidetone = | |
850 | SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); | |
851 | ||
852 | static const struct soc_enum right_sidetone_enum = | |
853 | SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text); | |
854 | ||
855 | static const struct snd_kcontrol_new right_sidetone = | |
856 | SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); | |
857 | ||
858 | static const char *spk_text[] = { | |
859 | "DAC1L", "DAC1R", "DAC2L", "DAC2R" | |
860 | }; | |
861 | ||
862 | static const struct soc_enum spkl_enum = | |
863 | SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text); | |
864 | ||
865 | static const struct snd_kcontrol_new spkl_mux = | |
866 | SOC_DAPM_ENUM("SPKL", spkl_enum); | |
867 | ||
868 | static const struct soc_enum spkr_enum = | |
869 | SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text); | |
870 | ||
871 | static const struct snd_kcontrol_new spkr_mux = | |
872 | SOC_DAPM_ENUM("SPKR", spkr_enum); | |
873 | ||
874 | static const char *dsp1rx_text[] = { | |
875 | "AIF1", "AIF2" | |
876 | }; | |
877 | ||
878 | static const struct soc_enum dsp1rx_enum = | |
879 | SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text); | |
880 | ||
881 | static const struct snd_kcontrol_new dsp1rx = | |
882 | SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); | |
883 | ||
884 | static const char *dsp2rx_text[] = { | |
885 | "AIF2", "AIF1" | |
886 | }; | |
887 | ||
888 | static const struct soc_enum dsp2rx_enum = | |
889 | SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text); | |
890 | ||
891 | static const struct snd_kcontrol_new dsp2rx = | |
892 | SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); | |
893 | ||
894 | static const char *aif2tx_text[] = { | |
895 | "DSP2", "DSP1", "AIF1" | |
896 | }; | |
897 | ||
898 | static const struct soc_enum aif2tx_enum = | |
899 | SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text); | |
900 | ||
901 | static const struct snd_kcontrol_new aif2tx = | |
902 | SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); | |
903 | ||
904 | static const char *inmux_text[] = { | |
905 | "ADC", "DMIC1", "DMIC2" | |
906 | }; | |
907 | ||
908 | static const struct soc_enum in1_enum = | |
909 | SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text); | |
910 | ||
911 | static const struct snd_kcontrol_new in1_mux = | |
912 | SOC_DAPM_ENUM("IN1 Mux", in1_enum); | |
913 | ||
914 | static const struct soc_enum in2_enum = | |
915 | SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text); | |
916 | ||
917 | static const struct snd_kcontrol_new in2_mux = | |
918 | SOC_DAPM_ENUM("IN2 Mux", in2_enum); | |
919 | ||
920 | static const struct snd_kcontrol_new dac2r_mix[] = { | |
921 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, | |
922 | 5, 1, 0), | |
923 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, | |
924 | 4, 1, 0), | |
925 | SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), | |
926 | SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), | |
927 | }; | |
928 | ||
929 | static const struct snd_kcontrol_new dac2l_mix[] = { | |
930 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, | |
931 | 5, 1, 0), | |
932 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, | |
933 | 4, 1, 0), | |
934 | SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), | |
935 | SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), | |
936 | }; | |
937 | ||
938 | static const struct snd_kcontrol_new dac1r_mix[] = { | |
939 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, | |
940 | 5, 1, 0), | |
941 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, | |
942 | 4, 1, 0), | |
943 | SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), | |
944 | SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), | |
945 | }; | |
946 | ||
947 | static const struct snd_kcontrol_new dac1l_mix[] = { | |
948 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, | |
949 | 5, 1, 0), | |
950 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, | |
951 | 4, 1, 0), | |
952 | SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), | |
953 | SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), | |
954 | }; | |
955 | ||
956 | static const struct snd_kcontrol_new dsp1txl[] = { | |
957 | SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, | |
958 | 1, 1, 0), | |
959 | SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, | |
960 | 0, 1, 0), | |
961 | }; | |
962 | ||
963 | static const struct snd_kcontrol_new dsp1txr[] = { | |
964 | SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, | |
965 | 1, 1, 0), | |
966 | SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, | |
967 | 0, 1, 0), | |
968 | }; | |
969 | ||
970 | static const struct snd_kcontrol_new dsp2txl[] = { | |
971 | SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, | |
972 | 1, 1, 0), | |
973 | SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, | |
974 | 0, 1, 0), | |
975 | }; | |
976 | ||
977 | static const struct snd_kcontrol_new dsp2txr[] = { | |
978 | SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, | |
979 | 1, 1, 0), | |
980 | SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, | |
981 | 0, 1, 0), | |
982 | }; | |
983 | ||
984 | ||
985 | static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = { | |
986 | SND_SOC_DAPM_INPUT("IN1LN"), | |
987 | SND_SOC_DAPM_INPUT("IN1LP"), | |
988 | SND_SOC_DAPM_INPUT("IN1RN"), | |
989 | SND_SOC_DAPM_INPUT("IN1RP"), | |
990 | ||
991 | SND_SOC_DAPM_INPUT("IN2LN"), | |
992 | SND_SOC_DAPM_INPUT("IN2LP"), | |
993 | SND_SOC_DAPM_INPUT("IN2RN"), | |
994 | SND_SOC_DAPM_INPUT("IN2RP"), | |
995 | ||
996 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
997 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
998 | ||
999 | SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0), | |
1000 | SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0), | |
1001 | SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0), | |
1002 | SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event, | |
c83495af MB |
1003 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1004 | SND_SOC_DAPM_POST_PMD), | |
a9ba6151 MB |
1005 | |
1006 | SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0), | |
889c85c5 MB |
1007 | SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0), |
1008 | SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0), | |
a9ba6151 MB |
1009 | SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0), |
1010 | SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0), | |
1011 | ||
1012 | SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0), | |
1013 | SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0), | |
1014 | ||
7691cd74 MB |
1015 | SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux), |
1016 | SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux), | |
1017 | SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux), | |
1018 | SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux), | |
a9ba6151 MB |
1019 | |
1020 | SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0), | |
1021 | SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0), | |
1022 | ||
1023 | SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0), | |
1024 | SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0), | |
1025 | SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0), | |
1026 | SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0), | |
1027 | ||
1028 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0), | |
1029 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0), | |
1030 | ||
1031 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), | |
1032 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), | |
1033 | ||
1034 | SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0), | |
1035 | SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0), | |
1036 | SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0), | |
1037 | SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0), | |
1038 | ||
1039 | SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0, | |
1040 | dsp2txl, ARRAY_SIZE(dsp2txl)), | |
1041 | SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0, | |
1042 | dsp2txr, ARRAY_SIZE(dsp2txr)), | |
1043 | SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0, | |
1044 | dsp1txl, ARRAY_SIZE(dsp1txl)), | |
1045 | SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0, | |
1046 | dsp1txr, ARRAY_SIZE(dsp1txr)), | |
1047 | ||
1048 | SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, | |
1049 | dac2l_mix, ARRAY_SIZE(dac2l_mix)), | |
1050 | SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, | |
1051 | dac2r_mix, ARRAY_SIZE(dac2r_mix)), | |
1052 | SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, | |
1053 | dac1l_mix, ARRAY_SIZE(dac1l_mix)), | |
1054 | SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, | |
1055 | dac1r_mix, ARRAY_SIZE(dac1r_mix)), | |
1056 | ||
1057 | SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0), | |
1058 | SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0), | |
1059 | SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0), | |
1060 | SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0), | |
1061 | ||
1062 | SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1, | |
1063 | WM8996_POWER_MANAGEMENT_4, 9, 0), | |
1064 | SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2, | |
1065 | WM8996_POWER_MANAGEMENT_4, 8, 0), | |
1066 | ||
1067 | SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1, | |
1068 | WM8996_POWER_MANAGEMENT_6, 9, 0), | |
1069 | SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2, | |
1070 | WM8996_POWER_MANAGEMENT_6, 8, 0), | |
1071 | ||
1072 | SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5, | |
1073 | WM8996_POWER_MANAGEMENT_4, 5, 0), | |
1074 | SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4, | |
1075 | WM8996_POWER_MANAGEMENT_4, 4, 0), | |
1076 | SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3, | |
1077 | WM8996_POWER_MANAGEMENT_4, 3, 0), | |
1078 | SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2, | |
1079 | WM8996_POWER_MANAGEMENT_4, 2, 0), | |
1080 | SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1, | |
1081 | WM8996_POWER_MANAGEMENT_4, 1, 0), | |
1082 | SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0, | |
1083 | WM8996_POWER_MANAGEMENT_4, 0, 0), | |
1084 | ||
1085 | SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5, | |
1086 | WM8996_POWER_MANAGEMENT_6, 5, 0), | |
1087 | SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4, | |
1088 | WM8996_POWER_MANAGEMENT_6, 4, 0), | |
1089 | SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3, | |
1090 | WM8996_POWER_MANAGEMENT_6, 3, 0), | |
1091 | SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2, | |
1092 | WM8996_POWER_MANAGEMENT_6, 2, 0), | |
1093 | SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1, | |
1094 | WM8996_POWER_MANAGEMENT_6, 1, 0), | |
1095 | SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0, | |
1096 | WM8996_POWER_MANAGEMENT_6, 0, 0), | |
1097 | ||
1098 | /* We route as stereo pairs so define some dummy widgets to squash | |
1099 | * things down for now. RXA = 0,1, RXB = 2,3 and so on */ | |
1100 | SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1101 | SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1102 | SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1103 | SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1104 | SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1105 | ||
1106 | SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), | |
1107 | SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), | |
1108 | SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), | |
1109 | ||
1110 | SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), | |
1111 | SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), | |
1112 | SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), | |
1113 | SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), | |
1114 | ||
1115 | SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0), | |
1116 | SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0), | |
1117 | SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start, | |
1118 | SND_SOC_DAPM_POST_PMU), | |
1119 | SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0), | |
1120 | SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, | |
1121 | rmv_short_event, | |
1122 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1123 | ||
1124 | SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0), | |
1125 | SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0), | |
1126 | SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start, | |
1127 | SND_SOC_DAPM_POST_PMU), | |
1128 | SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0), | |
1129 | SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, | |
1130 | rmv_short_event, | |
1131 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1132 | ||
1133 | SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0), | |
1134 | SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0), | |
1135 | SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start, | |
1136 | SND_SOC_DAPM_POST_PMU), | |
1137 | SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0), | |
1138 | SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, | |
1139 | rmv_short_event, | |
1140 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1141 | ||
1142 | SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0), | |
1143 | SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0), | |
1144 | SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start, | |
1145 | SND_SOC_DAPM_POST_PMU), | |
1146 | SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0), | |
1147 | SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, | |
1148 | rmv_short_event, | |
1149 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1150 | ||
1151 | SND_SOC_DAPM_OUTPUT("HPOUT1L"), | |
1152 | SND_SOC_DAPM_OUTPUT("HPOUT1R"), | |
1153 | SND_SOC_DAPM_OUTPUT("HPOUT2L"), | |
1154 | SND_SOC_DAPM_OUTPUT("HPOUT2R"), | |
1155 | SND_SOC_DAPM_OUTPUT("SPKDAT"), | |
1156 | }; | |
1157 | ||
1158 | static const struct snd_soc_dapm_route wm8996_dapm_routes[] = { | |
1159 | { "AIFCLK", NULL, "SYSCLK" }, | |
1160 | { "SYSDSPCLK", NULL, "SYSCLK" }, | |
1161 | { "Charge Pump", NULL, "SYSCLK" }, | |
1162 | ||
1163 | { "MICB1", NULL, "LDO2" }, | |
889c85c5 | 1164 | { "MICB1", NULL, "MICB1 Audio" }, |
a9ba6151 | 1165 | { "MICB2", NULL, "LDO2" }, |
889c85c5 | 1166 | { "MICB2", NULL, "MICB2 Audio" }, |
a9ba6151 MB |
1167 | |
1168 | { "IN1L PGA", NULL, "IN2LN" }, | |
1169 | { "IN1L PGA", NULL, "IN2LP" }, | |
1170 | { "IN1L PGA", NULL, "IN1LN" }, | |
1171 | { "IN1L PGA", NULL, "IN1LP" }, | |
1172 | ||
1173 | { "IN1R PGA", NULL, "IN2RN" }, | |
1174 | { "IN1R PGA", NULL, "IN2RP" }, | |
1175 | { "IN1R PGA", NULL, "IN1RN" }, | |
1176 | { "IN1R PGA", NULL, "IN1RP" }, | |
1177 | ||
1178 | { "ADCL", NULL, "IN1L PGA" }, | |
1179 | ||
1180 | { "ADCR", NULL, "IN1R PGA" }, | |
1181 | ||
1182 | { "DMIC1L", NULL, "DMIC1DAT" }, | |
1183 | { "DMIC1R", NULL, "DMIC1DAT" }, | |
1184 | { "DMIC2L", NULL, "DMIC2DAT" }, | |
1185 | { "DMIC2R", NULL, "DMIC2DAT" }, | |
1186 | ||
1187 | { "DMIC2L", NULL, "DMIC2" }, | |
1188 | { "DMIC2R", NULL, "DMIC2" }, | |
1189 | { "DMIC1L", NULL, "DMIC1" }, | |
1190 | { "DMIC1R", NULL, "DMIC1" }, | |
1191 | ||
1192 | { "IN1L Mux", "ADC", "ADCL" }, | |
1193 | { "IN1L Mux", "DMIC1", "DMIC1L" }, | |
1194 | { "IN1L Mux", "DMIC2", "DMIC2L" }, | |
1195 | ||
1196 | { "IN1R Mux", "ADC", "ADCR" }, | |
1197 | { "IN1R Mux", "DMIC1", "DMIC1R" }, | |
1198 | { "IN1R Mux", "DMIC2", "DMIC2R" }, | |
1199 | ||
1200 | { "IN2L Mux", "ADC", "ADCL" }, | |
1201 | { "IN2L Mux", "DMIC1", "DMIC1L" }, | |
1202 | { "IN2L Mux", "DMIC2", "DMIC2L" }, | |
1203 | ||
1204 | { "IN2R Mux", "ADC", "ADCR" }, | |
1205 | { "IN2R Mux", "DMIC1", "DMIC1R" }, | |
1206 | { "IN2R Mux", "DMIC2", "DMIC2R" }, | |
1207 | ||
1208 | { "Left Sidetone", "IN1", "IN1L Mux" }, | |
1209 | { "Left Sidetone", "IN2", "IN2L Mux" }, | |
1210 | ||
1211 | { "Right Sidetone", "IN1", "IN1R Mux" }, | |
1212 | { "Right Sidetone", "IN2", "IN2R Mux" }, | |
1213 | ||
1214 | { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, | |
1215 | { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, | |
1216 | ||
1217 | { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, | |
1218 | { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, | |
1219 | ||
1220 | { "AIF1TX0", NULL, "DSP1TXL" }, | |
1221 | { "AIF1TX1", NULL, "DSP1TXR" }, | |
1222 | { "AIF1TX2", NULL, "DSP2TXL" }, | |
1223 | { "AIF1TX3", NULL, "DSP2TXR" }, | |
1224 | { "AIF1TX4", NULL, "AIF2RX0" }, | |
1225 | { "AIF1TX5", NULL, "AIF2RX1" }, | |
1226 | ||
1227 | { "AIF1RX0", NULL, "AIFCLK" }, | |
1228 | { "AIF1RX1", NULL, "AIFCLK" }, | |
1229 | { "AIF1RX2", NULL, "AIFCLK" }, | |
1230 | { "AIF1RX3", NULL, "AIFCLK" }, | |
1231 | { "AIF1RX4", NULL, "AIFCLK" }, | |
1232 | { "AIF1RX5", NULL, "AIFCLK" }, | |
1233 | ||
1234 | { "AIF2RX0", NULL, "AIFCLK" }, | |
1235 | { "AIF2RX1", NULL, "AIFCLK" }, | |
1236 | ||
4f41adfd MB |
1237 | { "AIF1TX0", NULL, "AIFCLK" }, |
1238 | { "AIF1TX1", NULL, "AIFCLK" }, | |
1239 | { "AIF1TX2", NULL, "AIFCLK" }, | |
1240 | { "AIF1TX3", NULL, "AIFCLK" }, | |
1241 | { "AIF1TX4", NULL, "AIFCLK" }, | |
1242 | { "AIF1TX5", NULL, "AIFCLK" }, | |
1243 | ||
1244 | { "AIF2TX0", NULL, "AIFCLK" }, | |
1245 | { "AIF2TX1", NULL, "AIFCLK" }, | |
1246 | ||
a9ba6151 MB |
1247 | { "DSP1RXL", NULL, "SYSDSPCLK" }, |
1248 | { "DSP1RXR", NULL, "SYSDSPCLK" }, | |
1249 | { "DSP2RXL", NULL, "SYSDSPCLK" }, | |
1250 | { "DSP2RXR", NULL, "SYSDSPCLK" }, | |
1251 | { "DSP1TXL", NULL, "SYSDSPCLK" }, | |
1252 | { "DSP1TXR", NULL, "SYSDSPCLK" }, | |
1253 | { "DSP2TXL", NULL, "SYSDSPCLK" }, | |
1254 | { "DSP2TXR", NULL, "SYSDSPCLK" }, | |
1255 | ||
1256 | { "AIF1RXA", NULL, "AIF1RX0" }, | |
1257 | { "AIF1RXA", NULL, "AIF1RX1" }, | |
1258 | { "AIF1RXB", NULL, "AIF1RX2" }, | |
1259 | { "AIF1RXB", NULL, "AIF1RX3" }, | |
1260 | { "AIF1RXC", NULL, "AIF1RX4" }, | |
1261 | { "AIF1RXC", NULL, "AIF1RX5" }, | |
1262 | ||
1263 | { "AIF2RX", NULL, "AIF2RX0" }, | |
1264 | { "AIF2RX", NULL, "AIF2RX1" }, | |
1265 | ||
1266 | { "AIF2TX", "DSP2", "DSP2TX" }, | |
1267 | { "AIF2TX", "DSP1", "DSP1RX" }, | |
1268 | { "AIF2TX", "AIF1", "AIF1RXC" }, | |
1269 | ||
1270 | { "DSP1RXL", NULL, "DSP1RX" }, | |
1271 | { "DSP1RXR", NULL, "DSP1RX" }, | |
1272 | { "DSP2RXL", NULL, "DSP2RX" }, | |
1273 | { "DSP2RXR", NULL, "DSP2RX" }, | |
1274 | ||
1275 | { "DSP2TX", NULL, "DSP2TXL" }, | |
1276 | { "DSP2TX", NULL, "DSP2TXR" }, | |
1277 | ||
1278 | { "DSP1RX", "AIF1", "AIF1RXA" }, | |
1279 | { "DSP1RX", "AIF2", "AIF2RX" }, | |
1280 | ||
1281 | { "DSP2RX", "AIF1", "AIF1RXB" }, | |
1282 | { "DSP2RX", "AIF2", "AIF2RX" }, | |
1283 | ||
1284 | { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, | |
1285 | { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, | |
1286 | { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1287 | { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1288 | ||
1289 | { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, | |
1290 | { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, | |
1291 | { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1292 | { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1293 | ||
1294 | { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, | |
1295 | { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, | |
1296 | { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1297 | { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1298 | ||
1299 | { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, | |
1300 | { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, | |
1301 | { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1302 | { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1303 | ||
1304 | { "DAC1L", NULL, "DAC1L Mixer" }, | |
1305 | { "DAC1R", NULL, "DAC1R Mixer" }, | |
1306 | { "DAC2L", NULL, "DAC2L Mixer" }, | |
1307 | { "DAC2R", NULL, "DAC2R Mixer" }, | |
1308 | ||
1309 | { "HPOUT2L PGA", NULL, "Charge Pump" }, | |
1310 | { "HPOUT2L PGA", NULL, "DAC2L" }, | |
1311 | { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, | |
1312 | { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, | |
1313 | { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" }, | |
1314 | { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" }, | |
1315 | ||
1316 | { "HPOUT2R PGA", NULL, "Charge Pump" }, | |
1317 | { "HPOUT2R PGA", NULL, "DAC2R" }, | |
1318 | { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, | |
1319 | { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, | |
1320 | { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" }, | |
1321 | { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" }, | |
1322 | ||
1323 | { "HPOUT1L PGA", NULL, "Charge Pump" }, | |
1324 | { "HPOUT1L PGA", NULL, "DAC1L" }, | |
1325 | { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, | |
1326 | { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, | |
1327 | { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" }, | |
1328 | { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" }, | |
1329 | ||
1330 | { "HPOUT1R PGA", NULL, "Charge Pump" }, | |
1331 | { "HPOUT1R PGA", NULL, "DAC1R" }, | |
1332 | { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, | |
1333 | { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, | |
1334 | { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" }, | |
1335 | { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" }, | |
1336 | ||
1337 | { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, | |
1338 | { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, | |
1339 | { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, | |
1340 | { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, | |
1341 | ||
1342 | { "SPKL", "DAC1L", "DAC1L" }, | |
1343 | { "SPKL", "DAC1R", "DAC1R" }, | |
1344 | { "SPKL", "DAC2L", "DAC2L" }, | |
1345 | { "SPKL", "DAC2R", "DAC2R" }, | |
1346 | ||
1347 | { "SPKR", "DAC1L", "DAC1L" }, | |
1348 | { "SPKR", "DAC1R", "DAC1R" }, | |
1349 | { "SPKR", "DAC2L", "DAC2L" }, | |
1350 | { "SPKR", "DAC2R", "DAC2R" }, | |
1351 | ||
1352 | { "SPKL PGA", NULL, "SPKL" }, | |
1353 | { "SPKR PGA", NULL, "SPKR" }, | |
1354 | ||
1355 | { "SPKDAT", NULL, "SPKL PGA" }, | |
1356 | { "SPKDAT", NULL, "SPKR PGA" }, | |
1357 | }; | |
1358 | ||
1359 | static int wm8996_readable_register(struct snd_soc_codec *codec, | |
1360 | unsigned int reg) | |
1361 | { | |
1362 | /* Due to the sparseness of the register map the compiler | |
1363 | * output from an explicit switch statement ends up being much | |
1364 | * more efficient than a table. | |
1365 | */ | |
1366 | switch (reg) { | |
1367 | case WM8996_SOFTWARE_RESET: | |
1368 | case WM8996_POWER_MANAGEMENT_1: | |
1369 | case WM8996_POWER_MANAGEMENT_2: | |
1370 | case WM8996_POWER_MANAGEMENT_3: | |
1371 | case WM8996_POWER_MANAGEMENT_4: | |
1372 | case WM8996_POWER_MANAGEMENT_5: | |
1373 | case WM8996_POWER_MANAGEMENT_6: | |
1374 | case WM8996_POWER_MANAGEMENT_7: | |
1375 | case WM8996_POWER_MANAGEMENT_8: | |
1376 | case WM8996_LEFT_LINE_INPUT_VOLUME: | |
1377 | case WM8996_RIGHT_LINE_INPUT_VOLUME: | |
1378 | case WM8996_LINE_INPUT_CONTROL: | |
1379 | case WM8996_DAC1_HPOUT1_VOLUME: | |
1380 | case WM8996_DAC2_HPOUT2_VOLUME: | |
1381 | case WM8996_DAC1_LEFT_VOLUME: | |
1382 | case WM8996_DAC1_RIGHT_VOLUME: | |
1383 | case WM8996_DAC2_LEFT_VOLUME: | |
1384 | case WM8996_DAC2_RIGHT_VOLUME: | |
1385 | case WM8996_OUTPUT1_LEFT_VOLUME: | |
1386 | case WM8996_OUTPUT1_RIGHT_VOLUME: | |
1387 | case WM8996_OUTPUT2_LEFT_VOLUME: | |
1388 | case WM8996_OUTPUT2_RIGHT_VOLUME: | |
1389 | case WM8996_MICBIAS_1: | |
1390 | case WM8996_MICBIAS_2: | |
1391 | case WM8996_LDO_1: | |
1392 | case WM8996_LDO_2: | |
1393 | case WM8996_ACCESSORY_DETECT_MODE_1: | |
1394 | case WM8996_ACCESSORY_DETECT_MODE_2: | |
1395 | case WM8996_HEADPHONE_DETECT_1: | |
1396 | case WM8996_HEADPHONE_DETECT_2: | |
1397 | case WM8996_MIC_DETECT_1: | |
1398 | case WM8996_MIC_DETECT_2: | |
1399 | case WM8996_MIC_DETECT_3: | |
1400 | case WM8996_CHARGE_PUMP_1: | |
1401 | case WM8996_CHARGE_PUMP_2: | |
1402 | case WM8996_DC_SERVO_1: | |
1403 | case WM8996_DC_SERVO_2: | |
1404 | case WM8996_DC_SERVO_3: | |
1405 | case WM8996_DC_SERVO_5: | |
1406 | case WM8996_DC_SERVO_6: | |
1407 | case WM8996_DC_SERVO_7: | |
1408 | case WM8996_DC_SERVO_READBACK_0: | |
1409 | case WM8996_ANALOGUE_HP_1: | |
1410 | case WM8996_ANALOGUE_HP_2: | |
1411 | case WM8996_CHIP_REVISION: | |
1412 | case WM8996_CONTROL_INTERFACE_1: | |
1413 | case WM8996_WRITE_SEQUENCER_CTRL_1: | |
1414 | case WM8996_WRITE_SEQUENCER_CTRL_2: | |
1415 | case WM8996_AIF_CLOCKING_1: | |
1416 | case WM8996_AIF_CLOCKING_2: | |
1417 | case WM8996_CLOCKING_1: | |
1418 | case WM8996_CLOCKING_2: | |
1419 | case WM8996_AIF_RATE: | |
1420 | case WM8996_FLL_CONTROL_1: | |
1421 | case WM8996_FLL_CONTROL_2: | |
1422 | case WM8996_FLL_CONTROL_3: | |
1423 | case WM8996_FLL_CONTROL_4: | |
1424 | case WM8996_FLL_CONTROL_5: | |
1425 | case WM8996_FLL_CONTROL_6: | |
1426 | case WM8996_FLL_EFS_1: | |
1427 | case WM8996_FLL_EFS_2: | |
1428 | case WM8996_AIF1_CONTROL: | |
1429 | case WM8996_AIF1_BCLK: | |
1430 | case WM8996_AIF1_TX_LRCLK_1: | |
1431 | case WM8996_AIF1_TX_LRCLK_2: | |
1432 | case WM8996_AIF1_RX_LRCLK_1: | |
1433 | case WM8996_AIF1_RX_LRCLK_2: | |
1434 | case WM8996_AIF1TX_DATA_CONFIGURATION_1: | |
1435 | case WM8996_AIF1TX_DATA_CONFIGURATION_2: | |
1436 | case WM8996_AIF1RX_DATA_CONFIGURATION: | |
1437 | case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION: | |
1438 | case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION: | |
1439 | case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION: | |
1440 | case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION: | |
1441 | case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION: | |
1442 | case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION: | |
1443 | case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION: | |
1444 | case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION: | |
1445 | case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION: | |
1446 | case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION: | |
1447 | case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION: | |
1448 | case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION: | |
1449 | case WM8996_AIF1RX_MONO_CONFIGURATION: | |
1450 | case WM8996_AIF1TX_TEST: | |
1451 | case WM8996_AIF2_CONTROL: | |
1452 | case WM8996_AIF2_BCLK: | |
1453 | case WM8996_AIF2_TX_LRCLK_1: | |
1454 | case WM8996_AIF2_TX_LRCLK_2: | |
1455 | case WM8996_AIF2_RX_LRCLK_1: | |
1456 | case WM8996_AIF2_RX_LRCLK_2: | |
1457 | case WM8996_AIF2TX_DATA_CONFIGURATION_1: | |
1458 | case WM8996_AIF2TX_DATA_CONFIGURATION_2: | |
1459 | case WM8996_AIF2RX_DATA_CONFIGURATION: | |
1460 | case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION: | |
1461 | case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION: | |
1462 | case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION: | |
1463 | case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION: | |
1464 | case WM8996_AIF2RX_MONO_CONFIGURATION: | |
1465 | case WM8996_AIF2TX_TEST: | |
1466 | case WM8996_DSP1_TX_LEFT_VOLUME: | |
1467 | case WM8996_DSP1_TX_RIGHT_VOLUME: | |
1468 | case WM8996_DSP1_RX_LEFT_VOLUME: | |
1469 | case WM8996_DSP1_RX_RIGHT_VOLUME: | |
1470 | case WM8996_DSP1_TX_FILTERS: | |
1471 | case WM8996_DSP1_RX_FILTERS_1: | |
1472 | case WM8996_DSP1_RX_FILTERS_2: | |
1473 | case WM8996_DSP1_DRC_1: | |
1474 | case WM8996_DSP1_DRC_2: | |
1475 | case WM8996_DSP1_DRC_3: | |
1476 | case WM8996_DSP1_DRC_4: | |
1477 | case WM8996_DSP1_DRC_5: | |
1478 | case WM8996_DSP1_RX_EQ_GAINS_1: | |
1479 | case WM8996_DSP1_RX_EQ_GAINS_2: | |
1480 | case WM8996_DSP1_RX_EQ_BAND_1_A: | |
1481 | case WM8996_DSP1_RX_EQ_BAND_1_B: | |
1482 | case WM8996_DSP1_RX_EQ_BAND_1_PG: | |
1483 | case WM8996_DSP1_RX_EQ_BAND_2_A: | |
1484 | case WM8996_DSP1_RX_EQ_BAND_2_B: | |
1485 | case WM8996_DSP1_RX_EQ_BAND_2_C: | |
1486 | case WM8996_DSP1_RX_EQ_BAND_2_PG: | |
1487 | case WM8996_DSP1_RX_EQ_BAND_3_A: | |
1488 | case WM8996_DSP1_RX_EQ_BAND_3_B: | |
1489 | case WM8996_DSP1_RX_EQ_BAND_3_C: | |
1490 | case WM8996_DSP1_RX_EQ_BAND_3_PG: | |
1491 | case WM8996_DSP1_RX_EQ_BAND_4_A: | |
1492 | case WM8996_DSP1_RX_EQ_BAND_4_B: | |
1493 | case WM8996_DSP1_RX_EQ_BAND_4_C: | |
1494 | case WM8996_DSP1_RX_EQ_BAND_4_PG: | |
1495 | case WM8996_DSP1_RX_EQ_BAND_5_A: | |
1496 | case WM8996_DSP1_RX_EQ_BAND_5_B: | |
1497 | case WM8996_DSP1_RX_EQ_BAND_5_PG: | |
1498 | case WM8996_DSP2_TX_LEFT_VOLUME: | |
1499 | case WM8996_DSP2_TX_RIGHT_VOLUME: | |
1500 | case WM8996_DSP2_RX_LEFT_VOLUME: | |
1501 | case WM8996_DSP2_RX_RIGHT_VOLUME: | |
1502 | case WM8996_DSP2_TX_FILTERS: | |
1503 | case WM8996_DSP2_RX_FILTERS_1: | |
1504 | case WM8996_DSP2_RX_FILTERS_2: | |
1505 | case WM8996_DSP2_DRC_1: | |
1506 | case WM8996_DSP2_DRC_2: | |
1507 | case WM8996_DSP2_DRC_3: | |
1508 | case WM8996_DSP2_DRC_4: | |
1509 | case WM8996_DSP2_DRC_5: | |
1510 | case WM8996_DSP2_RX_EQ_GAINS_1: | |
1511 | case WM8996_DSP2_RX_EQ_GAINS_2: | |
1512 | case WM8996_DSP2_RX_EQ_BAND_1_A: | |
1513 | case WM8996_DSP2_RX_EQ_BAND_1_B: | |
1514 | case WM8996_DSP2_RX_EQ_BAND_1_PG: | |
1515 | case WM8996_DSP2_RX_EQ_BAND_2_A: | |
1516 | case WM8996_DSP2_RX_EQ_BAND_2_B: | |
1517 | case WM8996_DSP2_RX_EQ_BAND_2_C: | |
1518 | case WM8996_DSP2_RX_EQ_BAND_2_PG: | |
1519 | case WM8996_DSP2_RX_EQ_BAND_3_A: | |
1520 | case WM8996_DSP2_RX_EQ_BAND_3_B: | |
1521 | case WM8996_DSP2_RX_EQ_BAND_3_C: | |
1522 | case WM8996_DSP2_RX_EQ_BAND_3_PG: | |
1523 | case WM8996_DSP2_RX_EQ_BAND_4_A: | |
1524 | case WM8996_DSP2_RX_EQ_BAND_4_B: | |
1525 | case WM8996_DSP2_RX_EQ_BAND_4_C: | |
1526 | case WM8996_DSP2_RX_EQ_BAND_4_PG: | |
1527 | case WM8996_DSP2_RX_EQ_BAND_5_A: | |
1528 | case WM8996_DSP2_RX_EQ_BAND_5_B: | |
1529 | case WM8996_DSP2_RX_EQ_BAND_5_PG: | |
1530 | case WM8996_DAC1_MIXER_VOLUMES: | |
1531 | case WM8996_DAC1_LEFT_MIXER_ROUTING: | |
1532 | case WM8996_DAC1_RIGHT_MIXER_ROUTING: | |
1533 | case WM8996_DAC2_MIXER_VOLUMES: | |
1534 | case WM8996_DAC2_LEFT_MIXER_ROUTING: | |
1535 | case WM8996_DAC2_RIGHT_MIXER_ROUTING: | |
1536 | case WM8996_DSP1_TX_LEFT_MIXER_ROUTING: | |
1537 | case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING: | |
1538 | case WM8996_DSP2_TX_LEFT_MIXER_ROUTING: | |
1539 | case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING: | |
1540 | case WM8996_DSP_TX_MIXER_SELECT: | |
1541 | case WM8996_DAC_SOFTMUTE: | |
1542 | case WM8996_OVERSAMPLING: | |
1543 | case WM8996_SIDETONE: | |
1544 | case WM8996_GPIO_1: | |
1545 | case WM8996_GPIO_2: | |
1546 | case WM8996_GPIO_3: | |
1547 | case WM8996_GPIO_4: | |
1548 | case WM8996_GPIO_5: | |
1549 | case WM8996_PULL_CONTROL_1: | |
1550 | case WM8996_PULL_CONTROL_2: | |
1551 | case WM8996_INTERRUPT_STATUS_1: | |
1552 | case WM8996_INTERRUPT_STATUS_2: | |
1553 | case WM8996_INTERRUPT_RAW_STATUS_2: | |
1554 | case WM8996_INTERRUPT_STATUS_1_MASK: | |
1555 | case WM8996_INTERRUPT_STATUS_2_MASK: | |
1556 | case WM8996_INTERRUPT_CONTROL: | |
1557 | case WM8996_LEFT_PDM_SPEAKER: | |
1558 | case WM8996_RIGHT_PDM_SPEAKER: | |
1559 | case WM8996_PDM_SPEAKER_MUTE_SEQUENCE: | |
1560 | case WM8996_PDM_SPEAKER_VOLUME: | |
1561 | return 1; | |
1562 | default: | |
1563 | return 0; | |
1564 | } | |
1565 | } | |
1566 | ||
1567 | static int wm8996_volatile_register(struct snd_soc_codec *codec, | |
1568 | unsigned int reg) | |
1569 | { | |
1570 | switch (reg) { | |
1571 | case WM8996_SOFTWARE_RESET: | |
1572 | case WM8996_CHIP_REVISION: | |
1573 | case WM8996_LDO_1: | |
1574 | case WM8996_LDO_2: | |
1575 | case WM8996_INTERRUPT_STATUS_1: | |
1576 | case WM8996_INTERRUPT_STATUS_2: | |
1577 | case WM8996_INTERRUPT_RAW_STATUS_2: | |
1578 | case WM8996_DC_SERVO_READBACK_0: | |
1579 | case WM8996_DC_SERVO_2: | |
1580 | case WM8996_DC_SERVO_6: | |
1581 | case WM8996_DC_SERVO_7: | |
1582 | case WM8996_FLL_CONTROL_6: | |
1583 | case WM8996_MIC_DETECT_3: | |
1584 | case WM8996_HEADPHONE_DETECT_1: | |
1585 | case WM8996_HEADPHONE_DETECT_2: | |
1586 | return 1; | |
1587 | default: | |
1588 | return 0; | |
1589 | } | |
1590 | } | |
1591 | ||
1592 | static int wm8996_reset(struct snd_soc_codec *codec) | |
1593 | { | |
1594 | return snd_soc_write(codec, WM8996_SOFTWARE_RESET, 0x8915); | |
1595 | } | |
1596 | ||
1597 | static const int bclk_divs[] = { | |
1598 | 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 | |
1599 | }; | |
1600 | ||
1601 | static void wm8996_update_bclk(struct snd_soc_codec *codec) | |
1602 | { | |
1603 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
1604 | int aif, best, cur_val, bclk_rate, bclk_reg, i; | |
1605 | ||
1606 | /* Don't bother if we're in a low frequency idle mode that | |
1607 | * can't support audio. | |
1608 | */ | |
1609 | if (wm8996->sysclk < 64000) | |
1610 | return; | |
1611 | ||
1612 | for (aif = 0; aif < WM8996_AIFS; aif++) { | |
1613 | switch (aif) { | |
1614 | case 0: | |
1615 | bclk_reg = WM8996_AIF1_BCLK; | |
1616 | break; | |
1617 | case 1: | |
1618 | bclk_reg = WM8996_AIF2_BCLK; | |
1619 | break; | |
1620 | } | |
1621 | ||
1622 | bclk_rate = wm8996->bclk_rate[aif]; | |
1623 | ||
1624 | /* Pick a divisor for BCLK as close as we can get to ideal */ | |
1625 | best = 0; | |
1626 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1627 | cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate; | |
1628 | if (cur_val < 0) /* BCLK table is sorted */ | |
1629 | break; | |
1630 | best = i; | |
1631 | } | |
1632 | bclk_rate = wm8996->sysclk / bclk_divs[best]; | |
1633 | dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", | |
1634 | bclk_divs[best], bclk_rate); | |
1635 | ||
1636 | snd_soc_update_bits(codec, bclk_reg, | |
1637 | WM8996_AIF1_BCLK_DIV_MASK, best); | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | static int wm8996_set_bias_level(struct snd_soc_codec *codec, | |
1642 | enum snd_soc_bias_level level) | |
1643 | { | |
1644 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
1645 | int ret; | |
1646 | ||
1647 | switch (level) { | |
1648 | case SND_SOC_BIAS_ON: | |
1649 | break; | |
1650 | ||
1651 | case SND_SOC_BIAS_PREPARE: | |
1652 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { | |
1653 | snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, | |
1654 | WM8996_BG_ENA, WM8996_BG_ENA); | |
1655 | msleep(2); | |
1656 | } | |
1657 | break; | |
1658 | ||
1659 | case SND_SOC_BIAS_STANDBY: | |
1660 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
1661 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), | |
1662 | wm8996->supplies); | |
1663 | if (ret != 0) { | |
1664 | dev_err(codec->dev, | |
1665 | "Failed to enable supplies: %d\n", | |
1666 | ret); | |
1667 | return ret; | |
1668 | } | |
1669 | ||
1670 | if (wm8996->pdata.ldo_ena >= 0) { | |
1671 | gpio_set_value_cansleep(wm8996->pdata.ldo_ena, | |
1672 | 1); | |
1673 | msleep(5); | |
1674 | } | |
1675 | ||
1676 | codec->cache_only = false; | |
1677 | snd_soc_cache_sync(codec); | |
1678 | } | |
1679 | ||
1680 | snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, | |
1681 | WM8996_BG_ENA, 0); | |
1682 | break; | |
1683 | ||
1684 | case SND_SOC_BIAS_OFF: | |
1685 | codec->cache_only = true; | |
1686 | if (wm8996->pdata.ldo_ena >= 0) | |
1687 | gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); | |
1688 | regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), | |
1689 | wm8996->supplies); | |
1690 | break; | |
1691 | } | |
1692 | ||
1693 | codec->dapm.bias_level = level; | |
1694 | ||
1695 | return 0; | |
1696 | } | |
1697 | ||
1698 | static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1699 | { | |
1700 | struct snd_soc_codec *codec = dai->codec; | |
1701 | int aifctrl = 0; | |
1702 | int bclk = 0; | |
1703 | int lrclk_tx = 0; | |
1704 | int lrclk_rx = 0; | |
1705 | int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; | |
1706 | ||
1707 | switch (dai->id) { | |
1708 | case 0: | |
1709 | aifctrl_reg = WM8996_AIF1_CONTROL; | |
1710 | bclk_reg = WM8996_AIF1_BCLK; | |
1711 | lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2; | |
1712 | lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2; | |
1713 | break; | |
1714 | case 1: | |
1715 | aifctrl_reg = WM8996_AIF2_CONTROL; | |
1716 | bclk_reg = WM8996_AIF2_BCLK; | |
1717 | lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2; | |
1718 | lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2; | |
1719 | break; | |
1720 | default: | |
1721 | BUG(); | |
1722 | return -EINVAL; | |
1723 | } | |
1724 | ||
1725 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1726 | case SND_SOC_DAIFMT_NB_NF: | |
1727 | break; | |
1728 | case SND_SOC_DAIFMT_IB_NF: | |
1729 | bclk |= WM8996_AIF1_BCLK_INV; | |
1730 | break; | |
1731 | case SND_SOC_DAIFMT_NB_IF: | |
1732 | lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; | |
1733 | lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; | |
1734 | break; | |
1735 | case SND_SOC_DAIFMT_IB_IF: | |
1736 | bclk |= WM8996_AIF1_BCLK_INV; | |
1737 | lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; | |
1738 | lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; | |
1739 | break; | |
1740 | } | |
1741 | ||
1742 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1743 | case SND_SOC_DAIFMT_CBS_CFS: | |
1744 | break; | |
1745 | case SND_SOC_DAIFMT_CBS_CFM: | |
1746 | lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; | |
1747 | lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; | |
1748 | break; | |
1749 | case SND_SOC_DAIFMT_CBM_CFS: | |
1750 | bclk |= WM8996_AIF1_BCLK_MSTR; | |
1751 | break; | |
1752 | case SND_SOC_DAIFMT_CBM_CFM: | |
1753 | bclk |= WM8996_AIF1_BCLK_MSTR; | |
1754 | lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; | |
1755 | lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; | |
1756 | break; | |
1757 | default: | |
1758 | return -EINVAL; | |
1759 | } | |
1760 | ||
1761 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1762 | case SND_SOC_DAIFMT_DSP_A: | |
1763 | break; | |
1764 | case SND_SOC_DAIFMT_DSP_B: | |
1765 | aifctrl |= 1; | |
1766 | break; | |
1767 | case SND_SOC_DAIFMT_I2S: | |
1768 | aifctrl |= 2; | |
1769 | break; | |
1770 | case SND_SOC_DAIFMT_LEFT_J: | |
1771 | aifctrl |= 3; | |
1772 | break; | |
1773 | default: | |
1774 | return -EINVAL; | |
1775 | } | |
1776 | ||
1777 | snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl); | |
1778 | snd_soc_update_bits(codec, bclk_reg, | |
1779 | WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR, | |
1780 | bclk); | |
1781 | snd_soc_update_bits(codec, lrclk_tx_reg, | |
1782 | WM8996_AIF1TX_LRCLK_INV | | |
1783 | WM8996_AIF1TX_LRCLK_MSTR, | |
1784 | lrclk_tx); | |
1785 | snd_soc_update_bits(codec, lrclk_rx_reg, | |
1786 | WM8996_AIF1RX_LRCLK_INV | | |
1787 | WM8996_AIF1RX_LRCLK_MSTR, | |
1788 | lrclk_rx); | |
1789 | ||
1790 | return 0; | |
1791 | } | |
1792 | ||
1793 | static const int dsp_divs[] = { | |
1794 | 48000, 32000, 16000, 8000 | |
1795 | }; | |
1796 | ||
1797 | static int wm8996_hw_params(struct snd_pcm_substream *substream, | |
1798 | struct snd_pcm_hw_params *params, | |
1799 | struct snd_soc_dai *dai) | |
1800 | { | |
1801 | struct snd_soc_codec *codec = dai->codec; | |
1802 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
1803 | int bits, i, bclk_rate; | |
1804 | int aifdata = 0; | |
1805 | int lrclk = 0; | |
1806 | int dsp = 0; | |
1807 | int aifdata_reg, lrclk_reg, dsp_shift; | |
1808 | ||
1809 | switch (dai->id) { | |
1810 | case 0: | |
1811 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
1812 | (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) { | |
1813 | aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION; | |
1814 | lrclk_reg = WM8996_AIF1_RX_LRCLK_1; | |
1815 | } else { | |
1816 | aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1; | |
1817 | lrclk_reg = WM8996_AIF1_TX_LRCLK_1; | |
1818 | } | |
1819 | dsp_shift = 0; | |
1820 | break; | |
1821 | case 1: | |
1822 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
1823 | (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) { | |
1824 | aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION; | |
1825 | lrclk_reg = WM8996_AIF2_RX_LRCLK_1; | |
1826 | } else { | |
1827 | aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1; | |
1828 | lrclk_reg = WM8996_AIF2_TX_LRCLK_1; | |
1829 | } | |
1830 | dsp_shift = WM8996_DSP2_DIV_SHIFT; | |
1831 | break; | |
1832 | default: | |
1833 | BUG(); | |
1834 | return -EINVAL; | |
1835 | } | |
1836 | ||
1837 | bclk_rate = snd_soc_params_to_bclk(params); | |
1838 | if (bclk_rate < 0) { | |
1839 | dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); | |
1840 | return bclk_rate; | |
1841 | } | |
1842 | ||
1843 | wm8996->bclk_rate[dai->id] = bclk_rate; | |
1844 | wm8996->rx_rate[dai->id] = params_rate(params); | |
1845 | ||
1846 | /* Needs looking at for TDM */ | |
1847 | bits = snd_pcm_format_width(params_format(params)); | |
1848 | if (bits < 0) | |
1849 | return bits; | |
1850 | aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits; | |
1851 | ||
1852 | for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { | |
1853 | if (dsp_divs[i] == params_rate(params)) | |
1854 | break; | |
1855 | } | |
1856 | if (i == ARRAY_SIZE(dsp_divs)) { | |
1857 | dev_err(codec->dev, "Unsupported sample rate %dHz\n", | |
1858 | params_rate(params)); | |
1859 | return -EINVAL; | |
1860 | } | |
1861 | dsp |= i << dsp_shift; | |
1862 | ||
1863 | wm8996_update_bclk(codec); | |
1864 | ||
1865 | lrclk = bclk_rate / params_rate(params); | |
1866 | dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", | |
1867 | lrclk, bclk_rate / lrclk); | |
1868 | ||
1869 | snd_soc_update_bits(codec, aifdata_reg, | |
1870 | WM8996_AIF1TX_WL_MASK | | |
1871 | WM8996_AIF1TX_SLOT_LEN_MASK, | |
1872 | aifdata); | |
1873 | snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK, | |
1874 | lrclk); | |
1875 | snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2, | |
1876 | WM8996_DSP1_DIV_SHIFT << dsp_shift, dsp); | |
1877 | ||
1878 | return 0; | |
1879 | } | |
1880 | ||
1881 | static int wm8996_set_sysclk(struct snd_soc_dai *dai, | |
1882 | int clk_id, unsigned int freq, int dir) | |
1883 | { | |
1884 | struct snd_soc_codec *codec = dai->codec; | |
1885 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
1886 | int lfclk = 0; | |
1887 | int ratediv = 0; | |
1888 | int src; | |
1889 | int old; | |
1890 | ||
1891 | if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src) | |
1892 | return 0; | |
1893 | ||
1894 | /* Disable SYSCLK while we reconfigure */ | |
1895 | old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA; | |
1896 | snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, | |
1897 | WM8996_SYSCLK_ENA, 0); | |
1898 | ||
1899 | switch (clk_id) { | |
1900 | case WM8996_SYSCLK_MCLK1: | |
1901 | wm8996->sysclk = freq; | |
1902 | src = 0; | |
1903 | break; | |
1904 | case WM8996_SYSCLK_MCLK2: | |
1905 | wm8996->sysclk = freq; | |
1906 | src = 1; | |
1907 | break; | |
1908 | case WM8996_SYSCLK_FLL: | |
1909 | wm8996->sysclk = freq; | |
1910 | src = 2; | |
1911 | break; | |
1912 | default: | |
1913 | dev_err(codec->dev, "Unsupported clock source %d\n", clk_id); | |
1914 | return -EINVAL; | |
1915 | } | |
1916 | ||
1917 | switch (wm8996->sysclk) { | |
1918 | case 6144000: | |
1919 | snd_soc_update_bits(codec, WM8996_AIF_RATE, | |
1920 | WM8996_SYSCLK_RATE, 0); | |
1921 | break; | |
1922 | case 24576000: | |
1923 | ratediv = WM8996_SYSCLK_DIV; | |
1924 | case 12288000: | |
1925 | snd_soc_update_bits(codec, WM8996_AIF_RATE, | |
1926 | WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE); | |
1927 | break; | |
1928 | case 32000: | |
1929 | case 32768: | |
1930 | lfclk = WM8996_LFCLK_ENA; | |
1931 | break; | |
1932 | default: | |
1933 | dev_warn(codec->dev, "Unsupported clock rate %dHz\n", | |
1934 | wm8996->sysclk); | |
1935 | return -EINVAL; | |
1936 | } | |
1937 | ||
1938 | wm8996_update_bclk(codec); | |
1939 | ||
1940 | snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, | |
1941 | WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK, | |
1942 | src << WM8996_SYSCLK_SRC_SHIFT | ratediv); | |
1943 | snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk); | |
1944 | snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, | |
1945 | WM8996_SYSCLK_ENA, old); | |
1946 | ||
1947 | wm8996->sysclk_src = clk_id; | |
1948 | ||
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | struct _fll_div { | |
1953 | u16 fll_fratio; | |
1954 | u16 fll_outdiv; | |
1955 | u16 fll_refclk_div; | |
1956 | u16 fll_loop_gain; | |
1957 | u16 fll_ref_freq; | |
1958 | u16 n; | |
1959 | u16 theta; | |
1960 | u16 lambda; | |
1961 | }; | |
1962 | ||
1963 | static struct { | |
1964 | unsigned int min; | |
1965 | unsigned int max; | |
1966 | u16 fll_fratio; | |
1967 | int ratio; | |
1968 | } fll_fratios[] = { | |
1969 | { 0, 64000, 4, 16 }, | |
1970 | { 64000, 128000, 3, 8 }, | |
1971 | { 128000, 256000, 2, 4 }, | |
1972 | { 256000, 1000000, 1, 2 }, | |
1973 | { 1000000, 13500000, 0, 1 }, | |
1974 | }; | |
1975 | ||
1976 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
1977 | unsigned int Fout) | |
1978 | { | |
1979 | unsigned int target; | |
1980 | unsigned int div; | |
1981 | unsigned int fratio, gcd_fll; | |
1982 | int i; | |
1983 | ||
1984 | /* Fref must be <=13.5MHz */ | |
1985 | div = 1; | |
1986 | fll_div->fll_refclk_div = 0; | |
1987 | while ((Fref / div) > 13500000) { | |
1988 | div *= 2; | |
1989 | fll_div->fll_refclk_div++; | |
1990 | ||
1991 | if (div > 8) { | |
1992 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
1993 | Fref); | |
1994 | return -EINVAL; | |
1995 | } | |
1996 | } | |
1997 | ||
1998 | pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); | |
1999 | ||
2000 | /* Apply the division for our remaining calculations */ | |
2001 | Fref /= div; | |
2002 | ||
2003 | if (Fref >= 3000000) | |
2004 | fll_div->fll_loop_gain = 5; | |
2005 | else | |
2006 | fll_div->fll_loop_gain = 0; | |
2007 | ||
2008 | if (Fref >= 48000) | |
2009 | fll_div->fll_ref_freq = 0; | |
2010 | else | |
2011 | fll_div->fll_ref_freq = 1; | |
2012 | ||
2013 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
2014 | div = 2; | |
2015 | while (Fout * div < 90000000) { | |
2016 | div++; | |
2017 | if (div > 64) { | |
2018 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
2019 | Fout); | |
2020 | return -EINVAL; | |
2021 | } | |
2022 | } | |
2023 | target = Fout * div; | |
2024 | fll_div->fll_outdiv = div - 1; | |
2025 | ||
2026 | pr_debug("FLL Fvco=%dHz\n", target); | |
2027 | ||
2028 | /* Find an appropraite FLL_FRATIO and factor it out of the target */ | |
2029 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { | |
2030 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
2031 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
2032 | fratio = fll_fratios[i].ratio; | |
2033 | break; | |
2034 | } | |
2035 | } | |
2036 | if (i == ARRAY_SIZE(fll_fratios)) { | |
2037 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
2038 | return -EINVAL; | |
2039 | } | |
2040 | ||
2041 | fll_div->n = target / (fratio * Fref); | |
2042 | ||
2043 | if (target % Fref == 0) { | |
2044 | fll_div->theta = 0; | |
2045 | fll_div->lambda = 0; | |
2046 | } else { | |
2047 | gcd_fll = gcd(target, fratio * Fref); | |
2048 | ||
2049 | fll_div->theta = (target - (fll_div->n * fratio * Fref)) | |
2050 | / gcd_fll; | |
2051 | fll_div->lambda = (fratio * Fref) / gcd_fll; | |
2052 | } | |
2053 | ||
2054 | pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", | |
2055 | fll_div->n, fll_div->theta, fll_div->lambda); | |
2056 | pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", | |
2057 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
2058 | fll_div->fll_refclk_div); | |
2059 | ||
2060 | return 0; | |
2061 | } | |
2062 | ||
2063 | static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source, | |
2064 | unsigned int Fref, unsigned int Fout) | |
2065 | { | |
2066 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2067 | struct i2c_client *i2c = to_i2c_client(codec->dev); | |
2068 | struct _fll_div fll_div; | |
2069 | unsigned long timeout; | |
27b6d92a | 2070 | int ret, reg, retry; |
a9ba6151 MB |
2071 | |
2072 | /* Any change? */ | |
2073 | if (source == wm8996->fll_src && Fref == wm8996->fll_fref && | |
2074 | Fout == wm8996->fll_fout) | |
2075 | return 0; | |
2076 | ||
2077 | if (Fout == 0) { | |
2078 | dev_dbg(codec->dev, "FLL disabled\n"); | |
2079 | ||
2080 | wm8996->fll_fref = 0; | |
2081 | wm8996->fll_fout = 0; | |
2082 | ||
2083 | snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, | |
2084 | WM8996_FLL_ENA, 0); | |
2085 | ||
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | ret = fll_factors(&fll_div, Fref, Fout); | |
2090 | if (ret != 0) | |
2091 | return ret; | |
2092 | ||
2093 | switch (source) { | |
2094 | case WM8996_FLL_MCLK1: | |
2095 | reg = 0; | |
2096 | break; | |
2097 | case WM8996_FLL_MCLK2: | |
2098 | reg = 1; | |
2099 | break; | |
2100 | case WM8996_FLL_DACLRCLK1: | |
2101 | reg = 2; | |
2102 | break; | |
2103 | case WM8996_FLL_BCLK1: | |
2104 | reg = 3; | |
2105 | break; | |
2106 | default: | |
2107 | dev_err(codec->dev, "Unknown FLL source %d\n", ret); | |
2108 | return -EINVAL; | |
2109 | } | |
2110 | ||
2111 | reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT; | |
2112 | reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT; | |
2113 | ||
2114 | snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5, | |
2115 | WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ | | |
2116 | WM8996_FLL_REFCLK_SRC_MASK, reg); | |
2117 | ||
2118 | reg = 0; | |
2119 | if (fll_div.theta || fll_div.lambda) | |
2120 | reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT); | |
2121 | else | |
2122 | reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT; | |
2123 | snd_soc_write(codec, WM8996_FLL_EFS_2, reg); | |
2124 | ||
2125 | snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2, | |
2126 | WM8996_FLL_OUTDIV_MASK | | |
2127 | WM8996_FLL_FRATIO_MASK, | |
2128 | (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) | | |
2129 | (fll_div.fll_fratio)); | |
2130 | ||
2131 | snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta); | |
2132 | ||
2133 | snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4, | |
2134 | WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK, | |
2135 | (fll_div.n << WM8996_FLL_N_SHIFT) | | |
2136 | fll_div.fll_loop_gain); | |
2137 | ||
2138 | snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda); | |
2139 | ||
a4161945 MB |
2140 | /* Clear any pending completions (eg, from failed startups) */ |
2141 | try_wait_for_completion(&wm8996->fll_lock); | |
2142 | ||
a9ba6151 MB |
2143 | snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, |
2144 | WM8996_FLL_ENA, WM8996_FLL_ENA); | |
2145 | ||
2146 | /* The FLL supports live reconfiguration - kick that in case we were | |
2147 | * already enabled. | |
2148 | */ | |
2149 | snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK); | |
2150 | ||
2151 | /* Wait for the FLL to lock, using the interrupt if possible */ | |
2152 | if (Fref > 1000000) | |
2153 | timeout = usecs_to_jiffies(300); | |
2154 | else | |
2155 | timeout = msecs_to_jiffies(2); | |
2156 | ||
27b6d92a MB |
2157 | /* Allow substantially longer if we've actually got the IRQ, poll |
2158 | * at a slightly higher rate if we don't. | |
2159 | */ | |
a9ba6151 | 2160 | if (i2c->irq) |
27b6d92a MB |
2161 | timeout *= 10; |
2162 | else | |
2163 | timeout /= 2; | |
a9ba6151 | 2164 | |
27b6d92a MB |
2165 | for (retry = 0; retry < 10; retry++) { |
2166 | ret = wait_for_completion_timeout(&wm8996->fll_lock, | |
2167 | timeout); | |
2168 | if (ret != 0) { | |
2169 | WARN_ON(!i2c->irq); | |
2170 | break; | |
2171 | } | |
a9ba6151 | 2172 | |
27b6d92a MB |
2173 | ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2); |
2174 | if (ret & WM8996_FLL_LOCK_STS) | |
2175 | break; | |
2176 | } | |
2177 | if (retry == 10) { | |
a9ba6151 MB |
2178 | dev_err(codec->dev, "Timed out waiting for FLL\n"); |
2179 | ret = -ETIMEDOUT; | |
a9ba6151 MB |
2180 | } |
2181 | ||
2182 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); | |
2183 | ||
2184 | wm8996->fll_fref = Fref; | |
2185 | wm8996->fll_fout = Fout; | |
2186 | wm8996->fll_src = source; | |
2187 | ||
2188 | return ret; | |
2189 | } | |
2190 | ||
2191 | #ifdef CONFIG_GPIOLIB | |
2192 | static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip) | |
2193 | { | |
2194 | return container_of(chip, struct wm8996_priv, gpio_chip); | |
2195 | } | |
2196 | ||
2197 | static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
2198 | { | |
2199 | struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); | |
2200 | struct snd_soc_codec *codec = wm8996->codec; | |
2201 | ||
2202 | snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, | |
2203 | WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT); | |
2204 | } | |
2205 | ||
2206 | static int wm8996_gpio_direction_out(struct gpio_chip *chip, | |
2207 | unsigned offset, int value) | |
2208 | { | |
2209 | struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); | |
2210 | struct snd_soc_codec *codec = wm8996->codec; | |
2211 | int val; | |
2212 | ||
2213 | val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT); | |
2214 | ||
2215 | return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, | |
2216 | WM8996_GP1_FN_MASK | WM8996_GP1_DIR | | |
2217 | WM8996_GP1_LVL, val); | |
2218 | } | |
2219 | ||
2220 | static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset) | |
2221 | { | |
2222 | struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); | |
2223 | struct snd_soc_codec *codec = wm8996->codec; | |
2224 | int ret; | |
2225 | ||
2226 | ret = snd_soc_read(codec, WM8996_GPIO_1 + offset); | |
2227 | if (ret < 0) | |
2228 | return ret; | |
2229 | ||
2230 | return (ret & WM8996_GP1_LVL) != 0; | |
2231 | } | |
2232 | ||
2233 | static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset) | |
2234 | { | |
2235 | struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); | |
2236 | struct snd_soc_codec *codec = wm8996->codec; | |
2237 | ||
2238 | return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, | |
2239 | WM8996_GP1_FN_MASK | WM8996_GP1_DIR, | |
2240 | (1 << WM8996_GP1_FN_SHIFT) | | |
2241 | (1 << WM8996_GP1_DIR_SHIFT)); | |
2242 | } | |
2243 | ||
2244 | static struct gpio_chip wm8996_template_chip = { | |
2245 | .label = "wm8996", | |
2246 | .owner = THIS_MODULE, | |
2247 | .direction_output = wm8996_gpio_direction_out, | |
2248 | .set = wm8996_gpio_set, | |
2249 | .direction_input = wm8996_gpio_direction_in, | |
2250 | .get = wm8996_gpio_get, | |
2251 | .can_sleep = 1, | |
2252 | }; | |
2253 | ||
2254 | static void wm8996_init_gpio(struct snd_soc_codec *codec) | |
2255 | { | |
2256 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2257 | int ret; | |
2258 | ||
2259 | wm8996->gpio_chip = wm8996_template_chip; | |
2260 | wm8996->gpio_chip.ngpio = 5; | |
2261 | wm8996->gpio_chip.dev = codec->dev; | |
2262 | ||
2263 | if (wm8996->pdata.gpio_base) | |
2264 | wm8996->gpio_chip.base = wm8996->pdata.gpio_base; | |
2265 | else | |
2266 | wm8996->gpio_chip.base = -1; | |
2267 | ||
2268 | ret = gpiochip_add(&wm8996->gpio_chip); | |
2269 | if (ret != 0) | |
2270 | dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); | |
2271 | } | |
2272 | ||
2273 | static void wm8996_free_gpio(struct snd_soc_codec *codec) | |
2274 | { | |
2275 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2276 | int ret; | |
2277 | ||
2278 | ret = gpiochip_remove(&wm8996->gpio_chip); | |
2279 | if (ret != 0) | |
2280 | dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); | |
2281 | } | |
2282 | #else | |
2283 | static void wm8996_init_gpio(struct snd_soc_codec *codec) | |
2284 | { | |
2285 | } | |
2286 | ||
2287 | static void wm8996_free_gpio(struct snd_soc_codec *codec) | |
2288 | { | |
2289 | } | |
2290 | #endif | |
2291 | ||
2292 | /** | |
2293 | * wm8996_detect - Enable default WM8996 jack detection | |
2294 | * | |
2295 | * The WM8996 has advanced accessory detection support for headsets. | |
2296 | * This function provides a default implementation which integrates | |
2297 | * the majority of this functionality with minimal user configuration. | |
2298 | * | |
2299 | * This will detect headset, headphone and short circuit button and | |
2300 | * will also detect inverted microphone ground connections and update | |
2301 | * the polarity of the connections. | |
2302 | */ | |
2303 | int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
2304 | wm8996_polarity_fn polarity_cb) | |
2305 | { | |
2306 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2307 | ||
2308 | wm8996->jack = jack; | |
2309 | wm8996->detecting = true; | |
2310 | wm8996->polarity_cb = polarity_cb; | |
2311 | ||
2312 | if (wm8996->polarity_cb) | |
2313 | wm8996->polarity_cb(codec, 0); | |
2314 | ||
2315 | /* Clear discarge to avoid noise during detection */ | |
2316 | snd_soc_update_bits(codec, WM8996_MICBIAS_1, | |
2317 | WM8996_MICB1_DISCH, 0); | |
2318 | snd_soc_update_bits(codec, WM8996_MICBIAS_2, | |
2319 | WM8996_MICB2_DISCH, 0); | |
2320 | ||
2321 | /* LDO2 powers the microphones, SYSCLK clocks detection */ | |
2322 | snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); | |
2323 | snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); | |
2324 | ||
2325 | /* We start off just enabling microphone detection - even a | |
2326 | * plain headphone will trigger detection. | |
2327 | */ | |
2328 | snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, | |
2329 | WM8996_MICD_ENA, WM8996_MICD_ENA); | |
2330 | ||
2331 | /* Slowest detection rate, gives debounce for initial detection */ | |
2332 | snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, | |
2333 | WM8996_MICD_RATE_MASK, | |
2334 | WM8996_MICD_RATE_MASK); | |
2335 | ||
2336 | /* Enable interrupts and we're off */ | |
2337 | snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK, | |
2338 | WM8996_IM_MICD_EINT, 0); | |
2339 | ||
2340 | return 0; | |
2341 | } | |
2342 | EXPORT_SYMBOL_GPL(wm8996_detect); | |
2343 | ||
2344 | static void wm8996_micd(struct snd_soc_codec *codec) | |
2345 | { | |
2346 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2347 | int val, reg; | |
2348 | ||
2349 | val = snd_soc_read(codec, WM8996_MIC_DETECT_3); | |
2350 | ||
2351 | dev_dbg(codec->dev, "Microphone event: %x\n", val); | |
2352 | ||
2353 | if (!(val & WM8996_MICD_VALID)) { | |
2354 | dev_warn(codec->dev, "Microphone detection state invalid\n"); | |
2355 | return; | |
2356 | } | |
2357 | ||
2358 | /* No accessory, reset everything and report removal */ | |
2359 | if (!(val & WM8996_MICD_STS)) { | |
2360 | dev_dbg(codec->dev, "Jack removal detected\n"); | |
2361 | wm8996->jack_mic = false; | |
2362 | wm8996->detecting = true; | |
2363 | snd_soc_jack_report(wm8996->jack, 0, | |
2364 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2365 | snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, | |
2366 | WM8996_MICD_RATE_MASK, | |
2367 | WM8996_MICD_RATE_MASK); | |
2368 | return; | |
2369 | } | |
2370 | ||
2371 | /* If the measurement is very high we've got a microphone but | |
2372 | * do a little debounce to account for mechanical issues. | |
2373 | */ | |
2374 | if (val & 0x400) { | |
2375 | dev_dbg(codec->dev, "Microphone detected\n"); | |
2376 | snd_soc_jack_report(wm8996->jack, SND_JACK_HEADSET, | |
2377 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2378 | wm8996->jack_mic = true; | |
2379 | wm8996->detecting = false; | |
2380 | ||
2381 | /* Increase poll rate to give better responsiveness | |
2382 | * for buttons */ | |
2383 | snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, | |
2384 | WM8996_MICD_RATE_MASK, | |
2385 | 5 << WM8996_MICD_RATE_SHIFT); | |
2386 | } | |
2387 | ||
2388 | /* If we detected a lower impedence during initial startup | |
2389 | * then we probably have the wrong polarity, flip it. Don't | |
2390 | * do this for the lowest impedences to speed up detection of | |
2391 | * plain headphones. | |
2392 | */ | |
2393 | if (wm8996->detecting && (val & 0x3f0)) { | |
2394 | reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2); | |
2395 | reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | | |
2396 | WM8996_MICD_BIAS_SRC; | |
2397 | snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, | |
2398 | WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | | |
2399 | WM8996_MICD_BIAS_SRC, reg); | |
2400 | ||
2401 | if (wm8996->polarity_cb) | |
2402 | wm8996->polarity_cb(codec, | |
2403 | (reg & WM8996_MICD_SRC) != 0); | |
2404 | ||
2405 | dev_dbg(codec->dev, "Set microphone polarity to %d\n", | |
2406 | (reg & WM8996_MICD_SRC) != 0); | |
2407 | ||
2408 | return; | |
2409 | } | |
2410 | ||
2411 | /* Don't distinguish between buttons, just report any low | |
2412 | * impedence as BTN_0. | |
2413 | */ | |
2414 | if (val & 0x3fc) { | |
2415 | if (wm8996->jack_mic) { | |
2416 | dev_dbg(codec->dev, "Mic button detected\n"); | |
2417 | snd_soc_jack_report(wm8996->jack, | |
2418 | SND_JACK_HEADSET | SND_JACK_BTN_0, | |
2419 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2420 | } else { | |
2421 | dev_dbg(codec->dev, "Headphone detected\n"); | |
2422 | snd_soc_jack_report(wm8996->jack, | |
2423 | SND_JACK_HEADPHONE, | |
2424 | SND_JACK_HEADSET | | |
2425 | SND_JACK_BTN_0); | |
2426 | ||
2427 | /* Increase the detection rate a bit for | |
2428 | * responsiveness. | |
2429 | */ | |
2430 | snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, | |
2431 | WM8996_MICD_RATE_MASK, | |
2432 | 7 << WM8996_MICD_RATE_SHIFT); | |
2433 | ||
2434 | wm8996->detecting = false; | |
2435 | } | |
2436 | } | |
2437 | } | |
2438 | ||
2439 | static irqreturn_t wm8996_irq(int irq, void *data) | |
2440 | { | |
2441 | struct snd_soc_codec *codec = data; | |
2442 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2443 | int irq_val; | |
2444 | ||
2445 | irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2); | |
2446 | if (irq_val < 0) { | |
2447 | dev_err(codec->dev, "Failed to read IRQ status: %d\n", | |
2448 | irq_val); | |
2449 | return IRQ_NONE; | |
2450 | } | |
2451 | irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK); | |
2452 | ||
2fde6e80 MB |
2453 | if (!irq_val) |
2454 | return IRQ_NONE; | |
2455 | ||
84497091 MB |
2456 | snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val); |
2457 | ||
a9ba6151 MB |
2458 | if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) { |
2459 | dev_dbg(codec->dev, "DC servo IRQ\n"); | |
2460 | complete(&wm8996->dcs_done); | |
2461 | } | |
2462 | ||
2463 | if (irq_val & WM8996_FIFOS_ERR_EINT) | |
2464 | dev_err(codec->dev, "Digital core FIFO error\n"); | |
2465 | ||
2466 | if (irq_val & WM8996_FLL_LOCK_EINT) { | |
2467 | dev_dbg(codec->dev, "FLL locked\n"); | |
2468 | complete(&wm8996->fll_lock); | |
2469 | } | |
2470 | ||
2471 | if (irq_val & WM8996_MICD_EINT) | |
2472 | wm8996_micd(codec); | |
2473 | ||
2fde6e80 | 2474 | return IRQ_HANDLED; |
a9ba6151 MB |
2475 | } |
2476 | ||
2477 | static irqreturn_t wm8996_edge_irq(int irq, void *data) | |
2478 | { | |
2479 | irqreturn_t ret = IRQ_NONE; | |
2480 | irqreturn_t val; | |
2481 | ||
2482 | do { | |
2483 | val = wm8996_irq(irq, data); | |
2484 | if (val != IRQ_NONE) | |
2485 | ret = val; | |
2486 | } while (val != IRQ_NONE); | |
2487 | ||
2488 | return ret; | |
2489 | } | |
2490 | ||
2491 | static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec) | |
2492 | { | |
2493 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2494 | struct wm8996_pdata *pdata = &wm8996->pdata; | |
2495 | ||
2496 | struct snd_kcontrol_new controls[] = { | |
2497 | SOC_ENUM_EXT("DSP1 EQ Mode", | |
2498 | wm8996->retune_mobile_enum, | |
2499 | wm8996_get_retune_mobile_enum, | |
2500 | wm8996_put_retune_mobile_enum), | |
2501 | SOC_ENUM_EXT("DSP2 EQ Mode", | |
2502 | wm8996->retune_mobile_enum, | |
2503 | wm8996_get_retune_mobile_enum, | |
2504 | wm8996_put_retune_mobile_enum), | |
2505 | }; | |
2506 | int ret, i, j; | |
2507 | const char **t; | |
2508 | ||
2509 | /* We need an array of texts for the enum API but the number | |
2510 | * of texts is likely to be less than the number of | |
2511 | * configurations due to the sample rate dependency of the | |
2512 | * configurations. */ | |
2513 | wm8996->num_retune_mobile_texts = 0; | |
2514 | wm8996->retune_mobile_texts = NULL; | |
2515 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
2516 | for (j = 0; j < wm8996->num_retune_mobile_texts; j++) { | |
2517 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
2518 | wm8996->retune_mobile_texts[j]) == 0) | |
2519 | break; | |
2520 | } | |
2521 | ||
2522 | if (j != wm8996->num_retune_mobile_texts) | |
2523 | continue; | |
2524 | ||
2525 | /* Expand the array... */ | |
2526 | t = krealloc(wm8996->retune_mobile_texts, | |
2527 | sizeof(char *) * | |
2528 | (wm8996->num_retune_mobile_texts + 1), | |
2529 | GFP_KERNEL); | |
2530 | if (t == NULL) | |
2531 | continue; | |
2532 | ||
2533 | /* ...store the new entry... */ | |
2534 | t[wm8996->num_retune_mobile_texts] = | |
2535 | pdata->retune_mobile_cfgs[i].name; | |
2536 | ||
2537 | /* ...and remember the new version. */ | |
2538 | wm8996->num_retune_mobile_texts++; | |
2539 | wm8996->retune_mobile_texts = t; | |
2540 | } | |
2541 | ||
2542 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
2543 | wm8996->num_retune_mobile_texts); | |
2544 | ||
2545 | wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts; | |
2546 | wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts; | |
2547 | ||
2548 | ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); | |
2549 | if (ret != 0) | |
2550 | dev_err(codec->dev, | |
2551 | "Failed to add ReTune Mobile controls: %d\n", ret); | |
2552 | } | |
2553 | ||
2554 | static int wm8996_probe(struct snd_soc_codec *codec) | |
2555 | { | |
2556 | int ret; | |
2557 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2558 | struct i2c_client *i2c = to_i2c_client(codec->dev); | |
2559 | struct snd_soc_dapm_context *dapm = &codec->dapm; | |
2560 | int i, irq_flags; | |
2561 | ||
2562 | wm8996->codec = codec; | |
2563 | ||
2564 | init_completion(&wm8996->dcs_done); | |
2565 | init_completion(&wm8996->fll_lock); | |
2566 | ||
2567 | dapm->idle_bias_off = true; | |
2568 | dapm->bias_level = SND_SOC_BIAS_OFF; | |
2569 | ||
2570 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); | |
2571 | if (ret != 0) { | |
2572 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
2573 | goto err; | |
2574 | } | |
2575 | ||
2576 | for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) | |
2577 | wm8996->supplies[i].supply = wm8996_supply_names[i]; | |
2578 | ||
2579 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8996->supplies), | |
2580 | wm8996->supplies); | |
2581 | if (ret != 0) { | |
2582 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
2583 | goto err; | |
2584 | } | |
2585 | ||
2586 | wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0; | |
2587 | wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1; | |
2588 | wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2; | |
c83495af MB |
2589 | |
2590 | wm8996->cpvdd = regulator_get(&i2c->dev, "CPVDD"); | |
2591 | if (IS_ERR(wm8996->cpvdd)) { | |
2592 | ret = PTR_ERR(wm8996->cpvdd); | |
2593 | dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret); | |
2594 | goto err_get; | |
2595 | } | |
a9ba6151 MB |
2596 | |
2597 | /* This should really be moved into the regulator core */ | |
2598 | for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) { | |
2599 | ret = regulator_register_notifier(wm8996->supplies[i].consumer, | |
2600 | &wm8996->disable_nb[i]); | |
2601 | if (ret != 0) { | |
2602 | dev_err(codec->dev, | |
2603 | "Failed to register regulator notifier: %d\n", | |
2604 | ret); | |
2605 | } | |
2606 | } | |
2607 | ||
2608 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), | |
2609 | wm8996->supplies); | |
2610 | if (ret != 0) { | |
2611 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
c83495af | 2612 | goto err_cpvdd; |
a9ba6151 MB |
2613 | } |
2614 | ||
2615 | if (wm8996->pdata.ldo_ena >= 0) { | |
2616 | gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1); | |
2617 | msleep(5); | |
2618 | } | |
2619 | ||
2620 | ret = snd_soc_read(codec, WM8996_SOFTWARE_RESET); | |
2621 | if (ret < 0) { | |
2622 | dev_err(codec->dev, "Failed to read ID register: %d\n", ret); | |
2623 | goto err_enable; | |
2624 | } | |
2625 | if (ret != 0x8915) { | |
2626 | dev_err(codec->dev, "Device is not a WM8996, ID %x\n", ret); | |
2627 | ret = -EINVAL; | |
2628 | goto err_enable; | |
2629 | } | |
2630 | ||
2631 | ret = snd_soc_read(codec, WM8996_CHIP_REVISION); | |
2632 | if (ret < 0) { | |
2633 | dev_err(codec->dev, "Failed to read device revision: %d\n", | |
2634 | ret); | |
2635 | goto err_enable; | |
2636 | } | |
2637 | ||
2638 | dev_info(codec->dev, "revision %c\n", | |
2639 | (ret & WM8996_CHIP_REV_MASK) + 'A'); | |
2640 | ||
2641 | if (wm8996->pdata.ldo_ena >= 0) { | |
2642 | gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); | |
2643 | } else { | |
2644 | ret = wm8996_reset(codec); | |
2645 | if (ret < 0) { | |
2646 | dev_err(codec->dev, "Failed to issue reset\n"); | |
2647 | goto err_enable; | |
2648 | } | |
2649 | } | |
2650 | ||
2651 | codec->cache_only = true; | |
2652 | ||
2653 | /* Apply platform data settings */ | |
2654 | snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL, | |
2655 | WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK, | |
2656 | wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT | | |
2657 | wm8996->pdata.inr_mode); | |
2658 | ||
2659 | for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) { | |
2660 | if (!wm8996->pdata.gpio_default[i]) | |
2661 | continue; | |
2662 | ||
2663 | snd_soc_write(codec, WM8996_GPIO_1 + i, | |
2664 | wm8996->pdata.gpio_default[i] & 0xffff); | |
2665 | } | |
2666 | ||
2667 | if (wm8996->pdata.spkmute_seq) | |
2668 | snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE, | |
2669 | WM8996_SPK_MUTE_ENDIAN | | |
2670 | WM8996_SPK_MUTE_SEQ1_MASK, | |
2671 | wm8996->pdata.spkmute_seq); | |
2672 | ||
2673 | snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, | |
2674 | WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC | | |
2675 | WM8996_MICD_SRC, wm8996->pdata.micdet_def); | |
2676 | ||
2677 | /* Latch volume update bits */ | |
2678 | snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME, | |
2679 | WM8996_IN1_VU, WM8996_IN1_VU); | |
2680 | snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME, | |
2681 | WM8996_IN1_VU, WM8996_IN1_VU); | |
2682 | ||
2683 | snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME, | |
2684 | WM8996_DAC1_VU, WM8996_DAC1_VU); | |
2685 | snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME, | |
2686 | WM8996_DAC1_VU, WM8996_DAC1_VU); | |
2687 | snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME, | |
2688 | WM8996_DAC2_VU, WM8996_DAC2_VU); | |
2689 | snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME, | |
2690 | WM8996_DAC2_VU, WM8996_DAC2_VU); | |
2691 | ||
2692 | snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME, | |
2693 | WM8996_DAC1_VU, WM8996_DAC1_VU); | |
2694 | snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME, | |
2695 | WM8996_DAC1_VU, WM8996_DAC1_VU); | |
2696 | snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME, | |
2697 | WM8996_DAC2_VU, WM8996_DAC2_VU); | |
2698 | snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME, | |
2699 | WM8996_DAC2_VU, WM8996_DAC2_VU); | |
2700 | ||
2701 | snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME, | |
2702 | WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); | |
2703 | snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME, | |
2704 | WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); | |
2705 | snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME, | |
2706 | WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); | |
2707 | snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME, | |
2708 | WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); | |
2709 | ||
2710 | snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME, | |
2711 | WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); | |
2712 | snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME, | |
2713 | WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); | |
2714 | snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME, | |
2715 | WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); | |
2716 | snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME, | |
2717 | WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); | |
2718 | ||
2719 | /* No support currently for the underclocked TDM modes and | |
2720 | * pick a default TDM layout with each channel pair working with | |
2721 | * slots 0 and 1. */ | |
2722 | snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, | |
2723 | WM8996_AIF1RX_CHAN0_SLOTS_MASK | | |
2724 | WM8996_AIF1RX_CHAN0_START_SLOT_MASK, | |
2725 | 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0); | |
2726 | snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, | |
2727 | WM8996_AIF1RX_CHAN1_SLOTS_MASK | | |
2728 | WM8996_AIF1RX_CHAN1_START_SLOT_MASK, | |
2729 | 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1); | |
2730 | snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, | |
2731 | WM8996_AIF1RX_CHAN2_SLOTS_MASK | | |
2732 | WM8996_AIF1RX_CHAN2_START_SLOT_MASK, | |
2733 | 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0); | |
2734 | snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, | |
2735 | WM8996_AIF1RX_CHAN3_SLOTS_MASK | | |
2736 | WM8996_AIF1RX_CHAN0_START_SLOT_MASK, | |
2737 | 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1); | |
2738 | snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, | |
2739 | WM8996_AIF1RX_CHAN4_SLOTS_MASK | | |
2740 | WM8996_AIF1RX_CHAN0_START_SLOT_MASK, | |
2741 | 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0); | |
2742 | snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, | |
2743 | WM8996_AIF1RX_CHAN5_SLOTS_MASK | | |
2744 | WM8996_AIF1RX_CHAN0_START_SLOT_MASK, | |
2745 | 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1); | |
2746 | ||
2747 | snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, | |
2748 | WM8996_AIF2RX_CHAN0_SLOTS_MASK | | |
2749 | WM8996_AIF2RX_CHAN0_START_SLOT_MASK, | |
2750 | 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0); | |
2751 | snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, | |
2752 | WM8996_AIF2RX_CHAN1_SLOTS_MASK | | |
2753 | WM8996_AIF2RX_CHAN1_START_SLOT_MASK, | |
2754 | 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1); | |
2755 | ||
2756 | snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, | |
2757 | WM8996_AIF1TX_CHAN0_SLOTS_MASK | | |
2758 | WM8996_AIF1TX_CHAN0_START_SLOT_MASK, | |
2759 | 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0); | |
2760 | snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, | |
2761 | WM8996_AIF1TX_CHAN1_SLOTS_MASK | | |
2762 | WM8996_AIF1TX_CHAN0_START_SLOT_MASK, | |
2763 | 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); | |
2764 | snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, | |
2765 | WM8996_AIF1TX_CHAN2_SLOTS_MASK | | |
2766 | WM8996_AIF1TX_CHAN0_START_SLOT_MASK, | |
2767 | 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0); | |
2768 | snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, | |
2769 | WM8996_AIF1TX_CHAN3_SLOTS_MASK | | |
2770 | WM8996_AIF1TX_CHAN0_START_SLOT_MASK, | |
2771 | 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1); | |
2772 | snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, | |
2773 | WM8996_AIF1TX_CHAN4_SLOTS_MASK | | |
2774 | WM8996_AIF1TX_CHAN0_START_SLOT_MASK, | |
2775 | 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0); | |
2776 | snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, | |
2777 | WM8996_AIF1TX_CHAN5_SLOTS_MASK | | |
2778 | WM8996_AIF1TX_CHAN0_START_SLOT_MASK, | |
2779 | 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1); | |
2780 | ||
2781 | snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, | |
2782 | WM8996_AIF2TX_CHAN0_SLOTS_MASK | | |
2783 | WM8996_AIF2TX_CHAN0_START_SLOT_MASK, | |
2784 | 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0); | |
2785 | snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, | |
2786 | WM8996_AIF2TX_CHAN1_SLOTS_MASK | | |
2787 | WM8996_AIF2TX_CHAN1_START_SLOT_MASK, | |
2788 | 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); | |
2789 | ||
2790 | if (wm8996->pdata.num_retune_mobile_cfgs) | |
2791 | wm8996_retune_mobile_pdata(codec); | |
2792 | else | |
2793 | snd_soc_add_controls(codec, wm8996_eq_controls, | |
2794 | ARRAY_SIZE(wm8996_eq_controls)); | |
2795 | ||
2796 | /* If the TX LRCLK pins are not in LRCLK mode configure the | |
2797 | * AIFs to source their clocks from the RX LRCLKs. | |
2798 | */ | |
2799 | if ((snd_soc_read(codec, WM8996_GPIO_1))) | |
2800 | snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2, | |
2801 | WM8996_AIF1TX_LRCLK_MODE, | |
2802 | WM8996_AIF1TX_LRCLK_MODE); | |
2803 | ||
2804 | if ((snd_soc_read(codec, WM8996_GPIO_2))) | |
2805 | snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2, | |
2806 | WM8996_AIF2TX_LRCLK_MODE, | |
2807 | WM8996_AIF2TX_LRCLK_MODE); | |
2808 | ||
2809 | regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); | |
2810 | ||
2811 | wm8996_init_gpio(codec); | |
2812 | ||
2813 | if (i2c->irq) { | |
2814 | if (wm8996->pdata.irq_flags) | |
2815 | irq_flags = wm8996->pdata.irq_flags; | |
2816 | else | |
2817 | irq_flags = IRQF_TRIGGER_LOW; | |
2818 | ||
2819 | irq_flags |= IRQF_ONESHOT; | |
2820 | ||
2821 | if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) | |
2822 | ret = request_threaded_irq(i2c->irq, NULL, | |
2823 | wm8996_edge_irq, | |
2824 | irq_flags, "wm8996", codec); | |
2825 | else | |
2826 | ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq, | |
2827 | irq_flags, "wm8996", codec); | |
2828 | ||
2829 | if (ret == 0) { | |
2830 | /* Unmask the interrupt */ | |
2831 | snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, | |
2832 | WM8996_IM_IRQ, 0); | |
2833 | ||
2834 | /* Enable error reporting and DC servo status */ | |
2835 | snd_soc_update_bits(codec, | |
2836 | WM8996_INTERRUPT_STATUS_2_MASK, | |
2837 | WM8996_IM_DCS_DONE_23_EINT | | |
2838 | WM8996_IM_DCS_DONE_01_EINT | | |
2839 | WM8996_IM_FLL_LOCK_EINT | | |
2840 | WM8996_IM_FIFOS_ERR_EINT, | |
2841 | 0); | |
2842 | } else { | |
2843 | dev_err(codec->dev, "Failed to request IRQ: %d\n", | |
2844 | ret); | |
2845 | } | |
2846 | } | |
2847 | ||
2848 | return 0; | |
2849 | ||
2850 | err_enable: | |
2851 | if (wm8996->pdata.ldo_ena >= 0) | |
2852 | gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); | |
2853 | ||
2854 | regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); | |
c83495af MB |
2855 | err_cpvdd: |
2856 | regulator_put(wm8996->cpvdd); | |
a9ba6151 MB |
2857 | err_get: |
2858 | regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); | |
2859 | err: | |
2860 | return ret; | |
2861 | } | |
2862 | ||
2863 | static int wm8996_remove(struct snd_soc_codec *codec) | |
2864 | { | |
2865 | struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); | |
2866 | struct i2c_client *i2c = to_i2c_client(codec->dev); | |
2867 | int i; | |
2868 | ||
2869 | snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, | |
2870 | WM8996_IM_IRQ, WM8996_IM_IRQ); | |
2871 | ||
2872 | if (i2c->irq) | |
2873 | free_irq(i2c->irq, codec); | |
2874 | ||
2875 | wm8996_free_gpio(codec); | |
2876 | ||
2877 | for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) | |
2878 | regulator_unregister_notifier(wm8996->supplies[i].consumer, | |
2879 | &wm8996->disable_nb[i]); | |
c83495af | 2880 | regulator_put(wm8996->cpvdd); |
a9ba6151 MB |
2881 | regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); |
2882 | ||
2883 | return 0; | |
2884 | } | |
2885 | ||
2886 | static struct snd_soc_codec_driver soc_codec_dev_wm8996 = { | |
2887 | .probe = wm8996_probe, | |
2888 | .remove = wm8996_remove, | |
2889 | .set_bias_level = wm8996_set_bias_level, | |
2890 | .seq_notifier = wm8996_seq_notifier, | |
2891 | .reg_cache_size = WM8996_MAX_REGISTER + 1, | |
2892 | .reg_word_size = sizeof(u16), | |
2893 | .reg_cache_default = wm8996_reg, | |
2894 | .volatile_register = wm8996_volatile_register, | |
2895 | .readable_register = wm8996_readable_register, | |
2896 | .compress_type = SND_SOC_RBTREE_COMPRESSION, | |
2897 | .controls = wm8996_snd_controls, | |
2898 | .num_controls = ARRAY_SIZE(wm8996_snd_controls), | |
2899 | .dapm_widgets = wm8996_dapm_widgets, | |
2900 | .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets), | |
2901 | .dapm_routes = wm8996_dapm_routes, | |
2902 | .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes), | |
2903 | .set_pll = wm8996_set_fll, | |
2904 | }; | |
2905 | ||
2906 | #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ | |
2907 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) | |
2908 | #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ | |
2909 | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ | |
2910 | SNDRV_PCM_FMTBIT_S32_LE) | |
2911 | ||
2912 | static struct snd_soc_dai_ops wm8996_dai_ops = { | |
2913 | .set_fmt = wm8996_set_fmt, | |
2914 | .hw_params = wm8996_hw_params, | |
2915 | .set_sysclk = wm8996_set_sysclk, | |
2916 | }; | |
2917 | ||
2918 | static struct snd_soc_dai_driver wm8996_dai[] = { | |
2919 | { | |
2920 | .name = "wm8996-aif1", | |
2921 | .playback = { | |
2922 | .stream_name = "AIF1 Playback", | |
2923 | .channels_min = 1, | |
2924 | .channels_max = 6, | |
2925 | .rates = WM8996_RATES, | |
2926 | .formats = WM8996_FORMATS, | |
2927 | }, | |
2928 | .capture = { | |
2929 | .stream_name = "AIF1 Capture", | |
2930 | .channels_min = 1, | |
2931 | .channels_max = 6, | |
2932 | .rates = WM8996_RATES, | |
2933 | .formats = WM8996_FORMATS, | |
2934 | }, | |
2935 | .ops = &wm8996_dai_ops, | |
2936 | }, | |
2937 | { | |
2938 | .name = "wm8996-aif2", | |
2939 | .playback = { | |
2940 | .stream_name = "AIF2 Playback", | |
2941 | .channels_min = 1, | |
2942 | .channels_max = 2, | |
2943 | .rates = WM8996_RATES, | |
2944 | .formats = WM8996_FORMATS, | |
2945 | }, | |
2946 | .capture = { | |
2947 | .stream_name = "AIF2 Capture", | |
2948 | .channels_min = 1, | |
2949 | .channels_max = 2, | |
2950 | .rates = WM8996_RATES, | |
2951 | .formats = WM8996_FORMATS, | |
2952 | }, | |
2953 | .ops = &wm8996_dai_ops, | |
2954 | }, | |
2955 | }; | |
2956 | ||
2957 | static __devinit int wm8996_i2c_probe(struct i2c_client *i2c, | |
2958 | const struct i2c_device_id *id) | |
2959 | { | |
2960 | struct wm8996_priv *wm8996; | |
2961 | int ret; | |
2962 | ||
2963 | wm8996 = kzalloc(sizeof(struct wm8996_priv), GFP_KERNEL); | |
2964 | if (wm8996 == NULL) | |
2965 | return -ENOMEM; | |
2966 | ||
2967 | i2c_set_clientdata(i2c, wm8996); | |
2968 | ||
2969 | if (dev_get_platdata(&i2c->dev)) | |
2970 | memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev), | |
2971 | sizeof(wm8996->pdata)); | |
2972 | ||
2973 | if (wm8996->pdata.ldo_ena > 0) { | |
2974 | ret = gpio_request_one(wm8996->pdata.ldo_ena, | |
2975 | GPIOF_OUT_INIT_LOW, "WM8996 ENA"); | |
2976 | if (ret < 0) { | |
2977 | dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", | |
2978 | wm8996->pdata.ldo_ena, ret); | |
2979 | goto err; | |
2980 | } | |
2981 | } | |
2982 | ||
2983 | ret = snd_soc_register_codec(&i2c->dev, | |
2984 | &soc_codec_dev_wm8996, wm8996_dai, | |
2985 | ARRAY_SIZE(wm8996_dai)); | |
2986 | if (ret < 0) | |
2987 | goto err_gpio; | |
2988 | ||
2989 | return ret; | |
2990 | ||
2991 | err_gpio: | |
2992 | if (wm8996->pdata.ldo_ena > 0) | |
2993 | gpio_free(wm8996->pdata.ldo_ena); | |
2994 | err: | |
2995 | kfree(wm8996); | |
2996 | ||
2997 | return ret; | |
2998 | } | |
2999 | ||
3000 | static __devexit int wm8996_i2c_remove(struct i2c_client *client) | |
3001 | { | |
3002 | struct wm8996_priv *wm8996 = i2c_get_clientdata(client); | |
3003 | ||
3004 | snd_soc_unregister_codec(&client->dev); | |
3005 | if (wm8996->pdata.ldo_ena > 0) | |
3006 | gpio_free(wm8996->pdata.ldo_ena); | |
3007 | kfree(i2c_get_clientdata(client)); | |
3008 | return 0; | |
3009 | } | |
3010 | ||
3011 | static const struct i2c_device_id wm8996_i2c_id[] = { | |
3012 | { "wm8996", 0 }, | |
3013 | { } | |
3014 | }; | |
3015 | MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id); | |
3016 | ||
3017 | static struct i2c_driver wm8996_i2c_driver = { | |
3018 | .driver = { | |
3019 | .name = "wm8996", | |
3020 | .owner = THIS_MODULE, | |
3021 | }, | |
3022 | .probe = wm8996_i2c_probe, | |
3023 | .remove = __devexit_p(wm8996_i2c_remove), | |
3024 | .id_table = wm8996_i2c_id, | |
3025 | }; | |
3026 | ||
3027 | static int __init wm8996_modinit(void) | |
3028 | { | |
3029 | int ret; | |
3030 | ||
3031 | ret = i2c_add_driver(&wm8996_i2c_driver); | |
3032 | if (ret != 0) { | |
3033 | printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n", | |
3034 | ret); | |
3035 | } | |
3036 | ||
3037 | return ret; | |
3038 | } | |
3039 | module_init(wm8996_modinit); | |
3040 | ||
3041 | static void __exit wm8996_exit(void) | |
3042 | { | |
3043 | i2c_del_driver(&wm8996_i2c_driver); | |
3044 | } | |
3045 | module_exit(wm8996_exit); | |
3046 | ||
3047 | MODULE_DESCRIPTION("ASoC WM8996 driver"); | |
3048 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
3049 | MODULE_LICENSE("GPL"); |