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ASoC: Fix unused variable warning in WM8996
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8996.c
CommitLineData
a9ba6151
MB		 1/*
2 * wm8996.c - WM8996 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <linux/workqueue.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <trace/events/asoc.h>
33
34#include <sound/wm8996.h>
35#include "wm8996.h"
36
37#define WM8996_AIFS 2
38
39#define HPOUT1L 1
40#define HPOUT1R 2
41#define HPOUT2L 4
42#define HPOUT2R 8
43
c83495af 44#define WM8996_NUM_SUPPLIES 3
a9ba6151
MB		 45static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
46 "DBVDD",
47 "AVDD1",
48 "AVDD2",
a9ba6151
MB		 49};
50
51struct wm8996_priv {
52 struct snd_soc_codec *codec;
53
54 int ldo1ena;
55
56 int sysclk;
57 int sysclk_src;
58
59 int fll_src;
60 int fll_fref;
61 int fll_fout;
62
63 struct completion fll_lock;
64
65 u16 dcs_pending;
66 struct completion dcs_done;
67
68 u16 hpout_ena;
69 u16 hpout_pending;
70
71 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
72 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
c83495af 73 struct regulator *cpvdd;
a9ba6151
MB		 74
75 struct wm8996_pdata pdata;
76
77 int rx_rate[WM8996_AIFS];
78 int bclk_rate[WM8996_AIFS];
79
80 /* Platform dependant ReTune mobile configuration */
81 int num_retune_mobile_texts;
82 const char **retune_mobile_texts;
83 int retune_mobile_cfg[2];
84 struct soc_enum retune_mobile_enum;
85
86 struct snd_soc_jack *jack;
87 bool detecting;
88 bool jack_mic;
89 wm8996_polarity_fn polarity_cb;
90
91#ifdef CONFIG_GPIOLIB
92 struct gpio_chip gpio_chip;
93#endif
94};
95
96/* We can't use the same notifier block for more than one supply and
97 * there's no way I can see to get from a callback to the caller
98 * except container_of().
99 */
100#define WM8996_REGULATOR_EVENT(n) \
101static int wm8996_regulator_event_##n(struct notifier_block *nb, \
102 unsigned long event, void *data) \
103{ \
104 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
105 disable_nb[n]); \
106 if (event & REGULATOR_EVENT_DISABLE) { \
107 wm8996->codec->cache_sync = 1; \
108 } \
109 return 0; \
110}
111
112WM8996_REGULATOR_EVENT(0)
113WM8996_REGULATOR_EVENT(1)
114WM8996_REGULATOR_EVENT(2)
a9ba6151
MB		 115
116static const u16 wm8996_reg[WM8996_MAX_REGISTER] = {
117 [WM8996_SOFTWARE_RESET] = 0x8996,
118 [WM8996_POWER_MANAGEMENT_7] = 0x10,
119 [WM8996_DAC1_HPOUT1_VOLUME] = 0x88,
120 [WM8996_DAC2_HPOUT2_VOLUME] = 0x88,
121 [WM8996_DAC1_LEFT_VOLUME] = 0x2c0,
122 [WM8996_DAC1_RIGHT_VOLUME] = 0x2c0,
123 [WM8996_DAC2_LEFT_VOLUME] = 0x2c0,
124 [WM8996_DAC2_RIGHT_VOLUME] = 0x2c0,
125 [WM8996_OUTPUT1_LEFT_VOLUME] = 0x80,
126 [WM8996_OUTPUT1_RIGHT_VOLUME] = 0x80,
127 [WM8996_OUTPUT2_LEFT_VOLUME] = 0x80,
128 [WM8996_OUTPUT2_RIGHT_VOLUME] = 0x80,
129 [WM8996_MICBIAS_1] = 0x39,
130 [WM8996_MICBIAS_2] = 0x39,
131 [WM8996_LDO_1] = 0x3,
132 [WM8996_LDO_2] = 0x13,
133 [WM8996_ACCESSORY_DETECT_MODE_1] = 0x4,
134 [WM8996_HEADPHONE_DETECT_1] = 0x20,
135 [WM8996_MIC_DETECT_1] = 0x7600,
136 [WM8996_MIC_DETECT_2] = 0xbf,
137 [WM8996_CHARGE_PUMP_1] = 0x1f25,
138 [WM8996_CHARGE_PUMP_2] = 0xab19,
139 [WM8996_DC_SERVO_5] = 0x2a2a,
140 [WM8996_CONTROL_INTERFACE_1] = 0x8004,
141 [WM8996_CLOCKING_1] = 0x10,
142 [WM8996_AIF_RATE] = 0x83,
143 [WM8996_FLL_CONTROL_4] = 0x5dc0,
144 [WM8996_FLL_CONTROL_5] = 0xc84,
145 [WM8996_FLL_EFS_2] = 0x2,
146 [WM8996_AIF1_TX_LRCLK_1] = 0x80,
147 [WM8996_AIF1_TX_LRCLK_2] = 0x8,
148 [WM8996_AIF1_RX_LRCLK_1] = 0x80,
149 [WM8996_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
150 [WM8996_AIF1RX_DATA_CONFIGURATION] = 0x1818,
151 [WM8996_AIF1TX_TEST] = 0x7,
152 [WM8996_AIF2_TX_LRCLK_1] = 0x80,
153 [WM8996_AIF2_TX_LRCLK_2] = 0x8,
154 [WM8996_AIF2_RX_LRCLK_1] = 0x80,
155 [WM8996_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
156 [WM8996_AIF2RX_DATA_CONFIGURATION] = 0x1818,
157 [WM8996_AIF2TX_TEST] = 0x1,
158 [WM8996_DSP1_TX_LEFT_VOLUME] = 0xc0,
159 [WM8996_DSP1_TX_RIGHT_VOLUME] = 0xc0,
160 [WM8996_DSP1_RX_LEFT_VOLUME] = 0xc0,
161 [WM8996_DSP1_RX_RIGHT_VOLUME] = 0xc0,
162 [WM8996_DSP1_TX_FILTERS] = 0x2000,
163 [WM8996_DSP1_RX_FILTERS_1] = 0x200,
164 [WM8996_DSP1_RX_FILTERS_2] = 0x10,
165 [WM8996_DSP1_DRC_1] = 0x98,
166 [WM8996_DSP1_DRC_2] = 0x845,
167 [WM8996_DSP1_RX_EQ_GAINS_1] = 0x6318,
168 [WM8996_DSP1_RX_EQ_GAINS_2] = 0x6300,
169 [WM8996_DSP1_RX_EQ_BAND_1_A] = 0xfca,
170 [WM8996_DSP1_RX_EQ_BAND_1_B] = 0x400,
171 [WM8996_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
172 [WM8996_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
173 [WM8996_DSP1_RX_EQ_BAND_2_B] = 0xf145,
174 [WM8996_DSP1_RX_EQ_BAND_2_C] = 0xb75,
175 [WM8996_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
176 [WM8996_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
177 [WM8996_DSP1_RX_EQ_BAND_3_B] = 0xf373,
178 [WM8996_DSP1_RX_EQ_BAND_3_C] = 0xa54,
179 [WM8996_DSP1_RX_EQ_BAND_3_PG] = 0x558,
180 [WM8996_DSP1_RX_EQ_BAND_4_A] = 0x168e,
181 [WM8996_DSP1_RX_EQ_BAND_4_B] = 0xf829,
182 [WM8996_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
183 [WM8996_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
184 [WM8996_DSP1_RX_EQ_BAND_5_A] = 0x564,
185 [WM8996_DSP1_RX_EQ_BAND_5_B] = 0x559,
186 [WM8996_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
187 [WM8996_DSP2_TX_LEFT_VOLUME] = 0xc0,
188 [WM8996_DSP2_TX_RIGHT_VOLUME] = 0xc0,
189 [WM8996_DSP2_RX_LEFT_VOLUME] = 0xc0,
190 [WM8996_DSP2_RX_RIGHT_VOLUME] = 0xc0,
191 [WM8996_DSP2_TX_FILTERS] = 0x2000,
192 [WM8996_DSP2_RX_FILTERS_1] = 0x200,
193 [WM8996_DSP2_RX_FILTERS_2] = 0x10,
194 [WM8996_DSP2_DRC_1] = 0x98,
195 [WM8996_DSP2_DRC_2] = 0x845,
196 [WM8996_DSP2_RX_EQ_GAINS_1] = 0x6318,
197 [WM8996_DSP2_RX_EQ_GAINS_2] = 0x6300,
198 [WM8996_DSP2_RX_EQ_BAND_1_A] = 0xfca,
199 [WM8996_DSP2_RX_EQ_BAND_1_B] = 0x400,
200 [WM8996_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
201 [WM8996_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
202 [WM8996_DSP2_RX_EQ_BAND_2_B] = 0xf145,
203 [WM8996_DSP2_RX_EQ_BAND_2_C] = 0xb75,
204 [WM8996_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
205 [WM8996_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
206 [WM8996_DSP2_RX_EQ_BAND_3_B] = 0xf373,
207 [WM8996_DSP2_RX_EQ_BAND_3_C] = 0xa54,
208 [WM8996_DSP2_RX_EQ_BAND_3_PG] = 0x558,
209 [WM8996_DSP2_RX_EQ_BAND_4_A] = 0x168e,
210 [WM8996_DSP2_RX_EQ_BAND_4_B] = 0xf829,
211 [WM8996_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
212 [WM8996_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
213 [WM8996_DSP2_RX_EQ_BAND_5_A] = 0x564,
214 [WM8996_DSP2_RX_EQ_BAND_5_B] = 0x559,
215 [WM8996_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
216 [WM8996_OVERSAMPLING] = 0xd,
217 [WM8996_SIDETONE] = 0x1040,
218 [WM8996_GPIO_1] = 0xa101,
219 [WM8996_GPIO_2] = 0xa101,
220 [WM8996_GPIO_3] = 0xa101,
221 [WM8996_GPIO_4] = 0xa101,
222 [WM8996_GPIO_5] = 0xa101,
223 [WM8996_PULL_CONTROL_2] = 0x140,
224 [WM8996_INTERRUPT_STATUS_1_MASK] = 0x1f,
225 [WM8996_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
226 [WM8996_RIGHT_PDM_SPEAKER] = 0x1,
227 [WM8996_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
228 [WM8996_PDM_SPEAKER_VOLUME] = 0x66,
229 [WM8996_WRITE_SEQUENCER_0] = 0x1,
230 [WM8996_WRITE_SEQUENCER_1] = 0x1,
231 [WM8996_WRITE_SEQUENCER_3] = 0x6,
232 [WM8996_WRITE_SEQUENCER_4] = 0x40,
233 [WM8996_WRITE_SEQUENCER_5] = 0x1,
234 [WM8996_WRITE_SEQUENCER_6] = 0xf,
235 [WM8996_WRITE_SEQUENCER_7] = 0x6,
236 [WM8996_WRITE_SEQUENCER_8] = 0x1,
237 [WM8996_WRITE_SEQUENCER_9] = 0x3,
238 [WM8996_WRITE_SEQUENCER_10] = 0x104,
239 [WM8996_WRITE_SEQUENCER_12] = 0x60,
240 [WM8996_WRITE_SEQUENCER_13] = 0x11,
241 [WM8996_WRITE_SEQUENCER_14] = 0x401,
242 [WM8996_WRITE_SEQUENCER_16] = 0x50,
243 [WM8996_WRITE_SEQUENCER_17] = 0x3,
244 [WM8996_WRITE_SEQUENCER_18] = 0x100,
245 [WM8996_WRITE_SEQUENCER_20] = 0x51,
246 [WM8996_WRITE_SEQUENCER_21] = 0x3,
247 [WM8996_WRITE_SEQUENCER_22] = 0x104,
248 [WM8996_WRITE_SEQUENCER_23] = 0xa,
249 [WM8996_WRITE_SEQUENCER_24] = 0x60,
250 [WM8996_WRITE_SEQUENCER_25] = 0x3b,
251 [WM8996_WRITE_SEQUENCER_26] = 0x502,
252 [WM8996_WRITE_SEQUENCER_27] = 0x100,
253 [WM8996_WRITE_SEQUENCER_28] = 0x2fff,
254 [WM8996_WRITE_SEQUENCER_32] = 0x2fff,
255 [WM8996_WRITE_SEQUENCER_36] = 0x2fff,
256 [WM8996_WRITE_SEQUENCER_40] = 0x2fff,
257 [WM8996_WRITE_SEQUENCER_44] = 0x2fff,
258 [WM8996_WRITE_SEQUENCER_48] = 0x2fff,
259 [WM8996_WRITE_SEQUENCER_52] = 0x2fff,
260 [WM8996_WRITE_SEQUENCER_56] = 0x2fff,
261 [WM8996_WRITE_SEQUENCER_60] = 0x2fff,
262 [WM8996_WRITE_SEQUENCER_64] = 0x1,
263 [WM8996_WRITE_SEQUENCER_65] = 0x1,
264 [WM8996_WRITE_SEQUENCER_67] = 0x6,
265 [WM8996_WRITE_SEQUENCER_68] = 0x40,
266 [WM8996_WRITE_SEQUENCER_69] = 0x1,
267 [WM8996_WRITE_SEQUENCER_70] = 0xf,
268 [WM8996_WRITE_SEQUENCER_71] = 0x6,
269 [WM8996_WRITE_SEQUENCER_72] = 0x1,
270 [WM8996_WRITE_SEQUENCER_73] = 0x3,
271 [WM8996_WRITE_SEQUENCER_74] = 0x104,
272 [WM8996_WRITE_SEQUENCER_76] = 0x60,
273 [WM8996_WRITE_SEQUENCER_77] = 0x11,
274 [WM8996_WRITE_SEQUENCER_78] = 0x401,
275 [WM8996_WRITE_SEQUENCER_80] = 0x50,
276 [WM8996_WRITE_SEQUENCER_81] = 0x3,
277 [WM8996_WRITE_SEQUENCER_82] = 0x100,
278 [WM8996_WRITE_SEQUENCER_84] = 0x60,
279 [WM8996_WRITE_SEQUENCER_85] = 0x3b,
280 [WM8996_WRITE_SEQUENCER_86] = 0x502,
281 [WM8996_WRITE_SEQUENCER_87] = 0x100,
282 [WM8996_WRITE_SEQUENCER_88] = 0x2fff,
283 [WM8996_WRITE_SEQUENCER_92] = 0x2fff,
284 [WM8996_WRITE_SEQUENCER_96] = 0x2fff,
285 [WM8996_WRITE_SEQUENCER_100] = 0x2fff,
286 [WM8996_WRITE_SEQUENCER_104] = 0x2fff,
287 [WM8996_WRITE_SEQUENCER_108] = 0x2fff,
288 [WM8996_WRITE_SEQUENCER_112] = 0x2fff,
289 [WM8996_WRITE_SEQUENCER_116] = 0x2fff,
290 [WM8996_WRITE_SEQUENCER_120] = 0x2fff,
291 [WM8996_WRITE_SEQUENCER_124] = 0x2fff,
292 [WM8996_WRITE_SEQUENCER_128] = 0x1,
293 [WM8996_WRITE_SEQUENCER_129] = 0x1,
294 [WM8996_WRITE_SEQUENCER_131] = 0x6,
295 [WM8996_WRITE_SEQUENCER_132] = 0x40,
296 [WM8996_WRITE_SEQUENCER_133] = 0x1,
297 [WM8996_WRITE_SEQUENCER_134] = 0xf,
298 [WM8996_WRITE_SEQUENCER_135] = 0x6,
299 [WM8996_WRITE_SEQUENCER_136] = 0x1,
300 [WM8996_WRITE_SEQUENCER_137] = 0x3,
301 [WM8996_WRITE_SEQUENCER_138] = 0x106,
302 [WM8996_WRITE_SEQUENCER_140] = 0x61,
303 [WM8996_WRITE_SEQUENCER_141] = 0x11,
304 [WM8996_WRITE_SEQUENCER_142] = 0x401,
305 [WM8996_WRITE_SEQUENCER_144] = 0x50,
306 [WM8996_WRITE_SEQUENCER_145] = 0x3,
307 [WM8996_WRITE_SEQUENCER_146] = 0x102,
308 [WM8996_WRITE_SEQUENCER_148] = 0x51,
309 [WM8996_WRITE_SEQUENCER_149] = 0x3,
310 [WM8996_WRITE_SEQUENCER_150] = 0x106,
311 [WM8996_WRITE_SEQUENCER_151] = 0xa,
312 [WM8996_WRITE_SEQUENCER_152] = 0x61,
313 [WM8996_WRITE_SEQUENCER_153] = 0x3b,
314 [WM8996_WRITE_SEQUENCER_154] = 0x502,
315 [WM8996_WRITE_SEQUENCER_155] = 0x100,
316 [WM8996_WRITE_SEQUENCER_156] = 0x2fff,
317 [WM8996_WRITE_SEQUENCER_160] = 0x2fff,
318 [WM8996_WRITE_SEQUENCER_164] = 0x2fff,
319 [WM8996_WRITE_SEQUENCER_168] = 0x2fff,
320 [WM8996_WRITE_SEQUENCER_172] = 0x2fff,
321 [WM8996_WRITE_SEQUENCER_176] = 0x2fff,
322 [WM8996_WRITE_SEQUENCER_180] = 0x2fff,
323 [WM8996_WRITE_SEQUENCER_184] = 0x2fff,
324 [WM8996_WRITE_SEQUENCER_188] = 0x2fff,
325 [WM8996_WRITE_SEQUENCER_192] = 0x1,
326 [WM8996_WRITE_SEQUENCER_193] = 0x1,
327 [WM8996_WRITE_SEQUENCER_195] = 0x6,
328 [WM8996_WRITE_SEQUENCER_196] = 0x40,
329 [WM8996_WRITE_SEQUENCER_197] = 0x1,
330 [WM8996_WRITE_SEQUENCER_198] = 0xf,
331 [WM8996_WRITE_SEQUENCER_199] = 0x6,
332 [WM8996_WRITE_SEQUENCER_200] = 0x1,
333 [WM8996_WRITE_SEQUENCER_201] = 0x3,
334 [WM8996_WRITE_SEQUENCER_202] = 0x106,
335 [WM8996_WRITE_SEQUENCER_204] = 0x61,
336 [WM8996_WRITE_SEQUENCER_205] = 0x11,
337 [WM8996_WRITE_SEQUENCER_206] = 0x401,
338 [WM8996_WRITE_SEQUENCER_208] = 0x50,
339 [WM8996_WRITE_SEQUENCER_209] = 0x3,
340 [WM8996_WRITE_SEQUENCER_210] = 0x102,
341 [WM8996_WRITE_SEQUENCER_212] = 0x61,
342 [WM8996_WRITE_SEQUENCER_213] = 0x3b,
343 [WM8996_WRITE_SEQUENCER_214] = 0x502,
344 [WM8996_WRITE_SEQUENCER_215] = 0x100,
345 [WM8996_WRITE_SEQUENCER_216] = 0x2fff,
346 [WM8996_WRITE_SEQUENCER_220] = 0x2fff,
347 [WM8996_WRITE_SEQUENCER_224] = 0x2fff,
348 [WM8996_WRITE_SEQUENCER_228] = 0x2fff,
349 [WM8996_WRITE_SEQUENCER_232] = 0x2fff,
350 [WM8996_WRITE_SEQUENCER_236] = 0x2fff,
351 [WM8996_WRITE_SEQUENCER_240] = 0x2fff,
352 [WM8996_WRITE_SEQUENCER_244] = 0x2fff,
353 [WM8996_WRITE_SEQUENCER_248] = 0x2fff,
354 [WM8996_WRITE_SEQUENCER_252] = 0x2fff,
355 [WM8996_WRITE_SEQUENCER_256] = 0x60,
356 [WM8996_WRITE_SEQUENCER_258] = 0x601,
357 [WM8996_WRITE_SEQUENCER_260] = 0x50,
358 [WM8996_WRITE_SEQUENCER_262] = 0x100,
359 [WM8996_WRITE_SEQUENCER_264] = 0x1,
360 [WM8996_WRITE_SEQUENCER_266] = 0x104,
361 [WM8996_WRITE_SEQUENCER_267] = 0x100,
362 [WM8996_WRITE_SEQUENCER_268] = 0x2fff,
363 [WM8996_WRITE_SEQUENCER_272] = 0x2fff,
364 [WM8996_WRITE_SEQUENCER_276] = 0x2fff,
365 [WM8996_WRITE_SEQUENCER_280] = 0x2fff,
366 [WM8996_WRITE_SEQUENCER_284] = 0x2fff,
367 [WM8996_WRITE_SEQUENCER_288] = 0x2fff,
368 [WM8996_WRITE_SEQUENCER_292] = 0x2fff,
369 [WM8996_WRITE_SEQUENCER_296] = 0x2fff,
370 [WM8996_WRITE_SEQUENCER_300] = 0x2fff,
371 [WM8996_WRITE_SEQUENCER_304] = 0x2fff,
372 [WM8996_WRITE_SEQUENCER_308] = 0x2fff,
373 [WM8996_WRITE_SEQUENCER_312] = 0x2fff,
374 [WM8996_WRITE_SEQUENCER_316] = 0x2fff,
375 [WM8996_WRITE_SEQUENCER_320] = 0x61,
376 [WM8996_WRITE_SEQUENCER_322] = 0x601,
377 [WM8996_WRITE_SEQUENCER_324] = 0x50,
378 [WM8996_WRITE_SEQUENCER_326] = 0x102,
379 [WM8996_WRITE_SEQUENCER_328] = 0x1,
380 [WM8996_WRITE_SEQUENCER_330] = 0x106,
381 [WM8996_WRITE_SEQUENCER_331] = 0x100,
382 [WM8996_WRITE_SEQUENCER_332] = 0x2fff,
383 [WM8996_WRITE_SEQUENCER_336] = 0x2fff,
384 [WM8996_WRITE_SEQUENCER_340] = 0x2fff,
385 [WM8996_WRITE_SEQUENCER_344] = 0x2fff,
386 [WM8996_WRITE_SEQUENCER_348] = 0x2fff,
387 [WM8996_WRITE_SEQUENCER_352] = 0x2fff,
388 [WM8996_WRITE_SEQUENCER_356] = 0x2fff,
389 [WM8996_WRITE_SEQUENCER_360] = 0x2fff,
390 [WM8996_WRITE_SEQUENCER_364] = 0x2fff,
391 [WM8996_WRITE_SEQUENCER_368] = 0x2fff,
392 [WM8996_WRITE_SEQUENCER_372] = 0x2fff,
393 [WM8996_WRITE_SEQUENCER_376] = 0x2fff,
394 [WM8996_WRITE_SEQUENCER_380] = 0x2fff,
395 [WM8996_WRITE_SEQUENCER_384] = 0x60,
396 [WM8996_WRITE_SEQUENCER_386] = 0x601,
397 [WM8996_WRITE_SEQUENCER_388] = 0x61,
398 [WM8996_WRITE_SEQUENCER_390] = 0x601,
399 [WM8996_WRITE_SEQUENCER_392] = 0x50,
400 [WM8996_WRITE_SEQUENCER_394] = 0x300,
401 [WM8996_WRITE_SEQUENCER_396] = 0x1,
402 [WM8996_WRITE_SEQUENCER_398] = 0x304,
403 [WM8996_WRITE_SEQUENCER_400] = 0x40,
404 [WM8996_WRITE_SEQUENCER_402] = 0xf,
405 [WM8996_WRITE_SEQUENCER_404] = 0x1,
406 [WM8996_WRITE_SEQUENCER_407] = 0x100,
407};
408
409static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
410static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
411static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
412static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
413static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
414static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
415static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
18a4eef3 416static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
a9ba6151
MB		 417
418static const char *sidetone_hpf_text[] = {
419 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
420};
421
422static const struct soc_enum sidetone_hpf =
18036b58 423 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
a9ba6151
MB		 424
425static const char *hpf_mode_text[] = {
426 "HiFi", "Custom", "Voice"
427};
428
429static const struct soc_enum dsp1tx_hpf_mode =
430 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
431
432static const struct soc_enum dsp2tx_hpf_mode =
433 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
434
435static const char *hpf_cutoff_text[] = {
436 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
437};
438
439static const struct soc_enum dsp1tx_hpf_cutoff =
440 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
441
442static const struct soc_enum dsp2tx_hpf_cutoff =
443 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
444
445static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
446{
447 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
448 struct wm8996_pdata *pdata = &wm8996->pdata;
449 int base, best, best_val, save, i, cfg, iface;
450
451 if (!wm8996->num_retune_mobile_texts)
452 return;
453
454 switch (block) {
455 case 0:
456 base = WM8996_DSP1_RX_EQ_GAINS_1;
457 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
458 WM8996_DSP1RX_SRC)
459 iface = 1;
460 else
461 iface = 0;
462 break;
463 case 1:
464 base = WM8996_DSP1_RX_EQ_GAINS_2;
465 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
466 WM8996_DSP2RX_SRC)
467 iface = 1;
468 else
469 iface = 0;
470 break;
471 default:
472 return;
473 }
474
475 /* Find the version of the currently selected configuration
476 * with the nearest sample rate. */
477 cfg = wm8996->retune_mobile_cfg[block];
478 best = 0;
479 best_val = INT_MAX;
480 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
481 if (strcmp(pdata->retune_mobile_cfgs[i].name,
482 wm8996->retune_mobile_texts[cfg]) == 0 &&
483 abs(pdata->retune_mobile_cfgs[i].rate
484 - wm8996->rx_rate[iface]) < best_val) {
485 best = i;
486 best_val = abs(pdata->retune_mobile_cfgs[i].rate
487 - wm8996->rx_rate[iface]);
488 }
489 }
490
491 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
492 block,
493 pdata->retune_mobile_cfgs[best].name,
494 pdata->retune_mobile_cfgs[best].rate,
495 wm8996->rx_rate[iface]);
496
497 /* The EQ will be disabled while reconfiguring it, remember the
498 * current configuration.
499 */
500 save = snd_soc_read(codec, base);
501 save &= WM8996_DSP1RX_EQ_ENA;
502
503 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
504 snd_soc_update_bits(codec, base + i, 0xffff,
505 pdata->retune_mobile_cfgs[best].regs[i]);
506
507 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
508}
509
510/* Icky as hell but saves code duplication */
511static int wm8996_get_retune_mobile_block(const char *name)
512{
513 if (strcmp(name, "DSP1 EQ Mode") == 0)
514 return 0;
515 if (strcmp(name, "DSP2 EQ Mode") == 0)
516 return 1;
517 return -EINVAL;
518}
519
520static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol)
522{
523 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
524 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
525 struct wm8996_pdata *pdata = &wm8996->pdata;
526 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
527 int value = ucontrol->value.integer.value[0];
528
529 if (block < 0)
530 return block;
531
532 if (value >= pdata->num_retune_mobile_cfgs)
533 return -EINVAL;
534
535 wm8996->retune_mobile_cfg[block] = value;
536
537 wm8996_set_retune_mobile(codec, block);
538
539 return 0;
540}
541
542static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
543 struct snd_ctl_elem_value *ucontrol)
544{
545 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
546 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
547 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
548
549 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
550
551 return 0;
552}
553
554static const struct snd_kcontrol_new wm8996_snd_controls[] = {
555SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
556 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
557SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
558 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
559
560SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
561 0, 5, 24, 0, sidetone_tlv),
562SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
563 0, 5, 24, 0, sidetone_tlv),
564SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
565SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
566SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
567
568SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
569 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
570SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
571 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
572
573SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
574 13, 1, 0),
575SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
576SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
577SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
578
579SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
580 13, 1, 0),
581SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
582SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
583SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
584
585SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
586 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
587SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
588
589SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
590 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
591SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
592
593SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
594 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
595SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
596 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
597
598SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
599 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
600SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
601 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
602
603SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
604SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
605SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
606SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
607
608SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
609SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
610
18a4eef3 611SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
612SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
613
614SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
615 0, threedstereo_tlv),
616SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
617 0, threedstereo_tlv),
618
a9ba6151
MB		 619SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
620 8, 0, out_digital_tlv),
621SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
622 8, 0, out_digital_tlv),
623
624SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
625 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
626SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
627 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
628
629SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
630 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
631SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
632 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
633
634SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
635 spk_tlv),
636SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
637 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
638SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
639 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
640
641SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
642SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
643};
644
645static const struct snd_kcontrol_new wm8996_eq_controls[] = {
646SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
649 eq_tlv),
650SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
651 eq_tlv),
652SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
653 eq_tlv),
654SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
655 eq_tlv),
656
657SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
660 eq_tlv),
661SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
662 eq_tlv),
663SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
664 eq_tlv),
665SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
666 eq_tlv),
667};
668
8259df12
MB		 669static int bg_event(struct snd_soc_dapm_widget *w,
670 struct snd_kcontrol *kcontrol, int event)
671{
8259df12
MB		 672 int ret = 0;
673
674 switch (event) {
675 case SND_SOC_DAPM_POST_PMU:
676 msleep(2);
677 break;
678 default:
679 BUG();
680 ret = -EINVAL;
681 }
682
683 return ret;
684}
685
a9ba6151
MB		 686static int cp_event(struct snd_soc_dapm_widget *w,
687 struct snd_kcontrol *kcontrol, int event)
688{
c83495af
MB		 689 struct snd_soc_codec *codec = w->codec;
690 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
691 int ret = 0;
692
a9ba6151 693 switch (event) {
c83495af
MB		 694 case SND_SOC_DAPM_PRE_PMU:
695 ret = regulator_enable(wm8996->cpvdd);
696 if (ret != 0)
697 dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
698 ret);
699 break;
a9ba6151
MB		 700 case SND_SOC_DAPM_POST_PMU:
701 msleep(5);
702 break;
c83495af
MB		 703 case SND_SOC_DAPM_POST_PMD:
704 regulator_disable_deferred(wm8996->cpvdd, 20);
705 break;
a9ba6151
MB		 706 default:
707 BUG();
c83495af 708 ret = -EINVAL;
a9ba6151
MB		 709 }
710
c83495af 711 return ret;
a9ba6151
MB		 712}
713
714static int rmv_short_event(struct snd_soc_dapm_widget *w,
715 struct snd_kcontrol *kcontrol, int event)
716{
717 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
718
719 /* Record which outputs we enabled */
720 switch (event) {
721 case SND_SOC_DAPM_PRE_PMD:
722 wm8996->hpout_pending &= ~w->shift;
723 break;
724 case SND_SOC_DAPM_PRE_PMU:
725 wm8996->hpout_pending |= w->shift;
726 break;
727 default:
728 BUG();
729 return -EINVAL;
730 }
731
732 return 0;
733}
734
735static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
736{
737 struct i2c_client *i2c = to_i2c_client(codec->dev);
738 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
f998f257 739 int ret;
a9ba6151
MB		 740 unsigned long timeout = 200;
741
742 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
743
744 /* Use the interrupt if possible */
745 do {
746 if (i2c->irq) {
747 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
748 msecs_to_jiffies(200));
749 if (timeout == 0)
750 dev_err(codec->dev, "DC servo timed out\n");
751
752 } else {
753 msleep(1);
f998f257 754 timeout--;
a9ba6151
MB		 755 }
756
757 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
758 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
f998f257 759 } while (timeout && ret & mask);
a9ba6151
MB		 760
761 if (timeout == 0)
762 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
763 else
764 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
765}
766
767static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
768 enum snd_soc_dapm_type event, int subseq)
769{
770 struct snd_soc_codec *codec = container_of(dapm,
771 struct snd_soc_codec, dapm);
772 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
773 u16 val, mask;
774
775 /* Complete any pending DC servo starts */
776 if (wm8996->dcs_pending) {
777 dev_dbg(codec->dev, "Starting DC servo for %x\n",
778 wm8996->dcs_pending);
779
780 /* Trigger a startup sequence */
781 wait_for_dc_servo(codec, wm8996->dcs_pending
782 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
783
784 wm8996->dcs_pending = 0;
785 }
786
787 if (wm8996->hpout_pending != wm8996->hpout_ena) {
788 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
789 wm8996->hpout_ena, wm8996->hpout_pending);
790
791 val = 0;
792 mask = 0;
793 if (wm8996->hpout_pending & HPOUT1L) {
794 val |= WM8996_HPOUT1L_RMV_SHORT;
795 mask |= WM8996_HPOUT1L_RMV_SHORT;
796 } else {
797 mask |= WM8996_HPOUT1L_RMV_SHORT |
798 WM8996_HPOUT1L_OUTP |
799 WM8996_HPOUT1L_DLY;
800 }
801
802 if (wm8996->hpout_pending & HPOUT1R) {
803 val |= WM8996_HPOUT1R_RMV_SHORT;
804 mask |= WM8996_HPOUT1R_RMV_SHORT;
805 } else {
806 mask |= WM8996_HPOUT1R_RMV_SHORT |
807 WM8996_HPOUT1R_OUTP |
808 WM8996_HPOUT1R_DLY;
809 }
810
811 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
812
813 val = 0;
814 mask = 0;
815 if (wm8996->hpout_pending & HPOUT2L) {
816 val |= WM8996_HPOUT2L_RMV_SHORT;
817 mask |= WM8996_HPOUT2L_RMV_SHORT;
818 } else {
819 mask |= WM8996_HPOUT2L_RMV_SHORT |
820 WM8996_HPOUT2L_OUTP |
821 WM8996_HPOUT2L_DLY;
822 }
823
824 if (wm8996->hpout_pending & HPOUT2R) {
825 val |= WM8996_HPOUT2R_RMV_SHORT;
826 mask |= WM8996_HPOUT2R_RMV_SHORT;
827 } else {
828 mask |= WM8996_HPOUT2R_RMV_SHORT |
829 WM8996_HPOUT2R_OUTP |
830 WM8996_HPOUT2R_DLY;
831 }
832
833 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
834
835 wm8996->hpout_ena = wm8996->hpout_pending;
836 }
837}
838
839static int dcs_start(struct snd_soc_dapm_widget *w,
840 struct snd_kcontrol *kcontrol, int event)
841{
842 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
843
844 switch (event) {
845 case SND_SOC_DAPM_POST_PMU:
846 wm8996->dcs_pending |= 1 << w->shift;
847 break;
848 default:
849 BUG();
850 return -EINVAL;
851 }
852
853 return 0;
854}
855
856static const char *sidetone_text[] = {
857 "IN1", "IN2",
858};
859
860static const struct soc_enum left_sidetone_enum =
861 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
862
863static const struct snd_kcontrol_new left_sidetone =
864 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
865
866static const struct soc_enum right_sidetone_enum =
867 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
868
869static const struct snd_kcontrol_new right_sidetone =
870 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
871
872static const char *spk_text[] = {
873 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
874};
875
876static const struct soc_enum spkl_enum =
877 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
878
879static const struct snd_kcontrol_new spkl_mux =
880 SOC_DAPM_ENUM("SPKL", spkl_enum);
881
882static const struct soc_enum spkr_enum =
883 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
884
885static const struct snd_kcontrol_new spkr_mux =
886 SOC_DAPM_ENUM("SPKR", spkr_enum);
887
888static const char *dsp1rx_text[] = {
889 "AIF1", "AIF2"
890};
891
892static const struct soc_enum dsp1rx_enum =
893 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
894
895static const struct snd_kcontrol_new dsp1rx =
896 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
897
898static const char *dsp2rx_text[] = {
899 "AIF2", "AIF1"
900};
901
902static const struct soc_enum dsp2rx_enum =
903 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
904
905static const struct snd_kcontrol_new dsp2rx =
906 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
907
908static const char *aif2tx_text[] = {
909 "DSP2", "DSP1", "AIF1"
910};
911
912static const struct soc_enum aif2tx_enum =
913 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
914
915static const struct snd_kcontrol_new aif2tx =
916 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
917
918static const char *inmux_text[] = {
919 "ADC", "DMIC1", "DMIC2"
920};
921
922static const struct soc_enum in1_enum =
923 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
924
925static const struct snd_kcontrol_new in1_mux =
926 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
927
928static const struct soc_enum in2_enum =
929 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
930
931static const struct snd_kcontrol_new in2_mux =
932 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
933
934static const struct snd_kcontrol_new dac2r_mix[] = {
935SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
936 5, 1, 0),
937SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
938 4, 1, 0),
939SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
940SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
941};
942
943static const struct snd_kcontrol_new dac2l_mix[] = {
944SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
945 5, 1, 0),
946SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
947 4, 1, 0),
948SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
949SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
950};
951
952static const struct snd_kcontrol_new dac1r_mix[] = {
953SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
954 5, 1, 0),
955SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
956 4, 1, 0),
957SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
958SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
959};
960
961static const struct snd_kcontrol_new dac1l_mix[] = {
962SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
963 5, 1, 0),
964SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
965 4, 1, 0),
966SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
967SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
968};
969
970static const struct snd_kcontrol_new dsp1txl[] = {
971SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
972 1, 1, 0),
973SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
974 0, 1, 0),
975};
976
977static const struct snd_kcontrol_new dsp1txr[] = {
978SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
979 1, 1, 0),
980SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
981 0, 1, 0),
982};
983
984static const struct snd_kcontrol_new dsp2txl[] = {
985SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
986 1, 1, 0),
987SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
988 0, 1, 0),
989};
990
991static const struct snd_kcontrol_new dsp2txr[] = {
992SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
993 1, 1, 0),
994SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
995 0, 1, 0),
996};
997
998
999static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
1000SND_SOC_DAPM_INPUT("IN1LN"),
1001SND_SOC_DAPM_INPUT("IN1LP"),
1002SND_SOC_DAPM_INPUT("IN1RN"),
1003SND_SOC_DAPM_INPUT("IN1RP"),
1004
1005SND_SOC_DAPM_INPUT("IN2LN"),
1006SND_SOC_DAPM_INPUT("IN2LP"),
1007SND_SOC_DAPM_INPUT("IN2RN"),
1008SND_SOC_DAPM_INPUT("IN2RP"),
1009
1010SND_SOC_DAPM_INPUT("DMIC1DAT"),
1011SND_SOC_DAPM_INPUT("DMIC2DAT"),
1012
1013SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
1014SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
1015SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
1016SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
c83495af
MB		 1017 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1018 SND_SOC_DAPM_POST_PMD),
8259df12
MB		 1019SND_SOC_DAPM_SUPPLY("Bandgap", WM8996_POWER_MANAGEMENT_1, WM8996_BG_ENA_SHIFT,
1020 0, bg_event, SND_SOC_DAPM_POST_PMU),
a9ba6151 1021SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
889c85c5
MB		 1022SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
1023SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
a9ba6151
MB		 1024SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
1025SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
1026
1027SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
1028SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
1029
7691cd74
MB		 1030SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
1031SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
1032SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
1033SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
a9ba6151
MB		 1034
1035SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1036SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1037
1038SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1039SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1040SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1041SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1042
1043SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1044SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1045
1046SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1047SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1048
1049SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1050SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1051SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1052SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1053
1054SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1055 dsp2txl, ARRAY_SIZE(dsp2txl)),
1056SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1057 dsp2txr, ARRAY_SIZE(dsp2txr)),
1058SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1059 dsp1txl, ARRAY_SIZE(dsp1txl)),
1060SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1061 dsp1txr, ARRAY_SIZE(dsp1txr)),
1062
1063SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1064 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1065SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1066 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1067SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1068 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1069SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1070 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1071
1072SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1073SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1074SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1075SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1076
32d2a0c1 1077SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
a9ba6151 1078 WM8996_POWER_MANAGEMENT_4, 9, 0),
32d2a0c1 1079SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 1,
a9ba6151
MB		 1080 WM8996_POWER_MANAGEMENT_4, 8, 0),
1081
32d2a0c1 1082SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 0,
a9ba6151 1083 WM8996_POWER_MANAGEMENT_6, 9, 0),
32d2a0c1 1084SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 1,
a9ba6151
MB		 1085 WM8996_POWER_MANAGEMENT_6, 8, 0),
1086
1087SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1088 WM8996_POWER_MANAGEMENT_4, 5, 0),
1089SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1090 WM8996_POWER_MANAGEMENT_4, 4, 0),
1091SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1092 WM8996_POWER_MANAGEMENT_4, 3, 0),
1093SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1094 WM8996_POWER_MANAGEMENT_4, 2, 0),
1095SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1096 WM8996_POWER_MANAGEMENT_4, 1, 0),
1097SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1098 WM8996_POWER_MANAGEMENT_4, 0, 0),
1099
1100SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1101 WM8996_POWER_MANAGEMENT_6, 5, 0),
1102SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1103 WM8996_POWER_MANAGEMENT_6, 4, 0),
1104SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1105 WM8996_POWER_MANAGEMENT_6, 3, 0),
1106SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1107 WM8996_POWER_MANAGEMENT_6, 2, 0),
1108SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1109 WM8996_POWER_MANAGEMENT_6, 1, 0),
1110SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1111 WM8996_POWER_MANAGEMENT_6, 0, 0),
1112
1113/* We route as stereo pairs so define some dummy widgets to squash
1114 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1115SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1116SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1117SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1118SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1119SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1120
1121SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1122SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1123SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1124
1125SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1126SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1127SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1128SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1129
1130SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1131SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1132SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1133 SND_SOC_DAPM_POST_PMU),
1134SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1135SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1136 rmv_short_event,
1137 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1138
1139SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1140SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1141SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1142 SND_SOC_DAPM_POST_PMU),
1143SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1144SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1145 rmv_short_event,
1146 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1147
1148SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1149SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1150SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1151 SND_SOC_DAPM_POST_PMU),
1152SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1153SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1154 rmv_short_event,
1155 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1156
1157SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1158SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1159SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1160 SND_SOC_DAPM_POST_PMU),
1161SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1162SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1163 rmv_short_event,
1164 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1165
1166SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1167SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1168SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1169SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1170SND_SOC_DAPM_OUTPUT("SPKDAT"),
1171};
1172
1173static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1174 { "AIFCLK", NULL, "SYSCLK" },
1175 { "SYSDSPCLK", NULL, "SYSCLK" },
1176 { "Charge Pump", NULL, "SYSCLK" },
1177
1178 { "MICB1", NULL, "LDO2" },
889c85c5 1179 { "MICB1", NULL, "MICB1 Audio" },
8259df12 1180 { "MICB1", NULL, "Bandgap" },
a9ba6151 1181 { "MICB2", NULL, "LDO2" },
889c85c5 1182 { "MICB2", NULL, "MICB2 Audio" },
8259df12 1183 { "MICB2", NULL, "Bandgap" },
a9ba6151
MB		 1184
1185 { "IN1L PGA", NULL, "IN2LN" },
1186 { "IN1L PGA", NULL, "IN2LP" },
1187 { "IN1L PGA", NULL, "IN1LN" },
1188 { "IN1L PGA", NULL, "IN1LP" },
8259df12 1189 { "IN1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1190
1191 { "IN1R PGA", NULL, "IN2RN" },
1192 { "IN1R PGA", NULL, "IN2RP" },
1193 { "IN1R PGA", NULL, "IN1RN" },
1194 { "IN1R PGA", NULL, "IN1RP" },
8259df12 1195 { "IN1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1196
1197 { "ADCL", NULL, "IN1L PGA" },
1198
1199 { "ADCR", NULL, "IN1R PGA" },
1200
1201 { "DMIC1L", NULL, "DMIC1DAT" },
1202 { "DMIC1R", NULL, "DMIC1DAT" },
1203 { "DMIC2L", NULL, "DMIC2DAT" },
1204 { "DMIC2R", NULL, "DMIC2DAT" },
1205
1206 { "DMIC2L", NULL, "DMIC2" },
1207 { "DMIC2R", NULL, "DMIC2" },
1208 { "DMIC1L", NULL, "DMIC1" },
1209 { "DMIC1R", NULL, "DMIC1" },
1210
1211 { "IN1L Mux", "ADC", "ADCL" },
1212 { "IN1L Mux", "DMIC1", "DMIC1L" },
1213 { "IN1L Mux", "DMIC2", "DMIC2L" },
1214
1215 { "IN1R Mux", "ADC", "ADCR" },
1216 { "IN1R Mux", "DMIC1", "DMIC1R" },
1217 { "IN1R Mux", "DMIC2", "DMIC2R" },
1218
1219 { "IN2L Mux", "ADC", "ADCL" },
1220 { "IN2L Mux", "DMIC1", "DMIC1L" },
1221 { "IN2L Mux", "DMIC2", "DMIC2L" },
1222
1223 { "IN2R Mux", "ADC", "ADCR" },
1224 { "IN2R Mux", "DMIC1", "DMIC1R" },
1225 { "IN2R Mux", "DMIC2", "DMIC2R" },
1226
1227 { "Left Sidetone", "IN1", "IN1L Mux" },
1228 { "Left Sidetone", "IN2", "IN2L Mux" },
1229
1230 { "Right Sidetone", "IN1", "IN1R Mux" },
1231 { "Right Sidetone", "IN2", "IN2R Mux" },
1232
1233 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1234 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1235
1236 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1237 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1238
1239 { "AIF1TX0", NULL, "DSP1TXL" },
1240 { "AIF1TX1", NULL, "DSP1TXR" },
1241 { "AIF1TX2", NULL, "DSP2TXL" },
1242 { "AIF1TX3", NULL, "DSP2TXR" },
1243 { "AIF1TX4", NULL, "AIF2RX0" },
1244 { "AIF1TX5", NULL, "AIF2RX1" },
1245
1246 { "AIF1RX0", NULL, "AIFCLK" },
1247 { "AIF1RX1", NULL, "AIFCLK" },
1248 { "AIF1RX2", NULL, "AIFCLK" },
1249 { "AIF1RX3", NULL, "AIFCLK" },
1250 { "AIF1RX4", NULL, "AIFCLK" },
1251 { "AIF1RX5", NULL, "AIFCLK" },
1252
1253 { "AIF2RX0", NULL, "AIFCLK" },
1254 { "AIF2RX1", NULL, "AIFCLK" },
1255
4f41adfd
MB		 1256 { "AIF1TX0", NULL, "AIFCLK" },
1257 { "AIF1TX1", NULL, "AIFCLK" },
1258 { "AIF1TX2", NULL, "AIFCLK" },
1259 { "AIF1TX3", NULL, "AIFCLK" },
1260 { "AIF1TX4", NULL, "AIFCLK" },
1261 { "AIF1TX5", NULL, "AIFCLK" },
1262
1263 { "AIF2TX0", NULL, "AIFCLK" },
1264 { "AIF2TX1", NULL, "AIFCLK" },
1265
a9ba6151
MB		 1266 { "DSP1RXL", NULL, "SYSDSPCLK" },
1267 { "DSP1RXR", NULL, "SYSDSPCLK" },
1268 { "DSP2RXL", NULL, "SYSDSPCLK" },
1269 { "DSP2RXR", NULL, "SYSDSPCLK" },
1270 { "DSP1TXL", NULL, "SYSDSPCLK" },
1271 { "DSP1TXR", NULL, "SYSDSPCLK" },
1272 { "DSP2TXL", NULL, "SYSDSPCLK" },
1273 { "DSP2TXR", NULL, "SYSDSPCLK" },
1274
1275 { "AIF1RXA", NULL, "AIF1RX0" },
1276 { "AIF1RXA", NULL, "AIF1RX1" },
1277 { "AIF1RXB", NULL, "AIF1RX2" },
1278 { "AIF1RXB", NULL, "AIF1RX3" },
1279 { "AIF1RXC", NULL, "AIF1RX4" },
1280 { "AIF1RXC", NULL, "AIF1RX5" },
1281
1282 { "AIF2RX", NULL, "AIF2RX0" },
1283 { "AIF2RX", NULL, "AIF2RX1" },
1284
1285 { "AIF2TX", "DSP2", "DSP2TX" },
1286 { "AIF2TX", "DSP1", "DSP1RX" },
1287 { "AIF2TX", "AIF1", "AIF1RXC" },
1288
1289 { "DSP1RXL", NULL, "DSP1RX" },
1290 { "DSP1RXR", NULL, "DSP1RX" },
1291 { "DSP2RXL", NULL, "DSP2RX" },
1292 { "DSP2RXR", NULL, "DSP2RX" },
1293
1294 { "DSP2TX", NULL, "DSP2TXL" },
1295 { "DSP2TX", NULL, "DSP2TXR" },
1296
1297 { "DSP1RX", "AIF1", "AIF1RXA" },
1298 { "DSP1RX", "AIF2", "AIF2RX" },
1299
1300 { "DSP2RX", "AIF1", "AIF1RXB" },
1301 { "DSP2RX", "AIF2", "AIF2RX" },
1302
1303 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1304 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1305 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1306 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1307
1308 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1309 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1310 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1311 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1312
1313 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1314 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1315 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1316 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1317
1318 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1319 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1320 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1321 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1322
1323 { "DAC1L", NULL, "DAC1L Mixer" },
1324 { "DAC1R", NULL, "DAC1R Mixer" },
1325 { "DAC2L", NULL, "DAC2L Mixer" },
1326 { "DAC2R", NULL, "DAC2R Mixer" },
1327
1328 { "HPOUT2L PGA", NULL, "Charge Pump" },
8259df12 1329 { "HPOUT2L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1330 { "HPOUT2L PGA", NULL, "DAC2L" },
1331 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1332 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1333 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1334 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1335
1336 { "HPOUT2R PGA", NULL, "Charge Pump" },
8259df12 1337 { "HPOUT2R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1338 { "HPOUT2R PGA", NULL, "DAC2R" },
1339 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1340 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1341 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1342 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1343
1344 { "HPOUT1L PGA", NULL, "Charge Pump" },
8259df12 1345 { "HPOUT1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1346 { "HPOUT1L PGA", NULL, "DAC1L" },
1347 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1348 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1349 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1350 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1351
1352 { "HPOUT1R PGA", NULL, "Charge Pump" },
8259df12 1353 { "HPOUT1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1354 { "HPOUT1R PGA", NULL, "DAC1R" },
1355 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1356 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1357 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1358 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1359
1360 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1361 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1362 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1363 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1364
1365 { "SPKL", "DAC1L", "DAC1L" },
1366 { "SPKL", "DAC1R", "DAC1R" },
1367 { "SPKL", "DAC2L", "DAC2L" },
1368 { "SPKL", "DAC2R", "DAC2R" },
1369
1370 { "SPKR", "DAC1L", "DAC1L" },
1371 { "SPKR", "DAC1R", "DAC1R" },
1372 { "SPKR", "DAC2L", "DAC2L" },
1373 { "SPKR", "DAC2R", "DAC2R" },
1374
1375 { "SPKL PGA", NULL, "SPKL" },
1376 { "SPKR PGA", NULL, "SPKR" },
1377
1378 { "SPKDAT", NULL, "SPKL PGA" },
1379 { "SPKDAT", NULL, "SPKR PGA" },
1380};
1381
1382static int wm8996_readable_register(struct snd_soc_codec *codec,
1383 unsigned int reg)
1384{
1385 /* Due to the sparseness of the register map the compiler
1386 * output from an explicit switch statement ends up being much
1387 * more efficient than a table.
1388 */
1389 switch (reg) {
1390 case WM8996_SOFTWARE_RESET:
1391 case WM8996_POWER_MANAGEMENT_1:
1392 case WM8996_POWER_MANAGEMENT_2:
1393 case WM8996_POWER_MANAGEMENT_3:
1394 case WM8996_POWER_MANAGEMENT_4:
1395 case WM8996_POWER_MANAGEMENT_5:
1396 case WM8996_POWER_MANAGEMENT_6:
1397 case WM8996_POWER_MANAGEMENT_7:
1398 case WM8996_POWER_MANAGEMENT_8:
1399 case WM8996_LEFT_LINE_INPUT_VOLUME:
1400 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1401 case WM8996_LINE_INPUT_CONTROL:
1402 case WM8996_DAC1_HPOUT1_VOLUME:
1403 case WM8996_DAC2_HPOUT2_VOLUME:
1404 case WM8996_DAC1_LEFT_VOLUME:
1405 case WM8996_DAC1_RIGHT_VOLUME:
1406 case WM8996_DAC2_LEFT_VOLUME:
1407 case WM8996_DAC2_RIGHT_VOLUME:
1408 case WM8996_OUTPUT1_LEFT_VOLUME:
1409 case WM8996_OUTPUT1_RIGHT_VOLUME:
1410 case WM8996_OUTPUT2_LEFT_VOLUME:
1411 case WM8996_OUTPUT2_RIGHT_VOLUME:
1412 case WM8996_MICBIAS_1:
1413 case WM8996_MICBIAS_2:
1414 case WM8996_LDO_1:
1415 case WM8996_LDO_2:
1416 case WM8996_ACCESSORY_DETECT_MODE_1:
1417 case WM8996_ACCESSORY_DETECT_MODE_2:
1418 case WM8996_HEADPHONE_DETECT_1:
1419 case WM8996_HEADPHONE_DETECT_2:
1420 case WM8996_MIC_DETECT_1:
1421 case WM8996_MIC_DETECT_2:
1422 case WM8996_MIC_DETECT_3:
1423 case WM8996_CHARGE_PUMP_1:
1424 case WM8996_CHARGE_PUMP_2:
1425 case WM8996_DC_SERVO_1:
1426 case WM8996_DC_SERVO_2:
1427 case WM8996_DC_SERVO_3:
1428 case WM8996_DC_SERVO_5:
1429 case WM8996_DC_SERVO_6:
1430 case WM8996_DC_SERVO_7:
1431 case WM8996_DC_SERVO_READBACK_0:
1432 case WM8996_ANALOGUE_HP_1:
1433 case WM8996_ANALOGUE_HP_2:
1434 case WM8996_CHIP_REVISION:
1435 case WM8996_CONTROL_INTERFACE_1:
1436 case WM8996_WRITE_SEQUENCER_CTRL_1:
1437 case WM8996_WRITE_SEQUENCER_CTRL_2:
1438 case WM8996_AIF_CLOCKING_1:
1439 case WM8996_AIF_CLOCKING_2:
1440 case WM8996_CLOCKING_1:
1441 case WM8996_CLOCKING_2:
1442 case WM8996_AIF_RATE:
1443 case WM8996_FLL_CONTROL_1:
1444 case WM8996_FLL_CONTROL_2:
1445 case WM8996_FLL_CONTROL_3:
1446 case WM8996_FLL_CONTROL_4:
1447 case WM8996_FLL_CONTROL_5:
1448 case WM8996_FLL_CONTROL_6:
1449 case WM8996_FLL_EFS_1:
1450 case WM8996_FLL_EFS_2:
1451 case WM8996_AIF1_CONTROL:
1452 case WM8996_AIF1_BCLK:
1453 case WM8996_AIF1_TX_LRCLK_1:
1454 case WM8996_AIF1_TX_LRCLK_2:
1455 case WM8996_AIF1_RX_LRCLK_1:
1456 case WM8996_AIF1_RX_LRCLK_2:
1457 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1458 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1459 case WM8996_AIF1RX_DATA_CONFIGURATION:
1460 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1461 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1462 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1463 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1464 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1465 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1466 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1467 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1468 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1469 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1470 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1471 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1472 case WM8996_AIF1RX_MONO_CONFIGURATION:
1473 case WM8996_AIF1TX_TEST:
1474 case WM8996_AIF2_CONTROL:
1475 case WM8996_AIF2_BCLK:
1476 case WM8996_AIF2_TX_LRCLK_1:
1477 case WM8996_AIF2_TX_LRCLK_2:
1478 case WM8996_AIF2_RX_LRCLK_1:
1479 case WM8996_AIF2_RX_LRCLK_2:
1480 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1481 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1482 case WM8996_AIF2RX_DATA_CONFIGURATION:
1483 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1484 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1485 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1486 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1487 case WM8996_AIF2RX_MONO_CONFIGURATION:
1488 case WM8996_AIF2TX_TEST:
1489 case WM8996_DSP1_TX_LEFT_VOLUME:
1490 case WM8996_DSP1_TX_RIGHT_VOLUME:
1491 case WM8996_DSP1_RX_LEFT_VOLUME:
1492 case WM8996_DSP1_RX_RIGHT_VOLUME:
1493 case WM8996_DSP1_TX_FILTERS:
1494 case WM8996_DSP1_RX_FILTERS_1:
1495 case WM8996_DSP1_RX_FILTERS_2:
1496 case WM8996_DSP1_DRC_1:
1497 case WM8996_DSP1_DRC_2:
1498 case WM8996_DSP1_DRC_3:
1499 case WM8996_DSP1_DRC_4:
1500 case WM8996_DSP1_DRC_5:
1501 case WM8996_DSP1_RX_EQ_GAINS_1:
1502 case WM8996_DSP1_RX_EQ_GAINS_2:
1503 case WM8996_DSP1_RX_EQ_BAND_1_A:
1504 case WM8996_DSP1_RX_EQ_BAND_1_B:
1505 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1506 case WM8996_DSP1_RX_EQ_BAND_2_A:
1507 case WM8996_DSP1_RX_EQ_BAND_2_B:
1508 case WM8996_DSP1_RX_EQ_BAND_2_C:
1509 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1510 case WM8996_DSP1_RX_EQ_BAND_3_A:
1511 case WM8996_DSP1_RX_EQ_BAND_3_B:
1512 case WM8996_DSP1_RX_EQ_BAND_3_C:
1513 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1514 case WM8996_DSP1_RX_EQ_BAND_4_A:
1515 case WM8996_DSP1_RX_EQ_BAND_4_B:
1516 case WM8996_DSP1_RX_EQ_BAND_4_C:
1517 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1518 case WM8996_DSP1_RX_EQ_BAND_5_A:
1519 case WM8996_DSP1_RX_EQ_BAND_5_B:
1520 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1521 case WM8996_DSP2_TX_LEFT_VOLUME:
1522 case WM8996_DSP2_TX_RIGHT_VOLUME:
1523 case WM8996_DSP2_RX_LEFT_VOLUME:
1524 case WM8996_DSP2_RX_RIGHT_VOLUME:
1525 case WM8996_DSP2_TX_FILTERS:
1526 case WM8996_DSP2_RX_FILTERS_1:
1527 case WM8996_DSP2_RX_FILTERS_2:
1528 case WM8996_DSP2_DRC_1:
1529 case WM8996_DSP2_DRC_2:
1530 case WM8996_DSP2_DRC_3:
1531 case WM8996_DSP2_DRC_4:
1532 case WM8996_DSP2_DRC_5:
1533 case WM8996_DSP2_RX_EQ_GAINS_1:
1534 case WM8996_DSP2_RX_EQ_GAINS_2:
1535 case WM8996_DSP2_RX_EQ_BAND_1_A:
1536 case WM8996_DSP2_RX_EQ_BAND_1_B:
1537 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1538 case WM8996_DSP2_RX_EQ_BAND_2_A:
1539 case WM8996_DSP2_RX_EQ_BAND_2_B:
1540 case WM8996_DSP2_RX_EQ_BAND_2_C:
1541 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1542 case WM8996_DSP2_RX_EQ_BAND_3_A:
1543 case WM8996_DSP2_RX_EQ_BAND_3_B:
1544 case WM8996_DSP2_RX_EQ_BAND_3_C:
1545 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1546 case WM8996_DSP2_RX_EQ_BAND_4_A:
1547 case WM8996_DSP2_RX_EQ_BAND_4_B:
1548 case WM8996_DSP2_RX_EQ_BAND_4_C:
1549 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1550 case WM8996_DSP2_RX_EQ_BAND_5_A:
1551 case WM8996_DSP2_RX_EQ_BAND_5_B:
1552 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1553 case WM8996_DAC1_MIXER_VOLUMES:
1554 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1555 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1556 case WM8996_DAC2_MIXER_VOLUMES:
1557 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1558 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1559 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1560 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1561 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1562 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1563 case WM8996_DSP_TX_MIXER_SELECT:
1564 case WM8996_DAC_SOFTMUTE:
1565 case WM8996_OVERSAMPLING:
1566 case WM8996_SIDETONE:
1567 case WM8996_GPIO_1:
1568 case WM8996_GPIO_2:
1569 case WM8996_GPIO_3:
1570 case WM8996_GPIO_4:
1571 case WM8996_GPIO_5:
1572 case WM8996_PULL_CONTROL_1:
1573 case WM8996_PULL_CONTROL_2:
1574 case WM8996_INTERRUPT_STATUS_1:
1575 case WM8996_INTERRUPT_STATUS_2:
1576 case WM8996_INTERRUPT_RAW_STATUS_2:
1577 case WM8996_INTERRUPT_STATUS_1_MASK:
1578 case WM8996_INTERRUPT_STATUS_2_MASK:
1579 case WM8996_INTERRUPT_CONTROL:
1580 case WM8996_LEFT_PDM_SPEAKER:
1581 case WM8996_RIGHT_PDM_SPEAKER:
1582 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1583 case WM8996_PDM_SPEAKER_VOLUME:
1584 return 1;
1585 default:
1586 return 0;
1587 }
1588}
1589
1590static int wm8996_volatile_register(struct snd_soc_codec *codec,
1591 unsigned int reg)
1592{
1593 switch (reg) {
1594 case WM8996_SOFTWARE_RESET:
1595 case WM8996_CHIP_REVISION:
1596 case WM8996_LDO_1:
1597 case WM8996_LDO_2:
1598 case WM8996_INTERRUPT_STATUS_1:
1599 case WM8996_INTERRUPT_STATUS_2:
1600 case WM8996_INTERRUPT_RAW_STATUS_2:
1601 case WM8996_DC_SERVO_READBACK_0:
1602 case WM8996_DC_SERVO_2:
1603 case WM8996_DC_SERVO_6:
1604 case WM8996_DC_SERVO_7:
1605 case WM8996_FLL_CONTROL_6:
1606 case WM8996_MIC_DETECT_3:
1607 case WM8996_HEADPHONE_DETECT_1:
1608 case WM8996_HEADPHONE_DETECT_2:
1609 return 1;
1610 default:
1611 return 0;
1612 }
1613}
1614
1615static int wm8996_reset(struct snd_soc_codec *codec)
1616{
1617 return snd_soc_write(codec, WM8996_SOFTWARE_RESET, 0x8915);
1618}
1619
1620static const int bclk_divs[] = {
1621 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1622};
1623
1624static void wm8996_update_bclk(struct snd_soc_codec *codec)
1625{
1626 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1627 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1628
1629 /* Don't bother if we're in a low frequency idle mode that
1630 * can't support audio.
1631 */
1632 if (wm8996->sysclk < 64000)
1633 return;
1634
1635 for (aif = 0; aif < WM8996_AIFS; aif++) {
1636 switch (aif) {
1637 case 0:
1638 bclk_reg = WM8996_AIF1_BCLK;
1639 break;
1640 case 1:
1641 bclk_reg = WM8996_AIF2_BCLK;
1642 break;
1643 }
1644
1645 bclk_rate = wm8996->bclk_rate[aif];
1646
1647 /* Pick a divisor for BCLK as close as we can get to ideal */
1648 best = 0;
1649 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1650 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1651 if (cur_val < 0) /* BCLK table is sorted */
1652 break;
1653 best = i;
1654 }
1655 bclk_rate = wm8996->sysclk / bclk_divs[best];
1656 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1657 bclk_divs[best], bclk_rate);
1658
1659 snd_soc_update_bits(codec, bclk_reg,
1660 WM8996_AIF1_BCLK_DIV_MASK, best);
1661 }
1662}
1663
1664static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1665 enum snd_soc_bias_level level)
1666{
1667 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1668 int ret;
1669
1670 switch (level) {
1671 case SND_SOC_BIAS_ON:
a9ba6151 1672 case SND_SOC_BIAS_PREPARE:
a9ba6151
MB		 1673 break;
1674
1675 case SND_SOC_BIAS_STANDBY:
1676 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1677 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1678 wm8996->supplies);
1679 if (ret != 0) {
1680 dev_err(codec->dev,
1681 "Failed to enable supplies: %d\n",
1682 ret);
1683 return ret;
1684 }
1685
1686 if (wm8996->pdata.ldo_ena >= 0) {
1687 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1688 1);
1689 msleep(5);
1690 }
1691
1692 codec->cache_only = false;
1693 snd_soc_cache_sync(codec);
1694 }
a9ba6151
MB		 1695 break;
1696
1697 case SND_SOC_BIAS_OFF:
1698 codec->cache_only = true;
1699 if (wm8996->pdata.ldo_ena >= 0)
1700 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1701 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1702 wm8996->supplies);
1703 break;
1704 }
1705
1706 codec->dapm.bias_level = level;
1707
1708 return 0;
1709}
1710
1711static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1712{
1713 struct snd_soc_codec *codec = dai->codec;
1714 int aifctrl = 0;
1715 int bclk = 0;
1716 int lrclk_tx = 0;
1717 int lrclk_rx = 0;
1718 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1719
1720 switch (dai->id) {
1721 case 0:
1722 aifctrl_reg = WM8996_AIF1_CONTROL;
1723 bclk_reg = WM8996_AIF1_BCLK;
1724 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1725 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1726 break;
1727 case 1:
1728 aifctrl_reg = WM8996_AIF2_CONTROL;
1729 bclk_reg = WM8996_AIF2_BCLK;
1730 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1731 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1732 break;
1733 default:
1734 BUG();
1735 return -EINVAL;
1736 }
1737
1738 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1739 case SND_SOC_DAIFMT_NB_NF:
1740 break;
1741 case SND_SOC_DAIFMT_IB_NF:
1742 bclk |= WM8996_AIF1_BCLK_INV;
1743 break;
1744 case SND_SOC_DAIFMT_NB_IF:
1745 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1746 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1747 break;
1748 case SND_SOC_DAIFMT_IB_IF:
1749 bclk |= WM8996_AIF1_BCLK_INV;
1750 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1751 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1752 break;
1753 }
1754
1755 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1756 case SND_SOC_DAIFMT_CBS_CFS:
1757 break;
1758 case SND_SOC_DAIFMT_CBS_CFM:
1759 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1760 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1761 break;
1762 case SND_SOC_DAIFMT_CBM_CFS:
1763 bclk |= WM8996_AIF1_BCLK_MSTR;
1764 break;
1765 case SND_SOC_DAIFMT_CBM_CFM:
1766 bclk |= WM8996_AIF1_BCLK_MSTR;
1767 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1768 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1769 break;
1770 default:
1771 return -EINVAL;
1772 }
1773
1774 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1775 case SND_SOC_DAIFMT_DSP_A:
1776 break;
1777 case SND_SOC_DAIFMT_DSP_B:
1778 aifctrl |= 1;
1779 break;
1780 case SND_SOC_DAIFMT_I2S:
1781 aifctrl |= 2;
1782 break;
1783 case SND_SOC_DAIFMT_LEFT_J:
1784 aifctrl |= 3;
1785 break;
1786 default:
1787 return -EINVAL;
1788 }
1789
1790 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1791 snd_soc_update_bits(codec, bclk_reg,
1792 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1793 bclk);
1794 snd_soc_update_bits(codec, lrclk_tx_reg,
1795 WM8996_AIF1TX_LRCLK_INV |
1796 WM8996_AIF1TX_LRCLK_MSTR,
1797 lrclk_tx);
1798 snd_soc_update_bits(codec, lrclk_rx_reg,
1799 WM8996_AIF1RX_LRCLK_INV |
1800 WM8996_AIF1RX_LRCLK_MSTR,
1801 lrclk_rx);
1802
1803 return 0;
1804}
1805
1806static const int dsp_divs[] = {
1807 48000, 32000, 16000, 8000
1808};
1809
1810static int wm8996_hw_params(struct snd_pcm_substream *substream,
1811 struct snd_pcm_hw_params *params,
1812 struct snd_soc_dai *dai)
1813{
1814 struct snd_soc_codec *codec = dai->codec;
1815 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1816 int bits, i, bclk_rate;
1817 int aifdata = 0;
1818 int lrclk = 0;
1819 int dsp = 0;
1820 int aifdata_reg, lrclk_reg, dsp_shift;
1821
1822 switch (dai->id) {
1823 case 0:
1824 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1825 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1826 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1827 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1828 } else {
1829 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1830 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1831 }
1832 dsp_shift = 0;
1833 break;
1834 case 1:
1835 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1836 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1837 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1838 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1839 } else {
1840 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1841 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1842 }
1843 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1844 break;
1845 default:
1846 BUG();
1847 return -EINVAL;
1848 }
1849
1850 bclk_rate = snd_soc_params_to_bclk(params);
1851 if (bclk_rate < 0) {
1852 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1853 return bclk_rate;
1854 }
1855
1856 wm8996->bclk_rate[dai->id] = bclk_rate;
1857 wm8996->rx_rate[dai->id] = params_rate(params);
1858
1859 /* Needs looking at for TDM */
1860 bits = snd_pcm_format_width(params_format(params));
1861 if (bits < 0)
1862 return bits;
1863 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1864
1865 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1866 if (dsp_divs[i] == params_rate(params))
1867 break;
1868 }
1869 if (i == ARRAY_SIZE(dsp_divs)) {
1870 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1871 params_rate(params));
1872 return -EINVAL;
1873 }
1874 dsp |= i << dsp_shift;
1875
1876 wm8996_update_bclk(codec);
1877
1878 lrclk = bclk_rate / params_rate(params);
1879 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1880 lrclk, bclk_rate / lrclk);
1881
1882 snd_soc_update_bits(codec, aifdata_reg,
1883 WM8996_AIF1TX_WL_MASK |
1884 WM8996_AIF1TX_SLOT_LEN_MASK,
1885 aifdata);
1886 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1887 lrclk);
1888 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1889 WM8996_DSP1_DIV_SHIFT << dsp_shift, dsp);
1890
1891 return 0;
1892}
1893
1894static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1895 int clk_id, unsigned int freq, int dir)
1896{
1897 struct snd_soc_codec *codec = dai->codec;
1898 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1899 int lfclk = 0;
1900 int ratediv = 0;
1901 int src;
1902 int old;
1903
1904 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1905 return 0;
1906
1907 /* Disable SYSCLK while we reconfigure */
1908 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1909 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1910 WM8996_SYSCLK_ENA, 0);
1911
1912 switch (clk_id) {
1913 case WM8996_SYSCLK_MCLK1:
1914 wm8996->sysclk = freq;
1915 src = 0;
1916 break;
1917 case WM8996_SYSCLK_MCLK2:
1918 wm8996->sysclk = freq;
1919 src = 1;
1920 break;
1921 case WM8996_SYSCLK_FLL:
1922 wm8996->sysclk = freq;
1923 src = 2;
1924 break;
1925 default:
1926 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1927 return -EINVAL;
1928 }
1929
1930 switch (wm8996->sysclk) {
1931 case 6144000:
1932 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1933 WM8996_SYSCLK_RATE, 0);
1934 break;
1935 case 24576000:
1936 ratediv = WM8996_SYSCLK_DIV;
1937 case 12288000:
1938 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1939 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1940 break;
1941 case 32000:
1942 case 32768:
1943 lfclk = WM8996_LFCLK_ENA;
1944 break;
1945 default:
1946 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1947 wm8996->sysclk);
1948 return -EINVAL;
1949 }
1950
1951 wm8996_update_bclk(codec);
1952
1953 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1954 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1955 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1956 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1957 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1958 WM8996_SYSCLK_ENA, old);
1959
1960 wm8996->sysclk_src = clk_id;
1961
1962 return 0;
1963}
1964
1965struct _fll_div {
1966 u16 fll_fratio;
1967 u16 fll_outdiv;
1968 u16 fll_refclk_div;
1969 u16 fll_loop_gain;
1970 u16 fll_ref_freq;
1971 u16 n;
1972 u16 theta;
1973 u16 lambda;
1974};
1975
1976static struct {
1977 unsigned int min;
1978 unsigned int max;
1979 u16 fll_fratio;
1980 int ratio;
1981} fll_fratios[] = {
1982 { 0, 64000, 4, 16 },
1983 { 64000, 128000, 3, 8 },
1984 { 128000, 256000, 2, 4 },
1985 { 256000, 1000000, 1, 2 },
1986 { 1000000, 13500000, 0, 1 },
1987};
1988
1989static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1990 unsigned int Fout)
1991{
1992 unsigned int target;
1993 unsigned int div;
1994 unsigned int fratio, gcd_fll;
1995 int i;
1996
1997 /* Fref must be <=13.5MHz */
1998 div = 1;
1999 fll_div->fll_refclk_div = 0;
2000 while ((Fref / div) > 13500000) {
2001 div *= 2;
2002 fll_div->fll_refclk_div++;
2003
2004 if (div > 8) {
2005 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2006 Fref);
2007 return -EINVAL;
2008 }
2009 }
2010
2011 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2012
2013 /* Apply the division for our remaining calculations */
2014 Fref /= div;
2015
2016 if (Fref >= 3000000)
2017 fll_div->fll_loop_gain = 5;
2018 else
2019 fll_div->fll_loop_gain = 0;
2020
2021 if (Fref >= 48000)
2022 fll_div->fll_ref_freq = 0;
2023 else
2024 fll_div->fll_ref_freq = 1;
2025
2026 /* Fvco should be 90-100MHz; don't check the upper bound */
2027 div = 2;
2028 while (Fout * div < 90000000) {
2029 div++;
2030 if (div > 64) {
2031 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2032 Fout);
2033 return -EINVAL;
2034 }
2035 }
2036 target = Fout * div;
2037 fll_div->fll_outdiv = div - 1;
2038
2039 pr_debug("FLL Fvco=%dHz\n", target);
2040
2041 /* Find an appropraite FLL_FRATIO and factor it out of the target */
2042 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2043 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2044 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2045 fratio = fll_fratios[i].ratio;
2046 break;
2047 }
2048 }
2049 if (i == ARRAY_SIZE(fll_fratios)) {
2050 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2051 return -EINVAL;
2052 }
2053
2054 fll_div->n = target / (fratio * Fref);
2055
2056 if (target % Fref == 0) {
2057 fll_div->theta = 0;
2058 fll_div->lambda = 0;
2059 } else {
2060 gcd_fll = gcd(target, fratio * Fref);
2061
2062 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2063 / gcd_fll;
2064 fll_div->lambda = (fratio * Fref) / gcd_fll;
2065 }
2066
2067 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2068 fll_div->n, fll_div->theta, fll_div->lambda);
2069 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2070 fll_div->fll_fratio, fll_div->fll_outdiv,
2071 fll_div->fll_refclk_div);
2072
2073 return 0;
2074}
2075
2076static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2077 unsigned int Fref, unsigned int Fout)
2078{
2079 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2080 struct i2c_client *i2c = to_i2c_client(codec->dev);
2081 struct _fll_div fll_div;
2082 unsigned long timeout;
27b6d92a 2083 int ret, reg, retry;
a9ba6151
MB		 2084
2085 /* Any change? */
2086 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2087 Fout == wm8996->fll_fout)
2088 return 0;
2089
2090 if (Fout == 0) {
2091 dev_dbg(codec->dev, "FLL disabled\n");
2092
2093 wm8996->fll_fref = 0;
2094 wm8996->fll_fout = 0;
2095
2096 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2097 WM8996_FLL_ENA, 0);
2098
2099 return 0;
2100 }
2101
2102 ret = fll_factors(&fll_div, Fref, Fout);
2103 if (ret != 0)
2104 return ret;
2105
2106 switch (source) {
2107 case WM8996_FLL_MCLK1:
2108 reg = 0;
2109 break;
2110 case WM8996_FLL_MCLK2:
2111 reg = 1;
2112 break;
2113 case WM8996_FLL_DACLRCLK1:
2114 reg = 2;
2115 break;
2116 case WM8996_FLL_BCLK1:
2117 reg = 3;
2118 break;
2119 default:
2120 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2121 return -EINVAL;
2122 }
2123
2124 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2125 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2126
2127 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2128 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2129 WM8996_FLL_REFCLK_SRC_MASK, reg);
2130
2131 reg = 0;
2132 if (fll_div.theta || fll_div.lambda)
2133 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2134 else
2135 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2136 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2137
2138 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2139 WM8996_FLL_OUTDIV_MASK |
2140 WM8996_FLL_FRATIO_MASK,
2141 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2142 (fll_div.fll_fratio));
2143
2144 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2145
2146 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2147 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2148 (fll_div.n << WM8996_FLL_N_SHIFT) |
2149 fll_div.fll_loop_gain);
2150
2151 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2152
a4161945
MB		 2153 /* Clear any pending completions (eg, from failed startups) */
2154 try_wait_for_completion(&wm8996->fll_lock);
2155
a9ba6151
MB		 2156 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2157 WM8996_FLL_ENA, WM8996_FLL_ENA);
2158
2159 /* The FLL supports live reconfiguration - kick that in case we were
2160 * already enabled.
2161 */
2162 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2163
2164 /* Wait for the FLL to lock, using the interrupt if possible */
2165 if (Fref > 1000000)
2166 timeout = usecs_to_jiffies(300);
2167 else
2168 timeout = msecs_to_jiffies(2);
2169
27b6d92a
MB		 2170 /* Allow substantially longer if we've actually got the IRQ, poll
2171 * at a slightly higher rate if we don't.
2172 */
a9ba6151 2173 if (i2c->irq)
27b6d92a
MB		 2174 timeout *= 10;
2175 else
2176 timeout /= 2;
a9ba6151 2177
27b6d92a
MB		 2178 for (retry = 0; retry < 10; retry++) {
2179 ret = wait_for_completion_timeout(&wm8996->fll_lock,
2180 timeout);
2181 if (ret != 0) {
2182 WARN_ON(!i2c->irq);
2183 break;
2184 }
a9ba6151 2185
27b6d92a
MB		 2186 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2187 if (ret & WM8996_FLL_LOCK_STS)
2188 break;
2189 }
2190 if (retry == 10) {
a9ba6151
MB		 2191 dev_err(codec->dev, "Timed out waiting for FLL\n");
2192 ret = -ETIMEDOUT;
a9ba6151
MB		 2193 }
2194
2195 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2196
2197 wm8996->fll_fref = Fref;
2198 wm8996->fll_fout = Fout;
2199 wm8996->fll_src = source;
2200
2201 return ret;
2202}
2203
2204#ifdef CONFIG_GPIOLIB
2205static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2206{
2207 return container_of(chip, struct wm8996_priv, gpio_chip);
2208}
2209
2210static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2211{
2212 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2213 struct snd_soc_codec *codec = wm8996->codec;
2214
2215 snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2216 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2217}
2218
2219static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2220 unsigned offset, int value)
2221{
2222 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2223 struct snd_soc_codec *codec = wm8996->codec;
2224 int val;
2225
2226 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2227
2228 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2229 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2230 WM8996_GP1_LVL, val);
2231}
2232
2233static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2234{
2235 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2236 struct snd_soc_codec *codec = wm8996->codec;
2237 int ret;
2238
2239 ret = snd_soc_read(codec, WM8996_GPIO_1 + offset);
2240 if (ret < 0)
2241 return ret;
2242
2243 return (ret & WM8996_GP1_LVL) != 0;
2244}
2245
2246static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2247{
2248 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2249 struct snd_soc_codec *codec = wm8996->codec;
2250
2251 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2252 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2253 (1 << WM8996_GP1_FN_SHIFT) |
2254 (1 << WM8996_GP1_DIR_SHIFT));
2255}
2256
2257static struct gpio_chip wm8996_template_chip = {
2258 .label = "wm8996",
2259 .owner = THIS_MODULE,
2260 .direction_output = wm8996_gpio_direction_out,
2261 .set = wm8996_gpio_set,
2262 .direction_input = wm8996_gpio_direction_in,
2263 .get = wm8996_gpio_get,
2264 .can_sleep = 1,
2265};
2266
2267static void wm8996_init_gpio(struct snd_soc_codec *codec)
2268{
2269 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2270 int ret;
2271
2272 wm8996->gpio_chip = wm8996_template_chip;
2273 wm8996->gpio_chip.ngpio = 5;
2274 wm8996->gpio_chip.dev = codec->dev;
2275
2276 if (wm8996->pdata.gpio_base)
2277 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2278 else
2279 wm8996->gpio_chip.base = -1;
2280
2281 ret = gpiochip_add(&wm8996->gpio_chip);
2282 if (ret != 0)
2283 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2284}
2285
2286static void wm8996_free_gpio(struct snd_soc_codec *codec)
2287{
2288 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2289 int ret;
2290
2291 ret = gpiochip_remove(&wm8996->gpio_chip);
2292 if (ret != 0)
2293 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2294}
2295#else
2296static void wm8996_init_gpio(struct snd_soc_codec *codec)
2297{
2298}
2299
2300static void wm8996_free_gpio(struct snd_soc_codec *codec)
2301{
2302}
2303#endif
2304
2305/**
2306 * wm8996_detect - Enable default WM8996 jack detection
2307 *
2308 * The WM8996 has advanced accessory detection support for headsets.
2309 * This function provides a default implementation which integrates
2310 * the majority of this functionality with minimal user configuration.
2311 *
2312 * This will detect headset, headphone and short circuit button and
2313 * will also detect inverted microphone ground connections and update
2314 * the polarity of the connections.
2315 */
2316int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2317 wm8996_polarity_fn polarity_cb)
2318{
2319 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2320
2321 wm8996->jack = jack;
2322 wm8996->detecting = true;
2323 wm8996->polarity_cb = polarity_cb;
2324
2325 if (wm8996->polarity_cb)
2326 wm8996->polarity_cb(codec, 0);
2327
2328 /* Clear discarge to avoid noise during detection */
2329 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2330 WM8996_MICB1_DISCH, 0);
2331 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2332 WM8996_MICB2_DISCH, 0);
2333
2334 /* LDO2 powers the microphones, SYSCLK clocks detection */
2335 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2336 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2337
2338 /* We start off just enabling microphone detection - even a
2339 * plain headphone will trigger detection.
2340 */
2341 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2342 WM8996_MICD_ENA, WM8996_MICD_ENA);
2343
2344 /* Slowest detection rate, gives debounce for initial detection */
2345 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2346 WM8996_MICD_RATE_MASK,
2347 WM8996_MICD_RATE_MASK);
2348
2349 /* Enable interrupts and we're off */
2350 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
0b684cc1 2351 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
a9ba6151
MB		 2352
2353 return 0;
2354}
2355EXPORT_SYMBOL_GPL(wm8996_detect);
2356
0b684cc1
MB		 2357static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2358{
2359 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2360 int val, reg, report;
2361
2362 /* Assume headphone in error conditions; we need to report
2363 * something or we stall our state machine.
2364 */
2365 report = SND_JACK_HEADPHONE;
2366
2367 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2368 if (reg < 0) {
2369 dev_err(codec->dev, "Failed to read HPDET status\n");
2370 goto out;
2371 }
2372
2373 if (!(reg & WM8996_HP_DONE)) {
2374 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2375 goto out;
2376 }
2377
2378 val = reg & WM8996_HP_LVL_MASK;
2379
2380 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2381
2382 /* If we've got high enough impedence then report as line,
2383 * otherwise assume headphone.
2384 */
2385 if (val >= 126)
2386 report = SND_JACK_LINEOUT;
2387 else
2388 report = SND_JACK_HEADPHONE;
2389
2390out:
2391 if (wm8996->jack_mic)
2392 report |= SND_JACK_MICROPHONE;
2393
2394 snd_soc_jack_report(wm8996->jack, report,
2395 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2396
2397 wm8996->detecting = false;
2398
2399 /* If the output isn't running re-clamp it */
2400 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2401 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2402 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2403 WM8996_HPOUT1L_RMV_SHORT |
2404 WM8996_HPOUT1R_RMV_SHORT, 0);
2405
2406 /* Go back to looking at the microphone */
2407 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2408 WM8996_JD_MODE_MASK, 0);
2409 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2410 WM8996_MICD_ENA);
2411
2412 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2413 snd_soc_dapm_sync(&codec->dapm);
2414}
2415
2416static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2417{
2418 /* Unclamp the output, we can't measure while we're shorting it */
2419 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2420 WM8996_HPOUT1L_RMV_SHORT |
2421 WM8996_HPOUT1R_RMV_SHORT,
2422 WM8996_HPOUT1L_RMV_SHORT |
2423 WM8996_HPOUT1R_RMV_SHORT);
2424
2425 /* We need bandgap for HPDET */
2426 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2427 snd_soc_dapm_sync(&codec->dapm);
2428
2429 /* Go into headphone detect left mode */
2430 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2431 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2432 WM8996_JD_MODE_MASK, 1);
2433
2434 /* Trigger a measurement */
2435 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2436 WM8996_HP_POLL, WM8996_HP_POLL);
2437}
2438
a9ba6151
MB		 2439static void wm8996_micd(struct snd_soc_codec *codec)
2440{
2441 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2442 int val, reg;
2443
2444 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2445
2446 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2447
2448 if (!(val & WM8996_MICD_VALID)) {
2449 dev_warn(codec->dev, "Microphone detection state invalid\n");
2450 return;
2451 }
2452
2453 /* No accessory, reset everything and report removal */
2454 if (!(val & WM8996_MICD_STS)) {
2455 dev_dbg(codec->dev, "Jack removal detected\n");
2456 wm8996->jack_mic = false;
2457 wm8996->detecting = true;
2458 snd_soc_jack_report(wm8996->jack, 0,
0b684cc1
MB		 2459 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2460 SND_JACK_BTN_0);
2461
a9ba6151
MB		 2462 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2463 WM8996_MICD_RATE_MASK,
2464 WM8996_MICD_RATE_MASK);
2465 return;
2466 }
2467
0b684cc1
MB		 2468 /* If the measurement is very high we've got a microphone,
2469 * either we just detected one or if we already reported then
2470 * we've got a button release event.
a9ba6151
MB		 2471 */
2472 if (val & 0x400) {
0b684cc1
MB		 2473 if (wm8996->detecting) {
2474 dev_dbg(codec->dev, "Microphone detected\n");
2475 wm8996->jack_mic = true;
2476 wm8996_hpdet_start(codec);
2477
2478 /* Increase poll rate to give better responsiveness
2479 * for buttons */
2480 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2481 WM8996_MICD_RATE_MASK,
2482 5 << WM8996_MICD_RATE_SHIFT);
2483 } else {
2484 dev_dbg(codec->dev, "Mic button up\n");
2485 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2486 }
2487
2488 return;
a9ba6151
MB		 2489 }
2490
2491 /* If we detected a lower impedence during initial startup
2492 * then we probably have the wrong polarity, flip it. Don't
2493 * do this for the lowest impedences to speed up detection of
2494 * plain headphones.
2495 */
2496 if (wm8996->detecting && (val & 0x3f0)) {
2497 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2498 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2499 WM8996_MICD_BIAS_SRC;
2500 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2501 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2502 WM8996_MICD_BIAS_SRC, reg);
2503
2504 if (wm8996->polarity_cb)
2505 wm8996->polarity_cb(codec,
2506 (reg & WM8996_MICD_SRC) != 0);
2507
2508 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2509 (reg & WM8996_MICD_SRC) != 0);
2510
2511 return;
2512 }
2513
2514 /* Don't distinguish between buttons, just report any low
2515 * impedence as BTN_0.
2516 */
2517 if (val & 0x3fc) {
2518 if (wm8996->jack_mic) {
2519 dev_dbg(codec->dev, "Mic button detected\n");
0b684cc1 2520 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
a9ba6151 2521 SND_JACK_BTN_0);
0b684cc1
MB		 2522 } else if (wm8996->detecting) {
2523 dev_dbg(codec->dev, "Headphone detected\n");
2524 wm8996_hpdet_start(codec);
a9ba6151
MB		 2525
2526 /* Increase the detection rate a bit for
2527 * responsiveness.
2528 */
2529 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2530 WM8996_MICD_RATE_MASK,
2531 7 << WM8996_MICD_RATE_SHIFT);
a9ba6151
MB		 2532 }
2533 }
2534}
2535
2536static irqreturn_t wm8996_irq(int irq, void *data)
2537{
2538 struct snd_soc_codec *codec = data;
2539 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2540 int irq_val;
2541
2542 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2543 if (irq_val < 0) {
2544 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2545 irq_val);
2546 return IRQ_NONE;
2547 }
2548 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2549
2fde6e80
MB		 2550 if (!irq_val)
2551 return IRQ_NONE;
2552
84497091
MB		 2553 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2554
a9ba6151
MB		 2555 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2556 dev_dbg(codec->dev, "DC servo IRQ\n");
2557 complete(&wm8996->dcs_done);
2558 }
2559
2560 if (irq_val & WM8996_FIFOS_ERR_EINT)
2561 dev_err(codec->dev, "Digital core FIFO error\n");
2562
2563 if (irq_val & WM8996_FLL_LOCK_EINT) {
2564 dev_dbg(codec->dev, "FLL locked\n");
2565 complete(&wm8996->fll_lock);
2566 }
2567
2568 if (irq_val & WM8996_MICD_EINT)
2569 wm8996_micd(codec);
2570
0b684cc1
MB		 2571 if (irq_val & WM8996_HP_DONE_EINT)
2572 wm8996_hpdet_irq(codec);
2573
2fde6e80 2574 return IRQ_HANDLED;
a9ba6151
MB		 2575}
2576
2577static irqreturn_t wm8996_edge_irq(int irq, void *data)
2578{
2579 irqreturn_t ret = IRQ_NONE;
2580 irqreturn_t val;
2581
2582 do {
2583 val = wm8996_irq(irq, data);
2584 if (val != IRQ_NONE)
2585 ret = val;
2586 } while (val != IRQ_NONE);
2587
2588 return ret;
2589}
2590
2591static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2592{
2593 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2594 struct wm8996_pdata *pdata = &wm8996->pdata;
2595
2596 struct snd_kcontrol_new controls[] = {
2597 SOC_ENUM_EXT("DSP1 EQ Mode",
2598 wm8996->retune_mobile_enum,
2599 wm8996_get_retune_mobile_enum,
2600 wm8996_put_retune_mobile_enum),
2601 SOC_ENUM_EXT("DSP2 EQ Mode",
2602 wm8996->retune_mobile_enum,
2603 wm8996_get_retune_mobile_enum,
2604 wm8996_put_retune_mobile_enum),
2605 };
2606 int ret, i, j;
2607 const char **t;
2608
2609 /* We need an array of texts for the enum API but the number
2610 * of texts is likely to be less than the number of
2611 * configurations due to the sample rate dependency of the
2612 * configurations. */
2613 wm8996->num_retune_mobile_texts = 0;
2614 wm8996->retune_mobile_texts = NULL;
2615 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2616 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2617 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2618 wm8996->retune_mobile_texts[j]) == 0)
2619 break;
2620 }
2621
2622 if (j != wm8996->num_retune_mobile_texts)
2623 continue;
2624
2625 /* Expand the array... */
2626 t = krealloc(wm8996->retune_mobile_texts,
2627 sizeof(char *) *
2628 (wm8996->num_retune_mobile_texts + 1),
2629 GFP_KERNEL);
2630 if (t == NULL)
2631 continue;
2632
2633 /* ...store the new entry... */
2634 t[wm8996->num_retune_mobile_texts] =
2635 pdata->retune_mobile_cfgs[i].name;
2636
2637 /* ...and remember the new version. */
2638 wm8996->num_retune_mobile_texts++;
2639 wm8996->retune_mobile_texts = t;
2640 }
2641
2642 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2643 wm8996->num_retune_mobile_texts);
2644
2645 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2646 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2647
2648 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2649 if (ret != 0)
2650 dev_err(codec->dev,
2651 "Failed to add ReTune Mobile controls: %d\n", ret);
2652}
2653
2654static int wm8996_probe(struct snd_soc_codec *codec)
2655{
2656 int ret;
2657 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2658 struct i2c_client *i2c = to_i2c_client(codec->dev);
2659 struct snd_soc_dapm_context *dapm = &codec->dapm;
2660 int i, irq_flags;
2661
2662 wm8996->codec = codec;
2663
2664 init_completion(&wm8996->dcs_done);
2665 init_completion(&wm8996->fll_lock);
2666
2667 dapm->idle_bias_off = true;
2668 dapm->bias_level = SND_SOC_BIAS_OFF;
2669
2670 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2671 if (ret != 0) {
2672 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2673 goto err;
2674 }
2675
2676 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2677 wm8996->supplies[i].supply = wm8996_supply_names[i];
2678
2679 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8996->supplies),
2680 wm8996->supplies);
2681 if (ret != 0) {
2682 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2683 goto err;
2684 }
2685
2686 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2687 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2688 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
c83495af
MB		 2689
2690 wm8996->cpvdd = regulator_get(&i2c->dev, "CPVDD");
2691 if (IS_ERR(wm8996->cpvdd)) {
2692 ret = PTR_ERR(wm8996->cpvdd);
2693 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
2694 goto err_get;
2695 }
a9ba6151
MB		 2696
2697 /* This should really be moved into the regulator core */
2698 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2699 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2700 &wm8996->disable_nb[i]);
2701 if (ret != 0) {
2702 dev_err(codec->dev,
2703 "Failed to register regulator notifier: %d\n",
2704 ret);
2705 }
2706 }
2707
2708 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2709 wm8996->supplies);
2710 if (ret != 0) {
2711 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
c83495af 2712 goto err_cpvdd;
a9ba6151
MB		 2713 }
2714
2715 if (wm8996->pdata.ldo_ena >= 0) {
2716 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2717 msleep(5);
2718 }
2719
2720 ret = snd_soc_read(codec, WM8996_SOFTWARE_RESET);
2721 if (ret < 0) {
2722 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2723 goto err_enable;
2724 }
2725 if (ret != 0x8915) {
2726 dev_err(codec->dev, "Device is not a WM8996, ID %x\n", ret);
2727 ret = -EINVAL;
2728 goto err_enable;
2729 }
2730
2731 ret = snd_soc_read(codec, WM8996_CHIP_REVISION);
2732 if (ret < 0) {
2733 dev_err(codec->dev, "Failed to read device revision: %d\n",
2734 ret);
2735 goto err_enable;
2736 }
2737
2738 dev_info(codec->dev, "revision %c\n",
2739 (ret & WM8996_CHIP_REV_MASK) + 'A');
2740
2741 if (wm8996->pdata.ldo_ena >= 0) {
2742 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2743 } else {
2744 ret = wm8996_reset(codec);
2745 if (ret < 0) {
2746 dev_err(codec->dev, "Failed to issue reset\n");
2747 goto err_enable;
2748 }
2749 }
2750
2751 codec->cache_only = true;
2752
2753 /* Apply platform data settings */
2754 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2755 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2756 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2757 wm8996->pdata.inr_mode);
2758
2759 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2760 if (!wm8996->pdata.gpio_default[i])
2761 continue;
2762
2763 snd_soc_write(codec, WM8996_GPIO_1 + i,
2764 wm8996->pdata.gpio_default[i] & 0xffff);
2765 }
2766
2767 if (wm8996->pdata.spkmute_seq)
2768 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2769 WM8996_SPK_MUTE_ENDIAN |
2770 WM8996_SPK_MUTE_SEQ1_MASK,
2771 wm8996->pdata.spkmute_seq);
2772
2773 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2774 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2775 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2776
2777 /* Latch volume update bits */
2778 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2779 WM8996_IN1_VU, WM8996_IN1_VU);
2780 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2781 WM8996_IN1_VU, WM8996_IN1_VU);
2782
2783 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2784 WM8996_DAC1_VU, WM8996_DAC1_VU);
2785 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2786 WM8996_DAC1_VU, WM8996_DAC1_VU);
2787 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2788 WM8996_DAC2_VU, WM8996_DAC2_VU);
2789 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2790 WM8996_DAC2_VU, WM8996_DAC2_VU);
2791
2792 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2793 WM8996_DAC1_VU, WM8996_DAC1_VU);
2794 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2795 WM8996_DAC1_VU, WM8996_DAC1_VU);
2796 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2797 WM8996_DAC2_VU, WM8996_DAC2_VU);
2798 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2799 WM8996_DAC2_VU, WM8996_DAC2_VU);
2800
2801 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2802 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2803 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2804 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2805 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2806 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2807 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2808 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2809
2810 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2811 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2812 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2813 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2814 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2815 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2816 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2817 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2818
2819 /* No support currently for the underclocked TDM modes and
2820 * pick a default TDM layout with each channel pair working with
2821 * slots 0 and 1. */
2822 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2823 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2824 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2825 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2826 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2827 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2828 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2829 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2830 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2831 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2832 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2833 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2834 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2835 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2836 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2837 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2838 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2839 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2840 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2841 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2842 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2843 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2844 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2845 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2846
2847 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2848 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2849 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2850 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2851 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2852 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2853 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2854 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2855
2856 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2857 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2858 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2859 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2860 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2861 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2862 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2863 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2864 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2865 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2866 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2867 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2868 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2869 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2870 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2871 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2872 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2873 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2874 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2875 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2876 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2877 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2878 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2879 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2880
2881 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2882 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2883 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2884 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2885 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2886 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2887 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2888 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2889
2890 if (wm8996->pdata.num_retune_mobile_cfgs)
2891 wm8996_retune_mobile_pdata(codec);
2892 else
2893 snd_soc_add_controls(codec, wm8996_eq_controls,
2894 ARRAY_SIZE(wm8996_eq_controls));
2895
2896 /* If the TX LRCLK pins are not in LRCLK mode configure the
2897 * AIFs to source their clocks from the RX LRCLKs.
2898 */
2899 if ((snd_soc_read(codec, WM8996_GPIO_1)))
2900 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2901 WM8996_AIF1TX_LRCLK_MODE,
2902 WM8996_AIF1TX_LRCLK_MODE);
2903
2904 if ((snd_soc_read(codec, WM8996_GPIO_2)))
2905 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2906 WM8996_AIF2TX_LRCLK_MODE,
2907 WM8996_AIF2TX_LRCLK_MODE);
2908
2909 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2910
2911 wm8996_init_gpio(codec);
2912
2913 if (i2c->irq) {
2914 if (wm8996->pdata.irq_flags)
2915 irq_flags = wm8996->pdata.irq_flags;
2916 else
2917 irq_flags = IRQF_TRIGGER_LOW;
2918
2919 irq_flags |= IRQF_ONESHOT;
2920
2921 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2922 ret = request_threaded_irq(i2c->irq, NULL,
2923 wm8996_edge_irq,
2924 irq_flags, "wm8996", codec);
2925 else
2926 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2927 irq_flags, "wm8996", codec);
2928
2929 if (ret == 0) {
2930 /* Unmask the interrupt */
2931 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2932 WM8996_IM_IRQ, 0);
2933
2934 /* Enable error reporting and DC servo status */
2935 snd_soc_update_bits(codec,
2936 WM8996_INTERRUPT_STATUS_2_MASK,
2937 WM8996_IM_DCS_DONE_23_EINT |
2938 WM8996_IM_DCS_DONE_01_EINT |
2939 WM8996_IM_FLL_LOCK_EINT |
2940 WM8996_IM_FIFOS_ERR_EINT,
2941 0);
2942 } else {
2943 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2944 ret);
2945 }
2946 }
2947
2948 return 0;
2949
2950err_enable:
2951 if (wm8996->pdata.ldo_ena >= 0)
2952 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2953
2954 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
c83495af
MB		 2955err_cpvdd:
2956 regulator_put(wm8996->cpvdd);
a9ba6151
MB		 2957err_get:
2958 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2959err:
2960 return ret;
2961}
2962
2963static int wm8996_remove(struct snd_soc_codec *codec)
2964{
2965 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2966 struct i2c_client *i2c = to_i2c_client(codec->dev);
2967 int i;
2968
2969 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2970 WM8996_IM_IRQ, WM8996_IM_IRQ);
2971
2972 if (i2c->irq)
2973 free_irq(i2c->irq, codec);
2974
2975 wm8996_free_gpio(codec);
2976
2977 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2978 regulator_unregister_notifier(wm8996->supplies[i].consumer,
2979 &wm8996->disable_nb[i]);
c83495af 2980 regulator_put(wm8996->cpvdd);
a9ba6151
MB		 2981 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2982
2983 return 0;
2984}
2985
2986static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
2987 .probe = wm8996_probe,
2988 .remove = wm8996_remove,
2989 .set_bias_level = wm8996_set_bias_level,
2990 .seq_notifier = wm8996_seq_notifier,
2991 .reg_cache_size = WM8996_MAX_REGISTER + 1,
2992 .reg_word_size = sizeof(u16),
2993 .reg_cache_default = wm8996_reg,
2994 .volatile_register = wm8996_volatile_register,
2995 .readable_register = wm8996_readable_register,
2996 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2997 .controls = wm8996_snd_controls,
2998 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2999 .dapm_widgets = wm8996_dapm_widgets,
3000 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
3001 .dapm_routes = wm8996_dapm_routes,
3002 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
3003 .set_pll = wm8996_set_fll,
3004};
3005
3006#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
3007 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
3008#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
3009 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
3010 SNDRV_PCM_FMTBIT_S32_LE)
3011
3012static struct snd_soc_dai_ops wm8996_dai_ops = {
3013 .set_fmt = wm8996_set_fmt,
3014 .hw_params = wm8996_hw_params,
3015 .set_sysclk = wm8996_set_sysclk,
3016};
3017
3018static struct snd_soc_dai_driver wm8996_dai[] = {
3019 {
3020 .name = "wm8996-aif1",
3021 .playback = {
3022 .stream_name = "AIF1 Playback",
3023 .channels_min = 1,
3024 .channels_max = 6,
3025 .rates = WM8996_RATES,
3026 .formats = WM8996_FORMATS,
3027 },
3028 .capture = {
3029 .stream_name = "AIF1 Capture",
3030 .channels_min = 1,
3031 .channels_max = 6,
3032 .rates = WM8996_RATES,
3033 .formats = WM8996_FORMATS,
3034 },
3035 .ops = &wm8996_dai_ops,
3036 },
3037 {
3038 .name = "wm8996-aif2",
3039 .playback = {
3040 .stream_name = "AIF2 Playback",
3041 .channels_min = 1,
3042 .channels_max = 2,
3043 .rates = WM8996_RATES,
3044 .formats = WM8996_FORMATS,
3045 },
3046 .capture = {
3047 .stream_name = "AIF2 Capture",
3048 .channels_min = 1,
3049 .channels_max = 2,
3050 .rates = WM8996_RATES,
3051 .formats = WM8996_FORMATS,
3052 },
3053 .ops = &wm8996_dai_ops,
3054 },
3055};
3056
3057static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3058 const struct i2c_device_id *id)
3059{
3060 struct wm8996_priv *wm8996;
3061 int ret;
3062
3063 wm8996 = kzalloc(sizeof(struct wm8996_priv), GFP_KERNEL);
3064 if (wm8996 == NULL)
3065 return -ENOMEM;
3066
3067 i2c_set_clientdata(i2c, wm8996);
3068
3069 if (dev_get_platdata(&i2c->dev))
3070 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
3071 sizeof(wm8996->pdata));
3072
3073 if (wm8996->pdata.ldo_ena > 0) {
3074 ret = gpio_request_one(wm8996->pdata.ldo_ena,
3075 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
3076 if (ret < 0) {
3077 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
3078 wm8996->pdata.ldo_ena, ret);
3079 goto err;
3080 }
3081 }
3082
3083 ret = snd_soc_register_codec(&i2c->dev,
3084 &soc_codec_dev_wm8996, wm8996_dai,
3085 ARRAY_SIZE(wm8996_dai));
3086 if (ret < 0)
3087 goto err_gpio;
3088
3089 return ret;
3090
3091err_gpio:
3092 if (wm8996->pdata.ldo_ena > 0)
3093 gpio_free(wm8996->pdata.ldo_ena);
3094err:
3095 kfree(wm8996);
3096
3097 return ret;
3098}
3099
3100static __devexit int wm8996_i2c_remove(struct i2c_client *client)
3101{
3102 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3103
3104 snd_soc_unregister_codec(&client->dev);
3105 if (wm8996->pdata.ldo_ena > 0)
3106 gpio_free(wm8996->pdata.ldo_ena);
3107 kfree(i2c_get_clientdata(client));
3108 return 0;
3109}
3110
3111static const struct i2c_device_id wm8996_i2c_id[] = {
3112 { "wm8996", 0 },
3113 { }
3114};
3115MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3116
3117static struct i2c_driver wm8996_i2c_driver = {
3118 .driver = {
3119 .name = "wm8996",
3120 .owner = THIS_MODULE,
3121 },
3122 .probe = wm8996_i2c_probe,
3123 .remove = __devexit_p(wm8996_i2c_remove),
3124 .id_table = wm8996_i2c_id,
3125};
3126
3127static int __init wm8996_modinit(void)
3128{
3129 int ret;
3130
3131 ret = i2c_add_driver(&wm8996_i2c_driver);
3132 if (ret != 0) {
3133 printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n",
3134 ret);
3135 }
3136
3137 return ret;
3138}
3139module_init(wm8996_modinit);
3140
3141static void __exit wm8996_exit(void)
3142{
3143 i2c_del_driver(&wm8996_i2c_driver);
3144}
3145module_exit(wm8996_exit);
3146
3147MODULE_DESCRIPTION("ASoC WM8996 driver");
3148MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3149MODULE_LICENSE("GPL");
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