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ASoC: wm5100: Implement DRC coefficient configuration
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8996.c
CommitLineData
a9ba6151
MB		 1/*
2 * wm8996.c - WM8996 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
79172746 22#include <linux/regmap.h>
a9ba6151
MB		 23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25#include <linux/workqueue.h>
26#include <sound/core.h>
27#include <sound/jack.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <trace/events/asoc.h>
34
35#include <sound/wm8996.h>
36#include "wm8996.h"
37
38#define WM8996_AIFS 2
39
40#define HPOUT1L 1
41#define HPOUT1R 2
42#define HPOUT2L 4
43#define HPOUT2R 8
44
c83495af 45#define WM8996_NUM_SUPPLIES 3
a9ba6151
MB		 46static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
47 "DBVDD",
48 "AVDD1",
49 "AVDD2",
a9ba6151
MB		 50};
51
52struct wm8996_priv {
b2d1e233 53 struct device *dev;
ee5f3872 54 struct regmap *regmap;
a9ba6151
MB		 55 struct snd_soc_codec *codec;
56
57 int ldo1ena;
58
59 int sysclk;
60 int sysclk_src;
61
62 int fll_src;
63 int fll_fref;
64 int fll_fout;
65
66 struct completion fll_lock;
67
68 u16 dcs_pending;
69 struct completion dcs_done;
70
71 u16 hpout_ena;
72 u16 hpout_pending;
73
74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
ded71dcb 76 int bg_ena;
a9ba6151
MB		 77
78 struct wm8996_pdata pdata;
79
80 int rx_rate[WM8996_AIFS];
81 int bclk_rate[WM8996_AIFS];
82
83 /* Platform dependant ReTune mobile configuration */
84 int num_retune_mobile_texts;
85 const char **retune_mobile_texts;
86 int retune_mobile_cfg[2];
87 struct soc_enum retune_mobile_enum;
88
89 struct snd_soc_jack *jack;
90 bool detecting;
91 bool jack_mic;
d7b35570 92 int jack_flips;
a9ba6151
MB		 93 wm8996_polarity_fn polarity_cb;
94
95#ifdef CONFIG_GPIOLIB
96 struct gpio_chip gpio_chip;
97#endif
98};
99
100/* We can't use the same notifier block for more than one supply and
101 * there's no way I can see to get from a callback to the caller
102 * except container_of().
103 */
104#define WM8996_REGULATOR_EVENT(n) \
105static int wm8996_regulator_event_##n(struct notifier_block *nb, \
106 unsigned long event, void *data) \
107{ \
108 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
109 disable_nb[n]); \
110 if (event & REGULATOR_EVENT_DISABLE) { \
1b76d2ee 111 regcache_mark_dirty(wm8996->regmap); \
a9ba6151
MB		 112 } \
113 return 0; \
114}
115
116WM8996_REGULATOR_EVENT(0)
117WM8996_REGULATOR_EVENT(1)
118WM8996_REGULATOR_EVENT(2)
a9ba6151 119
79172746
MB		 120static struct reg_default wm8996_reg[] = {
121 { WM8996_SOFTWARE_RESET, 0x8996 },
122 { WM8996_POWER_MANAGEMENT_1, 0x0 },
123 { WM8996_POWER_MANAGEMENT_2, 0x0 },
124 { WM8996_POWER_MANAGEMENT_3, 0x0 },
125 { WM8996_POWER_MANAGEMENT_4, 0x0 },
126 { WM8996_POWER_MANAGEMENT_5, 0x0 },
127 { WM8996_POWER_MANAGEMENT_6, 0x0 },
128 { WM8996_POWER_MANAGEMENT_7, 0x10 },
129 { WM8996_POWER_MANAGEMENT_8, 0x0 },
130 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
131 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
132 { WM8996_LINE_INPUT_CONTROL, 0x0 },
133 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
134 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
135 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
136 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
137 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
138 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
139 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
140 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
141 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
142 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
143 { WM8996_MICBIAS_1, 0x39 },
144 { WM8996_MICBIAS_2, 0x39 },
145 { WM8996_LDO_1, 0x3 },
146 { WM8996_LDO_2, 0x13 },
147 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
148 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
149 { WM8996_HEADPHONE_DETECT_1, 0x20 },
150 { WM8996_HEADPHONE_DETECT_2, 0x0 },
151 { WM8996_MIC_DETECT_1, 0x7600 },
152 { WM8996_MIC_DETECT_2, 0xbf },
153 { WM8996_CHARGE_PUMP_1, 0x1f25 },
154 { WM8996_CHARGE_PUMP_2, 0xab19 },
155 { WM8996_DC_SERVO_1, 0x0 },
156 { WM8996_DC_SERVO_2, 0x0 },
157 { WM8996_DC_SERVO_3, 0x0 },
158 { WM8996_DC_SERVO_5, 0x2a2a },
159 { WM8996_DC_SERVO_6, 0x0 },
160 { WM8996_DC_SERVO_7, 0x0 },
161 { WM8996_ANALOGUE_HP_1, 0x0 },
162 { WM8996_ANALOGUE_HP_2, 0x0 },
163 { WM8996_CONTROL_INTERFACE_1, 0x8004 },
164 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
165 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
166 { WM8996_AIF_CLOCKING_1, 0x0 },
167 { WM8996_AIF_CLOCKING_2, 0x0 },
168 { WM8996_CLOCKING_1, 0x10 },
169 { WM8996_CLOCKING_2, 0x0 },
170 { WM8996_AIF_RATE, 0x83 },
171 { WM8996_FLL_CONTROL_1, 0x0 },
172 { WM8996_FLL_CONTROL_2, 0x0 },
173 { WM8996_FLL_CONTROL_3, 0x0 },
174 { WM8996_FLL_CONTROL_4, 0x5dc0 },
175 { WM8996_FLL_CONTROL_5, 0xc84 },
176 { WM8996_FLL_EFS_1, 0x0 },
177 { WM8996_FLL_EFS_2, 0x2 },
178 { WM8996_AIF1_CONTROL, 0x0 },
179 { WM8996_AIF1_BCLK, 0x0 },
180 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
181 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
182 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
183 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
184 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
185 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
186 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
187 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
188 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
189 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
190 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
191 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
192 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
193 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
194 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
195 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
196 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
197 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
198 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
199 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
200 { WM8996_AIF1TX_TEST, 0x7 },
201 { WM8996_AIF2_CONTROL, 0x0 },
202 { WM8996_AIF2_BCLK, 0x0 },
203 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
204 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
205 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
206 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
207 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
208 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
209 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
210 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
211 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
212 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
213 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
214 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
215 { WM8996_AIF2TX_TEST, 0x1 },
216 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
217 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
218 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
219 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
220 { WM8996_DSP1_TX_FILTERS, 0x2000 },
221 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
222 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
223 { WM8996_DSP1_DRC_1, 0x98 },
224 { WM8996_DSP1_DRC_2, 0x845 },
225 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
226 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
227 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
228 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
229 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
230 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
231 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
232 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
233 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
234 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
235 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
236 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
237 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
238 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
239 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
240 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
241 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
242 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
243 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
244 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
245 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
246 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
247 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
248 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
249 { WM8996_DSP2_TX_FILTERS, 0x2000 },
250 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
251 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
252 { WM8996_DSP2_DRC_1, 0x98 },
253 { WM8996_DSP2_DRC_2, 0x845 },
254 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
255 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
256 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
257 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
258 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
259 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
260 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
261 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
262 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
263 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
264 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
265 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
266 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
267 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
268 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
269 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
270 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
271 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
272 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
273 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
274 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
275 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
276 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
277 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
278 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
279 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
280 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
281 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
282 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
283 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
284 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
285 { WM8996_DAC_SOFTMUTE, 0x0 },
286 { WM8996_OVERSAMPLING, 0xd },
287 { WM8996_SIDETONE, 0x1040 },
288 { WM8996_GPIO_1, 0xa101 },
289 { WM8996_GPIO_2, 0xa101 },
290 { WM8996_GPIO_3, 0xa101 },
291 { WM8996_GPIO_4, 0xa101 },
292 { WM8996_GPIO_5, 0xa101 },
293 { WM8996_PULL_CONTROL_1, 0x0 },
294 { WM8996_PULL_CONTROL_2, 0x140 },
295 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
296 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
297 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
298 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
299 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
300 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
301 { WM8996_WRITE_SEQUENCER_0, 0x1 },
302 { WM8996_WRITE_SEQUENCER_1, 0x1 },
303 { WM8996_WRITE_SEQUENCER_3, 0x6 },
304 { WM8996_WRITE_SEQUENCER_4, 0x40 },
305 { WM8996_WRITE_SEQUENCER_5, 0x1 },
306 { WM8996_WRITE_SEQUENCER_6, 0xf },
307 { WM8996_WRITE_SEQUENCER_7, 0x6 },
308 { WM8996_WRITE_SEQUENCER_8, 0x1 },
309 { WM8996_WRITE_SEQUENCER_9, 0x3 },
310 { WM8996_WRITE_SEQUENCER_10, 0x104 },
311 { WM8996_WRITE_SEQUENCER_12, 0x60 },
312 { WM8996_WRITE_SEQUENCER_13, 0x11 },
313 { WM8996_WRITE_SEQUENCER_14, 0x401 },
314 { WM8996_WRITE_SEQUENCER_16, 0x50 },
315 { WM8996_WRITE_SEQUENCER_17, 0x3 },
316 { WM8996_WRITE_SEQUENCER_18, 0x100 },
317 { WM8996_WRITE_SEQUENCER_20, 0x51 },
318 { WM8996_WRITE_SEQUENCER_21, 0x3 },
319 { WM8996_WRITE_SEQUENCER_22, 0x104 },
320 { WM8996_WRITE_SEQUENCER_23, 0xa },
321 { WM8996_WRITE_SEQUENCER_24, 0x60 },
322 { WM8996_WRITE_SEQUENCER_25, 0x3b },
323 { WM8996_WRITE_SEQUENCER_26, 0x502 },
324 { WM8996_WRITE_SEQUENCER_27, 0x100 },
325 { WM8996_WRITE_SEQUENCER_28, 0x2fff },
326 { WM8996_WRITE_SEQUENCER_32, 0x2fff },
327 { WM8996_WRITE_SEQUENCER_36, 0x2fff },
328 { WM8996_WRITE_SEQUENCER_40, 0x2fff },
329 { WM8996_WRITE_SEQUENCER_44, 0x2fff },
330 { WM8996_WRITE_SEQUENCER_48, 0x2fff },
331 { WM8996_WRITE_SEQUENCER_52, 0x2fff },
332 { WM8996_WRITE_SEQUENCER_56, 0x2fff },
333 { WM8996_WRITE_SEQUENCER_60, 0x2fff },
334 { WM8996_WRITE_SEQUENCER_64, 0x1 },
335 { WM8996_WRITE_SEQUENCER_65, 0x1 },
336 { WM8996_WRITE_SEQUENCER_67, 0x6 },
337 { WM8996_WRITE_SEQUENCER_68, 0x40 },
338 { WM8996_WRITE_SEQUENCER_69, 0x1 },
339 { WM8996_WRITE_SEQUENCER_70, 0xf },
340 { WM8996_WRITE_SEQUENCER_71, 0x6 },
341 { WM8996_WRITE_SEQUENCER_72, 0x1 },
342 { WM8996_WRITE_SEQUENCER_73, 0x3 },
343 { WM8996_WRITE_SEQUENCER_74, 0x104 },
344 { WM8996_WRITE_SEQUENCER_76, 0x60 },
345 { WM8996_WRITE_SEQUENCER_77, 0x11 },
346 { WM8996_WRITE_SEQUENCER_78, 0x401 },
347 { WM8996_WRITE_SEQUENCER_80, 0x50 },
348 { WM8996_WRITE_SEQUENCER_81, 0x3 },
349 { WM8996_WRITE_SEQUENCER_82, 0x100 },
350 { WM8996_WRITE_SEQUENCER_84, 0x60 },
351 { WM8996_WRITE_SEQUENCER_85, 0x3b },
352 { WM8996_WRITE_SEQUENCER_86, 0x502 },
353 { WM8996_WRITE_SEQUENCER_87, 0x100 },
354 { WM8996_WRITE_SEQUENCER_88, 0x2fff },
355 { WM8996_WRITE_SEQUENCER_92, 0x2fff },
356 { WM8996_WRITE_SEQUENCER_96, 0x2fff },
357 { WM8996_WRITE_SEQUENCER_100, 0x2fff },
358 { WM8996_WRITE_SEQUENCER_104, 0x2fff },
359 { WM8996_WRITE_SEQUENCER_108, 0x2fff },
360 { WM8996_WRITE_SEQUENCER_112, 0x2fff },
361 { WM8996_WRITE_SEQUENCER_116, 0x2fff },
362 { WM8996_WRITE_SEQUENCER_120, 0x2fff },
363 { WM8996_WRITE_SEQUENCER_124, 0x2fff },
364 { WM8996_WRITE_SEQUENCER_128, 0x1 },
365 { WM8996_WRITE_SEQUENCER_129, 0x1 },
366 { WM8996_WRITE_SEQUENCER_131, 0x6 },
367 { WM8996_WRITE_SEQUENCER_132, 0x40 },
368 { WM8996_WRITE_SEQUENCER_133, 0x1 },
369 { WM8996_WRITE_SEQUENCER_134, 0xf },
370 { WM8996_WRITE_SEQUENCER_135, 0x6 },
371 { WM8996_WRITE_SEQUENCER_136, 0x1 },
372 { WM8996_WRITE_SEQUENCER_137, 0x3 },
373 { WM8996_WRITE_SEQUENCER_138, 0x106 },
374 { WM8996_WRITE_SEQUENCER_140, 0x61 },
375 { WM8996_WRITE_SEQUENCER_141, 0x11 },
376 { WM8996_WRITE_SEQUENCER_142, 0x401 },
377 { WM8996_WRITE_SEQUENCER_144, 0x50 },
378 { WM8996_WRITE_SEQUENCER_145, 0x3 },
379 { WM8996_WRITE_SEQUENCER_146, 0x102 },
380 { WM8996_WRITE_SEQUENCER_148, 0x51 },
381 { WM8996_WRITE_SEQUENCER_149, 0x3 },
382 { WM8996_WRITE_SEQUENCER_150, 0x106 },
383 { WM8996_WRITE_SEQUENCER_151, 0xa },
384 { WM8996_WRITE_SEQUENCER_152, 0x61 },
385 { WM8996_WRITE_SEQUENCER_153, 0x3b },
386 { WM8996_WRITE_SEQUENCER_154, 0x502 },
387 { WM8996_WRITE_SEQUENCER_155, 0x100 },
388 { WM8996_WRITE_SEQUENCER_156, 0x2fff },
389 { WM8996_WRITE_SEQUENCER_160, 0x2fff },
390 { WM8996_WRITE_SEQUENCER_164, 0x2fff },
391 { WM8996_WRITE_SEQUENCER_168, 0x2fff },
392 { WM8996_WRITE_SEQUENCER_172, 0x2fff },
393 { WM8996_WRITE_SEQUENCER_176, 0x2fff },
394 { WM8996_WRITE_SEQUENCER_180, 0x2fff },
395 { WM8996_WRITE_SEQUENCER_184, 0x2fff },
396 { WM8996_WRITE_SEQUENCER_188, 0x2fff },
397 { WM8996_WRITE_SEQUENCER_192, 0x1 },
398 { WM8996_WRITE_SEQUENCER_193, 0x1 },
399 { WM8996_WRITE_SEQUENCER_195, 0x6 },
400 { WM8996_WRITE_SEQUENCER_196, 0x40 },
401 { WM8996_WRITE_SEQUENCER_197, 0x1 },
402 { WM8996_WRITE_SEQUENCER_198, 0xf },
403 { WM8996_WRITE_SEQUENCER_199, 0x6 },
404 { WM8996_WRITE_SEQUENCER_200, 0x1 },
405 { WM8996_WRITE_SEQUENCER_201, 0x3 },
406 { WM8996_WRITE_SEQUENCER_202, 0x106 },
407 { WM8996_WRITE_SEQUENCER_204, 0x61 },
408 { WM8996_WRITE_SEQUENCER_205, 0x11 },
409 { WM8996_WRITE_SEQUENCER_206, 0x401 },
410 { WM8996_WRITE_SEQUENCER_208, 0x50 },
411 { WM8996_WRITE_SEQUENCER_209, 0x3 },
412 { WM8996_WRITE_SEQUENCER_210, 0x102 },
413 { WM8996_WRITE_SEQUENCER_212, 0x61 },
414 { WM8996_WRITE_SEQUENCER_213, 0x3b },
415 { WM8996_WRITE_SEQUENCER_214, 0x502 },
416 { WM8996_WRITE_SEQUENCER_215, 0x100 },
417 { WM8996_WRITE_SEQUENCER_216, 0x2fff },
418 { WM8996_WRITE_SEQUENCER_220, 0x2fff },
419 { WM8996_WRITE_SEQUENCER_224, 0x2fff },
420 { WM8996_WRITE_SEQUENCER_228, 0x2fff },
421 { WM8996_WRITE_SEQUENCER_232, 0x2fff },
422 { WM8996_WRITE_SEQUENCER_236, 0x2fff },
423 { WM8996_WRITE_SEQUENCER_240, 0x2fff },
424 { WM8996_WRITE_SEQUENCER_244, 0x2fff },
425 { WM8996_WRITE_SEQUENCER_248, 0x2fff },
426 { WM8996_WRITE_SEQUENCER_252, 0x2fff },
427 { WM8996_WRITE_SEQUENCER_256, 0x60 },
428 { WM8996_WRITE_SEQUENCER_258, 0x601 },
429 { WM8996_WRITE_SEQUENCER_260, 0x50 },
430 { WM8996_WRITE_SEQUENCER_262, 0x100 },
431 { WM8996_WRITE_SEQUENCER_264, 0x1 },
432 { WM8996_WRITE_SEQUENCER_266, 0x104 },
433 { WM8996_WRITE_SEQUENCER_267, 0x100 },
434 { WM8996_WRITE_SEQUENCER_268, 0x2fff },
435 { WM8996_WRITE_SEQUENCER_272, 0x2fff },
436 { WM8996_WRITE_SEQUENCER_276, 0x2fff },
437 { WM8996_WRITE_SEQUENCER_280, 0x2fff },
438 { WM8996_WRITE_SEQUENCER_284, 0x2fff },
439 { WM8996_WRITE_SEQUENCER_288, 0x2fff },
440 { WM8996_WRITE_SEQUENCER_292, 0x2fff },
441 { WM8996_WRITE_SEQUENCER_296, 0x2fff },
442 { WM8996_WRITE_SEQUENCER_300, 0x2fff },
443 { WM8996_WRITE_SEQUENCER_304, 0x2fff },
444 { WM8996_WRITE_SEQUENCER_308, 0x2fff },
445 { WM8996_WRITE_SEQUENCER_312, 0x2fff },
446 { WM8996_WRITE_SEQUENCER_316, 0x2fff },
447 { WM8996_WRITE_SEQUENCER_320, 0x61 },
448 { WM8996_WRITE_SEQUENCER_322, 0x601 },
449 { WM8996_WRITE_SEQUENCER_324, 0x50 },
450 { WM8996_WRITE_SEQUENCER_326, 0x102 },
451 { WM8996_WRITE_SEQUENCER_328, 0x1 },
452 { WM8996_WRITE_SEQUENCER_330, 0x106 },
453 { WM8996_WRITE_SEQUENCER_331, 0x100 },
454 { WM8996_WRITE_SEQUENCER_332, 0x2fff },
455 { WM8996_WRITE_SEQUENCER_336, 0x2fff },
456 { WM8996_WRITE_SEQUENCER_340, 0x2fff },
457 { WM8996_WRITE_SEQUENCER_344, 0x2fff },
458 { WM8996_WRITE_SEQUENCER_348, 0x2fff },
459 { WM8996_WRITE_SEQUENCER_352, 0x2fff },
460 { WM8996_WRITE_SEQUENCER_356, 0x2fff },
461 { WM8996_WRITE_SEQUENCER_360, 0x2fff },
462 { WM8996_WRITE_SEQUENCER_364, 0x2fff },
463 { WM8996_WRITE_SEQUENCER_368, 0x2fff },
464 { WM8996_WRITE_SEQUENCER_372, 0x2fff },
465 { WM8996_WRITE_SEQUENCER_376, 0x2fff },
466 { WM8996_WRITE_SEQUENCER_380, 0x2fff },
467 { WM8996_WRITE_SEQUENCER_384, 0x60 },
468 { WM8996_WRITE_SEQUENCER_386, 0x601 },
469 { WM8996_WRITE_SEQUENCER_388, 0x61 },
470 { WM8996_WRITE_SEQUENCER_390, 0x601 },
471 { WM8996_WRITE_SEQUENCER_392, 0x50 },
472 { WM8996_WRITE_SEQUENCER_394, 0x300 },
473 { WM8996_WRITE_SEQUENCER_396, 0x1 },
474 { WM8996_WRITE_SEQUENCER_398, 0x304 },
475 { WM8996_WRITE_SEQUENCER_400, 0x40 },
476 { WM8996_WRITE_SEQUENCER_402, 0xf },
477 { WM8996_WRITE_SEQUENCER_404, 0x1 },
478 { WM8996_WRITE_SEQUENCER_407, 0x100 },
a9ba6151
MB		 479};
480
481static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
482static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
483static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
484static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
485static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
486static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
487static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
18a4eef3 488static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
a9ba6151
MB		 489
490static const char *sidetone_hpf_text[] = {
491 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
492};
493
494static const struct soc_enum sidetone_hpf =
18036b58 495 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
a9ba6151
MB		 496
497static const char *hpf_mode_text[] = {
498 "HiFi", "Custom", "Voice"
499};
500
501static const struct soc_enum dsp1tx_hpf_mode =
502 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
503
504static const struct soc_enum dsp2tx_hpf_mode =
505 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
506
507static const char *hpf_cutoff_text[] = {
508 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
509};
510
511static const struct soc_enum dsp1tx_hpf_cutoff =
512 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
513
514static const struct soc_enum dsp2tx_hpf_cutoff =
515 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
516
517static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
518{
519 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
520 struct wm8996_pdata *pdata = &wm8996->pdata;
521 int base, best, best_val, save, i, cfg, iface;
522
523 if (!wm8996->num_retune_mobile_texts)
524 return;
525
526 switch (block) {
527 case 0:
528 base = WM8996_DSP1_RX_EQ_GAINS_1;
529 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
530 WM8996_DSP1RX_SRC)
531 iface = 1;
532 else
533 iface = 0;
534 break;
535 case 1:
536 base = WM8996_DSP1_RX_EQ_GAINS_2;
537 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
538 WM8996_DSP2RX_SRC)
539 iface = 1;
540 else
541 iface = 0;
542 break;
543 default:
544 return;
545 }
546
547 /* Find the version of the currently selected configuration
548 * with the nearest sample rate. */
549 cfg = wm8996->retune_mobile_cfg[block];
550 best = 0;
551 best_val = INT_MAX;
552 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
553 if (strcmp(pdata->retune_mobile_cfgs[i].name,
554 wm8996->retune_mobile_texts[cfg]) == 0 &&
555 abs(pdata->retune_mobile_cfgs[i].rate
556 - wm8996->rx_rate[iface]) < best_val) {
557 best = i;
558 best_val = abs(pdata->retune_mobile_cfgs[i].rate
559 - wm8996->rx_rate[iface]);
560 }
561 }
562
563 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
564 block,
565 pdata->retune_mobile_cfgs[best].name,
566 pdata->retune_mobile_cfgs[best].rate,
567 wm8996->rx_rate[iface]);
568
569 /* The EQ will be disabled while reconfiguring it, remember the
570 * current configuration.
571 */
572 save = snd_soc_read(codec, base);
573 save &= WM8996_DSP1RX_EQ_ENA;
574
575 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
576 snd_soc_update_bits(codec, base + i, 0xffff,
577 pdata->retune_mobile_cfgs[best].regs[i]);
578
579 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
580}
581
582/* Icky as hell but saves code duplication */
583static int wm8996_get_retune_mobile_block(const char *name)
584{
585 if (strcmp(name, "DSP1 EQ Mode") == 0)
586 return 0;
587 if (strcmp(name, "DSP2 EQ Mode") == 0)
588 return 1;
589 return -EINVAL;
590}
591
592static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
593 struct snd_ctl_elem_value *ucontrol)
594{
595 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
596 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
597 struct wm8996_pdata *pdata = &wm8996->pdata;
598 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
599 int value = ucontrol->value.integer.value[0];
600
601 if (block < 0)
602 return block;
603
604 if (value >= pdata->num_retune_mobile_cfgs)
605 return -EINVAL;
606
607 wm8996->retune_mobile_cfg[block] = value;
608
609 wm8996_set_retune_mobile(codec, block);
610
611 return 0;
612}
613
614static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
615 struct snd_ctl_elem_value *ucontrol)
616{
617 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
618 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
619 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
620
621 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
622
623 return 0;
624}
625
626static const struct snd_kcontrol_new wm8996_snd_controls[] = {
627SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
628 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
629SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
630 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
631
632SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
633 0, 5, 24, 0, sidetone_tlv),
634SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
635 0, 5, 24, 0, sidetone_tlv),
636SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
637SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
638SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
639
640SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
641 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
642SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
643 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
644
645SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
646 13, 1, 0),
647SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
648SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
649SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
650
651SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
652 13, 1, 0),
653SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
654SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
655SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
656
657SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
658 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
659SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
660
661SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
662 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
663SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
664
665SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
666 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
667SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
668 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
669
670SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
671 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
672SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
673 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
674
675SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
676SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
677SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
678SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
679
680SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
681SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
682
18a4eef3 683SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
684SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
685
686SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
687 0, threedstereo_tlv),
688SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
689 0, threedstereo_tlv),
690
a9ba6151
MB		 691SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
692 8, 0, out_digital_tlv),
693SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
694 8, 0, out_digital_tlv),
695
696SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
697 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
698SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
699 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
700
701SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
702 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
703SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
704 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
705
706SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
707 spk_tlv),
708SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
709 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
710SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
711 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
712
713SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
714SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
bcec267a
KT		 715
716SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
717SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
718SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
29e3cc15
MB		 719SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
720 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
721 WM8996_DSP1TXR_DRC_ENA),
bcec267a
KT		 722
723SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
724SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
725SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
29e3cc15
MB		 726SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
727 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
728 WM8996_DSP2TXR_DRC_ENA),
a9ba6151
MB		 729};
730
731static const struct snd_kcontrol_new wm8996_eq_controls[] = {
732SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
733 eq_tlv),
734SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
735 eq_tlv),
736SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
737 eq_tlv),
738SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
739 eq_tlv),
740SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
741 eq_tlv),
742
743SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
744 eq_tlv),
745SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
746 eq_tlv),
747SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
748 eq_tlv),
749SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
750 eq_tlv),
751SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
752 eq_tlv),
753};
754
ded71dcb
MB		 755static void wm8996_bg_enable(struct snd_soc_codec *codec)
756{
757 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
758
759 wm8996->bg_ena++;
760 if (wm8996->bg_ena == 1) {
761 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
762 WM8996_BG_ENA, WM8996_BG_ENA);
763 msleep(2);
764 }
765}
766
767static void wm8996_bg_disable(struct snd_soc_codec *codec)
768{
769 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
770
771 wm8996->bg_ena--;
772 if (!wm8996->bg_ena)
773 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
774 WM8996_BG_ENA, 0);
775}
776
8259df12
MB		 777static int bg_event(struct snd_soc_dapm_widget *w,
778 struct snd_kcontrol *kcontrol, int event)
779{
ded71dcb 780 struct snd_soc_codec *codec = w->codec;
8259df12
MB		 781 int ret = 0;
782
783 switch (event) {
ded71dcb
MB		 784 case SND_SOC_DAPM_PRE_PMU:
785 wm8996_bg_enable(codec);
786 break;
787 case SND_SOC_DAPM_POST_PMD:
788 wm8996_bg_disable(codec);
8259df12
MB		 789 break;
790 default:
791 BUG();
792 ret = -EINVAL;
793 }
794
795 return ret;
796}
797
a9ba6151
MB		 798static int cp_event(struct snd_soc_dapm_widget *w,
799 struct snd_kcontrol *kcontrol, int event)
800{
c83495af
MB		 801 int ret = 0;
802
a9ba6151
MB		 803 switch (event) {
804 case SND_SOC_DAPM_POST_PMU:
805 msleep(5);
806 break;
807 default:
808 BUG();
c83495af 809 ret = -EINVAL;
a9ba6151
MB		 810 }
811
4a086e4c 812 return 0;
a9ba6151
MB		 813}
814
815static int rmv_short_event(struct snd_soc_dapm_widget *w,
816 struct snd_kcontrol *kcontrol, int event)
817{
818 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
819
820 /* Record which outputs we enabled */
821 switch (event) {
822 case SND_SOC_DAPM_PRE_PMD:
823 wm8996->hpout_pending &= ~w->shift;
824 break;
825 case SND_SOC_DAPM_PRE_PMU:
826 wm8996->hpout_pending |= w->shift;
827 break;
828 default:
829 BUG();
830 return -EINVAL;
831 }
832
833 return 0;
834}
835
836static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
837{
838 struct i2c_client *i2c = to_i2c_client(codec->dev);
839 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
f998f257 840 int ret;
a9ba6151
MB		 841 unsigned long timeout = 200;
842
843 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
844
845 /* Use the interrupt if possible */
846 do {
847 if (i2c->irq) {
848 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
849 msecs_to_jiffies(200));
850 if (timeout == 0)
851 dev_err(codec->dev, "DC servo timed out\n");
852
853 } else {
854 msleep(1);
f998f257 855 timeout--;
a9ba6151
MB		 856 }
857
858 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
859 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
f998f257 860 } while (timeout && ret & mask);
a9ba6151
MB		 861
862 if (timeout == 0)
863 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
864 else
865 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
866}
867
868static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
869 enum snd_soc_dapm_type event, int subseq)
870{
871 struct snd_soc_codec *codec = container_of(dapm,
872 struct snd_soc_codec, dapm);
873 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
874 u16 val, mask;
875
876 /* Complete any pending DC servo starts */
877 if (wm8996->dcs_pending) {
878 dev_dbg(codec->dev, "Starting DC servo for %x\n",
879 wm8996->dcs_pending);
880
881 /* Trigger a startup sequence */
882 wait_for_dc_servo(codec, wm8996->dcs_pending
883 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
884
885 wm8996->dcs_pending = 0;
886 }
887
888 if (wm8996->hpout_pending != wm8996->hpout_ena) {
889 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
890 wm8996->hpout_ena, wm8996->hpout_pending);
891
892 val = 0;
893 mask = 0;
894 if (wm8996->hpout_pending & HPOUT1L) {
895 val |= WM8996_HPOUT1L_RMV_SHORT;
896 mask |= WM8996_HPOUT1L_RMV_SHORT;
897 } else {
898 mask |= WM8996_HPOUT1L_RMV_SHORT |
899 WM8996_HPOUT1L_OUTP |
900 WM8996_HPOUT1L_DLY;
901 }
902
903 if (wm8996->hpout_pending & HPOUT1R) {
904 val |= WM8996_HPOUT1R_RMV_SHORT;
905 mask |= WM8996_HPOUT1R_RMV_SHORT;
906 } else {
907 mask |= WM8996_HPOUT1R_RMV_SHORT |
908 WM8996_HPOUT1R_OUTP |
909 WM8996_HPOUT1R_DLY;
910 }
911
912 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
913
914 val = 0;
915 mask = 0;
916 if (wm8996->hpout_pending & HPOUT2L) {
917 val |= WM8996_HPOUT2L_RMV_SHORT;
918 mask |= WM8996_HPOUT2L_RMV_SHORT;
919 } else {
920 mask |= WM8996_HPOUT2L_RMV_SHORT |
921 WM8996_HPOUT2L_OUTP |
922 WM8996_HPOUT2L_DLY;
923 }
924
925 if (wm8996->hpout_pending & HPOUT2R) {
926 val |= WM8996_HPOUT2R_RMV_SHORT;
927 mask |= WM8996_HPOUT2R_RMV_SHORT;
928 } else {
929 mask |= WM8996_HPOUT2R_RMV_SHORT |
930 WM8996_HPOUT2R_OUTP |
931 WM8996_HPOUT2R_DLY;
932 }
933
934 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
935
936 wm8996->hpout_ena = wm8996->hpout_pending;
937 }
938}
939
940static int dcs_start(struct snd_soc_dapm_widget *w,
941 struct snd_kcontrol *kcontrol, int event)
942{
943 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
944
945 switch (event) {
946 case SND_SOC_DAPM_POST_PMU:
947 wm8996->dcs_pending |= 1 << w->shift;
948 break;
949 default:
950 BUG();
951 return -EINVAL;
952 }
953
954 return 0;
955}
956
957static const char *sidetone_text[] = {
958 "IN1", "IN2",
959};
960
961static const struct soc_enum left_sidetone_enum =
962 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
963
964static const struct snd_kcontrol_new left_sidetone =
965 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
966
967static const struct soc_enum right_sidetone_enum =
968 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
969
970static const struct snd_kcontrol_new right_sidetone =
971 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
972
973static const char *spk_text[] = {
974 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
975};
976
977static const struct soc_enum spkl_enum =
978 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
979
980static const struct snd_kcontrol_new spkl_mux =
981 SOC_DAPM_ENUM("SPKL", spkl_enum);
982
983static const struct soc_enum spkr_enum =
984 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
985
986static const struct snd_kcontrol_new spkr_mux =
987 SOC_DAPM_ENUM("SPKR", spkr_enum);
988
989static const char *dsp1rx_text[] = {
990 "AIF1", "AIF2"
991};
992
993static const struct soc_enum dsp1rx_enum =
994 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
995
996static const struct snd_kcontrol_new dsp1rx =
997 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
998
999static const char *dsp2rx_text[] = {
1000 "AIF2", "AIF1"
1001};
1002
1003static const struct soc_enum dsp2rx_enum =
1004 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
1005
1006static const struct snd_kcontrol_new dsp2rx =
1007 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
1008
1009static const char *aif2tx_text[] = {
1010 "DSP2", "DSP1", "AIF1"
1011};
1012
1013static const struct soc_enum aif2tx_enum =
1014 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
1015
1016static const struct snd_kcontrol_new aif2tx =
1017 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
1018
1019static const char *inmux_text[] = {
1020 "ADC", "DMIC1", "DMIC2"
1021};
1022
1023static const struct soc_enum in1_enum =
1024 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
1025
1026static const struct snd_kcontrol_new in1_mux =
1027 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
1028
1029static const struct soc_enum in2_enum =
1030 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
1031
1032static const struct snd_kcontrol_new in2_mux =
1033 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
1034
1035static const struct snd_kcontrol_new dac2r_mix[] = {
1036SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1037 5, 1, 0),
1038SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1039 4, 1, 0),
1040SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
1041SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
1042};
1043
1044static const struct snd_kcontrol_new dac2l_mix[] = {
1045SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1046 5, 1, 0),
1047SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1048 4, 1, 0),
1049SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
1050SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
1051};
1052
1053static const struct snd_kcontrol_new dac1r_mix[] = {
1054SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1055 5, 1, 0),
1056SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1057 4, 1, 0),
1058SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
1059SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
1060};
1061
1062static const struct snd_kcontrol_new dac1l_mix[] = {
1063SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1064 5, 1, 0),
1065SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1066 4, 1, 0),
1067SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
1068SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
1069};
1070
1071static const struct snd_kcontrol_new dsp1txl[] = {
1072SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1073 1, 1, 0),
1074SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1075 0, 1, 0),
1076};
1077
1078static const struct snd_kcontrol_new dsp1txr[] = {
1079SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1080 1, 1, 0),
1081SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1082 0, 1, 0),
1083};
1084
1085static const struct snd_kcontrol_new dsp2txl[] = {
1086SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1087 1, 1, 0),
1088SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1089 0, 1, 0),
1090};
1091
1092static const struct snd_kcontrol_new dsp2txr[] = {
1093SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1094 1, 1, 0),
1095SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1096 0, 1, 0),
1097};
1098
1099
1100static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
1101SND_SOC_DAPM_INPUT("IN1LN"),
1102SND_SOC_DAPM_INPUT("IN1LP"),
1103SND_SOC_DAPM_INPUT("IN1RN"),
1104SND_SOC_DAPM_INPUT("IN1RP"),
1105
1106SND_SOC_DAPM_INPUT("IN2LN"),
1107SND_SOC_DAPM_INPUT("IN2LP"),
1108SND_SOC_DAPM_INPUT("IN2RN"),
1109SND_SOC_DAPM_INPUT("IN2RP"),
1110
1111SND_SOC_DAPM_INPUT("DMIC1DAT"),
1112SND_SOC_DAPM_INPUT("DMIC2DAT"),
1113
4a086e4c 1114SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20),
a9ba6151
MB		 1115SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
1116SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
1117SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
1118SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
4a086e4c 1119 SND_SOC_DAPM_POST_PMU),
ded71dcb
MB		 1120SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
1121 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
a9ba6151 1122SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
889c85c5
MB		 1123SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
1124SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
a9ba6151
MB		 1125SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
1126SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
1127
1128SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
1129SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
1130
7691cd74
MB		 1131SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
1132SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
1133SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
1134SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
a9ba6151
MB		 1135
1136SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1137SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1138
1139SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1140SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1141SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1142SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1143
1144SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1145SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1146
1147SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1148SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1149
1150SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1151SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1152SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1153SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1154
1155SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1156 dsp2txl, ARRAY_SIZE(dsp2txl)),
1157SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1158 dsp2txr, ARRAY_SIZE(dsp2txr)),
1159SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1160 dsp1txl, ARRAY_SIZE(dsp1txl)),
1161SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1162 dsp1txr, ARRAY_SIZE(dsp1txr)),
1163
1164SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1165 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1166SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1167 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1168SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1169 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1170SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1171 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1172
1173SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1174SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1175SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1176SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1177
32d2a0c1 1178SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
a9ba6151 1179 WM8996_POWER_MANAGEMENT_4, 9, 0),
32d2a0c1 1180SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 1,
a9ba6151
MB		 1181 WM8996_POWER_MANAGEMENT_4, 8, 0),
1182
ff39dbe9 1183SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
a9ba6151 1184 WM8996_POWER_MANAGEMENT_6, 9, 0),
ff39dbe9 1185SND_SOC_DAPM_AIF_OUT("AIF2TX0", "AIF2 Capture", 1,
a9ba6151
MB		 1186 WM8996_POWER_MANAGEMENT_6, 8, 0),
1187
1188SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1189 WM8996_POWER_MANAGEMENT_4, 5, 0),
1190SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1191 WM8996_POWER_MANAGEMENT_4, 4, 0),
1192SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1193 WM8996_POWER_MANAGEMENT_4, 3, 0),
1194SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1195 WM8996_POWER_MANAGEMENT_4, 2, 0),
1196SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1197 WM8996_POWER_MANAGEMENT_4, 1, 0),
1198SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1199 WM8996_POWER_MANAGEMENT_4, 0, 0),
1200
1201SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1202 WM8996_POWER_MANAGEMENT_6, 5, 0),
1203SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1204 WM8996_POWER_MANAGEMENT_6, 4, 0),
1205SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1206 WM8996_POWER_MANAGEMENT_6, 3, 0),
1207SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1208 WM8996_POWER_MANAGEMENT_6, 2, 0),
1209SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1210 WM8996_POWER_MANAGEMENT_6, 1, 0),
1211SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1212 WM8996_POWER_MANAGEMENT_6, 0, 0),
1213
1214/* We route as stereo pairs so define some dummy widgets to squash
1215 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1216SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1217SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1218SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1219SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1220SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1221
1222SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1223SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1224SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1225
1226SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1227SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1228SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1229SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1230
1231SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1232SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1233SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1234 SND_SOC_DAPM_POST_PMU),
1235SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1236SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1237 rmv_short_event,
1238 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1239
1240SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1241SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1242SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1243 SND_SOC_DAPM_POST_PMU),
1244SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1245SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1246 rmv_short_event,
1247 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1248
1249SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1250SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1251SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1252 SND_SOC_DAPM_POST_PMU),
1253SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1254SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1255 rmv_short_event,
1256 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1257
1258SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1259SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1260SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1261 SND_SOC_DAPM_POST_PMU),
1262SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1263SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1264 rmv_short_event,
1265 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1266
1267SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1268SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1269SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1270SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1271SND_SOC_DAPM_OUTPUT("SPKDAT"),
1272};
1273
1274static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1275 { "AIFCLK", NULL, "SYSCLK" },
1276 { "SYSDSPCLK", NULL, "SYSCLK" },
1277 { "Charge Pump", NULL, "SYSCLK" },
4a086e4c 1278 { "Charge Pump", NULL, "CPVDD" },
a9ba6151
MB		 1279
1280 { "MICB1", NULL, "LDO2" },
889c85c5 1281 { "MICB1", NULL, "MICB1 Audio" },
8259df12 1282 { "MICB1", NULL, "Bandgap" },
a9ba6151 1283 { "MICB2", NULL, "LDO2" },
889c85c5 1284 { "MICB2", NULL, "MICB2 Audio" },
8259df12 1285 { "MICB2", NULL, "Bandgap" },
a9ba6151
MB		 1286
1287 { "IN1L PGA", NULL, "IN2LN" },
1288 { "IN1L PGA", NULL, "IN2LP" },
1289 { "IN1L PGA", NULL, "IN1LN" },
1290 { "IN1L PGA", NULL, "IN1LP" },
8259df12 1291 { "IN1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1292
1293 { "IN1R PGA", NULL, "IN2RN" },
1294 { "IN1R PGA", NULL, "IN2RP" },
1295 { "IN1R PGA", NULL, "IN1RN" },
1296 { "IN1R PGA", NULL, "IN1RP" },
8259df12 1297 { "IN1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1298
1299 { "ADCL", NULL, "IN1L PGA" },
1300
1301 { "ADCR", NULL, "IN1R PGA" },
1302
1303 { "DMIC1L", NULL, "DMIC1DAT" },
1304 { "DMIC1R", NULL, "DMIC1DAT" },
1305 { "DMIC2L", NULL, "DMIC2DAT" },
1306 { "DMIC2R", NULL, "DMIC2DAT" },
1307
1308 { "DMIC2L", NULL, "DMIC2" },
1309 { "DMIC2R", NULL, "DMIC2" },
1310 { "DMIC1L", NULL, "DMIC1" },
1311 { "DMIC1R", NULL, "DMIC1" },
1312
1313 { "IN1L Mux", "ADC", "ADCL" },
1314 { "IN1L Mux", "DMIC1", "DMIC1L" },
1315 { "IN1L Mux", "DMIC2", "DMIC2L" },
1316
1317 { "IN1R Mux", "ADC", "ADCR" },
1318 { "IN1R Mux", "DMIC1", "DMIC1R" },
1319 { "IN1R Mux", "DMIC2", "DMIC2R" },
1320
1321 { "IN2L Mux", "ADC", "ADCL" },
1322 { "IN2L Mux", "DMIC1", "DMIC1L" },
1323 { "IN2L Mux", "DMIC2", "DMIC2L" },
1324
1325 { "IN2R Mux", "ADC", "ADCR" },
1326 { "IN2R Mux", "DMIC1", "DMIC1R" },
1327 { "IN2R Mux", "DMIC2", "DMIC2R" },
1328
1329 { "Left Sidetone", "IN1", "IN1L Mux" },
1330 { "Left Sidetone", "IN2", "IN2L Mux" },
1331
1332 { "Right Sidetone", "IN1", "IN1R Mux" },
1333 { "Right Sidetone", "IN2", "IN2R Mux" },
1334
1335 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1336 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1337
1338 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1339 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1340
1341 { "AIF1TX0", NULL, "DSP1TXL" },
1342 { "AIF1TX1", NULL, "DSP1TXR" },
1343 { "AIF1TX2", NULL, "DSP2TXL" },
1344 { "AIF1TX3", NULL, "DSP2TXR" },
1345 { "AIF1TX4", NULL, "AIF2RX0" },
1346 { "AIF1TX5", NULL, "AIF2RX1" },
1347
1348 { "AIF1RX0", NULL, "AIFCLK" },
1349 { "AIF1RX1", NULL, "AIFCLK" },
1350 { "AIF1RX2", NULL, "AIFCLK" },
1351 { "AIF1RX3", NULL, "AIFCLK" },
1352 { "AIF1RX4", NULL, "AIFCLK" },
1353 { "AIF1RX5", NULL, "AIFCLK" },
1354
1355 { "AIF2RX0", NULL, "AIFCLK" },
1356 { "AIF2RX1", NULL, "AIFCLK" },
1357
4f41adfd
MB		 1358 { "AIF1TX0", NULL, "AIFCLK" },
1359 { "AIF1TX1", NULL, "AIFCLK" },
1360 { "AIF1TX2", NULL, "AIFCLK" },
1361 { "AIF1TX3", NULL, "AIFCLK" },
1362 { "AIF1TX4", NULL, "AIFCLK" },
1363 { "AIF1TX5", NULL, "AIFCLK" },
1364
1365 { "AIF2TX0", NULL, "AIFCLK" },
1366 { "AIF2TX1", NULL, "AIFCLK" },
1367
a9ba6151
MB		 1368 { "DSP1RXL", NULL, "SYSDSPCLK" },
1369 { "DSP1RXR", NULL, "SYSDSPCLK" },
1370 { "DSP2RXL", NULL, "SYSDSPCLK" },
1371 { "DSP2RXR", NULL, "SYSDSPCLK" },
1372 { "DSP1TXL", NULL, "SYSDSPCLK" },
1373 { "DSP1TXR", NULL, "SYSDSPCLK" },
1374 { "DSP2TXL", NULL, "SYSDSPCLK" },
1375 { "DSP2TXR", NULL, "SYSDSPCLK" },
1376
1377 { "AIF1RXA", NULL, "AIF1RX0" },
1378 { "AIF1RXA", NULL, "AIF1RX1" },
1379 { "AIF1RXB", NULL, "AIF1RX2" },
1380 { "AIF1RXB", NULL, "AIF1RX3" },
1381 { "AIF1RXC", NULL, "AIF1RX4" },
1382 { "AIF1RXC", NULL, "AIF1RX5" },
1383
1384 { "AIF2RX", NULL, "AIF2RX0" },
1385 { "AIF2RX", NULL, "AIF2RX1" },
1386
1387 { "AIF2TX", "DSP2", "DSP2TX" },
1388 { "AIF2TX", "DSP1", "DSP1RX" },
1389 { "AIF2TX", "AIF1", "AIF1RXC" },
1390
1391 { "DSP1RXL", NULL, "DSP1RX" },
1392 { "DSP1RXR", NULL, "DSP1RX" },
1393 { "DSP2RXL", NULL, "DSP2RX" },
1394 { "DSP2RXR", NULL, "DSP2RX" },
1395
1396 { "DSP2TX", NULL, "DSP2TXL" },
1397 { "DSP2TX", NULL, "DSP2TXR" },
1398
1399 { "DSP1RX", "AIF1", "AIF1RXA" },
1400 { "DSP1RX", "AIF2", "AIF2RX" },
1401
1402 { "DSP2RX", "AIF1", "AIF1RXB" },
1403 { "DSP2RX", "AIF2", "AIF2RX" },
1404
1405 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1406 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1407 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1408 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1409
1410 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1411 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1412 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1413 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1414
1415 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1416 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1417 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1418 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1419
1420 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1421 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1422 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1423 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1424
1425 { "DAC1L", NULL, "DAC1L Mixer" },
1426 { "DAC1R", NULL, "DAC1R Mixer" },
1427 { "DAC2L", NULL, "DAC2L Mixer" },
1428 { "DAC2R", NULL, "DAC2R Mixer" },
1429
1430 { "HPOUT2L PGA", NULL, "Charge Pump" },
8259df12 1431 { "HPOUT2L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1432 { "HPOUT2L PGA", NULL, "DAC2L" },
1433 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1434 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1435 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1436 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1437
1438 { "HPOUT2R PGA", NULL, "Charge Pump" },
8259df12 1439 { "HPOUT2R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1440 { "HPOUT2R PGA", NULL, "DAC2R" },
1441 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1442 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1443 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1444 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1445
1446 { "HPOUT1L PGA", NULL, "Charge Pump" },
8259df12 1447 { "HPOUT1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1448 { "HPOUT1L PGA", NULL, "DAC1L" },
1449 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1450 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1451 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1452 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1453
1454 { "HPOUT1R PGA", NULL, "Charge Pump" },
8259df12 1455 { "HPOUT1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1456 { "HPOUT1R PGA", NULL, "DAC1R" },
1457 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1458 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1459 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1460 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1461
1462 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1463 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1464 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1465 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1466
1467 { "SPKL", "DAC1L", "DAC1L" },
1468 { "SPKL", "DAC1R", "DAC1R" },
1469 { "SPKL", "DAC2L", "DAC2L" },
1470 { "SPKL", "DAC2R", "DAC2R" },
1471
1472 { "SPKR", "DAC1L", "DAC1L" },
1473 { "SPKR", "DAC1R", "DAC1R" },
1474 { "SPKR", "DAC2L", "DAC2L" },
1475 { "SPKR", "DAC2R", "DAC2R" },
1476
1477 { "SPKL PGA", NULL, "SPKL" },
1478 { "SPKR PGA", NULL, "SPKR" },
1479
1480 { "SPKDAT", NULL, "SPKL PGA" },
1481 { "SPKDAT", NULL, "SPKR PGA" },
1482};
1483
79172746 1484static bool wm8996_readable_register(struct device *dev, unsigned int reg)
a9ba6151
MB		 1485{
1486 /* Due to the sparseness of the register map the compiler
1487 * output from an explicit switch statement ends up being much
1488 * more efficient than a table.
1489 */
1490 switch (reg) {
1491 case WM8996_SOFTWARE_RESET:
1492 case WM8996_POWER_MANAGEMENT_1:
1493 case WM8996_POWER_MANAGEMENT_2:
1494 case WM8996_POWER_MANAGEMENT_3:
1495 case WM8996_POWER_MANAGEMENT_4:
1496 case WM8996_POWER_MANAGEMENT_5:
1497 case WM8996_POWER_MANAGEMENT_6:
1498 case WM8996_POWER_MANAGEMENT_7:
1499 case WM8996_POWER_MANAGEMENT_8:
1500 case WM8996_LEFT_LINE_INPUT_VOLUME:
1501 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1502 case WM8996_LINE_INPUT_CONTROL:
1503 case WM8996_DAC1_HPOUT1_VOLUME:
1504 case WM8996_DAC2_HPOUT2_VOLUME:
1505 case WM8996_DAC1_LEFT_VOLUME:
1506 case WM8996_DAC1_RIGHT_VOLUME:
1507 case WM8996_DAC2_LEFT_VOLUME:
1508 case WM8996_DAC2_RIGHT_VOLUME:
1509 case WM8996_OUTPUT1_LEFT_VOLUME:
1510 case WM8996_OUTPUT1_RIGHT_VOLUME:
1511 case WM8996_OUTPUT2_LEFT_VOLUME:
1512 case WM8996_OUTPUT2_RIGHT_VOLUME:
1513 case WM8996_MICBIAS_1:
1514 case WM8996_MICBIAS_2:
1515 case WM8996_LDO_1:
1516 case WM8996_LDO_2:
1517 case WM8996_ACCESSORY_DETECT_MODE_1:
1518 case WM8996_ACCESSORY_DETECT_MODE_2:
1519 case WM8996_HEADPHONE_DETECT_1:
1520 case WM8996_HEADPHONE_DETECT_2:
1521 case WM8996_MIC_DETECT_1:
1522 case WM8996_MIC_DETECT_2:
1523 case WM8996_MIC_DETECT_3:
1524 case WM8996_CHARGE_PUMP_1:
1525 case WM8996_CHARGE_PUMP_2:
1526 case WM8996_DC_SERVO_1:
1527 case WM8996_DC_SERVO_2:
1528 case WM8996_DC_SERVO_3:
1529 case WM8996_DC_SERVO_5:
1530 case WM8996_DC_SERVO_6:
1531 case WM8996_DC_SERVO_7:
1532 case WM8996_DC_SERVO_READBACK_0:
1533 case WM8996_ANALOGUE_HP_1:
1534 case WM8996_ANALOGUE_HP_2:
1535 case WM8996_CHIP_REVISION:
1536 case WM8996_CONTROL_INTERFACE_1:
1537 case WM8996_WRITE_SEQUENCER_CTRL_1:
1538 case WM8996_WRITE_SEQUENCER_CTRL_2:
1539 case WM8996_AIF_CLOCKING_1:
1540 case WM8996_AIF_CLOCKING_2:
1541 case WM8996_CLOCKING_1:
1542 case WM8996_CLOCKING_2:
1543 case WM8996_AIF_RATE:
1544 case WM8996_FLL_CONTROL_1:
1545 case WM8996_FLL_CONTROL_2:
1546 case WM8996_FLL_CONTROL_3:
1547 case WM8996_FLL_CONTROL_4:
1548 case WM8996_FLL_CONTROL_5:
1549 case WM8996_FLL_CONTROL_6:
1550 case WM8996_FLL_EFS_1:
1551 case WM8996_FLL_EFS_2:
1552 case WM8996_AIF1_CONTROL:
1553 case WM8996_AIF1_BCLK:
1554 case WM8996_AIF1_TX_LRCLK_1:
1555 case WM8996_AIF1_TX_LRCLK_2:
1556 case WM8996_AIF1_RX_LRCLK_1:
1557 case WM8996_AIF1_RX_LRCLK_2:
1558 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1559 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1560 case WM8996_AIF1RX_DATA_CONFIGURATION:
1561 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1562 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1563 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1564 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1565 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1566 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1567 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1568 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1569 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1570 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1571 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1572 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1573 case WM8996_AIF1RX_MONO_CONFIGURATION:
1574 case WM8996_AIF1TX_TEST:
1575 case WM8996_AIF2_CONTROL:
1576 case WM8996_AIF2_BCLK:
1577 case WM8996_AIF2_TX_LRCLK_1:
1578 case WM8996_AIF2_TX_LRCLK_2:
1579 case WM8996_AIF2_RX_LRCLK_1:
1580 case WM8996_AIF2_RX_LRCLK_2:
1581 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1582 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1583 case WM8996_AIF2RX_DATA_CONFIGURATION:
1584 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1585 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1586 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1587 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1588 case WM8996_AIF2RX_MONO_CONFIGURATION:
1589 case WM8996_AIF2TX_TEST:
1590 case WM8996_DSP1_TX_LEFT_VOLUME:
1591 case WM8996_DSP1_TX_RIGHT_VOLUME:
1592 case WM8996_DSP1_RX_LEFT_VOLUME:
1593 case WM8996_DSP1_RX_RIGHT_VOLUME:
1594 case WM8996_DSP1_TX_FILTERS:
1595 case WM8996_DSP1_RX_FILTERS_1:
1596 case WM8996_DSP1_RX_FILTERS_2:
1597 case WM8996_DSP1_DRC_1:
1598 case WM8996_DSP1_DRC_2:
1599 case WM8996_DSP1_DRC_3:
1600 case WM8996_DSP1_DRC_4:
1601 case WM8996_DSP1_DRC_5:
1602 case WM8996_DSP1_RX_EQ_GAINS_1:
1603 case WM8996_DSP1_RX_EQ_GAINS_2:
1604 case WM8996_DSP1_RX_EQ_BAND_1_A:
1605 case WM8996_DSP1_RX_EQ_BAND_1_B:
1606 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1607 case WM8996_DSP1_RX_EQ_BAND_2_A:
1608 case WM8996_DSP1_RX_EQ_BAND_2_B:
1609 case WM8996_DSP1_RX_EQ_BAND_2_C:
1610 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1611 case WM8996_DSP1_RX_EQ_BAND_3_A:
1612 case WM8996_DSP1_RX_EQ_BAND_3_B:
1613 case WM8996_DSP1_RX_EQ_BAND_3_C:
1614 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1615 case WM8996_DSP1_RX_EQ_BAND_4_A:
1616 case WM8996_DSP1_RX_EQ_BAND_4_B:
1617 case WM8996_DSP1_RX_EQ_BAND_4_C:
1618 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1619 case WM8996_DSP1_RX_EQ_BAND_5_A:
1620 case WM8996_DSP1_RX_EQ_BAND_5_B:
1621 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1622 case WM8996_DSP2_TX_LEFT_VOLUME:
1623 case WM8996_DSP2_TX_RIGHT_VOLUME:
1624 case WM8996_DSP2_RX_LEFT_VOLUME:
1625 case WM8996_DSP2_RX_RIGHT_VOLUME:
1626 case WM8996_DSP2_TX_FILTERS:
1627 case WM8996_DSP2_RX_FILTERS_1:
1628 case WM8996_DSP2_RX_FILTERS_2:
1629 case WM8996_DSP2_DRC_1:
1630 case WM8996_DSP2_DRC_2:
1631 case WM8996_DSP2_DRC_3:
1632 case WM8996_DSP2_DRC_4:
1633 case WM8996_DSP2_DRC_5:
1634 case WM8996_DSP2_RX_EQ_GAINS_1:
1635 case WM8996_DSP2_RX_EQ_GAINS_2:
1636 case WM8996_DSP2_RX_EQ_BAND_1_A:
1637 case WM8996_DSP2_RX_EQ_BAND_1_B:
1638 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1639 case WM8996_DSP2_RX_EQ_BAND_2_A:
1640 case WM8996_DSP2_RX_EQ_BAND_2_B:
1641 case WM8996_DSP2_RX_EQ_BAND_2_C:
1642 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1643 case WM8996_DSP2_RX_EQ_BAND_3_A:
1644 case WM8996_DSP2_RX_EQ_BAND_3_B:
1645 case WM8996_DSP2_RX_EQ_BAND_3_C:
1646 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1647 case WM8996_DSP2_RX_EQ_BAND_4_A:
1648 case WM8996_DSP2_RX_EQ_BAND_4_B:
1649 case WM8996_DSP2_RX_EQ_BAND_4_C:
1650 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1651 case WM8996_DSP2_RX_EQ_BAND_5_A:
1652 case WM8996_DSP2_RX_EQ_BAND_5_B:
1653 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1654 case WM8996_DAC1_MIXER_VOLUMES:
1655 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1656 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1657 case WM8996_DAC2_MIXER_VOLUMES:
1658 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1659 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1660 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1661 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1662 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1663 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1664 case WM8996_DSP_TX_MIXER_SELECT:
1665 case WM8996_DAC_SOFTMUTE:
1666 case WM8996_OVERSAMPLING:
1667 case WM8996_SIDETONE:
1668 case WM8996_GPIO_1:
1669 case WM8996_GPIO_2:
1670 case WM8996_GPIO_3:
1671 case WM8996_GPIO_4:
1672 case WM8996_GPIO_5:
1673 case WM8996_PULL_CONTROL_1:
1674 case WM8996_PULL_CONTROL_2:
1675 case WM8996_INTERRUPT_STATUS_1:
1676 case WM8996_INTERRUPT_STATUS_2:
1677 case WM8996_INTERRUPT_RAW_STATUS_2:
1678 case WM8996_INTERRUPT_STATUS_1_MASK:
1679 case WM8996_INTERRUPT_STATUS_2_MASK:
1680 case WM8996_INTERRUPT_CONTROL:
1681 case WM8996_LEFT_PDM_SPEAKER:
1682 case WM8996_RIGHT_PDM_SPEAKER:
1683 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1684 case WM8996_PDM_SPEAKER_VOLUME:
1685 return 1;
1686 default:
1687 return 0;
1688 }
1689}
1690
79172746 1691static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
a9ba6151
MB		 1692{
1693 switch (reg) {
1694 case WM8996_SOFTWARE_RESET:
1695 case WM8996_CHIP_REVISION:
1696 case WM8996_LDO_1:
1697 case WM8996_LDO_2:
1698 case WM8996_INTERRUPT_STATUS_1:
1699 case WM8996_INTERRUPT_STATUS_2:
1700 case WM8996_INTERRUPT_RAW_STATUS_2:
1701 case WM8996_DC_SERVO_READBACK_0:
1702 case WM8996_DC_SERVO_2:
1703 case WM8996_DC_SERVO_6:
1704 case WM8996_DC_SERVO_7:
1705 case WM8996_FLL_CONTROL_6:
1706 case WM8996_MIC_DETECT_3:
1707 case WM8996_HEADPHONE_DETECT_1:
1708 case WM8996_HEADPHONE_DETECT_2:
1709 return 1;
1710 default:
1711 return 0;
1712 }
1713}
1714
ee5f3872 1715static int wm8996_reset(struct wm8996_priv *wm8996)
a9ba6151 1716{
ee5f3872 1717 if (wm8996->pdata.ldo_ena > 0) {
d5a7f23f 1718 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
ee5f3872
MB		 1719 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1720 return 0;
1721 } else {
1722 return regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
1723 0x8915);
1724 }
a9ba6151
MB		 1725}
1726
1727static const int bclk_divs[] = {
1728 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1729};
1730
1731static void wm8996_update_bclk(struct snd_soc_codec *codec)
1732{
1733 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1734 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1735
1736 /* Don't bother if we're in a low frequency idle mode that
1737 * can't support audio.
1738 */
1739 if (wm8996->sysclk < 64000)
1740 return;
1741
1742 for (aif = 0; aif < WM8996_AIFS; aif++) {
1743 switch (aif) {
1744 case 0:
1745 bclk_reg = WM8996_AIF1_BCLK;
1746 break;
1747 case 1:
1748 bclk_reg = WM8996_AIF2_BCLK;
1749 break;
1750 }
1751
1752 bclk_rate = wm8996->bclk_rate[aif];
1753
1754 /* Pick a divisor for BCLK as close as we can get to ideal */
1755 best = 0;
1756 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1757 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1758 if (cur_val < 0) /* BCLK table is sorted */
1759 break;
1760 best = i;
1761 }
1762 bclk_rate = wm8996->sysclk / bclk_divs[best];
1763 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1764 bclk_divs[best], bclk_rate);
1765
1766 snd_soc_update_bits(codec, bclk_reg,
1767 WM8996_AIF1_BCLK_DIV_MASK, best);
1768 }
1769}
1770
1771static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1772 enum snd_soc_bias_level level)
1773{
1774 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1775 int ret;
1776
1777 switch (level) {
1778 case SND_SOC_BIAS_ON:
a9ba6151 1779 case SND_SOC_BIAS_PREPARE:
a9ba6151
MB		 1780 break;
1781
1782 case SND_SOC_BIAS_STANDBY:
1783 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1784 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1785 wm8996->supplies);
1786 if (ret != 0) {
1787 dev_err(codec->dev,
1788 "Failed to enable supplies: %d\n",
1789 ret);
1790 return ret;
1791 }
1792
1793 if (wm8996->pdata.ldo_ena >= 0) {
1794 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1795 1);
1796 msleep(5);
1797 }
1798
79172746
MB		 1799 regcache_cache_only(codec->control_data, false);
1800 regcache_sync(codec->control_data);
a9ba6151 1801 }
a9ba6151
MB		 1802 break;
1803
1804 case SND_SOC_BIAS_OFF:
79172746 1805 regcache_cache_only(codec->control_data, true);
a9ba6151
MB		 1806 if (wm8996->pdata.ldo_ena >= 0)
1807 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1808 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1809 wm8996->supplies);
1810 break;
1811 }
1812
1813 codec->dapm.bias_level = level;
1814
1815 return 0;
1816}
1817
1818static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1819{
1820 struct snd_soc_codec *codec = dai->codec;
1821 int aifctrl = 0;
1822 int bclk = 0;
1823 int lrclk_tx = 0;
1824 int lrclk_rx = 0;
1825 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1826
1827 switch (dai->id) {
1828 case 0:
1829 aifctrl_reg = WM8996_AIF1_CONTROL;
1830 bclk_reg = WM8996_AIF1_BCLK;
1831 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1832 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1833 break;
1834 case 1:
1835 aifctrl_reg = WM8996_AIF2_CONTROL;
1836 bclk_reg = WM8996_AIF2_BCLK;
1837 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1838 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1839 break;
1840 default:
1841 BUG();
1842 return -EINVAL;
1843 }
1844
1845 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1846 case SND_SOC_DAIFMT_NB_NF:
1847 break;
1848 case SND_SOC_DAIFMT_IB_NF:
1849 bclk |= WM8996_AIF1_BCLK_INV;
1850 break;
1851 case SND_SOC_DAIFMT_NB_IF:
1852 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1853 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1854 break;
1855 case SND_SOC_DAIFMT_IB_IF:
1856 bclk |= WM8996_AIF1_BCLK_INV;
1857 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1858 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1859 break;
1860 }
1861
1862 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1863 case SND_SOC_DAIFMT_CBS_CFS:
1864 break;
1865 case SND_SOC_DAIFMT_CBS_CFM:
1866 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1867 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1868 break;
1869 case SND_SOC_DAIFMT_CBM_CFS:
1870 bclk |= WM8996_AIF1_BCLK_MSTR;
1871 break;
1872 case SND_SOC_DAIFMT_CBM_CFM:
1873 bclk |= WM8996_AIF1_BCLK_MSTR;
1874 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1875 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1876 break;
1877 default:
1878 return -EINVAL;
1879 }
1880
1881 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1882 case SND_SOC_DAIFMT_DSP_A:
1883 break;
1884 case SND_SOC_DAIFMT_DSP_B:
1885 aifctrl |= 1;
1886 break;
1887 case SND_SOC_DAIFMT_I2S:
1888 aifctrl |= 2;
1889 break;
1890 case SND_SOC_DAIFMT_LEFT_J:
1891 aifctrl |= 3;
1892 break;
1893 default:
1894 return -EINVAL;
1895 }
1896
1897 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1898 snd_soc_update_bits(codec, bclk_reg,
1899 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1900 bclk);
1901 snd_soc_update_bits(codec, lrclk_tx_reg,
1902 WM8996_AIF1TX_LRCLK_INV |
1903 WM8996_AIF1TX_LRCLK_MSTR,
1904 lrclk_tx);
1905 snd_soc_update_bits(codec, lrclk_rx_reg,
1906 WM8996_AIF1RX_LRCLK_INV |
1907 WM8996_AIF1RX_LRCLK_MSTR,
1908 lrclk_rx);
1909
1910 return 0;
1911}
1912
1913static const int dsp_divs[] = {
1914 48000, 32000, 16000, 8000
1915};
1916
1917static int wm8996_hw_params(struct snd_pcm_substream *substream,
1918 struct snd_pcm_hw_params *params,
1919 struct snd_soc_dai *dai)
1920{
1921 struct snd_soc_codec *codec = dai->codec;
1922 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1923 int bits, i, bclk_rate;
1924 int aifdata = 0;
1925 int lrclk = 0;
1926 int dsp = 0;
1927 int aifdata_reg, lrclk_reg, dsp_shift;
1928
1929 switch (dai->id) {
1930 case 0:
1931 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1932 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1933 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1934 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1935 } else {
1936 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1937 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1938 }
1939 dsp_shift = 0;
1940 break;
1941 case 1:
1942 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1943 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1944 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1945 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1946 } else {
1947 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1948 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1949 }
1950 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1951 break;
1952 default:
1953 BUG();
1954 return -EINVAL;
1955 }
1956
1957 bclk_rate = snd_soc_params_to_bclk(params);
1958 if (bclk_rate < 0) {
1959 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1960 return bclk_rate;
1961 }
1962
1963 wm8996->bclk_rate[dai->id] = bclk_rate;
1964 wm8996->rx_rate[dai->id] = params_rate(params);
1965
1966 /* Needs looking at for TDM */
1967 bits = snd_pcm_format_width(params_format(params));
1968 if (bits < 0)
1969 return bits;
1970 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1971
1972 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1973 if (dsp_divs[i] == params_rate(params))
1974 break;
1975 }
1976 if (i == ARRAY_SIZE(dsp_divs)) {
1977 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1978 params_rate(params));
1979 return -EINVAL;
1980 }
1981 dsp |= i << dsp_shift;
1982
1983 wm8996_update_bclk(codec);
1984
1985 lrclk = bclk_rate / params_rate(params);
1986 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1987 lrclk, bclk_rate / lrclk);
1988
1989 snd_soc_update_bits(codec, aifdata_reg,
1990 WM8996_AIF1TX_WL_MASK |
1991 WM8996_AIF1TX_SLOT_LEN_MASK,
1992 aifdata);
1993 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1994 lrclk);
1995 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
3205e662 1996 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
a9ba6151
MB		 1997
1998 return 0;
1999}
2000
2001static int wm8996_set_sysclk(struct snd_soc_dai *dai,
2002 int clk_id, unsigned int freq, int dir)
2003{
2004 struct snd_soc_codec *codec = dai->codec;
2005 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2006 int lfclk = 0;
2007 int ratediv = 0;
fed22007 2008 int sync = WM8996_REG_SYNC;
a9ba6151
MB		 2009 int src;
2010 int old;
2011
2012 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
2013 return 0;
2014
2015 /* Disable SYSCLK while we reconfigure */
2016 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
2017 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2018 WM8996_SYSCLK_ENA, 0);
2019
2020 switch (clk_id) {
2021 case WM8996_SYSCLK_MCLK1:
2022 wm8996->sysclk = freq;
2023 src = 0;
2024 break;
2025 case WM8996_SYSCLK_MCLK2:
2026 wm8996->sysclk = freq;
2027 src = 1;
2028 break;
2029 case WM8996_SYSCLK_FLL:
2030 wm8996->sysclk = freq;
2031 src = 2;
2032 break;
2033 default:
2034 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
2035 return -EINVAL;
2036 }
2037
2038 switch (wm8996->sysclk) {
2039 case 6144000:
2040 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2041 WM8996_SYSCLK_RATE, 0);
2042 break;
2043 case 24576000:
2044 ratediv = WM8996_SYSCLK_DIV;
37d5993c 2045 wm8996->sysclk /= 2;
a9ba6151
MB		 2046 case 12288000:
2047 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2048 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
2049 break;
2050 case 32000:
2051 case 32768:
2052 lfclk = WM8996_LFCLK_ENA;
fed22007 2053 sync = 0;
a9ba6151
MB		 2054 break;
2055 default:
2056 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
2057 wm8996->sysclk);
2058 return -EINVAL;
2059 }
2060
2061 wm8996_update_bclk(codec);
2062
2063 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2064 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
2065 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
2066 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
fed22007
MB		 2067 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
2068 WM8996_REG_SYNC, sync);
a9ba6151
MB		 2069 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2070 WM8996_SYSCLK_ENA, old);
2071
2072 wm8996->sysclk_src = clk_id;
2073
2074 return 0;
2075}
2076
2077struct _fll_div {
2078 u16 fll_fratio;
2079 u16 fll_outdiv;
2080 u16 fll_refclk_div;
2081 u16 fll_loop_gain;
2082 u16 fll_ref_freq;
2083 u16 n;
2084 u16 theta;
2085 u16 lambda;
2086};
2087
2088static struct {
2089 unsigned int min;
2090 unsigned int max;
2091 u16 fll_fratio;
2092 int ratio;
2093} fll_fratios[] = {
2094 { 0, 64000, 4, 16 },
2095 { 64000, 128000, 3, 8 },
2096 { 128000, 256000, 2, 4 },
2097 { 256000, 1000000, 1, 2 },
2098 { 1000000, 13500000, 0, 1 },
2099};
2100
2101static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2102 unsigned int Fout)
2103{
2104 unsigned int target;
2105 unsigned int div;
2106 unsigned int fratio, gcd_fll;
2107 int i;
2108
2109 /* Fref must be <=13.5MHz */
2110 div = 1;
2111 fll_div->fll_refclk_div = 0;
2112 while ((Fref / div) > 13500000) {
2113 div *= 2;
2114 fll_div->fll_refclk_div++;
2115
2116 if (div > 8) {
2117 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2118 Fref);
2119 return -EINVAL;
2120 }
2121 }
2122
2123 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2124
2125 /* Apply the division for our remaining calculations */
2126 Fref /= div;
2127
2128 if (Fref >= 3000000)
2129 fll_div->fll_loop_gain = 5;
2130 else
2131 fll_div->fll_loop_gain = 0;
2132
2133 if (Fref >= 48000)
2134 fll_div->fll_ref_freq = 0;
2135 else
2136 fll_div->fll_ref_freq = 1;
2137
2138 /* Fvco should be 90-100MHz; don't check the upper bound */
2139 div = 2;
2140 while (Fout * div < 90000000) {
2141 div++;
2142 if (div > 64) {
2143 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2144 Fout);
2145 return -EINVAL;
2146 }
2147 }
2148 target = Fout * div;
2149 fll_div->fll_outdiv = div - 1;
2150
2151 pr_debug("FLL Fvco=%dHz\n", target);
2152
2153 /* Find an appropraite FLL_FRATIO and factor it out of the target */
2154 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2155 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2156 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2157 fratio = fll_fratios[i].ratio;
2158 break;
2159 }
2160 }
2161 if (i == ARRAY_SIZE(fll_fratios)) {
2162 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2163 return -EINVAL;
2164 }
2165
2166 fll_div->n = target / (fratio * Fref);
2167
2168 if (target % Fref == 0) {
2169 fll_div->theta = 0;
2170 fll_div->lambda = 0;
2171 } else {
2172 gcd_fll = gcd(target, fratio * Fref);
2173
2174 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2175 / gcd_fll;
2176 fll_div->lambda = (fratio * Fref) / gcd_fll;
2177 }
2178
2179 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2180 fll_div->n, fll_div->theta, fll_div->lambda);
2181 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2182 fll_div->fll_fratio, fll_div->fll_outdiv,
2183 fll_div->fll_refclk_div);
2184
2185 return 0;
2186}
2187
2188static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2189 unsigned int Fref, unsigned int Fout)
2190{
2191 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2192 struct i2c_client *i2c = to_i2c_client(codec->dev);
2193 struct _fll_div fll_div;
2194 unsigned long timeout;
27b6d92a 2195 int ret, reg, retry;
a9ba6151
MB		 2196
2197 /* Any change? */
2198 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2199 Fout == wm8996->fll_fout)
2200 return 0;
2201
2202 if (Fout == 0) {
2203 dev_dbg(codec->dev, "FLL disabled\n");
2204
2205 wm8996->fll_fref = 0;
2206 wm8996->fll_fout = 0;
2207
2208 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2209 WM8996_FLL_ENA, 0);
2210
ded71dcb
MB		 2211 wm8996_bg_disable(codec);
2212
a9ba6151
MB		 2213 return 0;
2214 }
2215
2216 ret = fll_factors(&fll_div, Fref, Fout);
2217 if (ret != 0)
2218 return ret;
2219
2220 switch (source) {
2221 case WM8996_FLL_MCLK1:
2222 reg = 0;
2223 break;
2224 case WM8996_FLL_MCLK2:
2225 reg = 1;
2226 break;
2227 case WM8996_FLL_DACLRCLK1:
2228 reg = 2;
2229 break;
2230 case WM8996_FLL_BCLK1:
2231 reg = 3;
2232 break;
2233 default:
2234 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2235 return -EINVAL;
2236 }
2237
2238 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2239 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2240
2241 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2242 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2243 WM8996_FLL_REFCLK_SRC_MASK, reg);
2244
2245 reg = 0;
2246 if (fll_div.theta || fll_div.lambda)
2247 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2248 else
2249 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2250 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2251
2252 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2253 WM8996_FLL_OUTDIV_MASK |
2254 WM8996_FLL_FRATIO_MASK,
2255 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2256 (fll_div.fll_fratio));
2257
2258 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2259
2260 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2261 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2262 (fll_div.n << WM8996_FLL_N_SHIFT) |
2263 fll_div.fll_loop_gain);
2264
2265 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2266
ded71dcb
MB		 2267 /* Enable the bandgap if it's not already enabled */
2268 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2269 if (!(ret & WM8996_FLL_ENA))
2270 wm8996_bg_enable(codec);
2271
a4161945
MB		 2272 /* Clear any pending completions (eg, from failed startups) */
2273 try_wait_for_completion(&wm8996->fll_lock);
2274
a9ba6151
MB		 2275 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2276 WM8996_FLL_ENA, WM8996_FLL_ENA);
2277
2278 /* The FLL supports live reconfiguration - kick that in case we were
2279 * already enabled.
2280 */
2281 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2282
2283 /* Wait for the FLL to lock, using the interrupt if possible */
2284 if (Fref > 1000000)
2285 timeout = usecs_to_jiffies(300);
2286 else
2287 timeout = msecs_to_jiffies(2);
2288
27b6d92a
MB		 2289 /* Allow substantially longer if we've actually got the IRQ, poll
2290 * at a slightly higher rate if we don't.
2291 */
a9ba6151 2292 if (i2c->irq)
27b6d92a
MB		 2293 timeout *= 10;
2294 else
2295 timeout /= 2;
a9ba6151 2296
27b6d92a
MB		 2297 for (retry = 0; retry < 10; retry++) {
2298 ret = wait_for_completion_timeout(&wm8996->fll_lock,
2299 timeout);
2300 if (ret != 0) {
2301 WARN_ON(!i2c->irq);
2302 break;
2303 }
a9ba6151 2304
27b6d92a
MB		 2305 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2306 if (ret & WM8996_FLL_LOCK_STS)
2307 break;
2308 }
2309 if (retry == 10) {
a9ba6151
MB		 2310 dev_err(codec->dev, "Timed out waiting for FLL\n");
2311 ret = -ETIMEDOUT;
a9ba6151
MB		 2312 }
2313
2314 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2315
2316 wm8996->fll_fref = Fref;
2317 wm8996->fll_fout = Fout;
2318 wm8996->fll_src = source;
2319
2320 return ret;
2321}
2322
2323#ifdef CONFIG_GPIOLIB
2324static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2325{
2326 return container_of(chip, struct wm8996_priv, gpio_chip);
2327}
2328
2329static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2330{
2331 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151 2332
b2d1e233
MB		 2333 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2334 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
a9ba6151
MB		 2335}
2336
2337static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2338 unsigned offset, int value)
2339{
2340 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151
MB		 2341 int val;
2342
2343 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2344
b2d1e233
MB		 2345 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2346 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2347 WM8996_GP1_LVL, val);
a9ba6151
MB		 2348}
2349
2350static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2351{
2352 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
b2d1e233 2353 unsigned int reg;
a9ba6151
MB		 2354 int ret;
2355
b2d1e233 2356 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
a9ba6151
MB		 2357 if (ret < 0)
2358 return ret;
2359
b2d1e233 2360 return (reg & WM8996_GP1_LVL) != 0;
a9ba6151
MB		 2361}
2362
2363static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2364{
2365 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151 2366
b2d1e233
MB		 2367 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2368 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2369 (1 << WM8996_GP1_FN_SHIFT) |
2370 (1 << WM8996_GP1_DIR_SHIFT));
a9ba6151
MB		 2371}
2372
2373static struct gpio_chip wm8996_template_chip = {
2374 .label = "wm8996",
2375 .owner = THIS_MODULE,
2376 .direction_output = wm8996_gpio_direction_out,
2377 .set = wm8996_gpio_set,
2378 .direction_input = wm8996_gpio_direction_in,
2379 .get = wm8996_gpio_get,
2380 .can_sleep = 1,
2381};
2382
b2d1e233 2383static void wm8996_init_gpio(struct wm8996_priv *wm8996)
a9ba6151 2384{
a9ba6151
MB		 2385 int ret;
2386
2387 wm8996->gpio_chip = wm8996_template_chip;
2388 wm8996->gpio_chip.ngpio = 5;
b2d1e233 2389 wm8996->gpio_chip.dev = wm8996->dev;
a9ba6151
MB		 2390
2391 if (wm8996->pdata.gpio_base)
2392 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2393 else
2394 wm8996->gpio_chip.base = -1;
2395
2396 ret = gpiochip_add(&wm8996->gpio_chip);
2397 if (ret != 0)
b2d1e233 2398 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
a9ba6151
MB		 2399}
2400
b2d1e233 2401static void wm8996_free_gpio(struct wm8996_priv *wm8996)
a9ba6151 2402{
a9ba6151
MB		 2403 int ret;
2404
2405 ret = gpiochip_remove(&wm8996->gpio_chip);
2406 if (ret != 0)
b2d1e233 2407 dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret);
a9ba6151
MB		 2408}
2409#else
b2d1e233 2410static void wm8996_init_gpio(struct wm8996_priv *wm8996)
a9ba6151
MB		 2411{
2412}
2413
b2d1e233 2414static void wm8996_free_gpio(struct wm8996_priv *wm8996)
a9ba6151
MB		 2415{
2416}
2417#endif
2418
2419/**
2420 * wm8996_detect - Enable default WM8996 jack detection
2421 *
2422 * The WM8996 has advanced accessory detection support for headsets.
2423 * This function provides a default implementation which integrates
2424 * the majority of this functionality with minimal user configuration.
2425 *
2426 * This will detect headset, headphone and short circuit button and
2427 * will also detect inverted microphone ground connections and update
2428 * the polarity of the connections.
2429 */
2430int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2431 wm8996_polarity_fn polarity_cb)
2432{
2433 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2434
2435 wm8996->jack = jack;
2436 wm8996->detecting = true;
2437 wm8996->polarity_cb = polarity_cb;
d7b35570 2438 wm8996->jack_flips = 0;
a9ba6151
MB		 2439
2440 if (wm8996->polarity_cb)
2441 wm8996->polarity_cb(codec, 0);
2442
2443 /* Clear discarge to avoid noise during detection */
2444 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2445 WM8996_MICB1_DISCH, 0);
2446 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2447 WM8996_MICB2_DISCH, 0);
2448
2449 /* LDO2 powers the microphones, SYSCLK clocks detection */
2450 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2451 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2452
2453 /* We start off just enabling microphone detection - even a
2454 * plain headphone will trigger detection.
2455 */
2456 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2457 WM8996_MICD_ENA, WM8996_MICD_ENA);
2458
2459 /* Slowest detection rate, gives debounce for initial detection */
2460 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2461 WM8996_MICD_RATE_MASK,
2462 WM8996_MICD_RATE_MASK);
2463
2464 /* Enable interrupts and we're off */
2465 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
0b684cc1 2466 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
a9ba6151
MB		 2467
2468 return 0;
2469}
2470EXPORT_SYMBOL_GPL(wm8996_detect);
2471
0b684cc1
MB		 2472static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2473{
2474 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2475 int val, reg, report;
2476
2477 /* Assume headphone in error conditions; we need to report
2478 * something or we stall our state machine.
2479 */
2480 report = SND_JACK_HEADPHONE;
2481
2482 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2483 if (reg < 0) {
2484 dev_err(codec->dev, "Failed to read HPDET status\n");
2485 goto out;
2486 }
2487
2488 if (!(reg & WM8996_HP_DONE)) {
2489 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2490 goto out;
2491 }
2492
2493 val = reg & WM8996_HP_LVL_MASK;
2494
2495 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2496
2497 /* If we've got high enough impedence then report as line,
2498 * otherwise assume headphone.
2499 */
2500 if (val >= 126)
2501 report = SND_JACK_LINEOUT;
2502 else
2503 report = SND_JACK_HEADPHONE;
2504
2505out:
2506 if (wm8996->jack_mic)
2507 report |= SND_JACK_MICROPHONE;
2508
2509 snd_soc_jack_report(wm8996->jack, report,
2510 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2511
2512 wm8996->detecting = false;
2513
2514 /* If the output isn't running re-clamp it */
2515 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2516 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2517 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2518 WM8996_HPOUT1L_RMV_SHORT |
2519 WM8996_HPOUT1R_RMV_SHORT, 0);
2520
2521 /* Go back to looking at the microphone */
2522 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2523 WM8996_JD_MODE_MASK, 0);
2524 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2525 WM8996_MICD_ENA);
2526
2527 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2528 snd_soc_dapm_sync(&codec->dapm);
2529}
2530
2531static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2532{
2533 /* Unclamp the output, we can't measure while we're shorting it */
2534 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2535 WM8996_HPOUT1L_RMV_SHORT |
2536 WM8996_HPOUT1R_RMV_SHORT,
2537 WM8996_HPOUT1L_RMV_SHORT |
2538 WM8996_HPOUT1R_RMV_SHORT);
2539
2540 /* We need bandgap for HPDET */
2541 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2542 snd_soc_dapm_sync(&codec->dapm);
2543
2544 /* Go into headphone detect left mode */
2545 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2546 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2547 WM8996_JD_MODE_MASK, 1);
2548
2549 /* Trigger a measurement */
2550 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2551 WM8996_HP_POLL, WM8996_HP_POLL);
2552}
2553
d7b35570
MB		 2554static void wm8996_report_headphone(struct snd_soc_codec *codec)
2555{
2556 dev_dbg(codec->dev, "Headphone detected\n");
2557 wm8996_hpdet_start(codec);
2558
2559 /* Increase the detection rate a bit for responsiveness. */
2560 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2561 WM8996_MICD_RATE_MASK |
2562 WM8996_MICD_BIAS_STARTTIME_MASK,
2563 7 << WM8996_MICD_RATE_SHIFT |
2564 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2565}
2566
a9ba6151
MB		 2567static void wm8996_micd(struct snd_soc_codec *codec)
2568{
2569 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2570 int val, reg;
2571
2572 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2573
2574 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2575
2576 if (!(val & WM8996_MICD_VALID)) {
2577 dev_warn(codec->dev, "Microphone detection state invalid\n");
2578 return;
2579 }
2580
2581 /* No accessory, reset everything and report removal */
2582 if (!(val & WM8996_MICD_STS)) {
2583 dev_dbg(codec->dev, "Jack removal detected\n");
2584 wm8996->jack_mic = false;
2585 wm8996->detecting = true;
d7b35570 2586 wm8996->jack_flips = 0;
a9ba6151 2587 snd_soc_jack_report(wm8996->jack, 0,
0b684cc1
MB		 2588 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2589 SND_JACK_BTN_0);
2590
a9ba6151 2591 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
45ba82d8
MB		 2592 WM8996_MICD_RATE_MASK |
2593 WM8996_MICD_BIAS_STARTTIME_MASK,
2594 WM8996_MICD_RATE_MASK |
2595 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
a9ba6151
MB		 2596 return;
2597 }
2598
0b684cc1
MB		 2599 /* If the measurement is very high we've got a microphone,
2600 * either we just detected one or if we already reported then
2601 * we've got a button release event.
a9ba6151
MB		 2602 */
2603 if (val & 0x400) {
0b684cc1
MB		 2604 if (wm8996->detecting) {
2605 dev_dbg(codec->dev, "Microphone detected\n");
2606 wm8996->jack_mic = true;
2607 wm8996_hpdet_start(codec);
2608
2609 /* Increase poll rate to give better responsiveness
2610 * for buttons */
2611 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
45ba82d8
MB		 2612 WM8996_MICD_RATE_MASK |
2613 WM8996_MICD_BIAS_STARTTIME_MASK,
2614 5 << WM8996_MICD_RATE_SHIFT |
2615 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
0b684cc1
MB		 2616 } else {
2617 dev_dbg(codec->dev, "Mic button up\n");
2618 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2619 }
2620
2621 return;
a9ba6151
MB		 2622 }
2623
2624 /* If we detected a lower impedence during initial startup
2625 * then we probably have the wrong polarity, flip it. Don't
2626 * do this for the lowest impedences to speed up detection of
d7b35570
MB		 2627 * plain headphones. If both polarities report a low
2628 * impedence then give up and report headphones.
a9ba6151
MB		 2629 */
2630 if (wm8996->detecting && (val & 0x3f0)) {
d7b35570
MB		 2631 wm8996->jack_flips++;
2632
2633 if (wm8996->jack_flips > 1) {
2634 wm8996_report_headphone(codec);
2635 return;
2636 }
2637
a9ba6151
MB		 2638 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2639 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2640 WM8996_MICD_BIAS_SRC;
2641 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2642 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2643 WM8996_MICD_BIAS_SRC, reg);
2644
2645 if (wm8996->polarity_cb)
2646 wm8996->polarity_cb(codec,
2647 (reg & WM8996_MICD_SRC) != 0);
2648
2649 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2650 (reg & WM8996_MICD_SRC) != 0);
2651
2652 return;
2653 }
2654
2655 /* Don't distinguish between buttons, just report any low
2656 * impedence as BTN_0.
2657 */
2658 if (val & 0x3fc) {
2659 if (wm8996->jack_mic) {
2660 dev_dbg(codec->dev, "Mic button detected\n");
0b684cc1 2661 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
a9ba6151 2662 SND_JACK_BTN_0);
0b684cc1 2663 } else if (wm8996->detecting) {
d7b35570 2664 wm8996_report_headphone(codec);
a9ba6151
MB		 2665 }
2666 }
2667}
2668
2669static irqreturn_t wm8996_irq(int irq, void *data)
2670{
2671 struct snd_soc_codec *codec = data;
2672 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2673 int irq_val;
2674
2675 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2676 if (irq_val < 0) {
2677 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2678 irq_val);
2679 return IRQ_NONE;
2680 }
2681 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2682
2fde6e80
MB		 2683 if (!irq_val)
2684 return IRQ_NONE;
2685
84497091
MB		 2686 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2687
a9ba6151
MB		 2688 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2689 dev_dbg(codec->dev, "DC servo IRQ\n");
2690 complete(&wm8996->dcs_done);
2691 }
2692
2693 if (irq_val & WM8996_FIFOS_ERR_EINT)
2694 dev_err(codec->dev, "Digital core FIFO error\n");
2695
2696 if (irq_val & WM8996_FLL_LOCK_EINT) {
2697 dev_dbg(codec->dev, "FLL locked\n");
2698 complete(&wm8996->fll_lock);
2699 }
2700
2701 if (irq_val & WM8996_MICD_EINT)
2702 wm8996_micd(codec);
2703
0b684cc1
MB		 2704 if (irq_val & WM8996_HP_DONE_EINT)
2705 wm8996_hpdet_irq(codec);
2706
2fde6e80 2707 return IRQ_HANDLED;
a9ba6151
MB		 2708}
2709
2710static irqreturn_t wm8996_edge_irq(int irq, void *data)
2711{
2712 irqreturn_t ret = IRQ_NONE;
2713 irqreturn_t val;
2714
2715 do {
2716 val = wm8996_irq(irq, data);
2717 if (val != IRQ_NONE)
2718 ret = val;
2719 } while (val != IRQ_NONE);
2720
2721 return ret;
2722}
2723
2724static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2725{
2726 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2727 struct wm8996_pdata *pdata = &wm8996->pdata;
2728
2729 struct snd_kcontrol_new controls[] = {
2730 SOC_ENUM_EXT("DSP1 EQ Mode",
2731 wm8996->retune_mobile_enum,
2732 wm8996_get_retune_mobile_enum,
2733 wm8996_put_retune_mobile_enum),
2734 SOC_ENUM_EXT("DSP2 EQ Mode",
2735 wm8996->retune_mobile_enum,
2736 wm8996_get_retune_mobile_enum,
2737 wm8996_put_retune_mobile_enum),
2738 };
2739 int ret, i, j;
2740 const char **t;
2741
2742 /* We need an array of texts for the enum API but the number
2743 * of texts is likely to be less than the number of
2744 * configurations due to the sample rate dependency of the
2745 * configurations. */
2746 wm8996->num_retune_mobile_texts = 0;
2747 wm8996->retune_mobile_texts = NULL;
2748 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2749 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2750 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2751 wm8996->retune_mobile_texts[j]) == 0)
2752 break;
2753 }
2754
2755 if (j != wm8996->num_retune_mobile_texts)
2756 continue;
2757
2758 /* Expand the array... */
2759 t = krealloc(wm8996->retune_mobile_texts,
2760 sizeof(char *) *
2761 (wm8996->num_retune_mobile_texts + 1),
2762 GFP_KERNEL);
2763 if (t == NULL)
2764 continue;
2765
2766 /* ...store the new entry... */
2767 t[wm8996->num_retune_mobile_texts] =
2768 pdata->retune_mobile_cfgs[i].name;
2769
2770 /* ...and remember the new version. */
2771 wm8996->num_retune_mobile_texts++;
2772 wm8996->retune_mobile_texts = t;
2773 }
2774
2775 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2776 wm8996->num_retune_mobile_texts);
2777
2778 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2779 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2780
022658be 2781 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
a9ba6151
MB		 2782 if (ret != 0)
2783 dev_err(codec->dev,
2784 "Failed to add ReTune Mobile controls: %d\n", ret);
2785}
2786
79172746
MB		 2787static const struct regmap_config wm8996_regmap = {
2788 .reg_bits = 16,
2789 .val_bits = 16,
2790
2791 .max_register = WM8996_MAX_REGISTER,
2792 .reg_defaults = wm8996_reg,
2793 .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2794 .volatile_reg = wm8996_volatile_register,
2795 .readable_reg = wm8996_readable_register,
2796 .cache_type = REGCACHE_RBTREE,
2797};
2798
a9ba6151
MB		 2799static int wm8996_probe(struct snd_soc_codec *codec)
2800{
2801 int ret;
2802 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2803 struct i2c_client *i2c = to_i2c_client(codec->dev);
a9ba6151
MB		 2804 int i, irq_flags;
2805
2806 wm8996->codec = codec;
2807
2808 init_completion(&wm8996->dcs_done);
2809 init_completion(&wm8996->fll_lock);
2810
ee5f3872 2811 codec->control_data = wm8996->regmap;
79172746
MB		 2812
2813 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
a9ba6151
MB		 2814 if (ret != 0) {
2815 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
ee5f3872 2816 goto err;
a9ba6151
MB		 2817 }
2818
2819 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2820 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2821 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
c83495af 2822
a9ba6151
MB		 2823 /* This should really be moved into the regulator core */
2824 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2825 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2826 &wm8996->disable_nb[i]);
2827 if (ret != 0) {
2828 dev_err(codec->dev,
2829 "Failed to register regulator notifier: %d\n",
2830 ret);
2831 }
2832 }
2833
79172746 2834 regcache_cache_only(codec->control_data, true);
a9ba6151
MB		 2835
2836 /* Apply platform data settings */
2837 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2838 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2839 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2840 wm8996->pdata.inr_mode);
2841
2842 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2843 if (!wm8996->pdata.gpio_default[i])
2844 continue;
2845
2846 snd_soc_write(codec, WM8996_GPIO_1 + i,
2847 wm8996->pdata.gpio_default[i] & 0xffff);
2848 }
2849
2850 if (wm8996->pdata.spkmute_seq)
2851 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2852 WM8996_SPK_MUTE_ENDIAN |
2853 WM8996_SPK_MUTE_SEQ1_MASK,
2854 wm8996->pdata.spkmute_seq);
2855
2856 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2857 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2858 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2859
2860 /* Latch volume update bits */
2861 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2862 WM8996_IN1_VU, WM8996_IN1_VU);
2863 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2864 WM8996_IN1_VU, WM8996_IN1_VU);
2865
2866 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2867 WM8996_DAC1_VU, WM8996_DAC1_VU);
2868 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2869 WM8996_DAC1_VU, WM8996_DAC1_VU);
2870 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2871 WM8996_DAC2_VU, WM8996_DAC2_VU);
2872 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2873 WM8996_DAC2_VU, WM8996_DAC2_VU);
2874
2875 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2876 WM8996_DAC1_VU, WM8996_DAC1_VU);
2877 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2878 WM8996_DAC1_VU, WM8996_DAC1_VU);
2879 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2880 WM8996_DAC2_VU, WM8996_DAC2_VU);
2881 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2882 WM8996_DAC2_VU, WM8996_DAC2_VU);
2883
2884 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2885 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2886 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2887 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2888 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2889 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2890 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2891 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2892
2893 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2894 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2895 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2896 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2897 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2898 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2899 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2900 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2901
2902 /* No support currently for the underclocked TDM modes and
2903 * pick a default TDM layout with each channel pair working with
2904 * slots 0 and 1. */
2905 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2906 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2907 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2908 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2909 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2910 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2911 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2912 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2913 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2914 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2915 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2916 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2917 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2918 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2919 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2920 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2921 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2922 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2923 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2924 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2925 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2926 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2927 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2928 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2929
2930 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2931 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2932 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2933 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2934 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2935 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2936 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2937 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2938
2939 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2940 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2941 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2942 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2943 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2944 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2945 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2946 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2947 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2948 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2949 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2950 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2951 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2952 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2953 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2954 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2955 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2956 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2957 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2958 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2959 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2960 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2961 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2962 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2963
2964 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2965 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2966 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2967 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2968 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2969 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2970 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2971 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2972
2973 if (wm8996->pdata.num_retune_mobile_cfgs)
2974 wm8996_retune_mobile_pdata(codec);
2975 else
022658be 2976 snd_soc_add_codec_controls(codec, wm8996_eq_controls,
a9ba6151
MB		 2977 ARRAY_SIZE(wm8996_eq_controls));
2978
2979 /* If the TX LRCLK pins are not in LRCLK mode configure the
2980 * AIFs to source their clocks from the RX LRCLKs.
2981 */
2982 if ((snd_soc_read(codec, WM8996_GPIO_1)))
2983 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2984 WM8996_AIF1TX_LRCLK_MODE,
2985 WM8996_AIF1TX_LRCLK_MODE);
2986
2987 if ((snd_soc_read(codec, WM8996_GPIO_2)))
2988 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2989 WM8996_AIF2TX_LRCLK_MODE,
2990 WM8996_AIF2TX_LRCLK_MODE);
2991
a9ba6151
MB		 2992 if (i2c->irq) {
2993 if (wm8996->pdata.irq_flags)
2994 irq_flags = wm8996->pdata.irq_flags;
2995 else
2996 irq_flags = IRQF_TRIGGER_LOW;
2997
2998 irq_flags |= IRQF_ONESHOT;
2999
3000 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
3001 ret = request_threaded_irq(i2c->irq, NULL,
3002 wm8996_edge_irq,
3003 irq_flags, "wm8996", codec);
3004 else
3005 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
3006 irq_flags, "wm8996", codec);
3007
3008 if (ret == 0) {
3009 /* Unmask the interrupt */
3010 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3011 WM8996_IM_IRQ, 0);
3012
3013 /* Enable error reporting and DC servo status */
3014 snd_soc_update_bits(codec,
3015 WM8996_INTERRUPT_STATUS_2_MASK,
3016 WM8996_IM_DCS_DONE_23_EINT |
3017 WM8996_IM_DCS_DONE_01_EINT |
3018 WM8996_IM_FLL_LOCK_EINT |
3019 WM8996_IM_FIFOS_ERR_EINT,
3020 0);
3021 } else {
3022 dev_err(codec->dev, "Failed to request IRQ: %d\n",
3023 ret);
3024 }
3025 }
3026
3027 return 0;
3028
a9ba6151
MB		 3029err:
3030 return ret;
3031}
3032
3033static int wm8996_remove(struct snd_soc_codec *codec)
3034{
3035 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
3036 struct i2c_client *i2c = to_i2c_client(codec->dev);
3037 int i;
3038
3039 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3040 WM8996_IM_IRQ, WM8996_IM_IRQ);
3041
3042 if (i2c->irq)
3043 free_irq(i2c->irq, codec);
3044
a9ba6151
MB		 3045 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3046 regulator_unregister_notifier(wm8996->supplies[i].consumer,
3047 &wm8996->disable_nb[i]);
3048 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3049
3050 return 0;
3051}
3052
1b39bf34
MB		 3053static int wm8996_soc_volatile_register(struct snd_soc_codec *codec,
3054 unsigned int reg)
3055{
3056 return true;
3057}
3058
a9ba6151
MB		 3059static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
3060 .probe = wm8996_probe,
3061 .remove = wm8996_remove,
3062 .set_bias_level = wm8996_set_bias_level,
eb3032f8 3063 .idle_bias_off = true,
a9ba6151 3064 .seq_notifier = wm8996_seq_notifier,
a9ba6151
MB		 3065 .controls = wm8996_snd_controls,
3066 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
3067 .dapm_widgets = wm8996_dapm_widgets,
3068 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
3069 .dapm_routes = wm8996_dapm_routes,
3070 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
3071 .set_pll = wm8996_set_fll,
1b39bf34
MB		 3072 .reg_cache_size = WM8996_MAX_REGISTER,
3073 .volatile_register = wm8996_soc_volatile_register,
a9ba6151
MB		 3074};
3075
3076#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
3077 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
3078#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
3079 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
3080 SNDRV_PCM_FMTBIT_S32_LE)
3081
85e7652d 3082static const struct snd_soc_dai_ops wm8996_dai_ops = {
a9ba6151
MB		 3083 .set_fmt = wm8996_set_fmt,
3084 .hw_params = wm8996_hw_params,
3085 .set_sysclk = wm8996_set_sysclk,
3086};
3087
3088static struct snd_soc_dai_driver wm8996_dai[] = {
3089 {
3090 .name = "wm8996-aif1",
3091 .playback = {
3092 .stream_name = "AIF1 Playback",
3093 .channels_min = 1,
3094 .channels_max = 6,
3095 .rates = WM8996_RATES,
3096 .formats = WM8996_FORMATS,
a4b52337 3097 .sig_bits = 24,
a9ba6151
MB		 3098 },
3099 .capture = {
3100 .stream_name = "AIF1 Capture",
3101 .channels_min = 1,
3102 .channels_max = 6,
3103 .rates = WM8996_RATES,
3104 .formats = WM8996_FORMATS,
a4b52337 3105 .sig_bits = 24,
a9ba6151
MB		 3106 },
3107 .ops = &wm8996_dai_ops,
3108 },
3109 {
3110 .name = "wm8996-aif2",
3111 .playback = {
3112 .stream_name = "AIF2 Playback",
3113 .channels_min = 1,
3114 .channels_max = 2,
3115 .rates = WM8996_RATES,
3116 .formats = WM8996_FORMATS,
a4b52337 3117 .sig_bits = 24,
a9ba6151
MB		 3118 },
3119 .capture = {
3120 .stream_name = "AIF2 Capture",
3121 .channels_min = 1,
3122 .channels_max = 2,
3123 .rates = WM8996_RATES,
3124 .formats = WM8996_FORMATS,
a4b52337 3125 .sig_bits = 24,
a9ba6151
MB		 3126 },
3127 .ops = &wm8996_dai_ops,
3128 },
3129};
3130
3131static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3132 const struct i2c_device_id *id)
3133{
3134 struct wm8996_priv *wm8996;
ee5f3872
MB		 3135 int ret, i;
3136 unsigned int reg;
a9ba6151 3137
a290986b
MB		 3138 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
3139 GFP_KERNEL);
a9ba6151
MB		 3140 if (wm8996 == NULL)
3141 return -ENOMEM;
3142
3143 i2c_set_clientdata(i2c, wm8996);
b2d1e233 3144 wm8996->dev = &i2c->dev;
a9ba6151
MB		 3145
3146 if (dev_get_platdata(&i2c->dev))
3147 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
3148 sizeof(wm8996->pdata));
3149
3150 if (wm8996->pdata.ldo_ena > 0) {
3151 ret = gpio_request_one(wm8996->pdata.ldo_ena,
3152 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
3153 if (ret < 0) {
3154 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
3155 wm8996->pdata.ldo_ena, ret);
3156 goto err;
3157 }
3158 }
3159
ee5f3872
MB		 3160 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3161 wm8996->supplies[i].supply = wm8996_supply_names[i];
3162
24e0c57b
MB		 3163 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
3164 wm8996->supplies);
ee5f3872
MB		 3165 if (ret != 0) {
3166 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3167 goto err_gpio;
3168 }
3169
ee5f3872
MB		 3170 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
3171 wm8996->supplies);
3172 if (ret != 0) {
3173 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
24e0c57b 3174 goto err_gpio;
ee5f3872
MB		 3175 }
3176
3177 if (wm8996->pdata.ldo_ena > 0) {
3178 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
3179 msleep(5);
3180 }
3181
3182 wm8996->regmap = regmap_init_i2c(i2c, &wm8996_regmap);
3183 if (IS_ERR(wm8996->regmap)) {
3184 ret = PTR_ERR(wm8996->regmap);
3185 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
3186 goto err_enable;
3187 }
3188
3189 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
3190 if (ret < 0) {
3191 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
3192 goto err_regmap;
3193 }
3194 if (reg != 0x8915) {
905b4195 3195 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
ee5f3872
MB		 3196 ret = -EINVAL;
3197 goto err_regmap;
3198 }
3199
3200 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
3201 if (ret < 0) {
3202 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3203 ret);
3204 goto err_regmap;
3205 }
3206
3207 dev_info(&i2c->dev, "revision %c\n",
3208 (reg & WM8996_CHIP_REV_MASK) + 'A');
3209
3210 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3211
3212 ret = wm8996_reset(wm8996);
3213 if (ret < 0) {
3214 dev_err(&i2c->dev, "Failed to issue reset\n");
3215 goto err_regmap;
3216 }
3217
b2d1e233
MB		 3218 wm8996_init_gpio(wm8996);
3219
a9ba6151
MB		 3220 ret = snd_soc_register_codec(&i2c->dev,
3221 &soc_codec_dev_wm8996, wm8996_dai,
3222 ARRAY_SIZE(wm8996_dai));
3223 if (ret < 0)
b2d1e233 3224 goto err_gpiolib;
a9ba6151
MB		 3225
3226 return ret;
3227
b2d1e233
MB		 3228err_gpiolib:
3229 wm8996_free_gpio(wm8996);
ee5f3872
MB		 3230err_regmap:
3231 regmap_exit(wm8996->regmap);
3232err_enable:
3233 if (wm8996->pdata.ldo_ena > 0)
3234 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3235 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
a9ba6151
MB		 3236err_gpio:
3237 if (wm8996->pdata.ldo_ena > 0)
3238 gpio_free(wm8996->pdata.ldo_ena);
3239err:
a9ba6151
MB		 3240
3241 return ret;
3242}
3243
3244static __devexit int wm8996_i2c_remove(struct i2c_client *client)
3245{
3246 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3247
3248 snd_soc_unregister_codec(&client->dev);
b2d1e233 3249 wm8996_free_gpio(wm8996);
ee5f3872
MB		 3250 regmap_exit(wm8996->regmap);
3251 if (wm8996->pdata.ldo_ena > 0) {
3252 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
a9ba6151 3253 gpio_free(wm8996->pdata.ldo_ena);
ee5f3872 3254 }
a9ba6151
MB		 3255 return 0;
3256}
3257
3258static const struct i2c_device_id wm8996_i2c_id[] = {
3259 { "wm8996", 0 },
3260 { }
3261};
3262MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3263
3264static struct i2c_driver wm8996_i2c_driver = {
3265 .driver = {
3266 .name = "wm8996",
3267 .owner = THIS_MODULE,
3268 },
3269 .probe = wm8996_i2c_probe,
3270 .remove = __devexit_p(wm8996_i2c_remove),
3271 .id_table = wm8996_i2c_id,
3272};
3273
8005f394 3274module_i2c_driver(wm8996_i2c_driver);
a9ba6151
MB		 3275
3276MODULE_DESCRIPTION("ASoC WM8996 driver");
3277MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3278MODULE_LICENSE("GPL");
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