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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
b67f4487 | 29 | |
6479285d | 30 | #include <sound/asoundef.h> |
b67f4487 C |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/initval.h> | |
35 | #include <sound/soc.h> | |
453c4990 | 36 | #include <sound/dmaengine_pcm.h> |
87c19364 | 37 | #include <sound/omap-pcm.h> |
b67f4487 C |
38 | |
39 | #include "davinci-pcm.h" | |
f3f9cfa8 | 40 | #include "edma-pcm.h" |
b67f4487 C |
41 | #include "davinci-mcasp.h" |
42 | ||
0bf0e8ae PU |
43 | #define MCASP_MAX_AFIFO_DEPTH 64 |
44 | ||
1cc0c054 PU |
45 | static u32 context_regs[] = { |
46 | DAVINCI_MCASP_TXFMCTL_REG, | |
47 | DAVINCI_MCASP_RXFMCTL_REG, | |
48 | DAVINCI_MCASP_TXFMT_REG, | |
49 | DAVINCI_MCASP_RXFMT_REG, | |
50 | DAVINCI_MCASP_ACLKXCTL_REG, | |
51 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
52 | DAVINCI_MCASP_AHCLKXCTL_REG, |
53 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 54 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
55 | DAVINCI_MCASP_RXMASK_REG, |
56 | DAVINCI_MCASP_TXMASK_REG, | |
57 | DAVINCI_MCASP_RXTDM_REG, | |
58 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
59 | }; |
60 | ||
790bb94b | 61 | struct davinci_mcasp_context { |
1cc0c054 | 62 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
63 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
64 | u32 *xrsr_regs; /* for serializer configuration */ | |
790bb94b PU |
65 | }; |
66 | ||
70091a3e | 67 | struct davinci_mcasp { |
21400a72 | 68 | struct davinci_pcm_dma_params dma_params[2]; |
453c4990 | 69 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 70 | void __iomem *base; |
487dce88 | 71 | u32 fifo_base; |
21400a72 PU |
72 | struct device *dev; |
73 | ||
74 | /* McASP specific data */ | |
75 | int tdm_slots; | |
76 | u8 op_mode; | |
77 | u8 num_serializer; | |
78 | u8 *serial_dir; | |
79 | u8 version; | |
8267525c | 80 | u8 bclk_div; |
21400a72 | 81 | u16 bclk_lrclk_ratio; |
4dcb5a0b | 82 | int streams; |
21400a72 | 83 | |
ab8b14b6 JS |
84 | int sysclk_freq; |
85 | bool bclk_master; | |
86 | ||
21400a72 PU |
87 | /* McASP FIFO related */ |
88 | u8 txnumevt; | |
89 | u8 rxnumevt; | |
90 | ||
cbc7956c PU |
91 | bool dat_port; |
92 | ||
21400a72 | 93 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 94 | struct davinci_mcasp_context context; |
21400a72 PU |
95 | #endif |
96 | }; | |
97 | ||
f68205a7 PU |
98 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
99 | u32 val) | |
b67f4487 | 100 | { |
f68205a7 | 101 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
102 | __raw_writel(__raw_readl(reg) | val, reg); |
103 | } | |
104 | ||
f68205a7 PU |
105 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
106 | u32 val) | |
b67f4487 | 107 | { |
f68205a7 | 108 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
109 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
110 | } | |
111 | ||
f68205a7 PU |
112 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
113 | u32 val, u32 mask) | |
b67f4487 | 114 | { |
f68205a7 | 115 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
116 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
117 | } | |
118 | ||
f68205a7 PU |
119 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
120 | u32 val) | |
b67f4487 | 121 | { |
f68205a7 | 122 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
123 | } |
124 | ||
f68205a7 | 125 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 126 | { |
f68205a7 | 127 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
128 | } |
129 | ||
f68205a7 | 130 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
131 | { |
132 | int i = 0; | |
133 | ||
f68205a7 | 134 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
135 | |
136 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
137 | /* loop count is to avoid the lock-up */ | |
138 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 139 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
140 | break; |
141 | } | |
142 | ||
f68205a7 | 143 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
144 | printk(KERN_ERR "GBLCTL write error\n"); |
145 | } | |
146 | ||
4dcb5a0b PU |
147 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
148 | { | |
f68205a7 PU |
149 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
150 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
151 | |
152 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
153 | } | |
154 | ||
70091a3e | 155 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 156 | { |
44982735 | 157 | /* Start clocks */ |
f68205a7 PU |
158 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
159 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
160 | /* |
161 | * When ASYNC == 0 the transmit and receive sections operate | |
162 | * synchronously from the transmit clock and frame sync. We need to make | |
163 | * sure that the TX signlas are enabled when starting reception. | |
164 | */ | |
165 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
166 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
167 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
168 | } |
169 | ||
44982735 | 170 | /* Activate serializer(s) */ |
f68205a7 | 171 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 172 | /* Release RX state machine */ |
f68205a7 | 173 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 174 | /* Release Frame Sync generator */ |
f68205a7 | 175 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 176 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 177 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
b67f4487 C |
178 | } |
179 | ||
70091a3e | 180 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 181 | { |
6a99fb5f C |
182 | u32 cnt; |
183 | ||
36bcecd0 | 184 | /* Start clocks */ |
f68205a7 PU |
185 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
186 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
36bcecd0 | 187 | /* Activate serializer(s) */ |
f68205a7 | 188 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 189 | |
36bcecd0 | 190 | /* wait for XDATA to be cleared */ |
6a99fb5f | 191 | cnt = 0; |
36bcecd0 PU |
192 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & |
193 | ~XRDATA) && (cnt < 100000)) | |
6a99fb5f C |
194 | cnt++; |
195 | ||
36bcecd0 PU |
196 | /* Release TX state machine */ |
197 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
198 | /* Release Frame Sync generator */ | |
199 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
b67f4487 C |
200 | } |
201 | ||
70091a3e | 202 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 203 | { |
487dce88 PU |
204 | u32 reg; |
205 | ||
4dcb5a0b PU |
206 | mcasp->streams++; |
207 | ||
539d3d8c | 208 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 209 | if (mcasp->txnumevt) { /* enable FIFO */ |
487dce88 | 210 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 PU |
211 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
212 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 213 | } |
70091a3e | 214 | mcasp_start_tx(mcasp); |
539d3d8c | 215 | } else { |
70091a3e | 216 | if (mcasp->rxnumevt) { /* enable FIFO */ |
487dce88 | 217 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 PU |
218 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
219 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 220 | } |
70091a3e | 221 | mcasp_start_rx(mcasp); |
539d3d8c | 222 | } |
b67f4487 C |
223 | } |
224 | ||
70091a3e | 225 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 226 | { |
4dcb5a0b PU |
227 | /* |
228 | * In synchronous mode stop the TX clocks if no other stream is | |
229 | * running | |
230 | */ | |
231 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 232 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 233 | |
f68205a7 PU |
234 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
235 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
236 | |
237 | if (mcasp->rxnumevt) { /* disable FIFO */ | |
238 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
239 | ||
240 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
241 | } | |
b67f4487 C |
242 | } |
243 | ||
70091a3e | 244 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 245 | { |
4dcb5a0b PU |
246 | u32 val = 0; |
247 | ||
248 | /* | |
249 | * In synchronous mode keep TX clocks running if the capture stream is | |
250 | * still running. | |
251 | */ | |
252 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
253 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
254 | ||
f68205a7 PU |
255 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
256 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
257 | |
258 | if (mcasp->txnumevt) { /* disable FIFO */ | |
259 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
260 | ||
261 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
262 | } | |
b67f4487 C |
263 | } |
264 | ||
70091a3e | 265 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 266 | { |
4dcb5a0b PU |
267 | mcasp->streams--; |
268 | ||
0380866a | 269 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 270 | mcasp_stop_tx(mcasp); |
0380866a | 271 | else |
70091a3e | 272 | mcasp_stop_rx(mcasp); |
b67f4487 C |
273 | } |
274 | ||
275 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
276 | unsigned int fmt) | |
277 | { | |
70091a3e | 278 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 279 | int ret = 0; |
6dfa9a4e | 280 | u32 data_delay; |
83f12503 | 281 | bool fs_pol_rising; |
ffd950f7 | 282 | bool inv_fs = false; |
b67f4487 | 283 | |
1d17a04e | 284 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 285 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
286 | case SND_SOC_DAIFMT_DSP_A: |
287 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
288 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
289 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
290 | data_delay = 1; | |
291 | break; | |
5296cf2d DM |
292 | case SND_SOC_DAIFMT_DSP_B: |
293 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
294 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
295 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
296 | /* No delay after FS */ |
297 | data_delay = 0; | |
5296cf2d | 298 | break; |
ffd950f7 | 299 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 300 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
301 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
302 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
303 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
304 | data_delay = 1; | |
ffd950f7 PU |
305 | /* FS need to be inverted */ |
306 | inv_fs = true; | |
5296cf2d | 307 | break; |
423761e0 PU |
308 | case SND_SOC_DAIFMT_LEFT_J: |
309 | /* configure a full-word SYNC pulse (LRCLK) */ | |
310 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
311 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
312 | /* No delay after FS */ | |
313 | data_delay = 0; | |
314 | break; | |
ffd950f7 PU |
315 | default: |
316 | ret = -EINVAL; | |
317 | goto out; | |
5296cf2d DM |
318 | } |
319 | ||
6dfa9a4e PU |
320 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
321 | FSXDLY(3)); | |
322 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
323 | FSRDLY(3)); | |
324 | ||
b67f4487 C |
325 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
326 | case SND_SOC_DAIFMT_CBS_CFS: | |
327 | /* codec is clock and frame slave */ | |
f68205a7 PU |
328 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
329 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 330 | |
f68205a7 PU |
331 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
332 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 333 | |
f68205a7 PU |
334 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
335 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 336 | mcasp->bclk_master = 1; |
b67f4487 | 337 | break; |
517ee6cf C |
338 | case SND_SOC_DAIFMT_CBM_CFS: |
339 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
340 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
341 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 342 | |
f68205a7 PU |
343 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
344 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 345 | |
f68205a7 PU |
346 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
347 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 348 | mcasp->bclk_master = 0; |
517ee6cf | 349 | break; |
b67f4487 C |
350 | case SND_SOC_DAIFMT_CBM_CFM: |
351 | /* codec is clock and frame master */ | |
f68205a7 PU |
352 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
353 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 354 | |
f68205a7 PU |
355 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
356 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 357 | |
f68205a7 PU |
358 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
359 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 360 | mcasp->bclk_master = 0; |
b67f4487 | 361 | break; |
b67f4487 | 362 | default: |
1d17a04e PU |
363 | ret = -EINVAL; |
364 | goto out; | |
b67f4487 C |
365 | } |
366 | ||
367 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
368 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 369 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 370 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 371 | fs_pol_rising = true; |
b67f4487 | 372 | break; |
b67f4487 | 373 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 374 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 375 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 376 | fs_pol_rising = false; |
b67f4487 | 377 | break; |
b67f4487 | 378 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 379 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 380 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 381 | fs_pol_rising = false; |
b67f4487 | 382 | break; |
b67f4487 | 383 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 384 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 385 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 386 | fs_pol_rising = true; |
b67f4487 | 387 | break; |
b67f4487 | 388 | default: |
1d17a04e | 389 | ret = -EINVAL; |
83f12503 PU |
390 | goto out; |
391 | } | |
392 | ||
ffd950f7 PU |
393 | if (inv_fs) |
394 | fs_pol_rising = !fs_pol_rising; | |
395 | ||
83f12503 PU |
396 | if (fs_pol_rising) { |
397 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
398 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
399 | } else { | |
400 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
401 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 402 | } |
1d17a04e PU |
403 | out: |
404 | pm_runtime_put_sync(mcasp->dev); | |
405 | return ret; | |
b67f4487 C |
406 | } |
407 | ||
8813543e JS |
408 | static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
409 | int div, bool explicit) | |
4ed8c9b7 | 410 | { |
70091a3e | 411 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
412 | |
413 | switch (div_id) { | |
414 | case 0: /* MCLK divider */ | |
f68205a7 | 415 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 416 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 417 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
418 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
419 | break; | |
420 | ||
421 | case 1: /* BCLK divider */ | |
f68205a7 | 422 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 423 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 424 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 425 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
426 | if (explicit) |
427 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
428 | break; |
429 | ||
1b3bc060 | 430 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 431 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
432 | break; |
433 | ||
4ed8c9b7 DM |
434 | default: |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
8813543e JS |
441 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
442 | int div) | |
443 | { | |
444 | return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1); | |
445 | } | |
446 | ||
5b66aa2d DM |
447 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
448 | unsigned int freq, int dir) | |
449 | { | |
70091a3e | 450 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
451 | |
452 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
453 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
454 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
455 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 456 | } else { |
f68205a7 PU |
457 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
458 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
459 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
460 | } |
461 | ||
ab8b14b6 JS |
462 | mcasp->sysclk_freq = freq; |
463 | ||
5b66aa2d DM |
464 | return 0; |
465 | } | |
466 | ||
70091a3e | 467 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 468 | int word_length) |
b67f4487 | 469 | { |
ba764b3d | 470 | u32 fmt; |
79671892 | 471 | u32 tx_rotate = (word_length / 4) & 0x7; |
ba764b3d | 472 | u32 mask = (1ULL << word_length) - 1; |
fe0a29e1 PU |
473 | /* |
474 | * For captured data we should not rotate, inversion and masking is | |
475 | * enoguh to get the data to the right position: | |
476 | * Format data from bus after reverse (XRBUF) | |
477 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
478 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
479 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
480 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
481 | */ | |
482 | u32 rx_rotate = 0; | |
b67f4487 | 483 | |
1b3bc060 DM |
484 | /* |
485 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
486 | * callback, take it into account here. That allows us to for example | |
487 | * send 32 bits per channel to the codec, while only 16 of them carry | |
488 | * audio payload. | |
d486fea6 MB |
489 | * The clock ratio is given for a full period of data (for I2S format |
490 | * both left and right channels), so it has to be divided by number of | |
491 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 492 | */ |
70091a3e PU |
493 | if (mcasp->bclk_lrclk_ratio) |
494 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
1b3bc060 | 495 | |
ba764b3d DM |
496 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
497 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 498 | |
70091a3e | 499 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
500 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
501 | RXSSZ(0x0F)); | |
502 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
503 | TXSSZ(0x0F)); | |
504 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
505 | TXROT(7)); | |
506 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
507 | RXROT(7)); | |
508 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
509 | } |
510 | ||
f68205a7 | 511 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 512 | |
b67f4487 C |
513 | return 0; |
514 | } | |
515 | ||
662ffae9 | 516 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 517 | int period_words, int channels) |
b67f4487 | 518 | { |
5f04c603 PU |
519 | struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream]; |
520 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; | |
b67f4487 | 521 | int i; |
6a99fb5f C |
522 | u8 tx_ser = 0; |
523 | u8 rx_ser = 0; | |
70091a3e | 524 | u8 slots = mcasp->tdm_slots; |
2952b27e | 525 | u8 max_active_serializers = (channels + slots - 1) / slots; |
dd093a0f | 526 | int active_serializers, numevt, n; |
487dce88 | 527 | u32 reg; |
b67f4487 | 528 | /* Default configuration */ |
40448e5e | 529 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 530 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
531 | |
532 | /* All PINS as McASP */ | |
f68205a7 | 533 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
534 | |
535 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
536 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
537 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 538 | } else { |
f68205a7 PU |
539 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
540 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
541 | } |
542 | ||
70091a3e | 543 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
544 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
545 | mcasp->serial_dir[i]); | |
70091a3e | 546 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 547 | tx_ser < max_active_serializers) { |
f68205a7 | 548 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 549 | tx_ser++; |
70091a3e | 550 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 551 | rx_ser < max_active_serializers) { |
f68205a7 | 552 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 553 | rx_ser++; |
2952b27e | 554 | } else { |
f68205a7 PU |
555 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
556 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
557 | } |
558 | } | |
559 | ||
0bf0e8ae PU |
560 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
561 | active_serializers = tx_ser; | |
562 | numevt = mcasp->txnumevt; | |
563 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
564 | } else { | |
565 | active_serializers = rx_ser; | |
566 | numevt = mcasp->rxnumevt; | |
567 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
568 | } | |
ecf327c7 | 569 | |
0bf0e8ae | 570 | if (active_serializers < max_active_serializers) { |
70091a3e | 571 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
572 | "enabled in mcasp (%d)\n", channels, |
573 | active_serializers * slots); | |
ecf327c7 DM |
574 | return -EINVAL; |
575 | } | |
576 | ||
0bf0e8ae | 577 | /* AFIFO is not in use */ |
5f04c603 PU |
578 | if (!numevt) { |
579 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
580 | if (active_serializers > 1) { |
581 | /* | |
582 | * If more than one serializers are in use we have one | |
583 | * DMA request to provide data for all serializers. | |
584 | * For example if three serializers are enabled the DMA | |
585 | * need to transfer three words per DMA request. | |
586 | */ | |
587 | dma_params->fifo_level = active_serializers; | |
588 | dma_data->maxburst = active_serializers; | |
589 | } else { | |
590 | dma_params->fifo_level = 0; | |
591 | dma_data->maxburst = 0; | |
592 | } | |
0bf0e8ae | 593 | return 0; |
5f04c603 | 594 | } |
6a99fb5f | 595 | |
dd093a0f PU |
596 | if (period_words % active_serializers) { |
597 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
598 | "active serializers: %d, %d\n", period_words, | |
599 | active_serializers); | |
600 | return -EINVAL; | |
601 | } | |
602 | ||
603 | /* | |
604 | * Calculate the optimal AFIFO depth for platform side: | |
605 | * The number of words for numevt need to be in steps of active | |
606 | * serializers. | |
607 | */ | |
608 | n = numevt % active_serializers; | |
609 | if (n) | |
610 | numevt += (active_serializers - n); | |
611 | while (period_words % numevt && numevt > 0) | |
612 | numevt -= active_serializers; | |
613 | if (numevt <= 0) | |
0bf0e8ae | 614 | numevt = active_serializers; |
487dce88 | 615 | |
0bf0e8ae PU |
616 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
617 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 618 | |
5f04c603 | 619 | /* Configure the burst size for platform drivers */ |
33445643 PU |
620 | if (numevt == 1) |
621 | numevt = 0; | |
5f04c603 PU |
622 | dma_params->fifo_level = numevt; |
623 | dma_data->maxburst = numevt; | |
624 | ||
2952b27e | 625 | return 0; |
b67f4487 C |
626 | } |
627 | ||
2c56c4c2 | 628 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
b67f4487 C |
629 | { |
630 | int i, active_slots; | |
631 | u32 mask = 0; | |
cbc7956c | 632 | u32 busel = 0; |
b67f4487 | 633 | |
2c56c4c2 PU |
634 | if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) { |
635 | dev_err(mcasp->dev, "tdm slot %d not supported\n", | |
636 | mcasp->tdm_slots); | |
637 | return -EINVAL; | |
638 | } | |
639 | ||
70091a3e | 640 | active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; |
b67f4487 C |
641 | for (i = 0; i < active_slots; i++) |
642 | mask |= (1 << i); | |
643 | ||
f68205a7 | 644 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 645 | |
cbc7956c PU |
646 | if (!mcasp->dat_port) |
647 | busel = TXSEL; | |
648 | ||
2c56c4c2 PU |
649 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
650 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
651 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
652 | FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); | |
653 | ||
654 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
655 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
656 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
657 | FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); | |
658 | ||
659 | return 0; | |
b67f4487 C |
660 | } |
661 | ||
662 | /* S/PDIF */ | |
6479285d DM |
663 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
664 | unsigned int rate) | |
b67f4487 | 665 | { |
6479285d DM |
666 | u32 cs_value = 0; |
667 | u8 *cs_bytes = (u8*) &cs_value; | |
668 | ||
b67f4487 C |
669 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
670 | and LSB first */ | |
f68205a7 | 671 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
672 | |
673 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 674 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
675 | |
676 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 677 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
678 | |
679 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 680 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 681 | |
f68205a7 | 682 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
683 | |
684 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 685 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
686 | |
687 | /* Enable the DIT */ | |
f68205a7 | 688 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 689 | |
6479285d DM |
690 | /* Set S/PDIF channel status bits */ |
691 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
692 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
693 | ||
694 | switch (rate) { | |
695 | case 22050: | |
696 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
697 | break; | |
698 | case 24000: | |
699 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
700 | break; | |
701 | case 32000: | |
702 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
703 | break; | |
704 | case 44100: | |
705 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
706 | break; | |
707 | case 48000: | |
708 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
709 | break; | |
710 | case 88200: | |
711 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
712 | break; | |
713 | case 96000: | |
714 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
715 | break; | |
716 | case 176400: | |
717 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
718 | break; | |
719 | case 192000: | |
720 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
721 | break; | |
722 | default: | |
723 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
724 | return -EINVAL; | |
725 | } | |
726 | ||
727 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
728 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
729 | ||
2c56c4c2 | 730 | return 0; |
b67f4487 C |
731 | } |
732 | ||
733 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
734 | struct snd_pcm_hw_params *params, | |
735 | struct snd_soc_dai *cpu_dai) | |
736 | { | |
70091a3e | 737 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 738 | struct davinci_pcm_dma_params *dma_params = |
70091a3e | 739 | &mcasp->dma_params[substream->stream]; |
b67f4487 | 740 | int word_length; |
a7e46bd9 | 741 | int channels = params_channels(params); |
dd093a0f | 742 | int period_size = params_period_size(params); |
2c56c4c2 | 743 | int ret; |
ab8b14b6 | 744 | |
8267525c DM |
745 | /* |
746 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
747 | * the machine driver, we need to calculate the ratio. | |
748 | */ | |
749 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
ab8b14b6 | 750 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); |
0929878f | 751 | unsigned int div = mcasp->sysclk_freq / bclk_freq; |
ab8b14b6 | 752 | if (mcasp->sysclk_freq % bclk_freq != 0) { |
0929878f JS |
753 | if (((mcasp->sysclk_freq / div) - bclk_freq) > |
754 | (bclk_freq - (mcasp->sysclk_freq / (div+1)))) | |
755 | div++; | |
756 | dev_warn(mcasp->dev, | |
757 | "Inaccurate BCLK: %u Hz / %u != %u Hz\n", | |
758 | mcasp->sysclk_freq, div, bclk_freq); | |
ab8b14b6 | 759 | } |
8813543e | 760 | __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0); |
ab8b14b6 JS |
761 | } |
762 | ||
dd093a0f PU |
763 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
764 | period_size * channels, channels); | |
0f7d9a63 PU |
765 | if (ret) |
766 | return ret; | |
767 | ||
70091a3e | 768 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 769 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 770 | else |
2c56c4c2 PU |
771 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
772 | ||
773 | if (ret) | |
774 | return ret; | |
b67f4487 C |
775 | |
776 | switch (params_format(params)) { | |
0a9d1385 | 777 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
778 | case SNDRV_PCM_FORMAT_S8: |
779 | dma_params->data_type = 1; | |
ba764b3d | 780 | word_length = 8; |
b67f4487 C |
781 | break; |
782 | ||
0a9d1385 | 783 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
784 | case SNDRV_PCM_FORMAT_S16_LE: |
785 | dma_params->data_type = 2; | |
ba764b3d | 786 | word_length = 16; |
b67f4487 C |
787 | break; |
788 | ||
21eb24d8 DM |
789 | case SNDRV_PCM_FORMAT_U24_3LE: |
790 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 791 | dma_params->data_type = 3; |
ba764b3d | 792 | word_length = 24; |
21eb24d8 DM |
793 | break; |
794 | ||
6b7fa011 DM |
795 | case SNDRV_PCM_FORMAT_U24_LE: |
796 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
797 | dma_params->data_type = 4; |
798 | word_length = 24; | |
799 | break; | |
800 | ||
0a9d1385 | 801 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
802 | case SNDRV_PCM_FORMAT_S32_LE: |
803 | dma_params->data_type = 4; | |
ba764b3d | 804 | word_length = 32; |
b67f4487 C |
805 | break; |
806 | ||
807 | default: | |
808 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
809 | return -EINVAL; | |
810 | } | |
6a99fb5f | 811 | |
5f04c603 | 812 | if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level) |
4fa9c1a5 C |
813 | dma_params->acnt = 4; |
814 | else | |
6a99fb5f C |
815 | dma_params->acnt = dma_params->data_type; |
816 | ||
70091a3e | 817 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 C |
818 | |
819 | return 0; | |
820 | } | |
821 | ||
822 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
823 | int cmd, struct snd_soc_dai *cpu_dai) | |
824 | { | |
70091a3e | 825 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
826 | int ret = 0; |
827 | ||
828 | switch (cmd) { | |
b67f4487 | 829 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
830 | case SNDRV_PCM_TRIGGER_START: |
831 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 832 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 833 | break; |
b67f4487 | 834 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 835 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 836 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 837 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
838 | break; |
839 | ||
840 | default: | |
841 | ret = -EINVAL; | |
842 | } | |
843 | ||
844 | return ret; | |
845 | } | |
846 | ||
85e7652d | 847 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
b67f4487 C |
848 | .trigger = davinci_mcasp_trigger, |
849 | .hw_params = davinci_mcasp_hw_params, | |
850 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 851 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 852 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
853 | }; |
854 | ||
d5902f69 PU |
855 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
856 | { | |
857 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
858 | ||
f3f9cfa8 | 859 | if (mcasp->version >= MCASP_VERSION_3) { |
d5902f69 PU |
860 | /* Using dmaengine PCM */ |
861 | dai->playback_dma_data = | |
862 | &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; | |
863 | dai->capture_dma_data = | |
864 | &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
865 | } else { | |
866 | /* Using davinci-pcm */ | |
867 | dai->playback_dma_data = mcasp->dma_params; | |
868 | dai->capture_dma_data = mcasp->dma_params; | |
869 | } | |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
135014ad PU |
874 | #ifdef CONFIG_PM_SLEEP |
875 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
876 | { | |
877 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 878 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 879 | u32 reg; |
1cc0c054 | 880 | int i; |
135014ad | 881 | |
1cc0c054 PU |
882 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
883 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 884 | |
f114ce60 PU |
885 | if (mcasp->txnumevt) { |
886 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
887 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
888 | } | |
889 | if (mcasp->rxnumevt) { | |
890 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
891 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
892 | } | |
135014ad | 893 | |
f114ce60 PU |
894 | for (i = 0; i < mcasp->num_serializer; i++) |
895 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
896 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad PU |
897 | |
898 | return 0; | |
899 | } | |
900 | ||
901 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
902 | { | |
903 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 904 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 905 | u32 reg; |
1cc0c054 | 906 | int i; |
790bb94b | 907 | |
1cc0c054 PU |
908 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
909 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 910 | |
f114ce60 PU |
911 | if (mcasp->txnumevt) { |
912 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
913 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
914 | } | |
915 | if (mcasp->rxnumevt) { | |
916 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
917 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
918 | } | |
790bb94b | 919 | |
f114ce60 PU |
920 | for (i = 0; i < mcasp->num_serializer; i++) |
921 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
922 | context->xrsr_regs[i]); | |
135014ad PU |
923 | |
924 | return 0; | |
925 | } | |
926 | #else | |
927 | #define davinci_mcasp_suspend NULL | |
928 | #define davinci_mcasp_resume NULL | |
929 | #endif | |
930 | ||
ed29cd5e PU |
931 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
932 | ||
0a9d1385 BG |
933 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
934 | SNDRV_PCM_FMTBIT_U8 | \ | |
935 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
936 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
937 | SNDRV_PCM_FMTBIT_S24_LE | \ |
938 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
939 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
940 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
941 | SNDRV_PCM_FMTBIT_S32_LE | \ |
942 | SNDRV_PCM_FMTBIT_U32_LE) | |
943 | ||
f0fba2ad | 944 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 945 | { |
f0fba2ad | 946 | .name = "davinci-mcasp.0", |
d5902f69 | 947 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
948 | .suspend = davinci_mcasp_suspend, |
949 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
950 | .playback = { |
951 | .channels_min = 2, | |
2952b27e | 952 | .channels_max = 32 * 16, |
b67f4487 | 953 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 954 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
955 | }, |
956 | .capture = { | |
957 | .channels_min = 2, | |
2952b27e | 958 | .channels_max = 32 * 16, |
b67f4487 | 959 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 960 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
961 | }, |
962 | .ops = &davinci_mcasp_dai_ops, | |
963 | ||
964 | }, | |
965 | { | |
58e48d97 | 966 | .name = "davinci-mcasp.1", |
d5902f69 | 967 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
968 | .playback = { |
969 | .channels_min = 1, | |
970 | .channels_max = 384, | |
971 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 972 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
973 | }, |
974 | .ops = &davinci_mcasp_dai_ops, | |
975 | }, | |
976 | ||
977 | }; | |
b67f4487 | 978 | |
eeef0eda KM |
979 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
980 | .name = "davinci-mcasp", | |
981 | }; | |
982 | ||
256ba181 | 983 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 984 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
985 | .tx_dma_offset = 0x400, |
986 | .rx_dma_offset = 0x400, | |
987 | .asp_chan_q = EVENTQ_0, | |
988 | .version = MCASP_VERSION_1, | |
989 | }; | |
990 | ||
d1debafc | 991 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
992 | .tx_dma_offset = 0x2000, |
993 | .rx_dma_offset = 0x2000, | |
994 | .asp_chan_q = EVENTQ_0, | |
995 | .version = MCASP_VERSION_2, | |
996 | }; | |
997 | ||
d1debafc | 998 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
999 | .tx_dma_offset = 0, |
1000 | .rx_dma_offset = 0, | |
1001 | .asp_chan_q = EVENTQ_0, | |
1002 | .version = MCASP_VERSION_3, | |
1003 | }; | |
1004 | ||
d1debafc | 1005 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
1006 | .tx_dma_offset = 0x200, |
1007 | .rx_dma_offset = 0x284, | |
1008 | .asp_chan_q = EVENTQ_0, | |
1009 | .version = MCASP_VERSION_4, | |
1010 | }; | |
1011 | ||
3e3b8c34 HG |
1012 | static const struct of_device_id mcasp_dt_ids[] = { |
1013 | { | |
1014 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1015 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1016 | }, |
1017 | { | |
1018 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1019 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1020 | }, |
e5ec69da | 1021 | { |
3af9e031 | 1022 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1023 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1024 | }, |
453c4990 PU |
1025 | { |
1026 | .compatible = "ti,dra7-mcasp-audio", | |
1027 | .data = &dra7_mcasp_pdata, | |
1028 | }, | |
3e3b8c34 HG |
1029 | { /* sentinel */ } |
1030 | }; | |
1031 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1032 | ||
ae726e93 PU |
1033 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1034 | { | |
1035 | struct device_node *node = pdev->dev.of_node; | |
1036 | struct clk *gfclk, *parent_clk; | |
1037 | const char *parent_name; | |
1038 | int ret; | |
1039 | ||
1040 | if (!node) | |
1041 | return 0; | |
1042 | ||
1043 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1044 | if (!parent_name) | |
1045 | return 0; | |
1046 | ||
1047 | gfclk = clk_get(&pdev->dev, "fck"); | |
1048 | if (IS_ERR(gfclk)) { | |
1049 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1050 | return PTR_ERR(gfclk); | |
1051 | } | |
1052 | ||
1053 | parent_clk = clk_get(NULL, parent_name); | |
1054 | if (IS_ERR(parent_clk)) { | |
1055 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1056 | ret = PTR_ERR(parent_clk); | |
1057 | goto err1; | |
1058 | } | |
1059 | ||
1060 | ret = clk_set_parent(gfclk, parent_clk); | |
1061 | if (ret) { | |
1062 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1063 | goto err2; | |
1064 | } | |
1065 | ||
1066 | err2: | |
1067 | clk_put(parent_clk); | |
1068 | err1: | |
1069 | clk_put(gfclk); | |
1070 | return ret; | |
1071 | } | |
1072 | ||
d1debafc | 1073 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1074 | struct platform_device *pdev) |
1075 | { | |
1076 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1077 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1078 | const struct of_device_id *match = |
ea421eb1 | 1079 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1080 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1081 | |
1082 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1083 | u32 val; |
1084 | int i, ret = 0; | |
1085 | ||
1086 | if (pdev->dev.platform_data) { | |
1087 | pdata = pdev->dev.platform_data; | |
1088 | return pdata; | |
1089 | } else if (match) { | |
d1debafc | 1090 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1091 | } else { |
1092 | /* control shouldn't reach here. something is wrong */ | |
1093 | ret = -EINVAL; | |
1094 | goto nodata; | |
1095 | } | |
1096 | ||
3e3b8c34 HG |
1097 | ret = of_property_read_u32(np, "op-mode", &val); |
1098 | if (ret >= 0) | |
1099 | pdata->op_mode = val; | |
1100 | ||
1101 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1102 | if (ret >= 0) { |
1103 | if (val < 2 || val > 32) { | |
1104 | dev_err(&pdev->dev, | |
1105 | "tdm-slots must be in rage [2-32]\n"); | |
1106 | ret = -EINVAL; | |
1107 | goto nodata; | |
1108 | } | |
1109 | ||
3e3b8c34 | 1110 | pdata->tdm_slots = val; |
2952b27e | 1111 | } |
3e3b8c34 | 1112 | |
3e3b8c34 HG |
1113 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1114 | val /= sizeof(u32); | |
3e3b8c34 | 1115 | if (of_serial_dir32) { |
1427e660 PU |
1116 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1117 | (sizeof(*of_serial_dir) * val), | |
1118 | GFP_KERNEL); | |
3e3b8c34 HG |
1119 | if (!of_serial_dir) { |
1120 | ret = -ENOMEM; | |
1121 | goto nodata; | |
1122 | } | |
1123 | ||
1427e660 | 1124 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1125 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1126 | ||
1427e660 | 1127 | pdata->num_serializer = val; |
3e3b8c34 HG |
1128 | pdata->serial_dir = of_serial_dir; |
1129 | } | |
1130 | ||
4023fe6f JS |
1131 | ret = of_property_match_string(np, "dma-names", "tx"); |
1132 | if (ret < 0) | |
1133 | goto nodata; | |
1134 | ||
1135 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1136 | &dma_spec); | |
1137 | if (ret < 0) | |
1138 | goto nodata; | |
1139 | ||
1140 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1141 | ||
1142 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1143 | if (ret < 0) | |
1144 | goto nodata; | |
1145 | ||
1146 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1147 | &dma_spec); | |
1148 | if (ret < 0) | |
1149 | goto nodata; | |
1150 | ||
1151 | pdata->rx_dma_channel = dma_spec.args[0]; | |
1152 | ||
3e3b8c34 HG |
1153 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1154 | if (ret >= 0) | |
1155 | pdata->txnumevt = val; | |
1156 | ||
1157 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1158 | if (ret >= 0) | |
1159 | pdata->rxnumevt = val; | |
1160 | ||
1161 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1162 | if (ret >= 0) | |
1163 | pdata->sram_size_playback = val; | |
1164 | ||
1165 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1166 | if (ret >= 0) | |
1167 | pdata->sram_size_capture = val; | |
1168 | ||
1169 | return pdata; | |
1170 | ||
1171 | nodata: | |
1172 | if (ret < 0) { | |
1173 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1174 | ret); | |
1175 | pdata = NULL; | |
1176 | } | |
1177 | return pdata; | |
1178 | } | |
1179 | ||
b67f4487 C |
1180 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1181 | { | |
64ebdec3 | 1182 | struct davinci_pcm_dma_params *dma_params; |
8de131f2 | 1183 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1184 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1185 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1186 | struct davinci_mcasp *mcasp; |
96d31e2b | 1187 | int ret; |
b67f4487 | 1188 | |
3e3b8c34 HG |
1189 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1190 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1191 | return -EINVAL; | |
1192 | } | |
1193 | ||
70091a3e | 1194 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1195 | GFP_KERNEL); |
70091a3e | 1196 | if (!mcasp) |
b67f4487 C |
1197 | return -ENOMEM; |
1198 | ||
3e3b8c34 HG |
1199 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1200 | if (!pdata) { | |
1201 | dev_err(&pdev->dev, "no platform data\n"); | |
1202 | return -EINVAL; | |
1203 | } | |
1204 | ||
256ba181 | 1205 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1206 | if (!mem) { |
70091a3e | 1207 | dev_warn(mcasp->dev, |
256ba181 JS |
1208 | "\"mpu\" mem resource not found, using index 0\n"); |
1209 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1210 | if (!mem) { | |
1211 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1212 | return -ENODEV; | |
1213 | } | |
b67f4487 C |
1214 | } |
1215 | ||
96d31e2b | 1216 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1217 | resource_size(mem), pdev->name); |
b67f4487 C |
1218 | if (!ioarea) { |
1219 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1220 | return -EBUSY; |
b67f4487 C |
1221 | } |
1222 | ||
10884347 | 1223 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1224 | |
10884347 HG |
1225 | ret = pm_runtime_get_sync(&pdev->dev); |
1226 | if (IS_ERR_VALUE(ret)) { | |
1227 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
1228 | return ret; | |
1229 | } | |
b67f4487 | 1230 | |
70091a3e PU |
1231 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1232 | if (!mcasp->base) { | |
4f82f028 VB |
1233 | dev_err(&pdev->dev, "ioremap failed\n"); |
1234 | ret = -ENOMEM; | |
b6bb3709 | 1235 | goto err; |
4f82f028 VB |
1236 | } |
1237 | ||
70091a3e PU |
1238 | mcasp->op_mode = pdata->op_mode; |
1239 | mcasp->tdm_slots = pdata->tdm_slots; | |
1240 | mcasp->num_serializer = pdata->num_serializer; | |
f114ce60 PU |
1241 | #ifdef CONFIG_PM_SLEEP |
1242 | mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, | |
1243 | sizeof(u32) * mcasp->num_serializer, | |
1244 | GFP_KERNEL); | |
1245 | #endif | |
70091a3e PU |
1246 | mcasp->serial_dir = pdata->serial_dir; |
1247 | mcasp->version = pdata->version; | |
1248 | mcasp->txnumevt = pdata->txnumevt; | |
1249 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1250 | |
70091a3e | 1251 | mcasp->dev = &pdev->dev; |
b67f4487 | 1252 | |
256ba181 | 1253 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1254 | if (dat) |
1255 | mcasp->dat_port = true; | |
256ba181 | 1256 | |
64ebdec3 | 1257 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
8de131f2 | 1258 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
64ebdec3 PU |
1259 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1260 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1261 | dma_params->sram_pool = pdata->sram_pool; | |
1262 | dma_params->sram_size = pdata->sram_size_playback; | |
cbc7956c | 1263 | if (dat) |
64ebdec3 | 1264 | dma_params->dma_addr = dat->start; |
cbc7956c | 1265 | else |
64ebdec3 | 1266 | dma_params->dma_addr = mem->start + pdata->tx_dma_offset; |
b67f4487 | 1267 | |
453c4990 | 1268 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1269 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1270 | |
b67f4487 | 1271 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1272 | if (res) |
64ebdec3 | 1273 | dma_params->channel = res->start; |
4023fe6f | 1274 | else |
64ebdec3 | 1275 | dma_params->channel = pdata->tx_dma_channel; |
92e2a6f6 | 1276 | |
8de131f2 PU |
1277 | /* dmaengine filter data for DT and non-DT boot */ |
1278 | if (pdev->dev.of_node) | |
1279 | dma_data->filter_data = "tx"; | |
1280 | else | |
1281 | dma_data->filter_data = &dma_params->channel; | |
1282 | ||
64ebdec3 | 1283 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
8de131f2 | 1284 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
64ebdec3 PU |
1285 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1286 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1287 | dma_params->sram_pool = pdata->sram_pool; | |
1288 | dma_params->sram_size = pdata->sram_size_capture; | |
cbc7956c | 1289 | if (dat) |
64ebdec3 | 1290 | dma_params->dma_addr = dat->start; |
cbc7956c | 1291 | else |
64ebdec3 | 1292 | dma_params->dma_addr = mem->start + pdata->rx_dma_offset; |
cbc7956c | 1293 | |
453c4990 | 1294 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1295 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1296 | |
cbc7956c PU |
1297 | if (mcasp->version < MCASP_VERSION_3) { |
1298 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1299 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1300 | mcasp->dat_port = true; |
1301 | } else { | |
1302 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1303 | } | |
b67f4487 C |
1304 | |
1305 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
4023fe6f | 1306 | if (res) |
64ebdec3 | 1307 | dma_params->channel = res->start; |
4023fe6f | 1308 | else |
64ebdec3 | 1309 | dma_params->channel = pdata->rx_dma_channel; |
b67f4487 | 1310 | |
8de131f2 PU |
1311 | /* dmaengine filter data for DT and non-DT boot */ |
1312 | if (pdev->dev.of_node) | |
1313 | dma_data->filter_data = "rx"; | |
1314 | else | |
1315 | dma_data->filter_data = &dma_params->channel; | |
453c4990 | 1316 | |
70091a3e | 1317 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1318 | |
1319 | mcasp_reparent_fck(pdev); | |
1320 | ||
b6bb3709 PU |
1321 | ret = devm_snd_soc_register_component(&pdev->dev, |
1322 | &davinci_mcasp_component, | |
1323 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1324 | |
1325 | if (ret != 0) | |
b6bb3709 | 1326 | goto err; |
f08095a4 | 1327 | |
d5c6c59a | 1328 | switch (mcasp->version) { |
7f28f357 JS |
1329 | #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \ |
1330 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1331 | IS_MODULE(CONFIG_SND_DAVINCI_SOC)) | |
d5c6c59a PU |
1332 | case MCASP_VERSION_1: |
1333 | case MCASP_VERSION_2: | |
453c4990 | 1334 | ret = davinci_soc_platform_register(&pdev->dev); |
d5c6c59a | 1335 | break; |
7f28f357 | 1336 | #endif |
f3f9cfa8 PU |
1337 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1338 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1339 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
1340 | case MCASP_VERSION_3: | |
1341 | ret = edma_pcm_platform_register(&pdev->dev); | |
1342 | break; | |
1343 | #endif | |
7f28f357 JS |
1344 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
1345 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1346 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a PU |
1347 | case MCASP_VERSION_4: |
1348 | ret = omap_pcm_platform_register(&pdev->dev); | |
1349 | break; | |
7f28f357 | 1350 | #endif |
d5c6c59a PU |
1351 | default: |
1352 | dev_err(&pdev->dev, "Invalid McASP version: %d\n", | |
1353 | mcasp->version); | |
1354 | ret = -EINVAL; | |
1355 | break; | |
1356 | } | |
1357 | ||
1358 | if (ret) { | |
1359 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 1360 | goto err; |
f08095a4 HG |
1361 | } |
1362 | ||
b67f4487 C |
1363 | return 0; |
1364 | ||
b6bb3709 | 1365 | err: |
10884347 HG |
1366 | pm_runtime_put_sync(&pdev->dev); |
1367 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1368 | return ret; |
1369 | } | |
1370 | ||
1371 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1372 | { | |
10884347 HG |
1373 | pm_runtime_put_sync(&pdev->dev); |
1374 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1375 | |
b67f4487 C |
1376 | return 0; |
1377 | } | |
1378 | ||
1379 | static struct platform_driver davinci_mcasp_driver = { | |
1380 | .probe = davinci_mcasp_probe, | |
1381 | .remove = davinci_mcasp_remove, | |
1382 | .driver = { | |
1383 | .name = "davinci-mcasp", | |
1384 | .owner = THIS_MODULE, | |
ea421eb1 | 1385 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1386 | }, |
1387 | }; | |
1388 | ||
f9b8a514 | 1389 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1390 | |
1391 | MODULE_AUTHOR("Steve Chen"); | |
1392 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1393 | MODULE_LICENSE("GPL"); |