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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
9759e7ef | 29 | #include <linux/platform_data/davinci_asp.h> |
a75a053f | 30 | #include <linux/math64.h> |
b67f4487 | 31 | |
6479285d | 32 | #include <sound/asoundef.h> |
b67f4487 C |
33 | #include <sound/core.h> |
34 | #include <sound/pcm.h> | |
35 | #include <sound/pcm_params.h> | |
36 | #include <sound/initval.h> | |
37 | #include <sound/soc.h> | |
453c4990 | 38 | #include <sound/dmaengine_pcm.h> |
87c19364 | 39 | #include <sound/omap-pcm.h> |
b67f4487 | 40 | |
f3f9cfa8 | 41 | #include "edma-pcm.h" |
b67f4487 C |
42 | #include "davinci-mcasp.h" |
43 | ||
0bf0e8ae PU |
44 | #define MCASP_MAX_AFIFO_DEPTH 64 |
45 | ||
1cc0c054 PU |
46 | static u32 context_regs[] = { |
47 | DAVINCI_MCASP_TXFMCTL_REG, | |
48 | DAVINCI_MCASP_RXFMCTL_REG, | |
49 | DAVINCI_MCASP_TXFMT_REG, | |
50 | DAVINCI_MCASP_RXFMT_REG, | |
51 | DAVINCI_MCASP_ACLKXCTL_REG, | |
52 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
53 | DAVINCI_MCASP_AHCLKXCTL_REG, |
54 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 55 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
56 | DAVINCI_MCASP_RXMASK_REG, |
57 | DAVINCI_MCASP_TXMASK_REG, | |
58 | DAVINCI_MCASP_RXTDM_REG, | |
59 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
60 | }; |
61 | ||
790bb94b | 62 | struct davinci_mcasp_context { |
1cc0c054 | 63 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
64 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
65 | u32 *xrsr_regs; /* for serializer configuration */ | |
6afda7f5 | 66 | bool pm_state; |
790bb94b PU |
67 | }; |
68 | ||
a75a053f JS |
69 | struct davinci_mcasp_ruledata { |
70 | struct davinci_mcasp *mcasp; | |
71 | int serializers; | |
72 | }; | |
73 | ||
70091a3e | 74 | struct davinci_mcasp { |
453c4990 | 75 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 76 | void __iomem *base; |
487dce88 | 77 | u32 fifo_base; |
21400a72 | 78 | struct device *dev; |
a7a3324a | 79 | struct snd_pcm_substream *substreams[2]; |
21400a72 PU |
80 | |
81 | /* McASP specific data */ | |
82 | int tdm_slots; | |
83 | u8 op_mode; | |
84 | u8 num_serializer; | |
85 | u8 *serial_dir; | |
86 | u8 version; | |
8267525c | 87 | u8 bclk_div; |
21400a72 | 88 | u16 bclk_lrclk_ratio; |
4dcb5a0b | 89 | int streams; |
a7a3324a | 90 | u32 irq_request[2]; |
9759e7ef | 91 | int dma_request[2]; |
21400a72 | 92 | |
ab8b14b6 JS |
93 | int sysclk_freq; |
94 | bool bclk_master; | |
95 | ||
21400a72 PU |
96 | /* McASP FIFO related */ |
97 | u8 txnumevt; | |
98 | u8 rxnumevt; | |
99 | ||
cbc7956c PU |
100 | bool dat_port; |
101 | ||
11277833 PU |
102 | /* Used for comstraint setting on the second stream */ |
103 | u32 channels; | |
104 | ||
21400a72 | 105 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 106 | struct davinci_mcasp_context context; |
21400a72 | 107 | #endif |
a75a053f JS |
108 | |
109 | struct davinci_mcasp_ruledata ruledata[2]; | |
5935a056 | 110 | struct snd_pcm_hw_constraint_list chconstr[2]; |
21400a72 PU |
111 | }; |
112 | ||
f68205a7 PU |
113 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
114 | u32 val) | |
b67f4487 | 115 | { |
f68205a7 | 116 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
117 | __raw_writel(__raw_readl(reg) | val, reg); |
118 | } | |
119 | ||
f68205a7 PU |
120 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
121 | u32 val) | |
b67f4487 | 122 | { |
f68205a7 | 123 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
124 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
125 | } | |
126 | ||
f68205a7 PU |
127 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
128 | u32 val, u32 mask) | |
b67f4487 | 129 | { |
f68205a7 | 130 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
131 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
132 | } | |
133 | ||
f68205a7 PU |
134 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
135 | u32 val) | |
b67f4487 | 136 | { |
f68205a7 | 137 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
138 | } |
139 | ||
f68205a7 | 140 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 141 | { |
f68205a7 | 142 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
143 | } |
144 | ||
f68205a7 | 145 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
146 | { |
147 | int i = 0; | |
148 | ||
f68205a7 | 149 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
150 | |
151 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
152 | /* loop count is to avoid the lock-up */ | |
153 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 154 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
155 | break; |
156 | } | |
157 | ||
f68205a7 | 158 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
159 | printk(KERN_ERR "GBLCTL write error\n"); |
160 | } | |
161 | ||
4dcb5a0b PU |
162 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
163 | { | |
f68205a7 PU |
164 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
165 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
166 | |
167 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
168 | } | |
169 | ||
70091a3e | 170 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 171 | { |
bb372af0 PU |
172 | if (mcasp->rxnumevt) { /* enable FIFO */ |
173 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
174 | ||
175 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
176 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
177 | } | |
178 | ||
44982735 | 179 | /* Start clocks */ |
f68205a7 PU |
180 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
181 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
182 | /* |
183 | * When ASYNC == 0 the transmit and receive sections operate | |
184 | * synchronously from the transmit clock and frame sync. We need to make | |
185 | * sure that the TX signlas are enabled when starting reception. | |
186 | */ | |
187 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
188 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
189 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
190 | } |
191 | ||
44982735 | 192 | /* Activate serializer(s) */ |
f68205a7 | 193 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 194 | /* Release RX state machine */ |
f68205a7 | 195 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 196 | /* Release Frame Sync generator */ |
f68205a7 | 197 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 198 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 199 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
a7a3324a MLC |
200 | |
201 | /* enable receive IRQs */ | |
202 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
203 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
b67f4487 C |
204 | } |
205 | ||
70091a3e | 206 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 207 | { |
6a99fb5f C |
208 | u32 cnt; |
209 | ||
bb372af0 PU |
210 | if (mcasp->txnumevt) { /* enable FIFO */ |
211 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
212 | ||
213 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
214 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
215 | } | |
216 | ||
36bcecd0 | 217 | /* Start clocks */ |
f68205a7 PU |
218 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
219 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
36bcecd0 | 220 | /* Activate serializer(s) */ |
f68205a7 | 221 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 222 | |
36bcecd0 | 223 | /* wait for XDATA to be cleared */ |
6a99fb5f | 224 | cnt = 0; |
36bcecd0 PU |
225 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & |
226 | ~XRDATA) && (cnt < 100000)) | |
6a99fb5f C |
227 | cnt++; |
228 | ||
36bcecd0 PU |
229 | /* Release TX state machine */ |
230 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
231 | /* Release Frame Sync generator */ | |
232 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
a7a3324a MLC |
233 | |
234 | /* enable transmit IRQs */ | |
235 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
236 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
b67f4487 C |
237 | } |
238 | ||
70091a3e | 239 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 240 | { |
4dcb5a0b PU |
241 | mcasp->streams++; |
242 | ||
bb372af0 | 243 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 244 | mcasp_start_tx(mcasp); |
bb372af0 | 245 | else |
70091a3e | 246 | mcasp_start_rx(mcasp); |
b67f4487 C |
247 | } |
248 | ||
70091a3e | 249 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 250 | { |
a7a3324a MLC |
251 | /* disable IRQ sources */ |
252 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
253 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
254 | ||
4dcb5a0b PU |
255 | /* |
256 | * In synchronous mode stop the TX clocks if no other stream is | |
257 | * running | |
258 | */ | |
259 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 260 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 261 | |
f68205a7 PU |
262 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
263 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
264 | |
265 | if (mcasp->rxnumevt) { /* disable FIFO */ | |
266 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
267 | ||
268 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
269 | } | |
b67f4487 C |
270 | } |
271 | ||
70091a3e | 272 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 273 | { |
4dcb5a0b PU |
274 | u32 val = 0; |
275 | ||
a7a3324a MLC |
276 | /* disable IRQ sources */ |
277 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
278 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
279 | ||
4dcb5a0b PU |
280 | /* |
281 | * In synchronous mode keep TX clocks running if the capture stream is | |
282 | * still running. | |
283 | */ | |
284 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
285 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
286 | ||
f68205a7 PU |
287 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
288 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
289 | |
290 | if (mcasp->txnumevt) { /* disable FIFO */ | |
291 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
292 | ||
293 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
294 | } | |
b67f4487 C |
295 | } |
296 | ||
70091a3e | 297 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 298 | { |
4dcb5a0b PU |
299 | mcasp->streams--; |
300 | ||
0380866a | 301 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 302 | mcasp_stop_tx(mcasp); |
0380866a | 303 | else |
70091a3e | 304 | mcasp_stop_rx(mcasp); |
b67f4487 C |
305 | } |
306 | ||
a7a3324a MLC |
307 | static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) |
308 | { | |
309 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
310 | struct snd_pcm_substream *substream; | |
311 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; | |
312 | u32 handled_mask = 0; | |
313 | u32 stat; | |
314 | ||
315 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); | |
316 | if (stat & XUNDRN & irq_mask) { | |
317 | dev_warn(mcasp->dev, "Transmit buffer underflow\n"); | |
318 | handled_mask |= XUNDRN; | |
319 | ||
320 | substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; | |
321 | if (substream) { | |
322 | snd_pcm_stream_lock_irq(substream); | |
323 | if (snd_pcm_running(substream)) | |
324 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
325 | snd_pcm_stream_unlock_irq(substream); | |
326 | } | |
327 | } | |
328 | ||
329 | if (!handled_mask) | |
330 | dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", | |
331 | stat); | |
332 | ||
333 | if (stat & XRERR) | |
334 | handled_mask |= XRERR; | |
335 | ||
336 | /* Ack the handled event only */ | |
337 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); | |
338 | ||
339 | return IRQ_RETVAL(handled_mask); | |
340 | } | |
341 | ||
342 | static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) | |
343 | { | |
344 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
345 | struct snd_pcm_substream *substream; | |
346 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; | |
347 | u32 handled_mask = 0; | |
348 | u32 stat; | |
349 | ||
350 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); | |
351 | if (stat & ROVRN & irq_mask) { | |
352 | dev_warn(mcasp->dev, "Receive buffer overflow\n"); | |
353 | handled_mask |= ROVRN; | |
354 | ||
355 | substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; | |
356 | if (substream) { | |
357 | snd_pcm_stream_lock_irq(substream); | |
358 | if (snd_pcm_running(substream)) | |
359 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
360 | snd_pcm_stream_unlock_irq(substream); | |
361 | } | |
362 | } | |
363 | ||
364 | if (!handled_mask) | |
365 | dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", | |
366 | stat); | |
367 | ||
368 | if (stat & XRERR) | |
369 | handled_mask |= XRERR; | |
370 | ||
371 | /* Ack the handled event only */ | |
372 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); | |
373 | ||
374 | return IRQ_RETVAL(handled_mask); | |
375 | } | |
376 | ||
5a1b8a80 PU |
377 | static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) |
378 | { | |
379 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
380 | irqreturn_t ret = IRQ_NONE; | |
381 | ||
382 | if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) | |
383 | ret = davinci_mcasp_tx_irq_handler(irq, data); | |
384 | ||
385 | if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) | |
386 | ret |= davinci_mcasp_rx_irq_handler(irq, data); | |
387 | ||
388 | return ret; | |
389 | } | |
390 | ||
b67f4487 C |
391 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
392 | unsigned int fmt) | |
393 | { | |
70091a3e | 394 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 395 | int ret = 0; |
6dfa9a4e | 396 | u32 data_delay; |
83f12503 | 397 | bool fs_pol_rising; |
ffd950f7 | 398 | bool inv_fs = false; |
b67f4487 | 399 | |
1d17a04e | 400 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 401 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
402 | case SND_SOC_DAIFMT_DSP_A: |
403 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
404 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
405 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
406 | data_delay = 1; | |
407 | break; | |
5296cf2d DM |
408 | case SND_SOC_DAIFMT_DSP_B: |
409 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
410 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
411 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
412 | /* No delay after FS */ |
413 | data_delay = 0; | |
5296cf2d | 414 | break; |
ffd950f7 | 415 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 416 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
417 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
418 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
419 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
420 | data_delay = 1; | |
ffd950f7 PU |
421 | /* FS need to be inverted */ |
422 | inv_fs = true; | |
5296cf2d | 423 | break; |
423761e0 PU |
424 | case SND_SOC_DAIFMT_LEFT_J: |
425 | /* configure a full-word SYNC pulse (LRCLK) */ | |
426 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
427 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
428 | /* No delay after FS */ | |
429 | data_delay = 0; | |
430 | break; | |
ffd950f7 PU |
431 | default: |
432 | ret = -EINVAL; | |
433 | goto out; | |
5296cf2d DM |
434 | } |
435 | ||
6dfa9a4e PU |
436 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
437 | FSXDLY(3)); | |
438 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
439 | FSRDLY(3)); | |
440 | ||
b67f4487 C |
441 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
442 | case SND_SOC_DAIFMT_CBS_CFS: | |
443 | /* codec is clock and frame slave */ | |
f68205a7 PU |
444 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
445 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 446 | |
f68205a7 PU |
447 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
448 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 449 | |
f68205a7 PU |
450 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
451 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 452 | mcasp->bclk_master = 1; |
b67f4487 | 453 | break; |
226e2f1b PU |
454 | case SND_SOC_DAIFMT_CBS_CFM: |
455 | /* codec is clock slave and frame master */ | |
456 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); | |
457 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
458 | ||
459 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | |
460 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
461 | ||
462 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); | |
463 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
464 | mcasp->bclk_master = 1; | |
465 | break; | |
517ee6cf C |
466 | case SND_SOC_DAIFMT_CBM_CFS: |
467 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
468 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
469 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 470 | |
f68205a7 PU |
471 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
472 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 473 | |
f68205a7 PU |
474 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
475 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 476 | mcasp->bclk_master = 0; |
517ee6cf | 477 | break; |
b67f4487 C |
478 | case SND_SOC_DAIFMT_CBM_CFM: |
479 | /* codec is clock and frame master */ | |
f68205a7 PU |
480 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
481 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 482 | |
f68205a7 PU |
483 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
484 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 485 | |
f68205a7 PU |
486 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
487 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 488 | mcasp->bclk_master = 0; |
b67f4487 | 489 | break; |
b67f4487 | 490 | default: |
1d17a04e PU |
491 | ret = -EINVAL; |
492 | goto out; | |
b67f4487 C |
493 | } |
494 | ||
495 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
496 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 497 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 498 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 499 | fs_pol_rising = true; |
b67f4487 | 500 | break; |
b67f4487 | 501 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 502 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 503 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 504 | fs_pol_rising = false; |
b67f4487 | 505 | break; |
b67f4487 | 506 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 507 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 508 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 509 | fs_pol_rising = false; |
b67f4487 | 510 | break; |
b67f4487 | 511 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 512 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 513 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 514 | fs_pol_rising = true; |
b67f4487 | 515 | break; |
b67f4487 | 516 | default: |
1d17a04e | 517 | ret = -EINVAL; |
83f12503 PU |
518 | goto out; |
519 | } | |
520 | ||
ffd950f7 PU |
521 | if (inv_fs) |
522 | fs_pol_rising = !fs_pol_rising; | |
523 | ||
83f12503 PU |
524 | if (fs_pol_rising) { |
525 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
526 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
527 | } else { | |
528 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
529 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 530 | } |
1d17a04e | 531 | out: |
6afda7f5 | 532 | pm_runtime_put(mcasp->dev); |
1d17a04e | 533 | return ret; |
b67f4487 C |
534 | } |
535 | ||
8813543e JS |
536 | static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
537 | int div, bool explicit) | |
4ed8c9b7 | 538 | { |
70091a3e | 539 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 | 540 | |
6afda7f5 | 541 | pm_runtime_get_sync(mcasp->dev); |
4ed8c9b7 DM |
542 | switch (div_id) { |
543 | case 0: /* MCLK divider */ | |
f68205a7 | 544 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 545 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 546 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
547 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
548 | break; | |
549 | ||
550 | case 1: /* BCLK divider */ | |
f68205a7 | 551 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 552 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 553 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 554 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
555 | if (explicit) |
556 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
557 | break; |
558 | ||
1b3bc060 | 559 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 560 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
561 | break; |
562 | ||
4ed8c9b7 DM |
563 | default: |
564 | return -EINVAL; | |
565 | } | |
566 | ||
6afda7f5 | 567 | pm_runtime_put(mcasp->dev); |
4ed8c9b7 DM |
568 | return 0; |
569 | } | |
570 | ||
8813543e JS |
571 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
572 | int div) | |
573 | { | |
574 | return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1); | |
575 | } | |
576 | ||
5b66aa2d DM |
577 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
578 | unsigned int freq, int dir) | |
579 | { | |
70091a3e | 580 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d | 581 | |
6afda7f5 | 582 | pm_runtime_get_sync(mcasp->dev); |
5b66aa2d | 583 | if (dir == SND_SOC_CLOCK_OUT) { |
f68205a7 PU |
584 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
585 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
586 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 587 | } else { |
f68205a7 PU |
588 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
589 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
590 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
591 | } |
592 | ||
ab8b14b6 JS |
593 | mcasp->sysclk_freq = freq; |
594 | ||
6afda7f5 | 595 | pm_runtime_put(mcasp->dev); |
5b66aa2d DM |
596 | return 0; |
597 | } | |
598 | ||
70091a3e | 599 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 600 | int word_length) |
b67f4487 | 601 | { |
ba764b3d | 602 | u32 fmt; |
79671892 | 603 | u32 tx_rotate = (word_length / 4) & 0x7; |
ba764b3d | 604 | u32 mask = (1ULL << word_length) - 1; |
fe0a29e1 PU |
605 | /* |
606 | * For captured data we should not rotate, inversion and masking is | |
607 | * enoguh to get the data to the right position: | |
608 | * Format data from bus after reverse (XRBUF) | |
609 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
610 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
611 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
612 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
613 | */ | |
614 | u32 rx_rotate = 0; | |
b67f4487 | 615 | |
1b3bc060 DM |
616 | /* |
617 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
618 | * callback, take it into account here. That allows us to for example | |
619 | * send 32 bits per channel to the codec, while only 16 of them carry | |
620 | * audio payload. | |
d486fea6 MB |
621 | * The clock ratio is given for a full period of data (for I2S format |
622 | * both left and right channels), so it has to be divided by number of | |
623 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 624 | */ |
d742b925 PU |
625 | if (mcasp->bclk_lrclk_ratio) { |
626 | u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
627 | ||
628 | /* | |
629 | * When we have more bclk then it is needed for the data, we | |
630 | * need to use the rotation to move the received samples to have | |
631 | * correct alignment. | |
632 | */ | |
633 | rx_rotate = (slot_length - word_length) / 4; | |
634 | word_length = slot_length; | |
635 | } | |
1b3bc060 | 636 | |
ba764b3d DM |
637 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
638 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 639 | |
70091a3e | 640 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
641 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
642 | RXSSZ(0x0F)); | |
643 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
644 | TXSSZ(0x0F)); | |
645 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
646 | TXROT(7)); | |
647 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
648 | RXROT(7)); | |
649 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
650 | } |
651 | ||
f68205a7 | 652 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 653 | |
b67f4487 C |
654 | return 0; |
655 | } | |
656 | ||
662ffae9 | 657 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 658 | int period_words, int channels) |
b67f4487 | 659 | { |
5f04c603 | 660 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; |
b67f4487 | 661 | int i; |
6a99fb5f C |
662 | u8 tx_ser = 0; |
663 | u8 rx_ser = 0; | |
70091a3e | 664 | u8 slots = mcasp->tdm_slots; |
2952b27e | 665 | u8 max_active_serializers = (channels + slots - 1) / slots; |
dd093a0f | 666 | int active_serializers, numevt, n; |
487dce88 | 667 | u32 reg; |
b67f4487 | 668 | /* Default configuration */ |
40448e5e | 669 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 670 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
671 | |
672 | /* All PINS as McASP */ | |
f68205a7 | 673 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
674 | |
675 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
676 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
677 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 678 | } else { |
f68205a7 PU |
679 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
680 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
681 | } |
682 | ||
70091a3e | 683 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
684 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
685 | mcasp->serial_dir[i]); | |
70091a3e | 686 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 687 | tx_ser < max_active_serializers) { |
f68205a7 | 688 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
19db62ea MLC |
689 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
690 | DISMOD_LOW, DISMOD_MASK); | |
6a99fb5f | 691 | tx_ser++; |
70091a3e | 692 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 693 | rx_ser < max_active_serializers) { |
f68205a7 | 694 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 695 | rx_ser++; |
2952b27e | 696 | } else { |
f68205a7 PU |
697 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
698 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
699 | } |
700 | } | |
701 | ||
0bf0e8ae PU |
702 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
703 | active_serializers = tx_ser; | |
704 | numevt = mcasp->txnumevt; | |
705 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
706 | } else { | |
707 | active_serializers = rx_ser; | |
708 | numevt = mcasp->rxnumevt; | |
709 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
710 | } | |
ecf327c7 | 711 | |
0bf0e8ae | 712 | if (active_serializers < max_active_serializers) { |
70091a3e | 713 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
714 | "enabled in mcasp (%d)\n", channels, |
715 | active_serializers * slots); | |
ecf327c7 DM |
716 | return -EINVAL; |
717 | } | |
718 | ||
0bf0e8ae | 719 | /* AFIFO is not in use */ |
5f04c603 PU |
720 | if (!numevt) { |
721 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
722 | if (active_serializers > 1) { |
723 | /* | |
724 | * If more than one serializers are in use we have one | |
725 | * DMA request to provide data for all serializers. | |
726 | * For example if three serializers are enabled the DMA | |
727 | * need to transfer three words per DMA request. | |
728 | */ | |
33445643 PU |
729 | dma_data->maxburst = active_serializers; |
730 | } else { | |
33445643 PU |
731 | dma_data->maxburst = 0; |
732 | } | |
0bf0e8ae | 733 | return 0; |
5f04c603 | 734 | } |
6a99fb5f | 735 | |
dd093a0f PU |
736 | if (period_words % active_serializers) { |
737 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
738 | "active serializers: %d, %d\n", period_words, | |
739 | active_serializers); | |
740 | return -EINVAL; | |
741 | } | |
742 | ||
743 | /* | |
744 | * Calculate the optimal AFIFO depth for platform side: | |
745 | * The number of words for numevt need to be in steps of active | |
746 | * serializers. | |
747 | */ | |
748 | n = numevt % active_serializers; | |
749 | if (n) | |
750 | numevt += (active_serializers - n); | |
751 | while (period_words % numevt && numevt > 0) | |
752 | numevt -= active_serializers; | |
753 | if (numevt <= 0) | |
0bf0e8ae | 754 | numevt = active_serializers; |
487dce88 | 755 | |
0bf0e8ae PU |
756 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
757 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 758 | |
5f04c603 | 759 | /* Configure the burst size for platform drivers */ |
33445643 PU |
760 | if (numevt == 1) |
761 | numevt = 0; | |
5f04c603 PU |
762 | dma_data->maxburst = numevt; |
763 | ||
2952b27e | 764 | return 0; |
b67f4487 C |
765 | } |
766 | ||
18a4f557 MLC |
767 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, |
768 | int channels) | |
b67f4487 C |
769 | { |
770 | int i, active_slots; | |
18a4f557 MLC |
771 | int total_slots; |
772 | int active_serializers; | |
b67f4487 | 773 | u32 mask = 0; |
cbc7956c | 774 | u32 busel = 0; |
b67f4487 | 775 | |
18a4f557 MLC |
776 | total_slots = mcasp->tdm_slots; |
777 | ||
778 | /* | |
779 | * If more than one serializer is needed, then use them with | |
780 | * their specified tdm_slots count. Otherwise, one serializer | |
781 | * can cope with the transaction using as many slots as channels | |
782 | * in the stream, requires channels symmetry | |
783 | */ | |
784 | active_serializers = (channels + total_slots - 1) / total_slots; | |
785 | if (active_serializers == 1) | |
786 | active_slots = channels; | |
787 | else | |
788 | active_slots = total_slots; | |
789 | ||
b67f4487 C |
790 | for (i = 0; i < active_slots; i++) |
791 | mask |= (1 << i); | |
792 | ||
f68205a7 | 793 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 794 | |
cbc7956c PU |
795 | if (!mcasp->dat_port) |
796 | busel = TXSEL; | |
797 | ||
2c56c4c2 PU |
798 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
799 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
800 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
18a4f557 | 801 | FSXMOD(total_slots), FSXMOD(0x1FF)); |
2c56c4c2 PU |
802 | |
803 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
804 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
805 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
18a4f557 | 806 | FSRMOD(total_slots), FSRMOD(0x1FF)); |
2c56c4c2 PU |
807 | |
808 | return 0; | |
b67f4487 C |
809 | } |
810 | ||
811 | /* S/PDIF */ | |
6479285d DM |
812 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
813 | unsigned int rate) | |
b67f4487 | 814 | { |
6479285d DM |
815 | u32 cs_value = 0; |
816 | u8 *cs_bytes = (u8*) &cs_value; | |
817 | ||
b67f4487 C |
818 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
819 | and LSB first */ | |
f68205a7 | 820 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
821 | |
822 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 823 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
824 | |
825 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 826 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
827 | |
828 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 829 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 830 | |
f68205a7 | 831 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
832 | |
833 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 834 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
835 | |
836 | /* Enable the DIT */ | |
f68205a7 | 837 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 838 | |
6479285d DM |
839 | /* Set S/PDIF channel status bits */ |
840 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
841 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
842 | ||
843 | switch (rate) { | |
844 | case 22050: | |
845 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
846 | break; | |
847 | case 24000: | |
848 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
849 | break; | |
850 | case 32000: | |
851 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
852 | break; | |
853 | case 44100: | |
854 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
855 | break; | |
856 | case 48000: | |
857 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
858 | break; | |
859 | case 88200: | |
860 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
861 | break; | |
862 | case 96000: | |
863 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
864 | break; | |
865 | case 176400: | |
866 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
867 | break; | |
868 | case 192000: | |
869 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
870 | break; | |
871 | default: | |
872 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
873 | return -EINVAL; | |
874 | } | |
875 | ||
876 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
877 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
878 | ||
2c56c4c2 | 879 | return 0; |
b67f4487 C |
880 | } |
881 | ||
a75a053f JS |
882 | static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, |
883 | unsigned int bclk_freq, | |
884 | int *error_ppm) | |
885 | { | |
886 | int div = mcasp->sysclk_freq / bclk_freq; | |
887 | int rem = mcasp->sysclk_freq % bclk_freq; | |
888 | ||
889 | if (rem != 0) { | |
890 | if (div == 0 || | |
891 | ((mcasp->sysclk_freq / div) - bclk_freq) > | |
892 | (bclk_freq - (mcasp->sysclk_freq / (div+1)))) { | |
893 | div++; | |
894 | rem = rem - bclk_freq; | |
895 | } | |
896 | } | |
897 | if (error_ppm) | |
898 | *error_ppm = | |
899 | (div*1000000 + (int)div64_long(1000000LL*rem, | |
900 | (int)bclk_freq)) | |
901 | /div - 1000000; | |
902 | ||
903 | return div; | |
904 | } | |
905 | ||
b67f4487 C |
906 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, |
907 | struct snd_pcm_hw_params *params, | |
908 | struct snd_soc_dai *cpu_dai) | |
909 | { | |
70091a3e | 910 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 911 | int word_length; |
a7e46bd9 | 912 | int channels = params_channels(params); |
dd093a0f | 913 | int period_size = params_period_size(params); |
2c56c4c2 | 914 | int ret; |
ab8b14b6 | 915 | |
8267525c DM |
916 | /* |
917 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
918 | * the machine driver, we need to calculate the ratio. | |
919 | */ | |
920 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
1f114f77 | 921 | int slots = mcasp->tdm_slots; |
a75a053f JS |
922 | int rate = params_rate(params); |
923 | int sbits = params_width(params); | |
924 | int ppm, div; | |
925 | ||
1f114f77 | 926 | div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots, |
a75a053f JS |
927 | &ppm); |
928 | if (ppm) | |
929 | dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", | |
930 | ppm); | |
931 | ||
8813543e | 932 | __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0); |
ab8b14b6 JS |
933 | } |
934 | ||
dd093a0f PU |
935 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
936 | period_size * channels, channels); | |
0f7d9a63 PU |
937 | if (ret) |
938 | return ret; | |
939 | ||
70091a3e | 940 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 941 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 942 | else |
18a4f557 MLC |
943 | ret = mcasp_i2s_hw_param(mcasp, substream->stream, |
944 | channels); | |
2c56c4c2 PU |
945 | |
946 | if (ret) | |
947 | return ret; | |
b67f4487 C |
948 | |
949 | switch (params_format(params)) { | |
0a9d1385 | 950 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 | 951 | case SNDRV_PCM_FORMAT_S8: |
ba764b3d | 952 | word_length = 8; |
b67f4487 C |
953 | break; |
954 | ||
0a9d1385 | 955 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 | 956 | case SNDRV_PCM_FORMAT_S16_LE: |
ba764b3d | 957 | word_length = 16; |
b67f4487 C |
958 | break; |
959 | ||
21eb24d8 DM |
960 | case SNDRV_PCM_FORMAT_U24_3LE: |
961 | case SNDRV_PCM_FORMAT_S24_3LE: | |
ba764b3d | 962 | word_length = 24; |
21eb24d8 DM |
963 | break; |
964 | ||
6b7fa011 DM |
965 | case SNDRV_PCM_FORMAT_U24_LE: |
966 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
967 | word_length = 24; |
968 | break; | |
969 | ||
0a9d1385 | 970 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 | 971 | case SNDRV_PCM_FORMAT_S32_LE: |
ba764b3d | 972 | word_length = 32; |
b67f4487 C |
973 | break; |
974 | ||
975 | default: | |
976 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
977 | return -EINVAL; | |
978 | } | |
6a99fb5f | 979 | |
70091a3e | 980 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 | 981 | |
11277833 PU |
982 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) |
983 | mcasp->channels = channels; | |
984 | ||
b67f4487 C |
985 | return 0; |
986 | } | |
987 | ||
988 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
989 | int cmd, struct snd_soc_dai *cpu_dai) | |
990 | { | |
70091a3e | 991 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
992 | int ret = 0; |
993 | ||
994 | switch (cmd) { | |
b67f4487 | 995 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
996 | case SNDRV_PCM_TRIGGER_START: |
997 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 998 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 999 | break; |
b67f4487 | 1000 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 1001 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 1002 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 1003 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
1004 | break; |
1005 | ||
1006 | default: | |
1007 | ret = -EINVAL; | |
1008 | } | |
1009 | ||
1010 | return ret; | |
1011 | } | |
1012 | ||
a75a053f JS |
1013 | static const unsigned int davinci_mcasp_dai_rates[] = { |
1014 | 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, | |
1015 | 88200, 96000, 176400, 192000, | |
1016 | }; | |
1017 | ||
1018 | #define DAVINCI_MAX_RATE_ERROR_PPM 1000 | |
1019 | ||
1020 | static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, | |
1021 | struct snd_pcm_hw_rule *rule) | |
1022 | { | |
1023 | struct davinci_mcasp_ruledata *rd = rule->private; | |
1024 | struct snd_interval *ri = | |
1025 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1026 | int sbits = params_width(params); | |
1f114f77 | 1027 | int slots = rd->mcasp->tdm_slots; |
518f6bab JS |
1028 | struct snd_interval range; |
1029 | int i; | |
1030 | ||
1031 | snd_interval_any(&range); | |
1032 | range.empty = 1; | |
a75a053f | 1033 | |
a75a053f | 1034 | for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { |
518f6bab | 1035 | if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { |
1f114f77 | 1036 | uint bclk_freq = sbits*slots* |
a75a053f JS |
1037 | davinci_mcasp_dai_rates[i]; |
1038 | int ppm; | |
1039 | ||
1040 | davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm); | |
518f6bab JS |
1041 | if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { |
1042 | if (range.empty) { | |
1043 | range.min = davinci_mcasp_dai_rates[i]; | |
1044 | range.empty = 0; | |
1045 | } | |
1046 | range.max = davinci_mcasp_dai_rates[i]; | |
1047 | } | |
a75a053f JS |
1048 | } |
1049 | } | |
518f6bab | 1050 | |
a75a053f | 1051 | dev_dbg(rd->mcasp->dev, |
518f6bab JS |
1052 | "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", |
1053 | ri->min, ri->max, range.min, range.max, sbits, slots); | |
a75a053f | 1054 | |
518f6bab JS |
1055 | return snd_interval_refine(hw_param_interval(params, rule->var), |
1056 | &range); | |
a75a053f JS |
1057 | } |
1058 | ||
1059 | static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, | |
1060 | struct snd_pcm_hw_rule *rule) | |
1061 | { | |
1062 | struct davinci_mcasp_ruledata *rd = rule->private; | |
1063 | struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); | |
1064 | struct snd_mask nfmt; | |
1065 | int rate = params_rate(params); | |
1f114f77 | 1066 | int slots = rd->mcasp->tdm_slots; |
a75a053f JS |
1067 | int i, count = 0; |
1068 | ||
1069 | snd_mask_none(&nfmt); | |
1070 | ||
a75a053f JS |
1071 | for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) { |
1072 | if (snd_mask_test(fmt, i)) { | |
1f114f77 | 1073 | uint bclk_freq = snd_pcm_format_width(i)*slots*rate; |
a75a053f JS |
1074 | int ppm; |
1075 | ||
1076 | davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm); | |
1077 | if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { | |
1078 | snd_mask_set(&nfmt, i); | |
1079 | count++; | |
1080 | } | |
1081 | } | |
1082 | } | |
1083 | dev_dbg(rd->mcasp->dev, | |
1f114f77 JS |
1084 | "%d possible sample format for %d Hz and %d tdm slots\n", |
1085 | count, rate, slots); | |
a75a053f JS |
1086 | |
1087 | return snd_mask_refine(fmt, &nfmt); | |
1088 | } | |
1089 | ||
11277833 PU |
1090 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
1091 | struct snd_soc_dai *cpu_dai) | |
1092 | { | |
1093 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
4cd9db08 PU |
1094 | struct davinci_mcasp_ruledata *ruledata = |
1095 | &mcasp->ruledata[substream->stream]; | |
11277833 PU |
1096 | u32 max_channels = 0; |
1097 | int i, dir; | |
1098 | ||
a7a3324a MLC |
1099 | mcasp->substreams[substream->stream] = substream; |
1100 | ||
11277833 PU |
1101 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1102 | return 0; | |
1103 | ||
1104 | /* | |
1105 | * Limit the maximum allowed channels for the first stream: | |
1106 | * number of serializers for the direction * tdm slots per serializer | |
1107 | */ | |
1108 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1109 | dir = TX_MODE; | |
1110 | else | |
1111 | dir = RX_MODE; | |
1112 | ||
1113 | for (i = 0; i < mcasp->num_serializer; i++) { | |
1114 | if (mcasp->serial_dir[i] == dir) | |
1115 | max_channels++; | |
1116 | } | |
4cd9db08 | 1117 | ruledata->serializers = max_channels; |
11277833 PU |
1118 | max_channels *= mcasp->tdm_slots; |
1119 | /* | |
1120 | * If the already active stream has less channels than the calculated | |
1121 | * limnit based on the seirializers * tdm_slots, we need to use that as | |
1122 | * a constraint for the second stream. | |
1123 | * Otherwise (first stream or less allowed channels) we use the | |
1124 | * calculated constraint. | |
1125 | */ | |
1126 | if (mcasp->channels && mcasp->channels < max_channels) | |
1127 | max_channels = mcasp->channels; | |
1128 | ||
1129 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1130 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1131 | 2, max_channels); | |
a75a053f | 1132 | |
5935a056 JS |
1133 | if (mcasp->chconstr[substream->stream].count) |
1134 | snd_pcm_hw_constraint_list(substream->runtime, | |
1135 | 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
1136 | &mcasp->chconstr[substream->stream]); | |
1137 | ||
a75a053f JS |
1138 | /* |
1139 | * If we rely on implicit BCLK divider setting we should | |
1140 | * set constraints based on what we can provide. | |
1141 | */ | |
1142 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
1143 | int ret; | |
1144 | ||
4cd9db08 | 1145 | ruledata->mcasp = mcasp; |
a75a053f JS |
1146 | |
1147 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
1148 | SNDRV_PCM_HW_PARAM_RATE, | |
1149 | davinci_mcasp_hw_rule_rate, | |
4cd9db08 | 1150 | ruledata, |
1f114f77 | 1151 | SNDRV_PCM_HW_PARAM_FORMAT, -1); |
a75a053f JS |
1152 | if (ret) |
1153 | return ret; | |
1154 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
1155 | SNDRV_PCM_HW_PARAM_FORMAT, | |
1156 | davinci_mcasp_hw_rule_format, | |
4cd9db08 | 1157 | ruledata, |
1f114f77 | 1158 | SNDRV_PCM_HW_PARAM_RATE, -1); |
a75a053f JS |
1159 | if (ret) |
1160 | return ret; | |
1161 | } | |
1162 | ||
11277833 PU |
1163 | return 0; |
1164 | } | |
1165 | ||
1166 | static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, | |
1167 | struct snd_soc_dai *cpu_dai) | |
1168 | { | |
1169 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
1170 | ||
a7a3324a MLC |
1171 | mcasp->substreams[substream->stream] = NULL; |
1172 | ||
11277833 PU |
1173 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1174 | return; | |
1175 | ||
1176 | if (!cpu_dai->active) | |
1177 | mcasp->channels = 0; | |
1178 | } | |
1179 | ||
85e7652d | 1180 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
11277833 PU |
1181 | .startup = davinci_mcasp_startup, |
1182 | .shutdown = davinci_mcasp_shutdown, | |
b67f4487 C |
1183 | .trigger = davinci_mcasp_trigger, |
1184 | .hw_params = davinci_mcasp_hw_params, | |
1185 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 1186 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 1187 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
1188 | }; |
1189 | ||
d5902f69 PU |
1190 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
1191 | { | |
1192 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
1193 | ||
9759e7ef PU |
1194 | dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
1195 | dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
d5902f69 PU |
1196 | |
1197 | return 0; | |
1198 | } | |
1199 | ||
135014ad PU |
1200 | #ifdef CONFIG_PM_SLEEP |
1201 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
1202 | { | |
1203 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1204 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1205 | u32 reg; |
1cc0c054 | 1206 | int i; |
135014ad | 1207 | |
66e61885 | 1208 | context->pm_state = pm_runtime_enabled(mcasp->dev); |
6afda7f5 PU |
1209 | if (!context->pm_state) |
1210 | pm_runtime_get_sync(mcasp->dev); | |
1211 | ||
1cc0c054 PU |
1212 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1213 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 1214 | |
f114ce60 PU |
1215 | if (mcasp->txnumevt) { |
1216 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1217 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
1218 | } | |
1219 | if (mcasp->rxnumevt) { | |
1220 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1221 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
1222 | } | |
135014ad | 1223 | |
f114ce60 PU |
1224 | for (i = 0; i < mcasp->num_serializer; i++) |
1225 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
1226 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad | 1227 | |
6afda7f5 PU |
1228 | pm_runtime_put_sync(mcasp->dev); |
1229 | ||
135014ad PU |
1230 | return 0; |
1231 | } | |
1232 | ||
1233 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
1234 | { | |
1235 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1236 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1237 | u32 reg; |
1cc0c054 | 1238 | int i; |
790bb94b | 1239 | |
6afda7f5 PU |
1240 | pm_runtime_get_sync(mcasp->dev); |
1241 | ||
1cc0c054 PU |
1242 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1243 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 1244 | |
f114ce60 PU |
1245 | if (mcasp->txnumevt) { |
1246 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1247 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
1248 | } | |
1249 | if (mcasp->rxnumevt) { | |
1250 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1251 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
1252 | } | |
790bb94b | 1253 | |
f114ce60 PU |
1254 | for (i = 0; i < mcasp->num_serializer; i++) |
1255 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
1256 | context->xrsr_regs[i]); | |
135014ad | 1257 | |
6afda7f5 PU |
1258 | if (!context->pm_state) |
1259 | pm_runtime_put_sync(mcasp->dev); | |
1260 | ||
135014ad PU |
1261 | return 0; |
1262 | } | |
1263 | #else | |
1264 | #define davinci_mcasp_suspend NULL | |
1265 | #define davinci_mcasp_resume NULL | |
1266 | #endif | |
1267 | ||
ed29cd5e PU |
1268 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
1269 | ||
0a9d1385 BG |
1270 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
1271 | SNDRV_PCM_FMTBIT_U8 | \ | |
1272 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
1273 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
1274 | SNDRV_PCM_FMTBIT_S24_LE | \ |
1275 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
1276 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
1277 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
1278 | SNDRV_PCM_FMTBIT_S32_LE | \ |
1279 | SNDRV_PCM_FMTBIT_U32_LE) | |
1280 | ||
f0fba2ad | 1281 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 1282 | { |
f0fba2ad | 1283 | .name = "davinci-mcasp.0", |
d5902f69 | 1284 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
1285 | .suspend = davinci_mcasp_suspend, |
1286 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
1287 | .playback = { |
1288 | .channels_min = 2, | |
2952b27e | 1289 | .channels_max = 32 * 16, |
b67f4487 | 1290 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1291 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1292 | }, |
1293 | .capture = { | |
1294 | .channels_min = 2, | |
2952b27e | 1295 | .channels_max = 32 * 16, |
b67f4487 | 1296 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1297 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1298 | }, |
1299 | .ops = &davinci_mcasp_dai_ops, | |
1300 | ||
d75249f5 | 1301 | .symmetric_samplebits = 1, |
b67f4487 C |
1302 | }, |
1303 | { | |
58e48d97 | 1304 | .name = "davinci-mcasp.1", |
d5902f69 | 1305 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
1306 | .playback = { |
1307 | .channels_min = 1, | |
1308 | .channels_max = 384, | |
1309 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 1310 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1311 | }, |
1312 | .ops = &davinci_mcasp_dai_ops, | |
1313 | }, | |
1314 | ||
1315 | }; | |
b67f4487 | 1316 | |
eeef0eda KM |
1317 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
1318 | .name = "davinci-mcasp", | |
1319 | }; | |
1320 | ||
256ba181 | 1321 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 1322 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
1323 | .tx_dma_offset = 0x400, |
1324 | .rx_dma_offset = 0x400, | |
256ba181 JS |
1325 | .version = MCASP_VERSION_1, |
1326 | }; | |
1327 | ||
d1debafc | 1328 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
1329 | .tx_dma_offset = 0x2000, |
1330 | .rx_dma_offset = 0x2000, | |
256ba181 JS |
1331 | .version = MCASP_VERSION_2, |
1332 | }; | |
1333 | ||
d1debafc | 1334 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
1335 | .tx_dma_offset = 0, |
1336 | .rx_dma_offset = 0, | |
256ba181 JS |
1337 | .version = MCASP_VERSION_3, |
1338 | }; | |
1339 | ||
d1debafc | 1340 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
1341 | .tx_dma_offset = 0x200, |
1342 | .rx_dma_offset = 0x284, | |
453c4990 PU |
1343 | .version = MCASP_VERSION_4, |
1344 | }; | |
1345 | ||
3e3b8c34 HG |
1346 | static const struct of_device_id mcasp_dt_ids[] = { |
1347 | { | |
1348 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1349 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1350 | }, |
1351 | { | |
1352 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1353 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1354 | }, |
e5ec69da | 1355 | { |
3af9e031 | 1356 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1357 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1358 | }, |
453c4990 PU |
1359 | { |
1360 | .compatible = "ti,dra7-mcasp-audio", | |
1361 | .data = &dra7_mcasp_pdata, | |
1362 | }, | |
3e3b8c34 HG |
1363 | { /* sentinel */ } |
1364 | }; | |
1365 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1366 | ||
ae726e93 PU |
1367 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1368 | { | |
1369 | struct device_node *node = pdev->dev.of_node; | |
1370 | struct clk *gfclk, *parent_clk; | |
1371 | const char *parent_name; | |
1372 | int ret; | |
1373 | ||
1374 | if (!node) | |
1375 | return 0; | |
1376 | ||
1377 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1378 | if (!parent_name) | |
1379 | return 0; | |
1380 | ||
1381 | gfclk = clk_get(&pdev->dev, "fck"); | |
1382 | if (IS_ERR(gfclk)) { | |
1383 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1384 | return PTR_ERR(gfclk); | |
1385 | } | |
1386 | ||
1387 | parent_clk = clk_get(NULL, parent_name); | |
1388 | if (IS_ERR(parent_clk)) { | |
1389 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1390 | ret = PTR_ERR(parent_clk); | |
1391 | goto err1; | |
1392 | } | |
1393 | ||
1394 | ret = clk_set_parent(gfclk, parent_clk); | |
1395 | if (ret) { | |
1396 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1397 | goto err2; | |
1398 | } | |
1399 | ||
1400 | err2: | |
1401 | clk_put(parent_clk); | |
1402 | err1: | |
1403 | clk_put(gfclk); | |
1404 | return ret; | |
1405 | } | |
1406 | ||
d1debafc | 1407 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1408 | struct platform_device *pdev) |
1409 | { | |
1410 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1411 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1412 | const struct of_device_id *match = |
ea421eb1 | 1413 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1414 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1415 | |
1416 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1417 | u32 val; |
1418 | int i, ret = 0; | |
1419 | ||
1420 | if (pdev->dev.platform_data) { | |
1421 | pdata = pdev->dev.platform_data; | |
1422 | return pdata; | |
1423 | } else if (match) { | |
d1debafc | 1424 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1425 | } else { |
1426 | /* control shouldn't reach here. something is wrong */ | |
1427 | ret = -EINVAL; | |
1428 | goto nodata; | |
1429 | } | |
1430 | ||
3e3b8c34 HG |
1431 | ret = of_property_read_u32(np, "op-mode", &val); |
1432 | if (ret >= 0) | |
1433 | pdata->op_mode = val; | |
1434 | ||
1435 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1436 | if (ret >= 0) { |
1437 | if (val < 2 || val > 32) { | |
1438 | dev_err(&pdev->dev, | |
1439 | "tdm-slots must be in rage [2-32]\n"); | |
1440 | ret = -EINVAL; | |
1441 | goto nodata; | |
1442 | } | |
1443 | ||
3e3b8c34 | 1444 | pdata->tdm_slots = val; |
2952b27e | 1445 | } |
3e3b8c34 | 1446 | |
3e3b8c34 HG |
1447 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1448 | val /= sizeof(u32); | |
3e3b8c34 | 1449 | if (of_serial_dir32) { |
1427e660 PU |
1450 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1451 | (sizeof(*of_serial_dir) * val), | |
1452 | GFP_KERNEL); | |
3e3b8c34 HG |
1453 | if (!of_serial_dir) { |
1454 | ret = -ENOMEM; | |
1455 | goto nodata; | |
1456 | } | |
1457 | ||
1427e660 | 1458 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1459 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1460 | ||
1427e660 | 1461 | pdata->num_serializer = val; |
3e3b8c34 HG |
1462 | pdata->serial_dir = of_serial_dir; |
1463 | } | |
1464 | ||
4023fe6f JS |
1465 | ret = of_property_match_string(np, "dma-names", "tx"); |
1466 | if (ret < 0) | |
1467 | goto nodata; | |
1468 | ||
1469 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1470 | &dma_spec); | |
1471 | if (ret < 0) | |
1472 | goto nodata; | |
1473 | ||
1474 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1475 | ||
caa1d794 PU |
1476 | /* RX is not valid in DIT mode */ |
1477 | if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
1478 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1479 | if (ret < 0) | |
1480 | goto nodata; | |
4023fe6f | 1481 | |
caa1d794 PU |
1482 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
1483 | &dma_spec); | |
1484 | if (ret < 0) | |
1485 | goto nodata; | |
4023fe6f | 1486 | |
caa1d794 PU |
1487 | pdata->rx_dma_channel = dma_spec.args[0]; |
1488 | } | |
4023fe6f | 1489 | |
3e3b8c34 HG |
1490 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1491 | if (ret >= 0) | |
1492 | pdata->txnumevt = val; | |
1493 | ||
1494 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1495 | if (ret >= 0) | |
1496 | pdata->rxnumevt = val; | |
1497 | ||
1498 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1499 | if (ret >= 0) | |
1500 | pdata->sram_size_playback = val; | |
1501 | ||
1502 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1503 | if (ret >= 0) | |
1504 | pdata->sram_size_capture = val; | |
1505 | ||
1506 | return pdata; | |
1507 | ||
1508 | nodata: | |
1509 | if (ret < 0) { | |
1510 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1511 | ret); | |
1512 | pdata = NULL; | |
1513 | } | |
1514 | return pdata; | |
1515 | } | |
1516 | ||
5935a056 JS |
1517 | /* All serializers must have equal number of channels */ |
1518 | static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, | |
1519 | struct snd_pcm_hw_constraint_list *cl, | |
1520 | int serializers) | |
1521 | { | |
1522 | unsigned int *list; | |
1523 | int i, count = 0; | |
1524 | ||
1525 | if (serializers <= 1) | |
1526 | return 0; | |
1527 | ||
1528 | list = devm_kzalloc(mcasp->dev, sizeof(unsigned int) * | |
1529 | (mcasp->tdm_slots + serializers - 2), | |
1530 | GFP_KERNEL); | |
1531 | if (!list) | |
1532 | return -ENOMEM; | |
1533 | ||
1534 | for (i = 2; i <= mcasp->tdm_slots; i++) | |
1535 | list[count++] = i; | |
1536 | ||
1537 | for (i = 2; i <= serializers; i++) | |
1538 | list[count++] = i*mcasp->tdm_slots; | |
1539 | ||
1540 | cl->count = count; | |
1541 | cl->list = list; | |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | ||
1547 | static int davinci_mcasp_init_ch_constraints(struct davinci_mcasp *mcasp) | |
1548 | { | |
1549 | int rx_serializers = 0, tx_serializers = 0, ret, i; | |
1550 | ||
1551 | for (i = 0; i < mcasp->num_serializer; i++) | |
1552 | if (mcasp->serial_dir[i] == TX_MODE) | |
1553 | tx_serializers++; | |
1554 | else if (mcasp->serial_dir[i] == RX_MODE) | |
1555 | rx_serializers++; | |
1556 | ||
1557 | ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[ | |
1558 | SNDRV_PCM_STREAM_PLAYBACK], | |
1559 | tx_serializers); | |
1560 | if (ret) | |
1561 | return ret; | |
1562 | ||
1563 | ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[ | |
1564 | SNDRV_PCM_STREAM_CAPTURE], | |
1565 | rx_serializers); | |
1566 | ||
1567 | return ret; | |
1568 | } | |
1569 | ||
b67f4487 C |
1570 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1571 | { | |
8de131f2 | 1572 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1573 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1574 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1575 | struct davinci_mcasp *mcasp; |
a7a3324a | 1576 | char *irq_name; |
9759e7ef | 1577 | int *dma; |
a7a3324a | 1578 | int irq; |
96d31e2b | 1579 | int ret; |
b67f4487 | 1580 | |
3e3b8c34 HG |
1581 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1582 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1583 | return -EINVAL; | |
1584 | } | |
1585 | ||
70091a3e | 1586 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1587 | GFP_KERNEL); |
70091a3e | 1588 | if (!mcasp) |
b67f4487 C |
1589 | return -ENOMEM; |
1590 | ||
3e3b8c34 HG |
1591 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1592 | if (!pdata) { | |
1593 | dev_err(&pdev->dev, "no platform data\n"); | |
1594 | return -EINVAL; | |
1595 | } | |
1596 | ||
256ba181 | 1597 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1598 | if (!mem) { |
70091a3e | 1599 | dev_warn(mcasp->dev, |
256ba181 JS |
1600 | "\"mpu\" mem resource not found, using index 0\n"); |
1601 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1602 | if (!mem) { | |
1603 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1604 | return -ENODEV; | |
1605 | } | |
b67f4487 C |
1606 | } |
1607 | ||
96d31e2b | 1608 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1609 | resource_size(mem), pdev->name); |
b67f4487 C |
1610 | if (!ioarea) { |
1611 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1612 | return -EBUSY; |
b67f4487 C |
1613 | } |
1614 | ||
10884347 | 1615 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1616 | |
70091a3e PU |
1617 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1618 | if (!mcasp->base) { | |
4f82f028 VB |
1619 | dev_err(&pdev->dev, "ioremap failed\n"); |
1620 | ret = -ENOMEM; | |
b6bb3709 | 1621 | goto err; |
4f82f028 VB |
1622 | } |
1623 | ||
70091a3e | 1624 | mcasp->op_mode = pdata->op_mode; |
1a5923da PU |
1625 | /* sanity check for tdm slots parameter */ |
1626 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { | |
1627 | if (pdata->tdm_slots < 2) { | |
1628 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1629 | pdata->tdm_slots); | |
1630 | mcasp->tdm_slots = 2; | |
1631 | } else if (pdata->tdm_slots > 32) { | |
1632 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1633 | pdata->tdm_slots); | |
1634 | mcasp->tdm_slots = 32; | |
1635 | } else { | |
1636 | mcasp->tdm_slots = pdata->tdm_slots; | |
1637 | } | |
1638 | } | |
1639 | ||
70091a3e | 1640 | mcasp->num_serializer = pdata->num_serializer; |
f114ce60 PU |
1641 | #ifdef CONFIG_PM_SLEEP |
1642 | mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, | |
1643 | sizeof(u32) * mcasp->num_serializer, | |
1644 | GFP_KERNEL); | |
1645 | #endif | |
70091a3e PU |
1646 | mcasp->serial_dir = pdata->serial_dir; |
1647 | mcasp->version = pdata->version; | |
1648 | mcasp->txnumevt = pdata->txnumevt; | |
1649 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1650 | |
70091a3e | 1651 | mcasp->dev = &pdev->dev; |
b67f4487 | 1652 | |
5a1b8a80 PU |
1653 | irq = platform_get_irq_byname(pdev, "common"); |
1654 | if (irq >= 0) { | |
1655 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common\n", | |
1656 | dev_name(&pdev->dev)); | |
1657 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1658 | davinci_mcasp_common_irq_handler, | |
8f511ffb PU |
1659 | IRQF_ONESHOT | IRQF_SHARED, |
1660 | irq_name, mcasp); | |
5a1b8a80 PU |
1661 | if (ret) { |
1662 | dev_err(&pdev->dev, "common IRQ request failed\n"); | |
1663 | goto err; | |
1664 | } | |
1665 | ||
1666 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1667 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1668 | } | |
1669 | ||
a7a3324a MLC |
1670 | irq = platform_get_irq_byname(pdev, "rx"); |
1671 | if (irq >= 0) { | |
1672 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n", | |
1673 | dev_name(&pdev->dev)); | |
1674 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1675 | davinci_mcasp_rx_irq_handler, | |
1676 | IRQF_ONESHOT, irq_name, mcasp); | |
1677 | if (ret) { | |
1678 | dev_err(&pdev->dev, "RX IRQ request failed\n"); | |
1679 | goto err; | |
1680 | } | |
1681 | ||
1682 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1683 | } | |
1684 | ||
1685 | irq = platform_get_irq_byname(pdev, "tx"); | |
1686 | if (irq >= 0) { | |
1687 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n", | |
1688 | dev_name(&pdev->dev)); | |
1689 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1690 | davinci_mcasp_tx_irq_handler, | |
1691 | IRQF_ONESHOT, irq_name, mcasp); | |
1692 | if (ret) { | |
1693 | dev_err(&pdev->dev, "TX IRQ request failed\n"); | |
1694 | goto err; | |
1695 | } | |
1696 | ||
1697 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1698 | } | |
1699 | ||
256ba181 | 1700 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1701 | if (dat) |
1702 | mcasp->dat_port = true; | |
256ba181 | 1703 | |
8de131f2 | 1704 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
cbc7956c | 1705 | if (dat) |
9759e7ef | 1706 | dma_data->addr = dat->start; |
cbc7956c | 1707 | else |
9759e7ef | 1708 | dma_data->addr = mem->start + pdata->tx_dma_offset; |
453c4990 | 1709 | |
9759e7ef | 1710 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; |
b67f4487 | 1711 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1712 | if (res) |
9759e7ef | 1713 | *dma = res->start; |
4023fe6f | 1714 | else |
9759e7ef | 1715 | *dma = pdata->tx_dma_channel; |
92e2a6f6 | 1716 | |
8de131f2 PU |
1717 | /* dmaengine filter data for DT and non-DT boot */ |
1718 | if (pdev->dev.of_node) | |
1719 | dma_data->filter_data = "tx"; | |
1720 | else | |
9759e7ef | 1721 | dma_data->filter_data = dma; |
8de131f2 | 1722 | |
caa1d794 PU |
1723 | /* RX is not valid in DIT mode */ |
1724 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
caa1d794 | 1725 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 | 1726 | if (dat) |
9759e7ef | 1727 | dma_data->addr = dat->start; |
caa1d794 | 1728 | else |
9759e7ef | 1729 | dma_data->addr = mem->start + pdata->rx_dma_offset; |
caa1d794 | 1730 | |
9759e7ef | 1731 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 PU |
1732 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
1733 | if (res) | |
9759e7ef | 1734 | *dma = res->start; |
caa1d794 | 1735 | else |
9759e7ef | 1736 | *dma = pdata->rx_dma_channel; |
caa1d794 PU |
1737 | |
1738 | /* dmaengine filter data for DT and non-DT boot */ | |
1739 | if (pdev->dev.of_node) | |
1740 | dma_data->filter_data = "rx"; | |
1741 | else | |
9759e7ef | 1742 | dma_data->filter_data = dma; |
caa1d794 | 1743 | } |
453c4990 | 1744 | |
cbc7956c PU |
1745 | if (mcasp->version < MCASP_VERSION_3) { |
1746 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1747 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1748 | mcasp->dat_port = true; |
1749 | } else { | |
1750 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1751 | } | |
b67f4487 | 1752 | |
5935a056 JS |
1753 | ret = davinci_mcasp_init_ch_constraints(mcasp); |
1754 | if (ret) | |
1755 | goto err; | |
1756 | ||
70091a3e | 1757 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1758 | |
1759 | mcasp_reparent_fck(pdev); | |
1760 | ||
b6bb3709 PU |
1761 | ret = devm_snd_soc_register_component(&pdev->dev, |
1762 | &davinci_mcasp_component, | |
1763 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1764 | |
1765 | if (ret != 0) | |
b6bb3709 | 1766 | goto err; |
f08095a4 | 1767 | |
d5c6c59a | 1768 | switch (mcasp->version) { |
f3f9cfa8 PU |
1769 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1770 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1771 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
9759e7ef PU |
1772 | case MCASP_VERSION_1: |
1773 | case MCASP_VERSION_2: | |
f3f9cfa8 PU |
1774 | case MCASP_VERSION_3: |
1775 | ret = edma_pcm_platform_register(&pdev->dev); | |
1776 | break; | |
1777 | #endif | |
7f28f357 JS |
1778 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
1779 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1780 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a PU |
1781 | case MCASP_VERSION_4: |
1782 | ret = omap_pcm_platform_register(&pdev->dev); | |
1783 | break; | |
7f28f357 | 1784 | #endif |
d5c6c59a PU |
1785 | default: |
1786 | dev_err(&pdev->dev, "Invalid McASP version: %d\n", | |
1787 | mcasp->version); | |
1788 | ret = -EINVAL; | |
1789 | break; | |
1790 | } | |
1791 | ||
1792 | if (ret) { | |
1793 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 1794 | goto err; |
f08095a4 HG |
1795 | } |
1796 | ||
b67f4487 C |
1797 | return 0; |
1798 | ||
b6bb3709 | 1799 | err: |
10884347 | 1800 | pm_runtime_disable(&pdev->dev); |
b67f4487 C |
1801 | return ret; |
1802 | } | |
1803 | ||
1804 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1805 | { | |
10884347 | 1806 | pm_runtime_disable(&pdev->dev); |
b67f4487 | 1807 | |
b67f4487 C |
1808 | return 0; |
1809 | } | |
1810 | ||
1811 | static struct platform_driver davinci_mcasp_driver = { | |
1812 | .probe = davinci_mcasp_probe, | |
1813 | .remove = davinci_mcasp_remove, | |
1814 | .driver = { | |
1815 | .name = "davinci-mcasp", | |
ea421eb1 | 1816 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1817 | }, |
1818 | }; | |
1819 | ||
f9b8a514 | 1820 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1821 | |
1822 | MODULE_AUTHOR("Steve Chen"); | |
1823 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1824 | MODULE_LICENSE("GPL"); |