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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
b67f4487 | 29 | |
6479285d | 30 | #include <sound/asoundef.h> |
b67f4487 C |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/initval.h> | |
35 | #include <sound/soc.h> | |
453c4990 | 36 | #include <sound/dmaengine_pcm.h> |
87c19364 | 37 | #include <sound/omap-pcm.h> |
b67f4487 C |
38 | |
39 | #include "davinci-pcm.h" | |
f3f9cfa8 | 40 | #include "edma-pcm.h" |
b67f4487 C |
41 | #include "davinci-mcasp.h" |
42 | ||
0bf0e8ae PU |
43 | #define MCASP_MAX_AFIFO_DEPTH 64 |
44 | ||
1cc0c054 PU |
45 | static u32 context_regs[] = { |
46 | DAVINCI_MCASP_TXFMCTL_REG, | |
47 | DAVINCI_MCASP_RXFMCTL_REG, | |
48 | DAVINCI_MCASP_TXFMT_REG, | |
49 | DAVINCI_MCASP_RXFMT_REG, | |
50 | DAVINCI_MCASP_ACLKXCTL_REG, | |
51 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
52 | DAVINCI_MCASP_AHCLKXCTL_REG, |
53 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 54 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
55 | DAVINCI_MCASP_RXMASK_REG, |
56 | DAVINCI_MCASP_TXMASK_REG, | |
57 | DAVINCI_MCASP_RXTDM_REG, | |
58 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
59 | }; |
60 | ||
790bb94b | 61 | struct davinci_mcasp_context { |
1cc0c054 | 62 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
63 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
64 | u32 *xrsr_regs; /* for serializer configuration */ | |
790bb94b PU |
65 | }; |
66 | ||
70091a3e | 67 | struct davinci_mcasp { |
21400a72 | 68 | struct davinci_pcm_dma_params dma_params[2]; |
453c4990 | 69 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 70 | void __iomem *base; |
487dce88 | 71 | u32 fifo_base; |
21400a72 PU |
72 | struct device *dev; |
73 | ||
74 | /* McASP specific data */ | |
75 | int tdm_slots; | |
76 | u8 op_mode; | |
77 | u8 num_serializer; | |
78 | u8 *serial_dir; | |
79 | u8 version; | |
8267525c | 80 | u8 bclk_div; |
21400a72 | 81 | u16 bclk_lrclk_ratio; |
4dcb5a0b | 82 | int streams; |
21400a72 | 83 | |
ab8b14b6 JS |
84 | int sysclk_freq; |
85 | bool bclk_master; | |
86 | ||
21400a72 PU |
87 | /* McASP FIFO related */ |
88 | u8 txnumevt; | |
89 | u8 rxnumevt; | |
90 | ||
cbc7956c PU |
91 | bool dat_port; |
92 | ||
21400a72 | 93 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 94 | struct davinci_mcasp_context context; |
21400a72 PU |
95 | #endif |
96 | }; | |
97 | ||
f68205a7 PU |
98 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
99 | u32 val) | |
b67f4487 | 100 | { |
f68205a7 | 101 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
102 | __raw_writel(__raw_readl(reg) | val, reg); |
103 | } | |
104 | ||
f68205a7 PU |
105 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
106 | u32 val) | |
b67f4487 | 107 | { |
f68205a7 | 108 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
109 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
110 | } | |
111 | ||
f68205a7 PU |
112 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
113 | u32 val, u32 mask) | |
b67f4487 | 114 | { |
f68205a7 | 115 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
116 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
117 | } | |
118 | ||
f68205a7 PU |
119 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
120 | u32 val) | |
b67f4487 | 121 | { |
f68205a7 | 122 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
123 | } |
124 | ||
f68205a7 | 125 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 126 | { |
f68205a7 | 127 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
128 | } |
129 | ||
f68205a7 | 130 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
131 | { |
132 | int i = 0; | |
133 | ||
f68205a7 | 134 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
135 | |
136 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
137 | /* loop count is to avoid the lock-up */ | |
138 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 139 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
140 | break; |
141 | } | |
142 | ||
f68205a7 | 143 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
144 | printk(KERN_ERR "GBLCTL write error\n"); |
145 | } | |
146 | ||
4dcb5a0b PU |
147 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
148 | { | |
f68205a7 PU |
149 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
150 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
151 | |
152 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
153 | } | |
154 | ||
70091a3e | 155 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 156 | { |
bb372af0 PU |
157 | if (mcasp->rxnumevt) { /* enable FIFO */ |
158 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
159 | ||
160 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
161 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
162 | } | |
163 | ||
44982735 | 164 | /* Start clocks */ |
f68205a7 PU |
165 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
166 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
167 | /* |
168 | * When ASYNC == 0 the transmit and receive sections operate | |
169 | * synchronously from the transmit clock and frame sync. We need to make | |
170 | * sure that the TX signlas are enabled when starting reception. | |
171 | */ | |
172 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
173 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
174 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
175 | } |
176 | ||
44982735 | 177 | /* Activate serializer(s) */ |
f68205a7 | 178 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 179 | /* Release RX state machine */ |
f68205a7 | 180 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 181 | /* Release Frame Sync generator */ |
f68205a7 | 182 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 183 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 184 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
b67f4487 C |
185 | } |
186 | ||
70091a3e | 187 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 188 | { |
6a99fb5f C |
189 | u32 cnt; |
190 | ||
bb372af0 PU |
191 | if (mcasp->txnumevt) { /* enable FIFO */ |
192 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
193 | ||
194 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
195 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
196 | } | |
197 | ||
36bcecd0 | 198 | /* Start clocks */ |
f68205a7 PU |
199 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
200 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
36bcecd0 | 201 | /* Activate serializer(s) */ |
f68205a7 | 202 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 203 | |
36bcecd0 | 204 | /* wait for XDATA to be cleared */ |
6a99fb5f | 205 | cnt = 0; |
36bcecd0 PU |
206 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & |
207 | ~XRDATA) && (cnt < 100000)) | |
6a99fb5f C |
208 | cnt++; |
209 | ||
36bcecd0 PU |
210 | /* Release TX state machine */ |
211 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
212 | /* Release Frame Sync generator */ | |
213 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
b67f4487 C |
214 | } |
215 | ||
70091a3e | 216 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 217 | { |
4dcb5a0b PU |
218 | mcasp->streams++; |
219 | ||
bb372af0 | 220 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 221 | mcasp_start_tx(mcasp); |
bb372af0 | 222 | else |
70091a3e | 223 | mcasp_start_rx(mcasp); |
b67f4487 C |
224 | } |
225 | ||
70091a3e | 226 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 227 | { |
4dcb5a0b PU |
228 | /* |
229 | * In synchronous mode stop the TX clocks if no other stream is | |
230 | * running | |
231 | */ | |
232 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 233 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 234 | |
f68205a7 PU |
235 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
236 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
237 | |
238 | if (mcasp->rxnumevt) { /* disable FIFO */ | |
239 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
240 | ||
241 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
242 | } | |
b67f4487 C |
243 | } |
244 | ||
70091a3e | 245 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 246 | { |
4dcb5a0b PU |
247 | u32 val = 0; |
248 | ||
249 | /* | |
250 | * In synchronous mode keep TX clocks running if the capture stream is | |
251 | * still running. | |
252 | */ | |
253 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
254 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
255 | ||
f68205a7 PU |
256 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
257 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
258 | |
259 | if (mcasp->txnumevt) { /* disable FIFO */ | |
260 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
261 | ||
262 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
263 | } | |
b67f4487 C |
264 | } |
265 | ||
70091a3e | 266 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 267 | { |
4dcb5a0b PU |
268 | mcasp->streams--; |
269 | ||
0380866a | 270 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 271 | mcasp_stop_tx(mcasp); |
0380866a | 272 | else |
70091a3e | 273 | mcasp_stop_rx(mcasp); |
b67f4487 C |
274 | } |
275 | ||
276 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
277 | unsigned int fmt) | |
278 | { | |
70091a3e | 279 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 280 | int ret = 0; |
6dfa9a4e | 281 | u32 data_delay; |
83f12503 | 282 | bool fs_pol_rising; |
ffd950f7 | 283 | bool inv_fs = false; |
b67f4487 | 284 | |
1d17a04e | 285 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 286 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
287 | case SND_SOC_DAIFMT_DSP_A: |
288 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
289 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
290 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
291 | data_delay = 1; | |
292 | break; | |
5296cf2d DM |
293 | case SND_SOC_DAIFMT_DSP_B: |
294 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
295 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
296 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
297 | /* No delay after FS */ |
298 | data_delay = 0; | |
5296cf2d | 299 | break; |
ffd950f7 | 300 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 301 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
302 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
303 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
304 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
305 | data_delay = 1; | |
ffd950f7 PU |
306 | /* FS need to be inverted */ |
307 | inv_fs = true; | |
5296cf2d | 308 | break; |
423761e0 PU |
309 | case SND_SOC_DAIFMT_LEFT_J: |
310 | /* configure a full-word SYNC pulse (LRCLK) */ | |
311 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
312 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
313 | /* No delay after FS */ | |
314 | data_delay = 0; | |
315 | break; | |
ffd950f7 PU |
316 | default: |
317 | ret = -EINVAL; | |
318 | goto out; | |
5296cf2d DM |
319 | } |
320 | ||
6dfa9a4e PU |
321 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
322 | FSXDLY(3)); | |
323 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
324 | FSRDLY(3)); | |
325 | ||
b67f4487 C |
326 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
327 | case SND_SOC_DAIFMT_CBS_CFS: | |
328 | /* codec is clock and frame slave */ | |
f68205a7 PU |
329 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
330 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 331 | |
f68205a7 PU |
332 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
333 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 334 | |
f68205a7 PU |
335 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
336 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 337 | mcasp->bclk_master = 1; |
b67f4487 | 338 | break; |
517ee6cf C |
339 | case SND_SOC_DAIFMT_CBM_CFS: |
340 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
341 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
342 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 343 | |
f68205a7 PU |
344 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
345 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 346 | |
f68205a7 PU |
347 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
348 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 349 | mcasp->bclk_master = 0; |
517ee6cf | 350 | break; |
b67f4487 C |
351 | case SND_SOC_DAIFMT_CBM_CFM: |
352 | /* codec is clock and frame master */ | |
f68205a7 PU |
353 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
354 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 355 | |
f68205a7 PU |
356 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
357 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 358 | |
f68205a7 PU |
359 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
360 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 361 | mcasp->bclk_master = 0; |
b67f4487 | 362 | break; |
b67f4487 | 363 | default: |
1d17a04e PU |
364 | ret = -EINVAL; |
365 | goto out; | |
b67f4487 C |
366 | } |
367 | ||
368 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
369 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 370 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 371 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 372 | fs_pol_rising = true; |
b67f4487 | 373 | break; |
b67f4487 | 374 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 375 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 376 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 377 | fs_pol_rising = false; |
b67f4487 | 378 | break; |
b67f4487 | 379 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 380 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 381 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 382 | fs_pol_rising = false; |
b67f4487 | 383 | break; |
b67f4487 | 384 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 385 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 386 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 387 | fs_pol_rising = true; |
b67f4487 | 388 | break; |
b67f4487 | 389 | default: |
1d17a04e | 390 | ret = -EINVAL; |
83f12503 PU |
391 | goto out; |
392 | } | |
393 | ||
ffd950f7 PU |
394 | if (inv_fs) |
395 | fs_pol_rising = !fs_pol_rising; | |
396 | ||
83f12503 PU |
397 | if (fs_pol_rising) { |
398 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
399 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
400 | } else { | |
401 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
402 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 403 | } |
1d17a04e PU |
404 | out: |
405 | pm_runtime_put_sync(mcasp->dev); | |
406 | return ret; | |
b67f4487 C |
407 | } |
408 | ||
8813543e JS |
409 | static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
410 | int div, bool explicit) | |
4ed8c9b7 | 411 | { |
70091a3e | 412 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
413 | |
414 | switch (div_id) { | |
415 | case 0: /* MCLK divider */ | |
f68205a7 | 416 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 417 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 418 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
419 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
420 | break; | |
421 | ||
422 | case 1: /* BCLK divider */ | |
f68205a7 | 423 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 424 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 425 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 426 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
427 | if (explicit) |
428 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
429 | break; |
430 | ||
1b3bc060 | 431 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 432 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
433 | break; |
434 | ||
4ed8c9b7 DM |
435 | default: |
436 | return -EINVAL; | |
437 | } | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
8813543e JS |
442 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
443 | int div) | |
444 | { | |
445 | return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1); | |
446 | } | |
447 | ||
5b66aa2d DM |
448 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
449 | unsigned int freq, int dir) | |
450 | { | |
70091a3e | 451 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
452 | |
453 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
454 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
455 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
456 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 457 | } else { |
f68205a7 PU |
458 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
459 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
460 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
461 | } |
462 | ||
ab8b14b6 JS |
463 | mcasp->sysclk_freq = freq; |
464 | ||
5b66aa2d DM |
465 | return 0; |
466 | } | |
467 | ||
70091a3e | 468 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 469 | int word_length) |
b67f4487 | 470 | { |
ba764b3d | 471 | u32 fmt; |
79671892 | 472 | u32 tx_rotate = (word_length / 4) & 0x7; |
ba764b3d | 473 | u32 mask = (1ULL << word_length) - 1; |
fe0a29e1 PU |
474 | /* |
475 | * For captured data we should not rotate, inversion and masking is | |
476 | * enoguh to get the data to the right position: | |
477 | * Format data from bus after reverse (XRBUF) | |
478 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
479 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
480 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
481 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
482 | */ | |
483 | u32 rx_rotate = 0; | |
b67f4487 | 484 | |
1b3bc060 DM |
485 | /* |
486 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
487 | * callback, take it into account here. That allows us to for example | |
488 | * send 32 bits per channel to the codec, while only 16 of them carry | |
489 | * audio payload. | |
d486fea6 MB |
490 | * The clock ratio is given for a full period of data (for I2S format |
491 | * both left and right channels), so it has to be divided by number of | |
492 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 493 | */ |
70091a3e PU |
494 | if (mcasp->bclk_lrclk_ratio) |
495 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
1b3bc060 | 496 | |
ba764b3d DM |
497 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
498 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 499 | |
70091a3e | 500 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
501 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
502 | RXSSZ(0x0F)); | |
503 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
504 | TXSSZ(0x0F)); | |
505 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
506 | TXROT(7)); | |
507 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
508 | RXROT(7)); | |
509 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
510 | } |
511 | ||
f68205a7 | 512 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 513 | |
b67f4487 C |
514 | return 0; |
515 | } | |
516 | ||
662ffae9 | 517 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 518 | int period_words, int channels) |
b67f4487 | 519 | { |
5f04c603 PU |
520 | struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream]; |
521 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; | |
b67f4487 | 522 | int i; |
6a99fb5f C |
523 | u8 tx_ser = 0; |
524 | u8 rx_ser = 0; | |
70091a3e | 525 | u8 slots = mcasp->tdm_slots; |
2952b27e | 526 | u8 max_active_serializers = (channels + slots - 1) / slots; |
dd093a0f | 527 | int active_serializers, numevt, n; |
487dce88 | 528 | u32 reg; |
b67f4487 | 529 | /* Default configuration */ |
40448e5e | 530 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 531 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
532 | |
533 | /* All PINS as McASP */ | |
f68205a7 | 534 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
535 | |
536 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
537 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
538 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 539 | } else { |
f68205a7 PU |
540 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
541 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
542 | } |
543 | ||
70091a3e | 544 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
545 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
546 | mcasp->serial_dir[i]); | |
70091a3e | 547 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 548 | tx_ser < max_active_serializers) { |
f68205a7 | 549 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 550 | tx_ser++; |
70091a3e | 551 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 552 | rx_ser < max_active_serializers) { |
f68205a7 | 553 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 554 | rx_ser++; |
2952b27e | 555 | } else { |
f68205a7 PU |
556 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
557 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
558 | } |
559 | } | |
560 | ||
0bf0e8ae PU |
561 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
562 | active_serializers = tx_ser; | |
563 | numevt = mcasp->txnumevt; | |
564 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
565 | } else { | |
566 | active_serializers = rx_ser; | |
567 | numevt = mcasp->rxnumevt; | |
568 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
569 | } | |
ecf327c7 | 570 | |
0bf0e8ae | 571 | if (active_serializers < max_active_serializers) { |
70091a3e | 572 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
573 | "enabled in mcasp (%d)\n", channels, |
574 | active_serializers * slots); | |
ecf327c7 DM |
575 | return -EINVAL; |
576 | } | |
577 | ||
0bf0e8ae | 578 | /* AFIFO is not in use */ |
5f04c603 PU |
579 | if (!numevt) { |
580 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
581 | if (active_serializers > 1) { |
582 | /* | |
583 | * If more than one serializers are in use we have one | |
584 | * DMA request to provide data for all serializers. | |
585 | * For example if three serializers are enabled the DMA | |
586 | * need to transfer three words per DMA request. | |
587 | */ | |
588 | dma_params->fifo_level = active_serializers; | |
589 | dma_data->maxburst = active_serializers; | |
590 | } else { | |
591 | dma_params->fifo_level = 0; | |
592 | dma_data->maxburst = 0; | |
593 | } | |
0bf0e8ae | 594 | return 0; |
5f04c603 | 595 | } |
6a99fb5f | 596 | |
dd093a0f PU |
597 | if (period_words % active_serializers) { |
598 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
599 | "active serializers: %d, %d\n", period_words, | |
600 | active_serializers); | |
601 | return -EINVAL; | |
602 | } | |
603 | ||
604 | /* | |
605 | * Calculate the optimal AFIFO depth for platform side: | |
606 | * The number of words for numevt need to be in steps of active | |
607 | * serializers. | |
608 | */ | |
609 | n = numevt % active_serializers; | |
610 | if (n) | |
611 | numevt += (active_serializers - n); | |
612 | while (period_words % numevt && numevt > 0) | |
613 | numevt -= active_serializers; | |
614 | if (numevt <= 0) | |
0bf0e8ae | 615 | numevt = active_serializers; |
487dce88 | 616 | |
0bf0e8ae PU |
617 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
618 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 619 | |
5f04c603 | 620 | /* Configure the burst size for platform drivers */ |
33445643 PU |
621 | if (numevt == 1) |
622 | numevt = 0; | |
5f04c603 PU |
623 | dma_params->fifo_level = numevt; |
624 | dma_data->maxburst = numevt; | |
625 | ||
2952b27e | 626 | return 0; |
b67f4487 C |
627 | } |
628 | ||
2c56c4c2 | 629 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
b67f4487 C |
630 | { |
631 | int i, active_slots; | |
632 | u32 mask = 0; | |
cbc7956c | 633 | u32 busel = 0; |
b67f4487 | 634 | |
1a5923da | 635 | active_slots = mcasp->tdm_slots; |
b67f4487 C |
636 | for (i = 0; i < active_slots; i++) |
637 | mask |= (1 << i); | |
638 | ||
f68205a7 | 639 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 640 | |
cbc7956c PU |
641 | if (!mcasp->dat_port) |
642 | busel = TXSEL; | |
643 | ||
2c56c4c2 PU |
644 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
645 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
646 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
1a5923da | 647 | FSXMOD(active_slots), FSXMOD(0x1FF)); |
2c56c4c2 PU |
648 | |
649 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
650 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
651 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
1a5923da | 652 | FSRMOD(active_slots), FSRMOD(0x1FF)); |
2c56c4c2 PU |
653 | |
654 | return 0; | |
b67f4487 C |
655 | } |
656 | ||
657 | /* S/PDIF */ | |
6479285d DM |
658 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
659 | unsigned int rate) | |
b67f4487 | 660 | { |
6479285d DM |
661 | u32 cs_value = 0; |
662 | u8 *cs_bytes = (u8*) &cs_value; | |
663 | ||
b67f4487 C |
664 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
665 | and LSB first */ | |
f68205a7 | 666 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
667 | |
668 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 669 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
670 | |
671 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 672 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
673 | |
674 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 675 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 676 | |
f68205a7 | 677 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
678 | |
679 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 680 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
681 | |
682 | /* Enable the DIT */ | |
f68205a7 | 683 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 684 | |
6479285d DM |
685 | /* Set S/PDIF channel status bits */ |
686 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
687 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
688 | ||
689 | switch (rate) { | |
690 | case 22050: | |
691 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
692 | break; | |
693 | case 24000: | |
694 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
695 | break; | |
696 | case 32000: | |
697 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
698 | break; | |
699 | case 44100: | |
700 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
701 | break; | |
702 | case 48000: | |
703 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
704 | break; | |
705 | case 88200: | |
706 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
707 | break; | |
708 | case 96000: | |
709 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
710 | break; | |
711 | case 176400: | |
712 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
713 | break; | |
714 | case 192000: | |
715 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
716 | break; | |
717 | default: | |
718 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
719 | return -EINVAL; | |
720 | } | |
721 | ||
722 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
723 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
724 | ||
2c56c4c2 | 725 | return 0; |
b67f4487 C |
726 | } |
727 | ||
728 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
729 | struct snd_pcm_hw_params *params, | |
730 | struct snd_soc_dai *cpu_dai) | |
731 | { | |
70091a3e | 732 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 733 | struct davinci_pcm_dma_params *dma_params = |
70091a3e | 734 | &mcasp->dma_params[substream->stream]; |
b67f4487 | 735 | int word_length; |
a7e46bd9 | 736 | int channels = params_channels(params); |
dd093a0f | 737 | int period_size = params_period_size(params); |
2c56c4c2 | 738 | int ret; |
ab8b14b6 | 739 | |
8267525c DM |
740 | /* |
741 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
742 | * the machine driver, we need to calculate the ratio. | |
743 | */ | |
744 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
ab8b14b6 | 745 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); |
0929878f | 746 | unsigned int div = mcasp->sysclk_freq / bclk_freq; |
ab8b14b6 | 747 | if (mcasp->sysclk_freq % bclk_freq != 0) { |
0929878f JS |
748 | if (((mcasp->sysclk_freq / div) - bclk_freq) > |
749 | (bclk_freq - (mcasp->sysclk_freq / (div+1)))) | |
750 | div++; | |
751 | dev_warn(mcasp->dev, | |
752 | "Inaccurate BCLK: %u Hz / %u != %u Hz\n", | |
753 | mcasp->sysclk_freq, div, bclk_freq); | |
ab8b14b6 | 754 | } |
8813543e | 755 | __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0); |
ab8b14b6 JS |
756 | } |
757 | ||
dd093a0f PU |
758 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
759 | period_size * channels, channels); | |
0f7d9a63 PU |
760 | if (ret) |
761 | return ret; | |
762 | ||
70091a3e | 763 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 764 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 765 | else |
2c56c4c2 PU |
766 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
767 | ||
768 | if (ret) | |
769 | return ret; | |
b67f4487 C |
770 | |
771 | switch (params_format(params)) { | |
0a9d1385 | 772 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
773 | case SNDRV_PCM_FORMAT_S8: |
774 | dma_params->data_type = 1; | |
ba764b3d | 775 | word_length = 8; |
b67f4487 C |
776 | break; |
777 | ||
0a9d1385 | 778 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
779 | case SNDRV_PCM_FORMAT_S16_LE: |
780 | dma_params->data_type = 2; | |
ba764b3d | 781 | word_length = 16; |
b67f4487 C |
782 | break; |
783 | ||
21eb24d8 DM |
784 | case SNDRV_PCM_FORMAT_U24_3LE: |
785 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 786 | dma_params->data_type = 3; |
ba764b3d | 787 | word_length = 24; |
21eb24d8 DM |
788 | break; |
789 | ||
6b7fa011 DM |
790 | case SNDRV_PCM_FORMAT_U24_LE: |
791 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
792 | dma_params->data_type = 4; |
793 | word_length = 24; | |
794 | break; | |
795 | ||
0a9d1385 | 796 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
797 | case SNDRV_PCM_FORMAT_S32_LE: |
798 | dma_params->data_type = 4; | |
ba764b3d | 799 | word_length = 32; |
b67f4487 C |
800 | break; |
801 | ||
802 | default: | |
803 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
804 | return -EINVAL; | |
805 | } | |
6a99fb5f | 806 | |
5f04c603 | 807 | if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level) |
4fa9c1a5 C |
808 | dma_params->acnt = 4; |
809 | else | |
6a99fb5f C |
810 | dma_params->acnt = dma_params->data_type; |
811 | ||
70091a3e | 812 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 C |
813 | |
814 | return 0; | |
815 | } | |
816 | ||
817 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
818 | int cmd, struct snd_soc_dai *cpu_dai) | |
819 | { | |
70091a3e | 820 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
821 | int ret = 0; |
822 | ||
823 | switch (cmd) { | |
b67f4487 | 824 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
825 | case SNDRV_PCM_TRIGGER_START: |
826 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 827 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 828 | break; |
b67f4487 | 829 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 830 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 831 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 832 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
833 | break; |
834 | ||
835 | default: | |
836 | ret = -EINVAL; | |
837 | } | |
838 | ||
839 | return ret; | |
840 | } | |
841 | ||
85e7652d | 842 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
b67f4487 C |
843 | .trigger = davinci_mcasp_trigger, |
844 | .hw_params = davinci_mcasp_hw_params, | |
845 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 846 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 847 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
848 | }; |
849 | ||
d5902f69 PU |
850 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
851 | { | |
852 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
853 | ||
f3f9cfa8 | 854 | if (mcasp->version >= MCASP_VERSION_3) { |
d5902f69 PU |
855 | /* Using dmaengine PCM */ |
856 | dai->playback_dma_data = | |
857 | &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; | |
858 | dai->capture_dma_data = | |
859 | &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
860 | } else { | |
861 | /* Using davinci-pcm */ | |
862 | dai->playback_dma_data = mcasp->dma_params; | |
863 | dai->capture_dma_data = mcasp->dma_params; | |
864 | } | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
135014ad PU |
869 | #ifdef CONFIG_PM_SLEEP |
870 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
871 | { | |
872 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 873 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 874 | u32 reg; |
1cc0c054 | 875 | int i; |
135014ad | 876 | |
1cc0c054 PU |
877 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
878 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 879 | |
f114ce60 PU |
880 | if (mcasp->txnumevt) { |
881 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
882 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
883 | } | |
884 | if (mcasp->rxnumevt) { | |
885 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
886 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
887 | } | |
135014ad | 888 | |
f114ce60 PU |
889 | for (i = 0; i < mcasp->num_serializer; i++) |
890 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
891 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad PU |
892 | |
893 | return 0; | |
894 | } | |
895 | ||
896 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
897 | { | |
898 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 899 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 900 | u32 reg; |
1cc0c054 | 901 | int i; |
790bb94b | 902 | |
1cc0c054 PU |
903 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
904 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 905 | |
f114ce60 PU |
906 | if (mcasp->txnumevt) { |
907 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
908 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
909 | } | |
910 | if (mcasp->rxnumevt) { | |
911 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
912 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
913 | } | |
790bb94b | 914 | |
f114ce60 PU |
915 | for (i = 0; i < mcasp->num_serializer; i++) |
916 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
917 | context->xrsr_regs[i]); | |
135014ad PU |
918 | |
919 | return 0; | |
920 | } | |
921 | #else | |
922 | #define davinci_mcasp_suspend NULL | |
923 | #define davinci_mcasp_resume NULL | |
924 | #endif | |
925 | ||
ed29cd5e PU |
926 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
927 | ||
0a9d1385 BG |
928 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
929 | SNDRV_PCM_FMTBIT_U8 | \ | |
930 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
931 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
932 | SNDRV_PCM_FMTBIT_S24_LE | \ |
933 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
934 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
935 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
936 | SNDRV_PCM_FMTBIT_S32_LE | \ |
937 | SNDRV_PCM_FMTBIT_U32_LE) | |
938 | ||
f0fba2ad | 939 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 940 | { |
f0fba2ad | 941 | .name = "davinci-mcasp.0", |
d5902f69 | 942 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
943 | .suspend = davinci_mcasp_suspend, |
944 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
945 | .playback = { |
946 | .channels_min = 2, | |
2952b27e | 947 | .channels_max = 32 * 16, |
b67f4487 | 948 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 949 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
950 | }, |
951 | .capture = { | |
952 | .channels_min = 2, | |
2952b27e | 953 | .channels_max = 32 * 16, |
b67f4487 | 954 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 955 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
956 | }, |
957 | .ops = &davinci_mcasp_dai_ops, | |
958 | ||
959 | }, | |
960 | { | |
58e48d97 | 961 | .name = "davinci-mcasp.1", |
d5902f69 | 962 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
963 | .playback = { |
964 | .channels_min = 1, | |
965 | .channels_max = 384, | |
966 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 967 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
968 | }, |
969 | .ops = &davinci_mcasp_dai_ops, | |
970 | }, | |
971 | ||
972 | }; | |
b67f4487 | 973 | |
eeef0eda KM |
974 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
975 | .name = "davinci-mcasp", | |
976 | }; | |
977 | ||
256ba181 | 978 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 979 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
980 | .tx_dma_offset = 0x400, |
981 | .rx_dma_offset = 0x400, | |
982 | .asp_chan_q = EVENTQ_0, | |
983 | .version = MCASP_VERSION_1, | |
984 | }; | |
985 | ||
d1debafc | 986 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
987 | .tx_dma_offset = 0x2000, |
988 | .rx_dma_offset = 0x2000, | |
989 | .asp_chan_q = EVENTQ_0, | |
990 | .version = MCASP_VERSION_2, | |
991 | }; | |
992 | ||
d1debafc | 993 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
994 | .tx_dma_offset = 0, |
995 | .rx_dma_offset = 0, | |
996 | .asp_chan_q = EVENTQ_0, | |
997 | .version = MCASP_VERSION_3, | |
998 | }; | |
999 | ||
d1debafc | 1000 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
1001 | .tx_dma_offset = 0x200, |
1002 | .rx_dma_offset = 0x284, | |
1003 | .asp_chan_q = EVENTQ_0, | |
1004 | .version = MCASP_VERSION_4, | |
1005 | }; | |
1006 | ||
3e3b8c34 HG |
1007 | static const struct of_device_id mcasp_dt_ids[] = { |
1008 | { | |
1009 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1010 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1011 | }, |
1012 | { | |
1013 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1014 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1015 | }, |
e5ec69da | 1016 | { |
3af9e031 | 1017 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1018 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1019 | }, |
453c4990 PU |
1020 | { |
1021 | .compatible = "ti,dra7-mcasp-audio", | |
1022 | .data = &dra7_mcasp_pdata, | |
1023 | }, | |
3e3b8c34 HG |
1024 | { /* sentinel */ } |
1025 | }; | |
1026 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1027 | ||
ae726e93 PU |
1028 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1029 | { | |
1030 | struct device_node *node = pdev->dev.of_node; | |
1031 | struct clk *gfclk, *parent_clk; | |
1032 | const char *parent_name; | |
1033 | int ret; | |
1034 | ||
1035 | if (!node) | |
1036 | return 0; | |
1037 | ||
1038 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1039 | if (!parent_name) | |
1040 | return 0; | |
1041 | ||
1042 | gfclk = clk_get(&pdev->dev, "fck"); | |
1043 | if (IS_ERR(gfclk)) { | |
1044 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1045 | return PTR_ERR(gfclk); | |
1046 | } | |
1047 | ||
1048 | parent_clk = clk_get(NULL, parent_name); | |
1049 | if (IS_ERR(parent_clk)) { | |
1050 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1051 | ret = PTR_ERR(parent_clk); | |
1052 | goto err1; | |
1053 | } | |
1054 | ||
1055 | ret = clk_set_parent(gfclk, parent_clk); | |
1056 | if (ret) { | |
1057 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1058 | goto err2; | |
1059 | } | |
1060 | ||
1061 | err2: | |
1062 | clk_put(parent_clk); | |
1063 | err1: | |
1064 | clk_put(gfclk); | |
1065 | return ret; | |
1066 | } | |
1067 | ||
d1debafc | 1068 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1069 | struct platform_device *pdev) |
1070 | { | |
1071 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1072 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1073 | const struct of_device_id *match = |
ea421eb1 | 1074 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1075 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1076 | |
1077 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1078 | u32 val; |
1079 | int i, ret = 0; | |
1080 | ||
1081 | if (pdev->dev.platform_data) { | |
1082 | pdata = pdev->dev.platform_data; | |
1083 | return pdata; | |
1084 | } else if (match) { | |
d1debafc | 1085 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1086 | } else { |
1087 | /* control shouldn't reach here. something is wrong */ | |
1088 | ret = -EINVAL; | |
1089 | goto nodata; | |
1090 | } | |
1091 | ||
3e3b8c34 HG |
1092 | ret = of_property_read_u32(np, "op-mode", &val); |
1093 | if (ret >= 0) | |
1094 | pdata->op_mode = val; | |
1095 | ||
1096 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1097 | if (ret >= 0) { |
1098 | if (val < 2 || val > 32) { | |
1099 | dev_err(&pdev->dev, | |
1100 | "tdm-slots must be in rage [2-32]\n"); | |
1101 | ret = -EINVAL; | |
1102 | goto nodata; | |
1103 | } | |
1104 | ||
3e3b8c34 | 1105 | pdata->tdm_slots = val; |
2952b27e | 1106 | } |
3e3b8c34 | 1107 | |
3e3b8c34 HG |
1108 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1109 | val /= sizeof(u32); | |
3e3b8c34 | 1110 | if (of_serial_dir32) { |
1427e660 PU |
1111 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1112 | (sizeof(*of_serial_dir) * val), | |
1113 | GFP_KERNEL); | |
3e3b8c34 HG |
1114 | if (!of_serial_dir) { |
1115 | ret = -ENOMEM; | |
1116 | goto nodata; | |
1117 | } | |
1118 | ||
1427e660 | 1119 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1120 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1121 | ||
1427e660 | 1122 | pdata->num_serializer = val; |
3e3b8c34 HG |
1123 | pdata->serial_dir = of_serial_dir; |
1124 | } | |
1125 | ||
4023fe6f JS |
1126 | ret = of_property_match_string(np, "dma-names", "tx"); |
1127 | if (ret < 0) | |
1128 | goto nodata; | |
1129 | ||
1130 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1131 | &dma_spec); | |
1132 | if (ret < 0) | |
1133 | goto nodata; | |
1134 | ||
1135 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1136 | ||
1137 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1138 | if (ret < 0) | |
1139 | goto nodata; | |
1140 | ||
1141 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1142 | &dma_spec); | |
1143 | if (ret < 0) | |
1144 | goto nodata; | |
1145 | ||
1146 | pdata->rx_dma_channel = dma_spec.args[0]; | |
1147 | ||
3e3b8c34 HG |
1148 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1149 | if (ret >= 0) | |
1150 | pdata->txnumevt = val; | |
1151 | ||
1152 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1153 | if (ret >= 0) | |
1154 | pdata->rxnumevt = val; | |
1155 | ||
1156 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1157 | if (ret >= 0) | |
1158 | pdata->sram_size_playback = val; | |
1159 | ||
1160 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1161 | if (ret >= 0) | |
1162 | pdata->sram_size_capture = val; | |
1163 | ||
1164 | return pdata; | |
1165 | ||
1166 | nodata: | |
1167 | if (ret < 0) { | |
1168 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1169 | ret); | |
1170 | pdata = NULL; | |
1171 | } | |
1172 | return pdata; | |
1173 | } | |
1174 | ||
b67f4487 C |
1175 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1176 | { | |
64ebdec3 | 1177 | struct davinci_pcm_dma_params *dma_params; |
8de131f2 | 1178 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1179 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1180 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1181 | struct davinci_mcasp *mcasp; |
96d31e2b | 1182 | int ret; |
b67f4487 | 1183 | |
3e3b8c34 HG |
1184 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1185 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1186 | return -EINVAL; | |
1187 | } | |
1188 | ||
70091a3e | 1189 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1190 | GFP_KERNEL); |
70091a3e | 1191 | if (!mcasp) |
b67f4487 C |
1192 | return -ENOMEM; |
1193 | ||
3e3b8c34 HG |
1194 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1195 | if (!pdata) { | |
1196 | dev_err(&pdev->dev, "no platform data\n"); | |
1197 | return -EINVAL; | |
1198 | } | |
1199 | ||
256ba181 | 1200 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1201 | if (!mem) { |
70091a3e | 1202 | dev_warn(mcasp->dev, |
256ba181 JS |
1203 | "\"mpu\" mem resource not found, using index 0\n"); |
1204 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1205 | if (!mem) { | |
1206 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1207 | return -ENODEV; | |
1208 | } | |
b67f4487 C |
1209 | } |
1210 | ||
96d31e2b | 1211 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1212 | resource_size(mem), pdev->name); |
b67f4487 C |
1213 | if (!ioarea) { |
1214 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1215 | return -EBUSY; |
b67f4487 C |
1216 | } |
1217 | ||
10884347 | 1218 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1219 | |
10884347 HG |
1220 | ret = pm_runtime_get_sync(&pdev->dev); |
1221 | if (IS_ERR_VALUE(ret)) { | |
1222 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
1223 | return ret; | |
1224 | } | |
b67f4487 | 1225 | |
70091a3e PU |
1226 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1227 | if (!mcasp->base) { | |
4f82f028 VB |
1228 | dev_err(&pdev->dev, "ioremap failed\n"); |
1229 | ret = -ENOMEM; | |
b6bb3709 | 1230 | goto err; |
4f82f028 VB |
1231 | } |
1232 | ||
70091a3e | 1233 | mcasp->op_mode = pdata->op_mode; |
1a5923da PU |
1234 | /* sanity check for tdm slots parameter */ |
1235 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { | |
1236 | if (pdata->tdm_slots < 2) { | |
1237 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1238 | pdata->tdm_slots); | |
1239 | mcasp->tdm_slots = 2; | |
1240 | } else if (pdata->tdm_slots > 32) { | |
1241 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1242 | pdata->tdm_slots); | |
1243 | mcasp->tdm_slots = 32; | |
1244 | } else { | |
1245 | mcasp->tdm_slots = pdata->tdm_slots; | |
1246 | } | |
1247 | } | |
1248 | ||
70091a3e | 1249 | mcasp->num_serializer = pdata->num_serializer; |
f114ce60 PU |
1250 | #ifdef CONFIG_PM_SLEEP |
1251 | mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, | |
1252 | sizeof(u32) * mcasp->num_serializer, | |
1253 | GFP_KERNEL); | |
1254 | #endif | |
70091a3e PU |
1255 | mcasp->serial_dir = pdata->serial_dir; |
1256 | mcasp->version = pdata->version; | |
1257 | mcasp->txnumevt = pdata->txnumevt; | |
1258 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1259 | |
70091a3e | 1260 | mcasp->dev = &pdev->dev; |
b67f4487 | 1261 | |
256ba181 | 1262 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1263 | if (dat) |
1264 | mcasp->dat_port = true; | |
256ba181 | 1265 | |
64ebdec3 | 1266 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
8de131f2 | 1267 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
64ebdec3 PU |
1268 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1269 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1270 | dma_params->sram_pool = pdata->sram_pool; | |
1271 | dma_params->sram_size = pdata->sram_size_playback; | |
cbc7956c | 1272 | if (dat) |
64ebdec3 | 1273 | dma_params->dma_addr = dat->start; |
cbc7956c | 1274 | else |
64ebdec3 | 1275 | dma_params->dma_addr = mem->start + pdata->tx_dma_offset; |
b67f4487 | 1276 | |
453c4990 | 1277 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1278 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1279 | |
b67f4487 | 1280 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1281 | if (res) |
64ebdec3 | 1282 | dma_params->channel = res->start; |
4023fe6f | 1283 | else |
64ebdec3 | 1284 | dma_params->channel = pdata->tx_dma_channel; |
92e2a6f6 | 1285 | |
8de131f2 PU |
1286 | /* dmaengine filter data for DT and non-DT boot */ |
1287 | if (pdev->dev.of_node) | |
1288 | dma_data->filter_data = "tx"; | |
1289 | else | |
1290 | dma_data->filter_data = &dma_params->channel; | |
1291 | ||
64ebdec3 | 1292 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
8de131f2 | 1293 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
64ebdec3 PU |
1294 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1295 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1296 | dma_params->sram_pool = pdata->sram_pool; | |
1297 | dma_params->sram_size = pdata->sram_size_capture; | |
cbc7956c | 1298 | if (dat) |
64ebdec3 | 1299 | dma_params->dma_addr = dat->start; |
cbc7956c | 1300 | else |
64ebdec3 | 1301 | dma_params->dma_addr = mem->start + pdata->rx_dma_offset; |
cbc7956c | 1302 | |
453c4990 | 1303 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1304 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1305 | |
cbc7956c PU |
1306 | if (mcasp->version < MCASP_VERSION_3) { |
1307 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1308 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1309 | mcasp->dat_port = true; |
1310 | } else { | |
1311 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1312 | } | |
b67f4487 C |
1313 | |
1314 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
4023fe6f | 1315 | if (res) |
64ebdec3 | 1316 | dma_params->channel = res->start; |
4023fe6f | 1317 | else |
64ebdec3 | 1318 | dma_params->channel = pdata->rx_dma_channel; |
b67f4487 | 1319 | |
8de131f2 PU |
1320 | /* dmaengine filter data for DT and non-DT boot */ |
1321 | if (pdev->dev.of_node) | |
1322 | dma_data->filter_data = "rx"; | |
1323 | else | |
1324 | dma_data->filter_data = &dma_params->channel; | |
453c4990 | 1325 | |
70091a3e | 1326 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1327 | |
1328 | mcasp_reparent_fck(pdev); | |
1329 | ||
b6bb3709 PU |
1330 | ret = devm_snd_soc_register_component(&pdev->dev, |
1331 | &davinci_mcasp_component, | |
1332 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1333 | |
1334 | if (ret != 0) | |
b6bb3709 | 1335 | goto err; |
f08095a4 | 1336 | |
d5c6c59a | 1337 | switch (mcasp->version) { |
7f28f357 JS |
1338 | #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \ |
1339 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1340 | IS_MODULE(CONFIG_SND_DAVINCI_SOC)) | |
d5c6c59a PU |
1341 | case MCASP_VERSION_1: |
1342 | case MCASP_VERSION_2: | |
453c4990 | 1343 | ret = davinci_soc_platform_register(&pdev->dev); |
d5c6c59a | 1344 | break; |
7f28f357 | 1345 | #endif |
f3f9cfa8 PU |
1346 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1347 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1348 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
1349 | case MCASP_VERSION_3: | |
1350 | ret = edma_pcm_platform_register(&pdev->dev); | |
1351 | break; | |
1352 | #endif | |
7f28f357 JS |
1353 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
1354 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1355 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a PU |
1356 | case MCASP_VERSION_4: |
1357 | ret = omap_pcm_platform_register(&pdev->dev); | |
1358 | break; | |
7f28f357 | 1359 | #endif |
d5c6c59a PU |
1360 | default: |
1361 | dev_err(&pdev->dev, "Invalid McASP version: %d\n", | |
1362 | mcasp->version); | |
1363 | ret = -EINVAL; | |
1364 | break; | |
1365 | } | |
1366 | ||
1367 | if (ret) { | |
1368 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 1369 | goto err; |
f08095a4 HG |
1370 | } |
1371 | ||
b67f4487 C |
1372 | return 0; |
1373 | ||
b6bb3709 | 1374 | err: |
10884347 HG |
1375 | pm_runtime_put_sync(&pdev->dev); |
1376 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1377 | return ret; |
1378 | } | |
1379 | ||
1380 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1381 | { | |
10884347 HG |
1382 | pm_runtime_put_sync(&pdev->dev); |
1383 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1384 | |
b67f4487 C |
1385 | return 0; |
1386 | } | |
1387 | ||
1388 | static struct platform_driver davinci_mcasp_driver = { | |
1389 | .probe = davinci_mcasp_probe, | |
1390 | .remove = davinci_mcasp_remove, | |
1391 | .driver = { | |
1392 | .name = "davinci-mcasp", | |
1393 | .owner = THIS_MODULE, | |
ea421eb1 | 1394 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1395 | }, |
1396 | }; | |
1397 | ||
f9b8a514 | 1398 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1399 | |
1400 | MODULE_AUTHOR("Steve Chen"); | |
1401 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1402 | MODULE_LICENSE("GPL"); |