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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
b67f4487 | 29 | |
6479285d | 30 | #include <sound/asoundef.h> |
b67f4487 C |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/initval.h> | |
35 | #include <sound/soc.h> | |
453c4990 | 36 | #include <sound/dmaengine_pcm.h> |
87c19364 | 37 | #include <sound/omap-pcm.h> |
b67f4487 C |
38 | |
39 | #include "davinci-pcm.h" | |
f3f9cfa8 | 40 | #include "edma-pcm.h" |
b67f4487 C |
41 | #include "davinci-mcasp.h" |
42 | ||
0bf0e8ae PU |
43 | #define MCASP_MAX_AFIFO_DEPTH 64 |
44 | ||
1cc0c054 PU |
45 | static u32 context_regs[] = { |
46 | DAVINCI_MCASP_TXFMCTL_REG, | |
47 | DAVINCI_MCASP_RXFMCTL_REG, | |
48 | DAVINCI_MCASP_TXFMT_REG, | |
49 | DAVINCI_MCASP_RXFMT_REG, | |
50 | DAVINCI_MCASP_ACLKXCTL_REG, | |
51 | DAVINCI_MCASP_ACLKRCTL_REG, | |
52 | DAVINCI_MCASP_PDIR_REG, | |
53 | }; | |
54 | ||
790bb94b | 55 | struct davinci_mcasp_context { |
1cc0c054 | 56 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
790bb94b PU |
57 | }; |
58 | ||
70091a3e | 59 | struct davinci_mcasp { |
21400a72 | 60 | struct davinci_pcm_dma_params dma_params[2]; |
453c4990 | 61 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 62 | void __iomem *base; |
487dce88 | 63 | u32 fifo_base; |
21400a72 PU |
64 | struct device *dev; |
65 | ||
66 | /* McASP specific data */ | |
67 | int tdm_slots; | |
68 | u8 op_mode; | |
69 | u8 num_serializer; | |
70 | u8 *serial_dir; | |
71 | u8 version; | |
8267525c | 72 | u8 bclk_div; |
21400a72 | 73 | u16 bclk_lrclk_ratio; |
4dcb5a0b | 74 | int streams; |
21400a72 | 75 | |
ab8b14b6 JS |
76 | int sysclk_freq; |
77 | bool bclk_master; | |
78 | ||
21400a72 PU |
79 | /* McASP FIFO related */ |
80 | u8 txnumevt; | |
81 | u8 rxnumevt; | |
82 | ||
cbc7956c PU |
83 | bool dat_port; |
84 | ||
21400a72 | 85 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 86 | struct davinci_mcasp_context context; |
21400a72 PU |
87 | #endif |
88 | }; | |
89 | ||
f68205a7 PU |
90 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
91 | u32 val) | |
b67f4487 | 92 | { |
f68205a7 | 93 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
94 | __raw_writel(__raw_readl(reg) | val, reg); |
95 | } | |
96 | ||
f68205a7 PU |
97 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
98 | u32 val) | |
b67f4487 | 99 | { |
f68205a7 | 100 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
101 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
102 | } | |
103 | ||
f68205a7 PU |
104 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
105 | u32 val, u32 mask) | |
b67f4487 | 106 | { |
f68205a7 | 107 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
108 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
109 | } | |
110 | ||
f68205a7 PU |
111 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
112 | u32 val) | |
b67f4487 | 113 | { |
f68205a7 | 114 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
115 | } |
116 | ||
f68205a7 | 117 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 118 | { |
f68205a7 | 119 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
120 | } |
121 | ||
f68205a7 | 122 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
123 | { |
124 | int i = 0; | |
125 | ||
f68205a7 | 126 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
127 | |
128 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
129 | /* loop count is to avoid the lock-up */ | |
130 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 131 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
132 | break; |
133 | } | |
134 | ||
f68205a7 | 135 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
136 | printk(KERN_ERR "GBLCTL write error\n"); |
137 | } | |
138 | ||
4dcb5a0b PU |
139 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
140 | { | |
f68205a7 PU |
141 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
142 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
143 | |
144 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
145 | } | |
146 | ||
70091a3e | 147 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 148 | { |
f68205a7 PU |
149 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
150 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
151 | |
152 | /* | |
153 | * When ASYNC == 0 the transmit and receive sections operate | |
154 | * synchronously from the transmit clock and frame sync. We need to make | |
155 | * sure that the TX signlas are enabled when starting reception. | |
156 | */ | |
157 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
158 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
159 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
160 | } |
161 | ||
f68205a7 PU |
162 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
163 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); | |
b67f4487 | 164 | |
f68205a7 PU |
165 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
166 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
167 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); | |
b67f4487 | 168 | |
f68205a7 PU |
169 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
170 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
4dcb5a0b PU |
171 | |
172 | if (mcasp_is_synchronous(mcasp)) | |
f68205a7 | 173 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
b67f4487 C |
174 | } |
175 | ||
70091a3e | 176 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 177 | { |
6a99fb5f C |
178 | u8 offset = 0, i; |
179 | u32 cnt; | |
180 | ||
f68205a7 PU |
181 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
182 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
183 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); | |
184 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); | |
b67f4487 | 185 | |
f68205a7 PU |
186 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); |
187 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
188 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); | |
70091a3e PU |
189 | for (i = 0; i < mcasp->num_serializer; i++) { |
190 | if (mcasp->serial_dir[i] == TX_MODE) { | |
6a99fb5f C |
191 | offset = i; |
192 | break; | |
193 | } | |
194 | } | |
195 | ||
196 | /* wait for TX ready */ | |
197 | cnt = 0; | |
f68205a7 | 198 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) & |
6a99fb5f C |
199 | TXSTATE) && (cnt < 100000)) |
200 | cnt++; | |
201 | ||
f68205a7 | 202 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
b67f4487 C |
203 | } |
204 | ||
70091a3e | 205 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 206 | { |
487dce88 PU |
207 | u32 reg; |
208 | ||
4dcb5a0b PU |
209 | mcasp->streams++; |
210 | ||
539d3d8c | 211 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 212 | if (mcasp->txnumevt) { /* enable FIFO */ |
487dce88 | 213 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 PU |
214 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
215 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 216 | } |
70091a3e | 217 | mcasp_start_tx(mcasp); |
539d3d8c | 218 | } else { |
70091a3e | 219 | if (mcasp->rxnumevt) { /* enable FIFO */ |
487dce88 | 220 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 PU |
221 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
222 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 223 | } |
70091a3e | 224 | mcasp_start_rx(mcasp); |
539d3d8c | 225 | } |
b67f4487 C |
226 | } |
227 | ||
70091a3e | 228 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 229 | { |
4dcb5a0b PU |
230 | /* |
231 | * In synchronous mode stop the TX clocks if no other stream is | |
232 | * running | |
233 | */ | |
234 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 235 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 236 | |
f68205a7 PU |
237 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
238 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
239 | } |
240 | ||
70091a3e | 241 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 242 | { |
4dcb5a0b PU |
243 | u32 val = 0; |
244 | ||
245 | /* | |
246 | * In synchronous mode keep TX clocks running if the capture stream is | |
247 | * still running. | |
248 | */ | |
249 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
250 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
251 | ||
f68205a7 PU |
252 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
253 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
254 | } |
255 | ||
70091a3e | 256 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 257 | { |
487dce88 PU |
258 | u32 reg; |
259 | ||
4dcb5a0b PU |
260 | mcasp->streams--; |
261 | ||
539d3d8c | 262 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 263 | if (mcasp->txnumevt) { /* disable FIFO */ |
487dce88 | 264 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 | 265 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 266 | } |
70091a3e | 267 | mcasp_stop_tx(mcasp); |
539d3d8c | 268 | } else { |
70091a3e | 269 | if (mcasp->rxnumevt) { /* disable FIFO */ |
487dce88 | 270 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 | 271 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 272 | } |
70091a3e | 273 | mcasp_stop_rx(mcasp); |
539d3d8c | 274 | } |
b67f4487 C |
275 | } |
276 | ||
277 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
278 | unsigned int fmt) | |
279 | { | |
70091a3e | 280 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 281 | int ret = 0; |
6dfa9a4e | 282 | u32 data_delay; |
83f12503 | 283 | bool fs_pol_rising; |
ffd950f7 | 284 | bool inv_fs = false; |
b67f4487 | 285 | |
1d17a04e | 286 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 287 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
288 | case SND_SOC_DAIFMT_DSP_A: |
289 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
290 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
291 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
292 | data_delay = 1; | |
293 | break; | |
5296cf2d DM |
294 | case SND_SOC_DAIFMT_DSP_B: |
295 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
296 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
297 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
298 | /* No delay after FS */ |
299 | data_delay = 0; | |
5296cf2d | 300 | break; |
ffd950f7 | 301 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 302 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
303 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
304 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
305 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
306 | data_delay = 1; | |
ffd950f7 PU |
307 | /* FS need to be inverted */ |
308 | inv_fs = true; | |
5296cf2d | 309 | break; |
423761e0 PU |
310 | case SND_SOC_DAIFMT_LEFT_J: |
311 | /* configure a full-word SYNC pulse (LRCLK) */ | |
312 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
313 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
314 | /* No delay after FS */ | |
315 | data_delay = 0; | |
316 | break; | |
ffd950f7 PU |
317 | default: |
318 | ret = -EINVAL; | |
319 | goto out; | |
5296cf2d DM |
320 | } |
321 | ||
6dfa9a4e PU |
322 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
323 | FSXDLY(3)); | |
324 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
325 | FSRDLY(3)); | |
326 | ||
b67f4487 C |
327 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
328 | case SND_SOC_DAIFMT_CBS_CFS: | |
329 | /* codec is clock and frame slave */ | |
f68205a7 PU |
330 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
331 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 332 | |
f68205a7 PU |
333 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
334 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 335 | |
f68205a7 PU |
336 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
337 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 338 | mcasp->bclk_master = 1; |
b67f4487 | 339 | break; |
517ee6cf C |
340 | case SND_SOC_DAIFMT_CBM_CFS: |
341 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
342 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
343 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 344 | |
f68205a7 PU |
345 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
346 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 347 | |
f68205a7 PU |
348 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
349 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 350 | mcasp->bclk_master = 0; |
517ee6cf | 351 | break; |
b67f4487 C |
352 | case SND_SOC_DAIFMT_CBM_CFM: |
353 | /* codec is clock and frame master */ | |
f68205a7 PU |
354 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
355 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 356 | |
f68205a7 PU |
357 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
358 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 359 | |
f68205a7 PU |
360 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
361 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 362 | mcasp->bclk_master = 0; |
b67f4487 | 363 | break; |
b67f4487 | 364 | default: |
1d17a04e PU |
365 | ret = -EINVAL; |
366 | goto out; | |
b67f4487 C |
367 | } |
368 | ||
369 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
370 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 371 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 372 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 373 | fs_pol_rising = true; |
b67f4487 | 374 | break; |
b67f4487 | 375 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 376 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 377 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 378 | fs_pol_rising = false; |
b67f4487 | 379 | break; |
b67f4487 | 380 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 381 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 382 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 383 | fs_pol_rising = false; |
b67f4487 | 384 | break; |
b67f4487 | 385 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 386 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 387 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 388 | fs_pol_rising = true; |
b67f4487 | 389 | break; |
b67f4487 | 390 | default: |
1d17a04e | 391 | ret = -EINVAL; |
83f12503 PU |
392 | goto out; |
393 | } | |
394 | ||
ffd950f7 PU |
395 | if (inv_fs) |
396 | fs_pol_rising = !fs_pol_rising; | |
397 | ||
83f12503 PU |
398 | if (fs_pol_rising) { |
399 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
400 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
401 | } else { | |
402 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
403 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 404 | } |
1d17a04e PU |
405 | out: |
406 | pm_runtime_put_sync(mcasp->dev); | |
407 | return ret; | |
b67f4487 C |
408 | } |
409 | ||
4ed8c9b7 DM |
410 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) |
411 | { | |
70091a3e | 412 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
413 | |
414 | switch (div_id) { | |
415 | case 0: /* MCLK divider */ | |
f68205a7 | 416 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 417 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 418 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
419 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
420 | break; | |
421 | ||
422 | case 1: /* BCLK divider */ | |
f68205a7 | 423 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 424 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 425 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 426 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8267525c | 427 | mcasp->bclk_div = div; |
4ed8c9b7 DM |
428 | break; |
429 | ||
1b3bc060 | 430 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 431 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
432 | break; |
433 | ||
4ed8c9b7 DM |
434 | default: |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
5b66aa2d DM |
441 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
442 | unsigned int freq, int dir) | |
443 | { | |
70091a3e | 444 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
445 | |
446 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
447 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
448 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
449 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 450 | } else { |
f68205a7 PU |
451 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
452 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
453 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
454 | } |
455 | ||
ab8b14b6 JS |
456 | mcasp->sysclk_freq = freq; |
457 | ||
5b66aa2d DM |
458 | return 0; |
459 | } | |
460 | ||
70091a3e | 461 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 462 | int word_length) |
b67f4487 | 463 | { |
ba764b3d | 464 | u32 fmt; |
79671892 DM |
465 | u32 tx_rotate = (word_length / 4) & 0x7; |
466 | u32 rx_rotate = (32 - word_length) / 4; | |
ba764b3d | 467 | u32 mask = (1ULL << word_length) - 1; |
b67f4487 | 468 | |
1b3bc060 DM |
469 | /* |
470 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
471 | * callback, take it into account here. That allows us to for example | |
472 | * send 32 bits per channel to the codec, while only 16 of them carry | |
473 | * audio payload. | |
d486fea6 MB |
474 | * The clock ratio is given for a full period of data (for I2S format |
475 | * both left and right channels), so it has to be divided by number of | |
476 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 477 | */ |
70091a3e PU |
478 | if (mcasp->bclk_lrclk_ratio) |
479 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
1b3bc060 | 480 | |
ba764b3d DM |
481 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
482 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 483 | |
70091a3e | 484 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
485 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
486 | RXSSZ(0x0F)); | |
487 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
488 | TXSSZ(0x0F)); | |
489 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
490 | TXROT(7)); | |
491 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
492 | RXROT(7)); | |
493 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
494 | } |
495 | ||
f68205a7 | 496 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 497 | |
b67f4487 C |
498 | return 0; |
499 | } | |
500 | ||
662ffae9 | 501 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 502 | int period_words, int channels) |
b67f4487 | 503 | { |
5f04c603 PU |
504 | struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream]; |
505 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; | |
b67f4487 | 506 | int i; |
6a99fb5f C |
507 | u8 tx_ser = 0; |
508 | u8 rx_ser = 0; | |
70091a3e | 509 | u8 slots = mcasp->tdm_slots; |
2952b27e | 510 | u8 max_active_serializers = (channels + slots - 1) / slots; |
dd093a0f | 511 | int active_serializers, numevt, n; |
487dce88 | 512 | u32 reg; |
b67f4487 | 513 | /* Default configuration */ |
40448e5e | 514 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 515 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
516 | |
517 | /* All PINS as McASP */ | |
f68205a7 | 518 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
519 | |
520 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
521 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
522 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 523 | } else { |
f68205a7 PU |
524 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
525 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
526 | } |
527 | ||
70091a3e | 528 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
529 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
530 | mcasp->serial_dir[i]); | |
70091a3e | 531 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 532 | tx_ser < max_active_serializers) { |
f68205a7 | 533 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 534 | tx_ser++; |
70091a3e | 535 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 536 | rx_ser < max_active_serializers) { |
f68205a7 | 537 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 538 | rx_ser++; |
2952b27e | 539 | } else { |
f68205a7 PU |
540 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
541 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
542 | } |
543 | } | |
544 | ||
0bf0e8ae PU |
545 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
546 | active_serializers = tx_ser; | |
547 | numevt = mcasp->txnumevt; | |
548 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
549 | } else { | |
550 | active_serializers = rx_ser; | |
551 | numevt = mcasp->rxnumevt; | |
552 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
553 | } | |
ecf327c7 | 554 | |
0bf0e8ae | 555 | if (active_serializers < max_active_serializers) { |
70091a3e | 556 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
557 | "enabled in mcasp (%d)\n", channels, |
558 | active_serializers * slots); | |
ecf327c7 DM |
559 | return -EINVAL; |
560 | } | |
561 | ||
0bf0e8ae | 562 | /* AFIFO is not in use */ |
5f04c603 PU |
563 | if (!numevt) { |
564 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
565 | if (active_serializers > 1) { |
566 | /* | |
567 | * If more than one serializers are in use we have one | |
568 | * DMA request to provide data for all serializers. | |
569 | * For example if three serializers are enabled the DMA | |
570 | * need to transfer three words per DMA request. | |
571 | */ | |
572 | dma_params->fifo_level = active_serializers; | |
573 | dma_data->maxburst = active_serializers; | |
574 | } else { | |
575 | dma_params->fifo_level = 0; | |
576 | dma_data->maxburst = 0; | |
577 | } | |
0bf0e8ae | 578 | return 0; |
5f04c603 | 579 | } |
6a99fb5f | 580 | |
dd093a0f PU |
581 | if (period_words % active_serializers) { |
582 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
583 | "active serializers: %d, %d\n", period_words, | |
584 | active_serializers); | |
585 | return -EINVAL; | |
586 | } | |
587 | ||
588 | /* | |
589 | * Calculate the optimal AFIFO depth for platform side: | |
590 | * The number of words for numevt need to be in steps of active | |
591 | * serializers. | |
592 | */ | |
593 | n = numevt % active_serializers; | |
594 | if (n) | |
595 | numevt += (active_serializers - n); | |
596 | while (period_words % numevt && numevt > 0) | |
597 | numevt -= active_serializers; | |
598 | if (numevt <= 0) | |
0bf0e8ae | 599 | numevt = active_serializers; |
487dce88 | 600 | |
0bf0e8ae PU |
601 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
602 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 603 | |
5f04c603 | 604 | /* Configure the burst size for platform drivers */ |
33445643 PU |
605 | if (numevt == 1) |
606 | numevt = 0; | |
5f04c603 PU |
607 | dma_params->fifo_level = numevt; |
608 | dma_data->maxburst = numevt; | |
609 | ||
2952b27e | 610 | return 0; |
b67f4487 C |
611 | } |
612 | ||
2c56c4c2 | 613 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
b67f4487 C |
614 | { |
615 | int i, active_slots; | |
616 | u32 mask = 0; | |
cbc7956c | 617 | u32 busel = 0; |
b67f4487 | 618 | |
2c56c4c2 PU |
619 | if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) { |
620 | dev_err(mcasp->dev, "tdm slot %d not supported\n", | |
621 | mcasp->tdm_slots); | |
622 | return -EINVAL; | |
623 | } | |
624 | ||
70091a3e | 625 | active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; |
b67f4487 C |
626 | for (i = 0; i < active_slots; i++) |
627 | mask |= (1 << i); | |
628 | ||
f68205a7 | 629 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 630 | |
cbc7956c PU |
631 | if (!mcasp->dat_port) |
632 | busel = TXSEL; | |
633 | ||
2c56c4c2 PU |
634 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
635 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
636 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
637 | FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); | |
638 | ||
639 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
640 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
641 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
642 | FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); | |
643 | ||
644 | return 0; | |
b67f4487 C |
645 | } |
646 | ||
647 | /* S/PDIF */ | |
6479285d DM |
648 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
649 | unsigned int rate) | |
b67f4487 | 650 | { |
6479285d DM |
651 | u32 cs_value = 0; |
652 | u8 *cs_bytes = (u8*) &cs_value; | |
653 | ||
b67f4487 C |
654 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
655 | and LSB first */ | |
f68205a7 | 656 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
657 | |
658 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 659 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
660 | |
661 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 662 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
663 | |
664 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 665 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 666 | |
f68205a7 | 667 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
668 | |
669 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 670 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
671 | |
672 | /* Enable the DIT */ | |
f68205a7 | 673 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 674 | |
6479285d DM |
675 | /* Set S/PDIF channel status bits */ |
676 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
677 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
678 | ||
679 | switch (rate) { | |
680 | case 22050: | |
681 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
682 | break; | |
683 | case 24000: | |
684 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
685 | break; | |
686 | case 32000: | |
687 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
688 | break; | |
689 | case 44100: | |
690 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
691 | break; | |
692 | case 48000: | |
693 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
694 | break; | |
695 | case 88200: | |
696 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
697 | break; | |
698 | case 96000: | |
699 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
700 | break; | |
701 | case 176400: | |
702 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
703 | break; | |
704 | case 192000: | |
705 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
706 | break; | |
707 | default: | |
708 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
709 | return -EINVAL; | |
710 | } | |
711 | ||
712 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
713 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
714 | ||
2c56c4c2 | 715 | return 0; |
b67f4487 C |
716 | } |
717 | ||
718 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
719 | struct snd_pcm_hw_params *params, | |
720 | struct snd_soc_dai *cpu_dai) | |
721 | { | |
70091a3e | 722 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 723 | struct davinci_pcm_dma_params *dma_params = |
70091a3e | 724 | &mcasp->dma_params[substream->stream]; |
b67f4487 | 725 | int word_length; |
a7e46bd9 | 726 | int channels = params_channels(params); |
dd093a0f | 727 | int period_size = params_period_size(params); |
2c56c4c2 | 728 | int ret; |
ab8b14b6 | 729 | |
8267525c DM |
730 | /* |
731 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
732 | * the machine driver, we need to calculate the ratio. | |
733 | */ | |
734 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
ab8b14b6 | 735 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); |
0929878f | 736 | unsigned int div = mcasp->sysclk_freq / bclk_freq; |
ab8b14b6 | 737 | if (mcasp->sysclk_freq % bclk_freq != 0) { |
0929878f JS |
738 | if (((mcasp->sysclk_freq / div) - bclk_freq) > |
739 | (bclk_freq - (mcasp->sysclk_freq / (div+1)))) | |
740 | div++; | |
741 | dev_warn(mcasp->dev, | |
742 | "Inaccurate BCLK: %u Hz / %u != %u Hz\n", | |
743 | mcasp->sysclk_freq, div, bclk_freq); | |
ab8b14b6 | 744 | } |
0929878f | 745 | davinci_mcasp_set_clkdiv(cpu_dai, 1, div); |
ab8b14b6 JS |
746 | } |
747 | ||
dd093a0f PU |
748 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
749 | period_size * channels, channels); | |
0f7d9a63 PU |
750 | if (ret) |
751 | return ret; | |
752 | ||
70091a3e | 753 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 754 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 755 | else |
2c56c4c2 PU |
756 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
757 | ||
758 | if (ret) | |
759 | return ret; | |
b67f4487 C |
760 | |
761 | switch (params_format(params)) { | |
0a9d1385 | 762 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
763 | case SNDRV_PCM_FORMAT_S8: |
764 | dma_params->data_type = 1; | |
ba764b3d | 765 | word_length = 8; |
b67f4487 C |
766 | break; |
767 | ||
0a9d1385 | 768 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
769 | case SNDRV_PCM_FORMAT_S16_LE: |
770 | dma_params->data_type = 2; | |
ba764b3d | 771 | word_length = 16; |
b67f4487 C |
772 | break; |
773 | ||
21eb24d8 DM |
774 | case SNDRV_PCM_FORMAT_U24_3LE: |
775 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 776 | dma_params->data_type = 3; |
ba764b3d | 777 | word_length = 24; |
21eb24d8 DM |
778 | break; |
779 | ||
6b7fa011 DM |
780 | case SNDRV_PCM_FORMAT_U24_LE: |
781 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
782 | dma_params->data_type = 4; |
783 | word_length = 24; | |
784 | break; | |
785 | ||
0a9d1385 | 786 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
787 | case SNDRV_PCM_FORMAT_S32_LE: |
788 | dma_params->data_type = 4; | |
ba764b3d | 789 | word_length = 32; |
b67f4487 C |
790 | break; |
791 | ||
792 | default: | |
793 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
794 | return -EINVAL; | |
795 | } | |
6a99fb5f | 796 | |
5f04c603 | 797 | if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level) |
4fa9c1a5 C |
798 | dma_params->acnt = 4; |
799 | else | |
6a99fb5f C |
800 | dma_params->acnt = dma_params->data_type; |
801 | ||
70091a3e | 802 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 C |
803 | |
804 | return 0; | |
805 | } | |
806 | ||
807 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
808 | int cmd, struct snd_soc_dai *cpu_dai) | |
809 | { | |
70091a3e | 810 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
811 | int ret = 0; |
812 | ||
813 | switch (cmd) { | |
b67f4487 | 814 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
815 | case SNDRV_PCM_TRIGGER_START: |
816 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 817 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 818 | break; |
b67f4487 | 819 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 820 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 821 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 822 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
823 | break; |
824 | ||
825 | default: | |
826 | ret = -EINVAL; | |
827 | } | |
828 | ||
829 | return ret; | |
830 | } | |
831 | ||
85e7652d | 832 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
b67f4487 C |
833 | .trigger = davinci_mcasp_trigger, |
834 | .hw_params = davinci_mcasp_hw_params, | |
835 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 836 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 837 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
838 | }; |
839 | ||
d5902f69 PU |
840 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
841 | { | |
842 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
843 | ||
f3f9cfa8 | 844 | if (mcasp->version >= MCASP_VERSION_3) { |
d5902f69 PU |
845 | /* Using dmaengine PCM */ |
846 | dai->playback_dma_data = | |
847 | &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; | |
848 | dai->capture_dma_data = | |
849 | &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
850 | } else { | |
851 | /* Using davinci-pcm */ | |
852 | dai->playback_dma_data = mcasp->dma_params; | |
853 | dai->capture_dma_data = mcasp->dma_params; | |
854 | } | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
135014ad PU |
859 | #ifdef CONFIG_PM_SLEEP |
860 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
861 | { | |
862 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 863 | struct davinci_mcasp_context *context = &mcasp->context; |
1cc0c054 | 864 | int i; |
135014ad | 865 | |
1cc0c054 PU |
866 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
867 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad PU |
868 | |
869 | return 0; | |
870 | } | |
871 | ||
872 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
873 | { | |
874 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 875 | struct davinci_mcasp_context *context = &mcasp->context; |
1cc0c054 | 876 | int i; |
790bb94b | 877 | |
1cc0c054 PU |
878 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
879 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad PU |
880 | |
881 | return 0; | |
882 | } | |
883 | #else | |
884 | #define davinci_mcasp_suspend NULL | |
885 | #define davinci_mcasp_resume NULL | |
886 | #endif | |
887 | ||
ed29cd5e PU |
888 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
889 | ||
0a9d1385 BG |
890 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
891 | SNDRV_PCM_FMTBIT_U8 | \ | |
892 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
893 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
894 | SNDRV_PCM_FMTBIT_S24_LE | \ |
895 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
896 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
897 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
898 | SNDRV_PCM_FMTBIT_S32_LE | \ |
899 | SNDRV_PCM_FMTBIT_U32_LE) | |
900 | ||
f0fba2ad | 901 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 902 | { |
f0fba2ad | 903 | .name = "davinci-mcasp.0", |
d5902f69 | 904 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
905 | .suspend = davinci_mcasp_suspend, |
906 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
907 | .playback = { |
908 | .channels_min = 2, | |
2952b27e | 909 | .channels_max = 32 * 16, |
b67f4487 | 910 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 911 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
912 | }, |
913 | .capture = { | |
914 | .channels_min = 2, | |
2952b27e | 915 | .channels_max = 32 * 16, |
b67f4487 | 916 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 917 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
918 | }, |
919 | .ops = &davinci_mcasp_dai_ops, | |
920 | ||
921 | }, | |
922 | { | |
58e48d97 | 923 | .name = "davinci-mcasp.1", |
d5902f69 | 924 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
925 | .playback = { |
926 | .channels_min = 1, | |
927 | .channels_max = 384, | |
928 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 929 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
930 | }, |
931 | .ops = &davinci_mcasp_dai_ops, | |
932 | }, | |
933 | ||
934 | }; | |
b67f4487 | 935 | |
eeef0eda KM |
936 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
937 | .name = "davinci-mcasp", | |
938 | }; | |
939 | ||
256ba181 | 940 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 941 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
942 | .tx_dma_offset = 0x400, |
943 | .rx_dma_offset = 0x400, | |
944 | .asp_chan_q = EVENTQ_0, | |
945 | .version = MCASP_VERSION_1, | |
946 | }; | |
947 | ||
d1debafc | 948 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
949 | .tx_dma_offset = 0x2000, |
950 | .rx_dma_offset = 0x2000, | |
951 | .asp_chan_q = EVENTQ_0, | |
952 | .version = MCASP_VERSION_2, | |
953 | }; | |
954 | ||
d1debafc | 955 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
956 | .tx_dma_offset = 0, |
957 | .rx_dma_offset = 0, | |
958 | .asp_chan_q = EVENTQ_0, | |
959 | .version = MCASP_VERSION_3, | |
960 | }; | |
961 | ||
d1debafc | 962 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
963 | .tx_dma_offset = 0x200, |
964 | .rx_dma_offset = 0x284, | |
965 | .asp_chan_q = EVENTQ_0, | |
966 | .version = MCASP_VERSION_4, | |
967 | }; | |
968 | ||
3e3b8c34 HG |
969 | static const struct of_device_id mcasp_dt_ids[] = { |
970 | { | |
971 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 972 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
973 | }, |
974 | { | |
975 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 976 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 977 | }, |
e5ec69da | 978 | { |
3af9e031 | 979 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 980 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 981 | }, |
453c4990 PU |
982 | { |
983 | .compatible = "ti,dra7-mcasp-audio", | |
984 | .data = &dra7_mcasp_pdata, | |
985 | }, | |
3e3b8c34 HG |
986 | { /* sentinel */ } |
987 | }; | |
988 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
989 | ||
ae726e93 PU |
990 | static int mcasp_reparent_fck(struct platform_device *pdev) |
991 | { | |
992 | struct device_node *node = pdev->dev.of_node; | |
993 | struct clk *gfclk, *parent_clk; | |
994 | const char *parent_name; | |
995 | int ret; | |
996 | ||
997 | if (!node) | |
998 | return 0; | |
999 | ||
1000 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1001 | if (!parent_name) | |
1002 | return 0; | |
1003 | ||
1004 | gfclk = clk_get(&pdev->dev, "fck"); | |
1005 | if (IS_ERR(gfclk)) { | |
1006 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1007 | return PTR_ERR(gfclk); | |
1008 | } | |
1009 | ||
1010 | parent_clk = clk_get(NULL, parent_name); | |
1011 | if (IS_ERR(parent_clk)) { | |
1012 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1013 | ret = PTR_ERR(parent_clk); | |
1014 | goto err1; | |
1015 | } | |
1016 | ||
1017 | ret = clk_set_parent(gfclk, parent_clk); | |
1018 | if (ret) { | |
1019 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1020 | goto err2; | |
1021 | } | |
1022 | ||
1023 | err2: | |
1024 | clk_put(parent_clk); | |
1025 | err1: | |
1026 | clk_put(gfclk); | |
1027 | return ret; | |
1028 | } | |
1029 | ||
d1debafc | 1030 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1031 | struct platform_device *pdev) |
1032 | { | |
1033 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1034 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1035 | const struct of_device_id *match = |
ea421eb1 | 1036 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1037 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1038 | |
1039 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1040 | u32 val; |
1041 | int i, ret = 0; | |
1042 | ||
1043 | if (pdev->dev.platform_data) { | |
1044 | pdata = pdev->dev.platform_data; | |
1045 | return pdata; | |
1046 | } else if (match) { | |
d1debafc | 1047 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1048 | } else { |
1049 | /* control shouldn't reach here. something is wrong */ | |
1050 | ret = -EINVAL; | |
1051 | goto nodata; | |
1052 | } | |
1053 | ||
3e3b8c34 HG |
1054 | ret = of_property_read_u32(np, "op-mode", &val); |
1055 | if (ret >= 0) | |
1056 | pdata->op_mode = val; | |
1057 | ||
1058 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1059 | if (ret >= 0) { |
1060 | if (val < 2 || val > 32) { | |
1061 | dev_err(&pdev->dev, | |
1062 | "tdm-slots must be in rage [2-32]\n"); | |
1063 | ret = -EINVAL; | |
1064 | goto nodata; | |
1065 | } | |
1066 | ||
3e3b8c34 | 1067 | pdata->tdm_slots = val; |
2952b27e | 1068 | } |
3e3b8c34 | 1069 | |
3e3b8c34 HG |
1070 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1071 | val /= sizeof(u32); | |
3e3b8c34 | 1072 | if (of_serial_dir32) { |
1427e660 PU |
1073 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1074 | (sizeof(*of_serial_dir) * val), | |
1075 | GFP_KERNEL); | |
3e3b8c34 HG |
1076 | if (!of_serial_dir) { |
1077 | ret = -ENOMEM; | |
1078 | goto nodata; | |
1079 | } | |
1080 | ||
1427e660 | 1081 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1082 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1083 | ||
1427e660 | 1084 | pdata->num_serializer = val; |
3e3b8c34 HG |
1085 | pdata->serial_dir = of_serial_dir; |
1086 | } | |
1087 | ||
4023fe6f JS |
1088 | ret = of_property_match_string(np, "dma-names", "tx"); |
1089 | if (ret < 0) | |
1090 | goto nodata; | |
1091 | ||
1092 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1093 | &dma_spec); | |
1094 | if (ret < 0) | |
1095 | goto nodata; | |
1096 | ||
1097 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1098 | ||
1099 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1100 | if (ret < 0) | |
1101 | goto nodata; | |
1102 | ||
1103 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1104 | &dma_spec); | |
1105 | if (ret < 0) | |
1106 | goto nodata; | |
1107 | ||
1108 | pdata->rx_dma_channel = dma_spec.args[0]; | |
1109 | ||
3e3b8c34 HG |
1110 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1111 | if (ret >= 0) | |
1112 | pdata->txnumevt = val; | |
1113 | ||
1114 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1115 | if (ret >= 0) | |
1116 | pdata->rxnumevt = val; | |
1117 | ||
1118 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1119 | if (ret >= 0) | |
1120 | pdata->sram_size_playback = val; | |
1121 | ||
1122 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1123 | if (ret >= 0) | |
1124 | pdata->sram_size_capture = val; | |
1125 | ||
1126 | return pdata; | |
1127 | ||
1128 | nodata: | |
1129 | if (ret < 0) { | |
1130 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1131 | ret); | |
1132 | pdata = NULL; | |
1133 | } | |
1134 | return pdata; | |
1135 | } | |
1136 | ||
b67f4487 C |
1137 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1138 | { | |
64ebdec3 | 1139 | struct davinci_pcm_dma_params *dma_params; |
8de131f2 | 1140 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1141 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1142 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1143 | struct davinci_mcasp *mcasp; |
96d31e2b | 1144 | int ret; |
b67f4487 | 1145 | |
3e3b8c34 HG |
1146 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1147 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1148 | return -EINVAL; | |
1149 | } | |
1150 | ||
70091a3e | 1151 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1152 | GFP_KERNEL); |
70091a3e | 1153 | if (!mcasp) |
b67f4487 C |
1154 | return -ENOMEM; |
1155 | ||
3e3b8c34 HG |
1156 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1157 | if (!pdata) { | |
1158 | dev_err(&pdev->dev, "no platform data\n"); | |
1159 | return -EINVAL; | |
1160 | } | |
1161 | ||
256ba181 | 1162 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1163 | if (!mem) { |
70091a3e | 1164 | dev_warn(mcasp->dev, |
256ba181 JS |
1165 | "\"mpu\" mem resource not found, using index 0\n"); |
1166 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1167 | if (!mem) { | |
1168 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1169 | return -ENODEV; | |
1170 | } | |
b67f4487 C |
1171 | } |
1172 | ||
96d31e2b | 1173 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1174 | resource_size(mem), pdev->name); |
b67f4487 C |
1175 | if (!ioarea) { |
1176 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1177 | return -EBUSY; |
b67f4487 C |
1178 | } |
1179 | ||
10884347 | 1180 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1181 | |
10884347 HG |
1182 | ret = pm_runtime_get_sync(&pdev->dev); |
1183 | if (IS_ERR_VALUE(ret)) { | |
1184 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
1185 | return ret; | |
1186 | } | |
b67f4487 | 1187 | |
70091a3e PU |
1188 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1189 | if (!mcasp->base) { | |
4f82f028 VB |
1190 | dev_err(&pdev->dev, "ioremap failed\n"); |
1191 | ret = -ENOMEM; | |
b6bb3709 | 1192 | goto err; |
4f82f028 VB |
1193 | } |
1194 | ||
70091a3e PU |
1195 | mcasp->op_mode = pdata->op_mode; |
1196 | mcasp->tdm_slots = pdata->tdm_slots; | |
1197 | mcasp->num_serializer = pdata->num_serializer; | |
1198 | mcasp->serial_dir = pdata->serial_dir; | |
1199 | mcasp->version = pdata->version; | |
1200 | mcasp->txnumevt = pdata->txnumevt; | |
1201 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1202 | |
70091a3e | 1203 | mcasp->dev = &pdev->dev; |
b67f4487 | 1204 | |
256ba181 | 1205 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1206 | if (dat) |
1207 | mcasp->dat_port = true; | |
256ba181 | 1208 | |
64ebdec3 | 1209 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
8de131f2 | 1210 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
64ebdec3 PU |
1211 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1212 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1213 | dma_params->sram_pool = pdata->sram_pool; | |
1214 | dma_params->sram_size = pdata->sram_size_playback; | |
cbc7956c | 1215 | if (dat) |
64ebdec3 | 1216 | dma_params->dma_addr = dat->start; |
cbc7956c | 1217 | else |
64ebdec3 | 1218 | dma_params->dma_addr = mem->start + pdata->tx_dma_offset; |
b67f4487 | 1219 | |
453c4990 | 1220 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1221 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1222 | |
b67f4487 | 1223 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1224 | if (res) |
64ebdec3 | 1225 | dma_params->channel = res->start; |
4023fe6f | 1226 | else |
64ebdec3 | 1227 | dma_params->channel = pdata->tx_dma_channel; |
92e2a6f6 | 1228 | |
8de131f2 PU |
1229 | /* dmaengine filter data for DT and non-DT boot */ |
1230 | if (pdev->dev.of_node) | |
1231 | dma_data->filter_data = "tx"; | |
1232 | else | |
1233 | dma_data->filter_data = &dma_params->channel; | |
1234 | ||
64ebdec3 | 1235 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
8de131f2 | 1236 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
64ebdec3 PU |
1237 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1238 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1239 | dma_params->sram_pool = pdata->sram_pool; | |
1240 | dma_params->sram_size = pdata->sram_size_capture; | |
cbc7956c | 1241 | if (dat) |
64ebdec3 | 1242 | dma_params->dma_addr = dat->start; |
cbc7956c | 1243 | else |
64ebdec3 | 1244 | dma_params->dma_addr = mem->start + pdata->rx_dma_offset; |
cbc7956c | 1245 | |
453c4990 | 1246 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1247 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1248 | |
cbc7956c PU |
1249 | if (mcasp->version < MCASP_VERSION_3) { |
1250 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1251 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1252 | mcasp->dat_port = true; |
1253 | } else { | |
1254 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1255 | } | |
b67f4487 C |
1256 | |
1257 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
4023fe6f | 1258 | if (res) |
64ebdec3 | 1259 | dma_params->channel = res->start; |
4023fe6f | 1260 | else |
64ebdec3 | 1261 | dma_params->channel = pdata->rx_dma_channel; |
b67f4487 | 1262 | |
8de131f2 PU |
1263 | /* dmaengine filter data for DT and non-DT boot */ |
1264 | if (pdev->dev.of_node) | |
1265 | dma_data->filter_data = "rx"; | |
1266 | else | |
1267 | dma_data->filter_data = &dma_params->channel; | |
453c4990 | 1268 | |
70091a3e | 1269 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1270 | |
1271 | mcasp_reparent_fck(pdev); | |
1272 | ||
b6bb3709 PU |
1273 | ret = devm_snd_soc_register_component(&pdev->dev, |
1274 | &davinci_mcasp_component, | |
1275 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1276 | |
1277 | if (ret != 0) | |
b6bb3709 | 1278 | goto err; |
f08095a4 | 1279 | |
d5c6c59a | 1280 | switch (mcasp->version) { |
7f28f357 JS |
1281 | #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \ |
1282 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1283 | IS_MODULE(CONFIG_SND_DAVINCI_SOC)) | |
d5c6c59a PU |
1284 | case MCASP_VERSION_1: |
1285 | case MCASP_VERSION_2: | |
453c4990 | 1286 | ret = davinci_soc_platform_register(&pdev->dev); |
d5c6c59a | 1287 | break; |
7f28f357 | 1288 | #endif |
f3f9cfa8 PU |
1289 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1290 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1291 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
1292 | case MCASP_VERSION_3: | |
1293 | ret = edma_pcm_platform_register(&pdev->dev); | |
1294 | break; | |
1295 | #endif | |
7f28f357 JS |
1296 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
1297 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1298 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a PU |
1299 | case MCASP_VERSION_4: |
1300 | ret = omap_pcm_platform_register(&pdev->dev); | |
1301 | break; | |
7f28f357 | 1302 | #endif |
d5c6c59a PU |
1303 | default: |
1304 | dev_err(&pdev->dev, "Invalid McASP version: %d\n", | |
1305 | mcasp->version); | |
1306 | ret = -EINVAL; | |
1307 | break; | |
1308 | } | |
1309 | ||
1310 | if (ret) { | |
1311 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 1312 | goto err; |
f08095a4 HG |
1313 | } |
1314 | ||
b67f4487 C |
1315 | return 0; |
1316 | ||
b6bb3709 | 1317 | err: |
10884347 HG |
1318 | pm_runtime_put_sync(&pdev->dev); |
1319 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1320 | return ret; |
1321 | } | |
1322 | ||
1323 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1324 | { | |
10884347 HG |
1325 | pm_runtime_put_sync(&pdev->dev); |
1326 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1327 | |
b67f4487 C |
1328 | return 0; |
1329 | } | |
1330 | ||
1331 | static struct platform_driver davinci_mcasp_driver = { | |
1332 | .probe = davinci_mcasp_probe, | |
1333 | .remove = davinci_mcasp_remove, | |
1334 | .driver = { | |
1335 | .name = "davinci-mcasp", | |
1336 | .owner = THIS_MODULE, | |
ea421eb1 | 1337 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1338 | }, |
1339 | }; | |
1340 | ||
f9b8a514 | 1341 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1342 | |
1343 | MODULE_AUTHOR("Steve Chen"); | |
1344 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1345 | MODULE_LICENSE("GPL"); |