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ASoC: McASP: add support for 24 bit samples
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1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
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22#include <linux/delay.h>
23#include <linux/io.h>
10884347 24#include <linux/pm_runtime.h>
3e3b8c34
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25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/of_device.h>
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28
29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/initval.h>
33#include <sound/soc.h>
34
35#include "davinci-pcm.h"
36#include "davinci-mcasp.h"
37
38/*
39 * McASP register definitions
40 */
41#define DAVINCI_MCASP_PID_REG 0x00
42#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
43
44#define DAVINCI_MCASP_PFUNC_REG 0x10
45#define DAVINCI_MCASP_PDIR_REG 0x14
46#define DAVINCI_MCASP_PDOUT_REG 0x18
47#define DAVINCI_MCASP_PDSET_REG 0x1c
48
49#define DAVINCI_MCASP_PDCLR_REG 0x20
50
51#define DAVINCI_MCASP_TLGC_REG 0x30
52#define DAVINCI_MCASP_TLMR_REG 0x34
53
54#define DAVINCI_MCASP_GBLCTL_REG 0x44
55#define DAVINCI_MCASP_AMUTE_REG 0x48
56#define DAVINCI_MCASP_LBCTL_REG 0x4c
57
58#define DAVINCI_MCASP_TXDITCTL_REG 0x50
59
60#define DAVINCI_MCASP_GBLCTLR_REG 0x60
61#define DAVINCI_MCASP_RXMASK_REG 0x64
62#define DAVINCI_MCASP_RXFMT_REG 0x68
63#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
64
65#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67#define DAVINCI_MCASP_RXTDM_REG 0x78
68#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
69
70#define DAVINCI_MCASP_RXSTAT_REG 0x80
71#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73#define DAVINCI_MCASP_REVTCTL_REG 0x8c
74
75#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76#define DAVINCI_MCASP_TXMASK_REG 0xa4
77#define DAVINCI_MCASP_TXFMT_REG 0xa8
78#define DAVINCI_MCASP_TXFMCTL_REG 0xac
79
80#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82#define DAVINCI_MCASP_TXTDM_REG 0xb8
83#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
84
85#define DAVINCI_MCASP_TXSTAT_REG 0xc0
86#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
89
90/* Left(even TDM Slot) Channel Status Register File */
91#define DAVINCI_MCASP_DITCSRA_REG 0x100
92/* Right(odd TDM slot) Channel Status Register File */
93#define DAVINCI_MCASP_DITCSRB_REG 0x118
94/* Left(even TDM slot) User Data Register File */
95#define DAVINCI_MCASP_DITUDRA_REG 0x130
96/* Right(odd TDM Slot) User Data Register File */
97#define DAVINCI_MCASP_DITUDRB_REG 0x148
98
99/* Serializer n Control Register */
100#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102 (n << 2))
103
104/* Transmit Buffer for Serializer n */
105#define DAVINCI_MCASP_TXBUF_REG 0x200
106/* Receive Buffer for Serializer n */
107#define DAVINCI_MCASP_RXBUF_REG 0x280
108
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109/* McASP FIFO Registers */
110#define DAVINCI_MCASP_WFIFOCTL (0x1010)
111#define DAVINCI_MCASP_WFIFOSTS (0x1014)
112#define DAVINCI_MCASP_RFIFOCTL (0x1018)
113#define DAVINCI_MCASP_RFIFOSTS (0x101C)
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114#define MCASP_VER3_WFIFOCTL (0x1000)
115#define MCASP_VER3_WFIFOSTS (0x1004)
116#define MCASP_VER3_RFIFOCTL (0x1008)
117#define MCASP_VER3_RFIFOSTS (0x100C)
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118
119/*
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
121 * Register Bits
122 */
123#define MCASP_FREE BIT(0)
124#define MCASP_SOFT BIT(1)
125
126/*
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
128 */
129#define AXR(n) (1<<n)
130#define PFUNC_AMUTE BIT(25)
131#define ACLKX BIT(26)
132#define AHCLKX BIT(27)
133#define AFSX BIT(28)
134#define ACLKR BIT(29)
135#define AHCLKR BIT(30)
136#define AFSR BIT(31)
137
138/*
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
140 */
141#define AXR(n) (1<<n)
142#define PDIR_AMUTE BIT(25)
143#define ACLKX BIT(26)
144#define AHCLKX BIT(27)
145#define AFSX BIT(28)
146#define ACLKR BIT(29)
147#define AHCLKR BIT(30)
148#define AFSR BIT(31)
149
150/*
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
152 */
153#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
154#define VA BIT(2)
155#define VB BIT(3)
156
157/*
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
159 */
160#define TXROT(val) (val)
161#define TXSEL BIT(3)
162#define TXSSZ(val) (val<<4)
163#define TXPBIT(val) (val<<8)
164#define TXPAD(val) (val<<13)
165#define TXORD BIT(15)
166#define FSXDLY(val) (val<<16)
167
168/*
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
170 */
171#define RXROT(val) (val)
172#define RXSEL BIT(3)
173#define RXSSZ(val) (val<<4)
174#define RXPBIT(val) (val<<8)
175#define RXPAD(val) (val<<13)
176#define RXORD BIT(15)
177#define FSRDLY(val) (val<<16)
178
179/*
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
181 */
182#define FSXPOL BIT(0)
183#define AFSXE BIT(1)
184#define FSXDUR BIT(4)
185#define FSXMOD(val) (val<<7)
186
187/*
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
189 */
190#define FSRPOL BIT(0)
191#define AFSRE BIT(1)
192#define FSRDUR BIT(4)
193#define FSRMOD(val) (val<<7)
194
195/*
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
197 */
198#define ACLKXDIV(val) (val)
199#define ACLKXE BIT(5)
200#define TX_ASYNC BIT(6)
201#define ACLKXPOL BIT(7)
4ed8c9b7 202#define ACLKXDIV_MASK 0x1f
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203
204/*
205 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
206 */
207#define ACLKRDIV(val) (val)
208#define ACLKRE BIT(5)
209#define RX_ASYNC BIT(6)
210#define ACLKRPOL BIT(7)
4ed8c9b7 211#define ACLKRDIV_MASK 0x1f
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212
213/*
214 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
215 * Register Bits
216 */
217#define AHCLKXDIV(val) (val)
218#define AHCLKXPOL BIT(14)
219#define AHCLKXE BIT(15)
4ed8c9b7 220#define AHCLKXDIV_MASK 0xfff
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221
222/*
223 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
224 * Register Bits
225 */
226#define AHCLKRDIV(val) (val)
227#define AHCLKRPOL BIT(14)
228#define AHCLKRE BIT(15)
4ed8c9b7 229#define AHCLKRDIV_MASK 0xfff
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230
231/*
232 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
233 */
234#define MODE(val) (val)
235#define DISMOD (val)(val<<2)
236#define TXSTATE BIT(4)
237#define RXSTATE BIT(5)
238
239/*
240 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
241 */
242#define LBEN BIT(0)
243#define LBORD BIT(1)
244#define LBGENMODE(val) (val<<2)
245
246/*
247 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
248 */
249#define TXTDMS(n) (1<<n)
250
251/*
252 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
253 */
254#define RXTDMS(n) (1<<n)
255
256/*
257 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
258 */
259#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
260#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
261#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
262#define RXSMRST BIT(3) /* Receiver State Machine Reset */
263#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
264#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
265#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
266#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
267#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
268#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
269
270/*
271 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
272 */
273#define MUTENA(val) (val)
274#define MUTEINPOL BIT(2)
275#define MUTEINENA BIT(3)
276#define MUTEIN BIT(4)
277#define MUTER BIT(5)
278#define MUTEX BIT(6)
279#define MUTEFSR BIT(7)
280#define MUTEFSX BIT(8)
281#define MUTEBADCLKR BIT(9)
282#define MUTEBADCLKX BIT(10)
283#define MUTERXDMAERR BIT(11)
284#define MUTETXDMAERR BIT(12)
285
286/*
287 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
288 */
289#define RXDATADMADIS BIT(0)
290
291/*
292 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
293 */
294#define TXDATADMADIS BIT(0)
295
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296/*
297 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
298 */
299#define FIFO_ENABLE BIT(16)
300#define NUMEVT_MASK (0xFF << 8)
301#define NUMDMA_MASK (0xFF)
302
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303#define DAVINCI_MCASP_NUM_SERIALIZER 16
304
305static inline void mcasp_set_bits(void __iomem *reg, u32 val)
306{
307 __raw_writel(__raw_readl(reg) | val, reg);
308}
309
310static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
311{
312 __raw_writel((__raw_readl(reg) & ~(val)), reg);
313}
314
315static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
316{
317 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
318}
319
320static inline void mcasp_set_reg(void __iomem *reg, u32 val)
321{
322 __raw_writel(val, reg);
323}
324
325static inline u32 mcasp_get_reg(void __iomem *reg)
326{
327 return (unsigned int)__raw_readl(reg);
328}
329
330static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
331{
332 int i = 0;
333
334 mcasp_set_bits(regs, val);
335
336 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
337 /* loop count is to avoid the lock-up */
338 for (i = 0; i < 1000; i++) {
339 if ((mcasp_get_reg(regs) & val) == val)
340 break;
341 }
342
343 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
344 printk(KERN_ERR "GBLCTL write error\n");
345}
346
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347static void mcasp_start_rx(struct davinci_audio_dev *dev)
348{
349 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
352 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
353
354 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
356 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
357
358 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
359 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
360}
361
362static void mcasp_start_tx(struct davinci_audio_dev *dev)
363{
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364 u8 offset = 0, i;
365 u32 cnt;
366
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367 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
368 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
370 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
371
372 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
373 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
374 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
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375 for (i = 0; i < dev->num_serializer; i++) {
376 if (dev->serial_dir[i] == TX_MODE) {
377 offset = i;
378 break;
379 }
380 }
381
382 /* wait for TX ready */
383 cnt = 0;
384 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
385 TXSTATE) && (cnt < 100000))
386 cnt++;
387
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388 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
389}
390
391static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
392{
539d3d8c 393 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0d624275 394 if (dev->txnumevt) { /* enable FIFO */
e5ec69da
HG
395 switch (dev->version) {
396 case MCASP_VERSION_3:
397 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
0d624275 398 FIFO_ENABLE);
e5ec69da 399 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
539d3d8c 400 FIFO_ENABLE);
e5ec69da
HG
401 break;
402 default:
403 mcasp_clr_bits(dev->base +
404 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
405 mcasp_set_bits(dev->base +
406 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407 }
0d624275 408 }
b67f4487 409 mcasp_start_tx(dev);
539d3d8c 410 } else {
0d624275 411 if (dev->rxnumevt) { /* enable FIFO */
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HG
412 switch (dev->version) {
413 case MCASP_VERSION_3:
414 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
0d624275 415 FIFO_ENABLE);
e5ec69da 416 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
539d3d8c 417 FIFO_ENABLE);
e5ec69da
HG
418 break;
419 default:
420 mcasp_clr_bits(dev->base +
421 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
422 mcasp_set_bits(dev->base +
423 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
424 }
0d624275 425 }
b67f4487 426 mcasp_start_rx(dev);
539d3d8c 427 }
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428}
429
430static void mcasp_stop_rx(struct davinci_audio_dev *dev)
431{
432 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
433 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
434}
435
436static void mcasp_stop_tx(struct davinci_audio_dev *dev)
437{
438 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
439 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
440}
441
442static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
443{
539d3d8c 444 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
e5ec69da
HG
445 if (dev->txnumevt) { /* disable FIFO */
446 switch (dev->version) {
447 case MCASP_VERSION_3:
448 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
539d3d8c 449 FIFO_ENABLE);
e5ec69da
HG
450 break;
451 default:
452 mcasp_clr_bits(dev->base +
453 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
454 }
455 }
b67f4487 456 mcasp_stop_tx(dev);
539d3d8c 457 } else {
e5ec69da
HG
458 if (dev->rxnumevt) { /* disable FIFO */
459 switch (dev->version) {
460 case MCASP_VERSION_3:
461 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
539d3d8c 462 FIFO_ENABLE);
e5ec69da
HG
463 break;
464
465 default:
466 mcasp_clr_bits(dev->base +
467 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
468 }
469 }
b67f4487 470 mcasp_stop_rx(dev);
539d3d8c 471 }
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472}
473
474static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
475 unsigned int fmt)
476{
f0fba2ad 477 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
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478 void __iomem *base = dev->base;
479
5296cf2d
DM
480 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
481 case SND_SOC_DAIFMT_DSP_B:
482 case SND_SOC_DAIFMT_AC97:
483 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
484 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
485 break;
486 default:
487 /* configure a full-word SYNC pulse (LRCLK) */
488 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
489 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
490
491 /* make 1st data bit occur one ACLK cycle after the frame sync */
492 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
493 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
494 break;
495 }
496
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497 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
498 case SND_SOC_DAIFMT_CBS_CFS:
499 /* codec is clock and frame slave */
500 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
501 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
502
503 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
504 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
505
5b66aa2d 506 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, ACLKX | AFSX);
b67f4487 507 break;
517ee6cf
C
508 case SND_SOC_DAIFMT_CBM_CFS:
509 /* codec is clock master and frame slave */
a90f549e 510 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
517ee6cf
C
511 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
512
a90f549e 513 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
517ee6cf
C
514 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
515
db92f437
BG
516 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
517 ACLKX | ACLKR);
9595c8f0 518 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
db92f437 519 AFSX | AFSR);
517ee6cf 520 break;
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521 case SND_SOC_DAIFMT_CBM_CFM:
522 /* codec is clock and frame master */
523 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
524 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
525
526 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
527 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
528
9595c8f0
BG
529 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
530 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
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531 break;
532
533 default:
534 return -EINVAL;
535 }
536
537 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
538 case SND_SOC_DAIFMT_IB_NF:
539 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
540 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
541
542 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
543 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
544 break;
545
546 case SND_SOC_DAIFMT_NB_IF:
547 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
548 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
549
550 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
551 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
552 break;
553
554 case SND_SOC_DAIFMT_IB_IF:
555 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
556 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
557
558 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
559 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
560 break;
561
562 case SND_SOC_DAIFMT_NB_NF:
563 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
564 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
565
566 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
567 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
568 break;
569
570 default:
571 return -EINVAL;
572 }
573
574 return 0;
575}
576
4ed8c9b7
DM
577static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
578{
579 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
580
581 switch (div_id) {
582 case 0: /* MCLK divider */
583 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
584 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
585 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
586 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
587 break;
588
589 case 1: /* BCLK divider */
590 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
591 ACLKXDIV(div - 1), ACLKXDIV_MASK);
592 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
593 ACLKRDIV(div - 1), ACLKRDIV_MASK);
594 break;
595
596 default:
597 return -EINVAL;
598 }
599
600 return 0;
601}
602
5b66aa2d
DM
603static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
604 unsigned int freq, int dir)
605{
606 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
607
608 if (dir == SND_SOC_CLOCK_OUT) {
609 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
610 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
611 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
612 } else {
613 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
614 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
615 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
616 }
617
618 return 0;
619}
620
b67f4487
C
621static int davinci_config_channel_size(struct davinci_audio_dev *dev,
622 int channel_size)
623{
624 u32 fmt = 0;
0c31cf3e 625 u32 mask, rotate;
b67f4487
C
626
627 switch (channel_size) {
628 case DAVINCI_AUDIO_WORD_8:
629 fmt = 0x03;
0c31cf3e
C
630 rotate = 6;
631 mask = 0x000000ff;
b67f4487
C
632 break;
633
634 case DAVINCI_AUDIO_WORD_12:
635 fmt = 0x05;
0c31cf3e
C
636 rotate = 5;
637 mask = 0x00000fff;
b67f4487
C
638 break;
639
640 case DAVINCI_AUDIO_WORD_16:
641 fmt = 0x07;
0c31cf3e
C
642 rotate = 4;
643 mask = 0x0000ffff;
b67f4487
C
644 break;
645
646 case DAVINCI_AUDIO_WORD_20:
647 fmt = 0x09;
0c31cf3e
C
648 rotate = 3;
649 mask = 0x000fffff;
b67f4487
C
650 break;
651
652 case DAVINCI_AUDIO_WORD_24:
653 fmt = 0x0B;
0c31cf3e
C
654 rotate = 2;
655 mask = 0x00ffffff;
b67f4487
C
656 break;
657
658 case DAVINCI_AUDIO_WORD_28:
659 fmt = 0x0D;
0c31cf3e
C
660 rotate = 1;
661 mask = 0x0fffffff;
b67f4487
C
662 break;
663
664 case DAVINCI_AUDIO_WORD_32:
665 fmt = 0x0F;
0c31cf3e
C
666 rotate = 0;
667 mask = 0xffffffff;
b67f4487
C
668 break;
669
670 default:
671 return -EINVAL;
672 }
673
674 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
675 RXSSZ(fmt), RXSSZ(0x0F));
676 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
677 TXSSZ(fmt), TXSSZ(0x0F));
0c31cf3e
C
678 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
679 TXROT(7));
680 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
681 RXROT(7));
682 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
683 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
684
b67f4487
C
685 return 0;
686}
687
688static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
689{
690 int i;
6a99fb5f
C
691 u8 tx_ser = 0;
692 u8 rx_ser = 0;
b67f4487
C
693
694 /* Default configuration */
695 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
696
697 /* All PINS as McASP */
698 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
699
700 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
701 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
702 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
703 TXDATADMADIS);
704 } else {
705 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
706 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
707 RXDATADMADIS);
708 }
709
710 for (i = 0; i < dev->num_serializer; i++) {
711 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
712 dev->serial_dir[i]);
6a99fb5f 713 if (dev->serial_dir[i] == TX_MODE) {
b67f4487
C
714 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
715 AXR(i));
6a99fb5f
C
716 tx_ser++;
717 } else if (dev->serial_dir[i] == RX_MODE) {
b67f4487
C
718 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
719 AXR(i));
6a99fb5f
C
720 rx_ser++;
721 }
722 }
723
724 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
725 if (dev->txnumevt * tx_ser > 64)
726 dev->txnumevt = 1;
727
e5ec69da
HG
728 switch (dev->version) {
729 case MCASP_VERSION_3:
730 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
6a99fb5f 731 NUMDMA_MASK);
e5ec69da 732 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
6a99fb5f 733 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
e5ec69da
HG
734 break;
735 default:
736 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
737 tx_ser, NUMDMA_MASK);
738 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
739 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
740 }
6a99fb5f
C
741 }
742
743 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
744 if (dev->rxnumevt * rx_ser > 64)
745 dev->rxnumevt = 1;
e5ec69da
HG
746 switch (dev->version) {
747 case MCASP_VERSION_3:
748 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
6a99fb5f 749 NUMDMA_MASK);
e5ec69da
HG
750 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
751 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
752 break;
753 default:
754 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
755 rx_ser, NUMDMA_MASK);
756 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
6a99fb5f 757 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
e5ec69da 758 }
b67f4487
C
759 }
760}
761
762static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
763{
764 int i, active_slots;
765 u32 mask = 0;
766
767 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
768 for (i = 0; i < active_slots; i++)
769 mask |= (1 << i);
770
6a99fb5f
C
771 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
772
b67f4487
C
773 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
774 /* bit stream is MSB first with no delay */
775 /* DSP_B mode */
b67f4487
C
776 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
777 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
778
049cfaaa 779 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
b67f4487
C
780 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
781 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
782 else
783 printk(KERN_ERR "playback tdm slot %d not supported\n",
784 dev->tdm_slots);
b67f4487
C
785 } else {
786 /* bit stream is MSB first with no delay */
787 /* DSP_B mode */
788 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
b67f4487
C
789 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
790
049cfaaa 791 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
b67f4487
C
792 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
793 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
794 else
795 printk(KERN_ERR "capture tdm slot %d not supported\n",
796 dev->tdm_slots);
b67f4487
C
797 }
798}
799
800/* S/PDIF */
801static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
802{
803 /* Set the PDIR for Serialiser as output */
804 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
805
806 /* TXMASK for 24 bits */
807 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
808
809 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
810 and LSB first */
811 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
812 TXROT(6) | TXSSZ(15));
813
814 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
815 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
816 AFSXE | FSXMOD(0x180));
817
818 /* Set the TX tdm : for all the slots */
819 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
820
821 /* Set the TX clock controls : div = 1 and internal */
822 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
823 ACLKXE | TX_ASYNC);
824
825 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
826
827 /* Only 44100 and 48000 are valid, both have the same setting */
828 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
829
830 /* Enable the DIT */
831 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
832}
833
834static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
835 struct snd_pcm_hw_params *params,
836 struct snd_soc_dai *cpu_dai)
837{
f0fba2ad 838 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 839 struct davinci_pcm_dma_params *dma_params =
92e2a6f6 840 &dev->dma_params[substream->stream];
b67f4487 841 int word_length;
4fa9c1a5 842 u8 fifo_level;
b67f4487
C
843
844 davinci_hw_common_param(dev, substream->stream);
6a99fb5f 845 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4fa9c1a5 846 fifo_level = dev->txnumevt;
6a99fb5f 847 else
4fa9c1a5 848 fifo_level = dev->rxnumevt;
b67f4487
C
849
850 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
851 davinci_hw_dit_param(dev);
852 else
853 davinci_hw_param(dev, substream->stream);
854
855 switch (params_format(params)) {
0a9d1385 856 case SNDRV_PCM_FORMAT_U8:
b67f4487
C
857 case SNDRV_PCM_FORMAT_S8:
858 dma_params->data_type = 1;
859 word_length = DAVINCI_AUDIO_WORD_8;
860 break;
861
0a9d1385 862 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487
C
863 case SNDRV_PCM_FORMAT_S16_LE:
864 dma_params->data_type = 2;
865 word_length = DAVINCI_AUDIO_WORD_16;
866 break;
867
21eb24d8
DM
868 case SNDRV_PCM_FORMAT_U24_3LE:
869 case SNDRV_PCM_FORMAT_S24_3LE:
870 case SNDRV_PCM_FORMAT_U24_LE:
871 case SNDRV_PCM_FORMAT_S24_LE:
872 dma_params->data_type = 3;
873 word_length = DAVINCI_AUDIO_WORD_24;
874 break;
875
0a9d1385 876 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487
C
877 case SNDRV_PCM_FORMAT_S32_LE:
878 dma_params->data_type = 4;
879 word_length = DAVINCI_AUDIO_WORD_32;
880 break;
881
882 default:
883 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
884 return -EINVAL;
885 }
6a99fb5f 886
4fa9c1a5
C
887 if (dev->version == MCASP_VERSION_2 && !fifo_level)
888 dma_params->acnt = 4;
889 else
6a99fb5f
C
890 dma_params->acnt = dma_params->data_type;
891
4fa9c1a5 892 dma_params->fifo_level = fifo_level;
b67f4487
C
893 davinci_config_channel_size(dev, word_length);
894
895 return 0;
896}
897
898static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
899 int cmd, struct snd_soc_dai *cpu_dai)
900{
f0fba2ad 901 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C
902 int ret = 0;
903
904 switch (cmd) {
b67f4487 905 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C
906 case SNDRV_PCM_TRIGGER_START:
907 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
10884347
HG
908 ret = pm_runtime_get_sync(dev->dev);
909 if (IS_ERR_VALUE(ret))
910 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
b67f4487
C
911 davinci_mcasp_start(dev, substream->stream);
912 break;
913
b67f4487 914 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 915 davinci_mcasp_stop(dev, substream->stream);
10884347
HG
916 ret = pm_runtime_put_sync(dev->dev);
917 if (IS_ERR_VALUE(ret))
918 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
a47979b5
C
919 break;
920
921 case SNDRV_PCM_TRIGGER_STOP:
b67f4487
C
922 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
923 davinci_mcasp_stop(dev, substream->stream);
924 break;
925
926 default:
927 ret = -EINVAL;
928 }
929
930 return ret;
931}
932
bedad0ca
CPE
933static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
934 struct snd_soc_dai *dai)
935{
936 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
937
938 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
939 return 0;
940}
941
85e7652d 942static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
bedad0ca 943 .startup = davinci_mcasp_startup,
b67f4487
C
944 .trigger = davinci_mcasp_trigger,
945 .hw_params = davinci_mcasp_hw_params,
946 .set_fmt = davinci_mcasp_set_dai_fmt,
4ed8c9b7 947 .set_clkdiv = davinci_mcasp_set_clkdiv,
5b66aa2d 948 .set_sysclk = davinci_mcasp_set_sysclk,
b67f4487
C
949};
950
0a9d1385
BG
951#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
952 SNDRV_PCM_FMTBIT_U8 | \
953 SNDRV_PCM_FMTBIT_S16_LE | \
954 SNDRV_PCM_FMTBIT_U16_LE | \
21eb24d8
DM
955 SNDRV_PCM_FMTBIT_S24_LE | \
956 SNDRV_PCM_FMTBIT_U24_LE | \
957 SNDRV_PCM_FMTBIT_S24_3LE | \
958 SNDRV_PCM_FMTBIT_U24_3LE | \
0a9d1385
BG
959 SNDRV_PCM_FMTBIT_S32_LE | \
960 SNDRV_PCM_FMTBIT_U32_LE)
961
f0fba2ad 962static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 963 {
f0fba2ad 964 .name = "davinci-mcasp.0",
b67f4487
C
965 .playback = {
966 .channels_min = 2,
967 .channels_max = 2,
968 .rates = DAVINCI_MCASP_RATES,
0a9d1385 969 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C
970 },
971 .capture = {
972 .channels_min = 2,
973 .channels_max = 2,
974 .rates = DAVINCI_MCASP_RATES,
0a9d1385 975 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C
976 },
977 .ops = &davinci_mcasp_dai_ops,
978
979 },
980 {
f0fba2ad 981 "davinci-mcasp.1",
b67f4487
C
982 .playback = {
983 .channels_min = 1,
984 .channels_max = 384,
985 .rates = DAVINCI_MCASP_RATES,
0a9d1385 986 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C
987 },
988 .ops = &davinci_mcasp_dai_ops,
989 },
990
991};
b67f4487 992
3e3b8c34
HG
993static const struct of_device_id mcasp_dt_ids[] = {
994 {
995 .compatible = "ti,dm646x-mcasp-audio",
996 .data = (void *)MCASP_VERSION_1,
997 },
998 {
999 .compatible = "ti,da830-mcasp-audio",
1000 .data = (void *)MCASP_VERSION_2,
1001 },
e5ec69da
HG
1002 {
1003 .compatible = "ti,omap2-mcasp-audio",
1004 .data = (void *)MCASP_VERSION_3,
1005 },
3e3b8c34
HG
1006 { /* sentinel */ }
1007};
1008MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1009
1010static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
1011 struct platform_device *pdev)
1012{
1013 struct device_node *np = pdev->dev.of_node;
1014 struct snd_platform_data *pdata = NULL;
1015 const struct of_device_id *match =
1016 of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
1017
1018 const u32 *of_serial_dir32;
1019 u8 *of_serial_dir;
1020 u32 val;
1021 int i, ret = 0;
1022
1023 if (pdev->dev.platform_data) {
1024 pdata = pdev->dev.platform_data;
1025 return pdata;
1026 } else if (match) {
1027 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1028 if (!pdata) {
1029 ret = -ENOMEM;
1030 goto nodata;
1031 }
1032 } else {
1033 /* control shouldn't reach here. something is wrong */
1034 ret = -EINVAL;
1035 goto nodata;
1036 }
1037
1038 if (match->data)
1039 pdata->version = (u8)((int)match->data);
1040
1041 ret = of_property_read_u32(np, "op-mode", &val);
1042 if (ret >= 0)
1043 pdata->op_mode = val;
1044
1045 ret = of_property_read_u32(np, "tdm-slots", &val);
1046 if (ret >= 0)
1047 pdata->tdm_slots = val;
1048
1049 ret = of_property_read_u32(np, "num-serializer", &val);
1050 if (ret >= 0)
1051 pdata->num_serializer = val;
1052
1053 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1054 val /= sizeof(u32);
1055 if (val != pdata->num_serializer) {
1056 dev_err(&pdev->dev,
1057 "num-serializer(%d) != serial-dir size(%d)\n",
1058 pdata->num_serializer, val);
1059 ret = -EINVAL;
1060 goto nodata;
1061 }
1062
1063 if (of_serial_dir32) {
1064 of_serial_dir = devm_kzalloc(&pdev->dev,
1065 (sizeof(*of_serial_dir) * val),
1066 GFP_KERNEL);
1067 if (!of_serial_dir) {
1068 ret = -ENOMEM;
1069 goto nodata;
1070 }
1071
1072 for (i = 0; i < pdata->num_serializer; i++)
1073 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1074
1075 pdata->serial_dir = of_serial_dir;
1076 }
1077
1078 ret = of_property_read_u32(np, "tx-num-evt", &val);
1079 if (ret >= 0)
1080 pdata->txnumevt = val;
1081
1082 ret = of_property_read_u32(np, "rx-num-evt", &val);
1083 if (ret >= 0)
1084 pdata->rxnumevt = val;
1085
1086 ret = of_property_read_u32(np, "sram-size-playback", &val);
1087 if (ret >= 0)
1088 pdata->sram_size_playback = val;
1089
1090 ret = of_property_read_u32(np, "sram-size-capture", &val);
1091 if (ret >= 0)
1092 pdata->sram_size_capture = val;
1093
1094 return pdata;
1095
1096nodata:
1097 if (ret < 0) {
1098 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1099 ret);
1100 pdata = NULL;
1101 }
1102 return pdata;
1103}
1104
b67f4487
C
1105static int davinci_mcasp_probe(struct platform_device *pdev)
1106{
1107 struct davinci_pcm_dma_params *dma_data;
1108 struct resource *mem, *ioarea, *res;
1109 struct snd_platform_data *pdata;
1110 struct davinci_audio_dev *dev;
96d31e2b 1111 int ret;
b67f4487 1112
3e3b8c34
HG
1113 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1114 dev_err(&pdev->dev, "No platform data supplied\n");
1115 return -EINVAL;
1116 }
1117
96d31e2b
JL
1118 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1119 GFP_KERNEL);
b67f4487
C
1120 if (!dev)
1121 return -ENOMEM;
1122
3e3b8c34
HG
1123 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1124 if (!pdata) {
1125 dev_err(&pdev->dev, "no platform data\n");
1126 return -EINVAL;
1127 }
1128
b67f4487
C
1129 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1130 if (!mem) {
1131 dev_err(&pdev->dev, "no mem resource?\n");
96d31e2b 1132 return -ENODEV;
b67f4487
C
1133 }
1134
96d31e2b 1135 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
d852f446 1136 resource_size(mem), pdev->name);
b67f4487
C
1137 if (!ioarea) {
1138 dev_err(&pdev->dev, "Audio region already claimed\n");
96d31e2b 1139 return -EBUSY;
b67f4487
C
1140 }
1141
10884347 1142 pm_runtime_enable(&pdev->dev);
b67f4487 1143
10884347
HG
1144 ret = pm_runtime_get_sync(&pdev->dev);
1145 if (IS_ERR_VALUE(ret)) {
1146 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1147 return ret;
1148 }
b67f4487 1149
96d31e2b 1150 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
4f82f028
VB
1151 if (!dev->base) {
1152 dev_err(&pdev->dev, "ioremap failed\n");
1153 ret = -ENOMEM;
1154 goto err_release_clk;
1155 }
1156
b67f4487
C
1157 dev->op_mode = pdata->op_mode;
1158 dev->tdm_slots = pdata->tdm_slots;
1159 dev->num_serializer = pdata->num_serializer;
1160 dev->serial_dir = pdata->serial_dir;
1161 dev->codec_fmt = pdata->codec_fmt;
6a99fb5f
C
1162 dev->version = pdata->version;
1163 dev->txnumevt = pdata->txnumevt;
1164 dev->rxnumevt = pdata->rxnumevt;
10884347 1165 dev->dev = &pdev->dev;
b67f4487 1166
92e2a6f6 1167 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
48519f0a
SN
1168 dma_data->asp_chan_q = pdata->asp_chan_q;
1169 dma_data->ram_chan_q = pdata->ram_chan_q;
a0c83263 1170 dma_data->sram_size = pdata->sram_size_playback;
92e2a6f6 1171 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
4f82f028 1172 mem->start);
b67f4487
C
1173
1174 /* first TX, then RX */
1175 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1176 if (!res) {
1177 dev_err(&pdev->dev, "no DMA resource\n");
02ffc5f3 1178 ret = -ENODEV;
96d31e2b 1179 goto err_release_clk;
b67f4487
C
1180 }
1181
92e2a6f6
TK
1182 dma_data->channel = res->start;
1183
1184 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
48519f0a
SN
1185 dma_data->asp_chan_q = pdata->asp_chan_q;
1186 dma_data->ram_chan_q = pdata->ram_chan_q;
a0c83263 1187 dma_data->sram_size = pdata->sram_size_capture;
92e2a6f6 1188 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
4f82f028 1189 mem->start);
b67f4487
C
1190
1191 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1192 if (!res) {
1193 dev_err(&pdev->dev, "no DMA resource\n");
02ffc5f3 1194 ret = -ENODEV;
96d31e2b 1195 goto err_release_clk;
b67f4487
C
1196 }
1197
92e2a6f6 1198 dma_data->channel = res->start;
f0fba2ad
LG
1199 dev_set_drvdata(&pdev->dev, dev);
1200 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
b67f4487
C
1201
1202 if (ret != 0)
96d31e2b 1203 goto err_release_clk;
f08095a4
HG
1204
1205 ret = davinci_soc_platform_register(&pdev->dev);
1206 if (ret) {
1207 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1208 goto err_unregister_dai;
1209 }
1210
b67f4487
C
1211 return 0;
1212
f08095a4
HG
1213err_unregister_dai:
1214 snd_soc_unregister_dai(&pdev->dev);
eef6d7b8 1215err_release_clk:
10884347
HG
1216 pm_runtime_put_sync(&pdev->dev);
1217 pm_runtime_disable(&pdev->dev);
b67f4487
C
1218 return ret;
1219}
1220
1221static int davinci_mcasp_remove(struct platform_device *pdev)
1222{
b67f4487 1223
f0fba2ad 1224 snd_soc_unregister_dai(&pdev->dev);
f08095a4 1225 davinci_soc_platform_unregister(&pdev->dev);
10884347
HG
1226
1227 pm_runtime_put_sync(&pdev->dev);
1228 pm_runtime_disable(&pdev->dev);
b67f4487 1229
b67f4487
C
1230 return 0;
1231}
1232
1233static struct platform_driver davinci_mcasp_driver = {
1234 .probe = davinci_mcasp_probe,
1235 .remove = davinci_mcasp_remove,
1236 .driver = {
1237 .name = "davinci-mcasp",
1238 .owner = THIS_MODULE,
3e3b8c34 1239 .of_match_table = of_match_ptr(mcasp_dt_ids),
b67f4487
C
1240 },
1241};
1242
f9b8a514 1243module_platform_driver(davinci_mcasp_driver);
b67f4487
C
1244
1245MODULE_AUTHOR("Steve Chen");
1246MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1247MODULE_LICENSE("GPL");
1248