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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
b67f4487 | 29 | |
6479285d | 30 | #include <sound/asoundef.h> |
b67f4487 C |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/initval.h> | |
35 | #include <sound/soc.h> | |
453c4990 | 36 | #include <sound/dmaengine_pcm.h> |
87c19364 | 37 | #include <sound/omap-pcm.h> |
b67f4487 C |
38 | |
39 | #include "davinci-pcm.h" | |
f3f9cfa8 | 40 | #include "edma-pcm.h" |
b67f4487 C |
41 | #include "davinci-mcasp.h" |
42 | ||
0bf0e8ae PU |
43 | #define MCASP_MAX_AFIFO_DEPTH 64 |
44 | ||
1cc0c054 PU |
45 | static u32 context_regs[] = { |
46 | DAVINCI_MCASP_TXFMCTL_REG, | |
47 | DAVINCI_MCASP_RXFMCTL_REG, | |
48 | DAVINCI_MCASP_TXFMT_REG, | |
49 | DAVINCI_MCASP_RXFMT_REG, | |
50 | DAVINCI_MCASP_ACLKXCTL_REG, | |
51 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
52 | DAVINCI_MCASP_AHCLKXCTL_REG, |
53 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 54 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
55 | DAVINCI_MCASP_RXMASK_REG, |
56 | DAVINCI_MCASP_TXMASK_REG, | |
57 | DAVINCI_MCASP_RXTDM_REG, | |
58 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
59 | }; |
60 | ||
790bb94b | 61 | struct davinci_mcasp_context { |
1cc0c054 | 62 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
63 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
64 | u32 *xrsr_regs; /* for serializer configuration */ | |
790bb94b PU |
65 | }; |
66 | ||
70091a3e | 67 | struct davinci_mcasp { |
21400a72 | 68 | struct davinci_pcm_dma_params dma_params[2]; |
453c4990 | 69 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 70 | void __iomem *base; |
487dce88 | 71 | u32 fifo_base; |
21400a72 PU |
72 | struct device *dev; |
73 | ||
74 | /* McASP specific data */ | |
75 | int tdm_slots; | |
76 | u8 op_mode; | |
77 | u8 num_serializer; | |
78 | u8 *serial_dir; | |
79 | u8 version; | |
8267525c | 80 | u8 bclk_div; |
21400a72 | 81 | u16 bclk_lrclk_ratio; |
4dcb5a0b | 82 | int streams; |
21400a72 | 83 | |
ab8b14b6 JS |
84 | int sysclk_freq; |
85 | bool bclk_master; | |
86 | ||
21400a72 PU |
87 | /* McASP FIFO related */ |
88 | u8 txnumevt; | |
89 | u8 rxnumevt; | |
90 | ||
cbc7956c PU |
91 | bool dat_port; |
92 | ||
21400a72 | 93 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 94 | struct davinci_mcasp_context context; |
21400a72 PU |
95 | #endif |
96 | }; | |
97 | ||
f68205a7 PU |
98 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
99 | u32 val) | |
b67f4487 | 100 | { |
f68205a7 | 101 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
102 | __raw_writel(__raw_readl(reg) | val, reg); |
103 | } | |
104 | ||
f68205a7 PU |
105 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
106 | u32 val) | |
b67f4487 | 107 | { |
f68205a7 | 108 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
109 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
110 | } | |
111 | ||
f68205a7 PU |
112 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
113 | u32 val, u32 mask) | |
b67f4487 | 114 | { |
f68205a7 | 115 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
116 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
117 | } | |
118 | ||
f68205a7 PU |
119 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
120 | u32 val) | |
b67f4487 | 121 | { |
f68205a7 | 122 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
123 | } |
124 | ||
f68205a7 | 125 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 126 | { |
f68205a7 | 127 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
128 | } |
129 | ||
f68205a7 | 130 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
131 | { |
132 | int i = 0; | |
133 | ||
f68205a7 | 134 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
135 | |
136 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
137 | /* loop count is to avoid the lock-up */ | |
138 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 139 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
140 | break; |
141 | } | |
142 | ||
f68205a7 | 143 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
144 | printk(KERN_ERR "GBLCTL write error\n"); |
145 | } | |
146 | ||
4dcb5a0b PU |
147 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
148 | { | |
f68205a7 PU |
149 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
150 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
151 | |
152 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
153 | } | |
154 | ||
70091a3e | 155 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 156 | { |
44982735 | 157 | /* Start clocks */ |
f68205a7 PU |
158 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
159 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
160 | /* |
161 | * When ASYNC == 0 the transmit and receive sections operate | |
162 | * synchronously from the transmit clock and frame sync. We need to make | |
163 | * sure that the TX signlas are enabled when starting reception. | |
164 | */ | |
165 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
166 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
167 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
168 | } |
169 | ||
44982735 | 170 | /* Activate serializer(s) */ |
f68205a7 | 171 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 172 | /* Release RX state machine */ |
f68205a7 | 173 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 174 | /* Release Frame Sync generator */ |
f68205a7 | 175 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 176 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 177 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
b67f4487 C |
178 | } |
179 | ||
70091a3e | 180 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 181 | { |
6a99fb5f C |
182 | u32 cnt; |
183 | ||
36bcecd0 | 184 | /* Start clocks */ |
f68205a7 PU |
185 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
186 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
36bcecd0 | 187 | /* Activate serializer(s) */ |
f68205a7 | 188 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 189 | |
36bcecd0 | 190 | /* wait for XDATA to be cleared */ |
6a99fb5f | 191 | cnt = 0; |
36bcecd0 PU |
192 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & |
193 | ~XRDATA) && (cnt < 100000)) | |
6a99fb5f C |
194 | cnt++; |
195 | ||
36bcecd0 PU |
196 | /* Release TX state machine */ |
197 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
198 | /* Release Frame Sync generator */ | |
199 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
b67f4487 C |
200 | } |
201 | ||
70091a3e | 202 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 203 | { |
487dce88 PU |
204 | u32 reg; |
205 | ||
4dcb5a0b PU |
206 | mcasp->streams++; |
207 | ||
539d3d8c | 208 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 209 | if (mcasp->txnumevt) { /* enable FIFO */ |
487dce88 | 210 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 PU |
211 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
212 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 213 | } |
70091a3e | 214 | mcasp_start_tx(mcasp); |
539d3d8c | 215 | } else { |
70091a3e | 216 | if (mcasp->rxnumevt) { /* enable FIFO */ |
487dce88 | 217 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 PU |
218 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
219 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 220 | } |
70091a3e | 221 | mcasp_start_rx(mcasp); |
539d3d8c | 222 | } |
b67f4487 C |
223 | } |
224 | ||
70091a3e | 225 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 226 | { |
4dcb5a0b PU |
227 | /* |
228 | * In synchronous mode stop the TX clocks if no other stream is | |
229 | * running | |
230 | */ | |
231 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 232 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 233 | |
f68205a7 PU |
234 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
235 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
236 | } |
237 | ||
70091a3e | 238 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 239 | { |
4dcb5a0b PU |
240 | u32 val = 0; |
241 | ||
242 | /* | |
243 | * In synchronous mode keep TX clocks running if the capture stream is | |
244 | * still running. | |
245 | */ | |
246 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
247 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
248 | ||
f68205a7 PU |
249 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
250 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
251 | } |
252 | ||
70091a3e | 253 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 254 | { |
487dce88 PU |
255 | u32 reg; |
256 | ||
4dcb5a0b PU |
257 | mcasp->streams--; |
258 | ||
539d3d8c | 259 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 260 | if (mcasp->txnumevt) { /* disable FIFO */ |
487dce88 | 261 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 | 262 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 263 | } |
70091a3e | 264 | mcasp_stop_tx(mcasp); |
539d3d8c | 265 | } else { |
70091a3e | 266 | if (mcasp->rxnumevt) { /* disable FIFO */ |
487dce88 | 267 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 | 268 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 269 | } |
70091a3e | 270 | mcasp_stop_rx(mcasp); |
539d3d8c | 271 | } |
b67f4487 C |
272 | } |
273 | ||
274 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
275 | unsigned int fmt) | |
276 | { | |
70091a3e | 277 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 278 | int ret = 0; |
6dfa9a4e | 279 | u32 data_delay; |
83f12503 | 280 | bool fs_pol_rising; |
ffd950f7 | 281 | bool inv_fs = false; |
b67f4487 | 282 | |
1d17a04e | 283 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 284 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
285 | case SND_SOC_DAIFMT_DSP_A: |
286 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
287 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
288 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
289 | data_delay = 1; | |
290 | break; | |
5296cf2d DM |
291 | case SND_SOC_DAIFMT_DSP_B: |
292 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
293 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
294 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
295 | /* No delay after FS */ |
296 | data_delay = 0; | |
5296cf2d | 297 | break; |
ffd950f7 | 298 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 299 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
300 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
301 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
302 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
303 | data_delay = 1; | |
ffd950f7 PU |
304 | /* FS need to be inverted */ |
305 | inv_fs = true; | |
5296cf2d | 306 | break; |
423761e0 PU |
307 | case SND_SOC_DAIFMT_LEFT_J: |
308 | /* configure a full-word SYNC pulse (LRCLK) */ | |
309 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
310 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
311 | /* No delay after FS */ | |
312 | data_delay = 0; | |
313 | break; | |
ffd950f7 PU |
314 | default: |
315 | ret = -EINVAL; | |
316 | goto out; | |
5296cf2d DM |
317 | } |
318 | ||
6dfa9a4e PU |
319 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
320 | FSXDLY(3)); | |
321 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
322 | FSRDLY(3)); | |
323 | ||
b67f4487 C |
324 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
325 | case SND_SOC_DAIFMT_CBS_CFS: | |
326 | /* codec is clock and frame slave */ | |
f68205a7 PU |
327 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
328 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 329 | |
f68205a7 PU |
330 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
331 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 332 | |
f68205a7 PU |
333 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
334 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 335 | mcasp->bclk_master = 1; |
b67f4487 | 336 | break; |
517ee6cf C |
337 | case SND_SOC_DAIFMT_CBM_CFS: |
338 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
339 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
340 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 341 | |
f68205a7 PU |
342 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
343 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 344 | |
f68205a7 PU |
345 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
346 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 347 | mcasp->bclk_master = 0; |
517ee6cf | 348 | break; |
b67f4487 C |
349 | case SND_SOC_DAIFMT_CBM_CFM: |
350 | /* codec is clock and frame master */ | |
f68205a7 PU |
351 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
352 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 353 | |
f68205a7 PU |
354 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
355 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 356 | |
f68205a7 PU |
357 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
358 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 359 | mcasp->bclk_master = 0; |
b67f4487 | 360 | break; |
b67f4487 | 361 | default: |
1d17a04e PU |
362 | ret = -EINVAL; |
363 | goto out; | |
b67f4487 C |
364 | } |
365 | ||
366 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
367 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 368 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 369 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 370 | fs_pol_rising = true; |
b67f4487 | 371 | break; |
b67f4487 | 372 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 373 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 374 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 375 | fs_pol_rising = false; |
b67f4487 | 376 | break; |
b67f4487 | 377 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 378 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 379 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 380 | fs_pol_rising = false; |
b67f4487 | 381 | break; |
b67f4487 | 382 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 383 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 384 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 385 | fs_pol_rising = true; |
b67f4487 | 386 | break; |
b67f4487 | 387 | default: |
1d17a04e | 388 | ret = -EINVAL; |
83f12503 PU |
389 | goto out; |
390 | } | |
391 | ||
ffd950f7 PU |
392 | if (inv_fs) |
393 | fs_pol_rising = !fs_pol_rising; | |
394 | ||
83f12503 PU |
395 | if (fs_pol_rising) { |
396 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
397 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
398 | } else { | |
399 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
400 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 401 | } |
1d17a04e PU |
402 | out: |
403 | pm_runtime_put_sync(mcasp->dev); | |
404 | return ret; | |
b67f4487 C |
405 | } |
406 | ||
8813543e JS |
407 | static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
408 | int div, bool explicit) | |
4ed8c9b7 | 409 | { |
70091a3e | 410 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
411 | |
412 | switch (div_id) { | |
413 | case 0: /* MCLK divider */ | |
f68205a7 | 414 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 415 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 416 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
417 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
418 | break; | |
419 | ||
420 | case 1: /* BCLK divider */ | |
f68205a7 | 421 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 422 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 423 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 424 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
425 | if (explicit) |
426 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
427 | break; |
428 | ||
1b3bc060 | 429 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 430 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
431 | break; |
432 | ||
4ed8c9b7 DM |
433 | default: |
434 | return -EINVAL; | |
435 | } | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
8813543e JS |
440 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
441 | int div) | |
442 | { | |
443 | return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1); | |
444 | } | |
445 | ||
5b66aa2d DM |
446 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
447 | unsigned int freq, int dir) | |
448 | { | |
70091a3e | 449 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
450 | |
451 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
452 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
453 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
454 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 455 | } else { |
f68205a7 PU |
456 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
457 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
458 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
459 | } |
460 | ||
ab8b14b6 JS |
461 | mcasp->sysclk_freq = freq; |
462 | ||
5b66aa2d DM |
463 | return 0; |
464 | } | |
465 | ||
70091a3e | 466 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 467 | int word_length) |
b67f4487 | 468 | { |
ba764b3d | 469 | u32 fmt; |
79671892 | 470 | u32 tx_rotate = (word_length / 4) & 0x7; |
ba764b3d | 471 | u32 mask = (1ULL << word_length) - 1; |
fe0a29e1 PU |
472 | /* |
473 | * For captured data we should not rotate, inversion and masking is | |
474 | * enoguh to get the data to the right position: | |
475 | * Format data from bus after reverse (XRBUF) | |
476 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
477 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
478 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
479 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
480 | */ | |
481 | u32 rx_rotate = 0; | |
b67f4487 | 482 | |
1b3bc060 DM |
483 | /* |
484 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
485 | * callback, take it into account here. That allows us to for example | |
486 | * send 32 bits per channel to the codec, while only 16 of them carry | |
487 | * audio payload. | |
d486fea6 MB |
488 | * The clock ratio is given for a full period of data (for I2S format |
489 | * both left and right channels), so it has to be divided by number of | |
490 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 491 | */ |
70091a3e PU |
492 | if (mcasp->bclk_lrclk_ratio) |
493 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
1b3bc060 | 494 | |
ba764b3d DM |
495 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
496 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 497 | |
70091a3e | 498 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
499 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
500 | RXSSZ(0x0F)); | |
501 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
502 | TXSSZ(0x0F)); | |
503 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
504 | TXROT(7)); | |
505 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
506 | RXROT(7)); | |
507 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
508 | } |
509 | ||
f68205a7 | 510 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 511 | |
b67f4487 C |
512 | return 0; |
513 | } | |
514 | ||
662ffae9 | 515 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 516 | int period_words, int channels) |
b67f4487 | 517 | { |
5f04c603 PU |
518 | struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream]; |
519 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; | |
b67f4487 | 520 | int i; |
6a99fb5f C |
521 | u8 tx_ser = 0; |
522 | u8 rx_ser = 0; | |
70091a3e | 523 | u8 slots = mcasp->tdm_slots; |
2952b27e | 524 | u8 max_active_serializers = (channels + slots - 1) / slots; |
dd093a0f | 525 | int active_serializers, numevt, n; |
487dce88 | 526 | u32 reg; |
b67f4487 | 527 | /* Default configuration */ |
40448e5e | 528 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 529 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
530 | |
531 | /* All PINS as McASP */ | |
f68205a7 | 532 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
533 | |
534 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
535 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
536 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 537 | } else { |
f68205a7 PU |
538 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
539 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
540 | } |
541 | ||
70091a3e | 542 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
543 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
544 | mcasp->serial_dir[i]); | |
70091a3e | 545 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 546 | tx_ser < max_active_serializers) { |
f68205a7 | 547 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 548 | tx_ser++; |
70091a3e | 549 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 550 | rx_ser < max_active_serializers) { |
f68205a7 | 551 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 552 | rx_ser++; |
2952b27e | 553 | } else { |
f68205a7 PU |
554 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
555 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
556 | } |
557 | } | |
558 | ||
0bf0e8ae PU |
559 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
560 | active_serializers = tx_ser; | |
561 | numevt = mcasp->txnumevt; | |
562 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
563 | } else { | |
564 | active_serializers = rx_ser; | |
565 | numevt = mcasp->rxnumevt; | |
566 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
567 | } | |
ecf327c7 | 568 | |
0bf0e8ae | 569 | if (active_serializers < max_active_serializers) { |
70091a3e | 570 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
571 | "enabled in mcasp (%d)\n", channels, |
572 | active_serializers * slots); | |
ecf327c7 DM |
573 | return -EINVAL; |
574 | } | |
575 | ||
0bf0e8ae | 576 | /* AFIFO is not in use */ |
5f04c603 PU |
577 | if (!numevt) { |
578 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
579 | if (active_serializers > 1) { |
580 | /* | |
581 | * If more than one serializers are in use we have one | |
582 | * DMA request to provide data for all serializers. | |
583 | * For example if three serializers are enabled the DMA | |
584 | * need to transfer three words per DMA request. | |
585 | */ | |
586 | dma_params->fifo_level = active_serializers; | |
587 | dma_data->maxburst = active_serializers; | |
588 | } else { | |
589 | dma_params->fifo_level = 0; | |
590 | dma_data->maxburst = 0; | |
591 | } | |
0bf0e8ae | 592 | return 0; |
5f04c603 | 593 | } |
6a99fb5f | 594 | |
dd093a0f PU |
595 | if (period_words % active_serializers) { |
596 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
597 | "active serializers: %d, %d\n", period_words, | |
598 | active_serializers); | |
599 | return -EINVAL; | |
600 | } | |
601 | ||
602 | /* | |
603 | * Calculate the optimal AFIFO depth for platform side: | |
604 | * The number of words for numevt need to be in steps of active | |
605 | * serializers. | |
606 | */ | |
607 | n = numevt % active_serializers; | |
608 | if (n) | |
609 | numevt += (active_serializers - n); | |
610 | while (period_words % numevt && numevt > 0) | |
611 | numevt -= active_serializers; | |
612 | if (numevt <= 0) | |
0bf0e8ae | 613 | numevt = active_serializers; |
487dce88 | 614 | |
0bf0e8ae PU |
615 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
616 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 617 | |
5f04c603 | 618 | /* Configure the burst size for platform drivers */ |
33445643 PU |
619 | if (numevt == 1) |
620 | numevt = 0; | |
5f04c603 PU |
621 | dma_params->fifo_level = numevt; |
622 | dma_data->maxburst = numevt; | |
623 | ||
2952b27e | 624 | return 0; |
b67f4487 C |
625 | } |
626 | ||
2c56c4c2 | 627 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
b67f4487 C |
628 | { |
629 | int i, active_slots; | |
630 | u32 mask = 0; | |
cbc7956c | 631 | u32 busel = 0; |
b67f4487 | 632 | |
2c56c4c2 PU |
633 | if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) { |
634 | dev_err(mcasp->dev, "tdm slot %d not supported\n", | |
635 | mcasp->tdm_slots); | |
636 | return -EINVAL; | |
637 | } | |
638 | ||
70091a3e | 639 | active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; |
b67f4487 C |
640 | for (i = 0; i < active_slots; i++) |
641 | mask |= (1 << i); | |
642 | ||
f68205a7 | 643 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 644 | |
cbc7956c PU |
645 | if (!mcasp->dat_port) |
646 | busel = TXSEL; | |
647 | ||
2c56c4c2 PU |
648 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
649 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
650 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
651 | FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); | |
652 | ||
653 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
654 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
655 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
656 | FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); | |
657 | ||
658 | return 0; | |
b67f4487 C |
659 | } |
660 | ||
661 | /* S/PDIF */ | |
6479285d DM |
662 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
663 | unsigned int rate) | |
b67f4487 | 664 | { |
6479285d DM |
665 | u32 cs_value = 0; |
666 | u8 *cs_bytes = (u8*) &cs_value; | |
667 | ||
b67f4487 C |
668 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
669 | and LSB first */ | |
f68205a7 | 670 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
671 | |
672 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 673 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
674 | |
675 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 676 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
677 | |
678 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 679 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 680 | |
f68205a7 | 681 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
682 | |
683 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 684 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
685 | |
686 | /* Enable the DIT */ | |
f68205a7 | 687 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 688 | |
6479285d DM |
689 | /* Set S/PDIF channel status bits */ |
690 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
691 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
692 | ||
693 | switch (rate) { | |
694 | case 22050: | |
695 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
696 | break; | |
697 | case 24000: | |
698 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
699 | break; | |
700 | case 32000: | |
701 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
702 | break; | |
703 | case 44100: | |
704 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
705 | break; | |
706 | case 48000: | |
707 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
708 | break; | |
709 | case 88200: | |
710 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
711 | break; | |
712 | case 96000: | |
713 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
714 | break; | |
715 | case 176400: | |
716 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
717 | break; | |
718 | case 192000: | |
719 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
720 | break; | |
721 | default: | |
722 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
723 | return -EINVAL; | |
724 | } | |
725 | ||
726 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
727 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
728 | ||
2c56c4c2 | 729 | return 0; |
b67f4487 C |
730 | } |
731 | ||
732 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
733 | struct snd_pcm_hw_params *params, | |
734 | struct snd_soc_dai *cpu_dai) | |
735 | { | |
70091a3e | 736 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 737 | struct davinci_pcm_dma_params *dma_params = |
70091a3e | 738 | &mcasp->dma_params[substream->stream]; |
b67f4487 | 739 | int word_length; |
a7e46bd9 | 740 | int channels = params_channels(params); |
dd093a0f | 741 | int period_size = params_period_size(params); |
2c56c4c2 | 742 | int ret; |
ab8b14b6 | 743 | |
8267525c DM |
744 | /* |
745 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
746 | * the machine driver, we need to calculate the ratio. | |
747 | */ | |
748 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
ab8b14b6 | 749 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); |
0929878f | 750 | unsigned int div = mcasp->sysclk_freq / bclk_freq; |
ab8b14b6 | 751 | if (mcasp->sysclk_freq % bclk_freq != 0) { |
0929878f JS |
752 | if (((mcasp->sysclk_freq / div) - bclk_freq) > |
753 | (bclk_freq - (mcasp->sysclk_freq / (div+1)))) | |
754 | div++; | |
755 | dev_warn(mcasp->dev, | |
756 | "Inaccurate BCLK: %u Hz / %u != %u Hz\n", | |
757 | mcasp->sysclk_freq, div, bclk_freq); | |
ab8b14b6 | 758 | } |
8813543e | 759 | __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0); |
ab8b14b6 JS |
760 | } |
761 | ||
dd093a0f PU |
762 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
763 | period_size * channels, channels); | |
0f7d9a63 PU |
764 | if (ret) |
765 | return ret; | |
766 | ||
70091a3e | 767 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 768 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 769 | else |
2c56c4c2 PU |
770 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
771 | ||
772 | if (ret) | |
773 | return ret; | |
b67f4487 C |
774 | |
775 | switch (params_format(params)) { | |
0a9d1385 | 776 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
777 | case SNDRV_PCM_FORMAT_S8: |
778 | dma_params->data_type = 1; | |
ba764b3d | 779 | word_length = 8; |
b67f4487 C |
780 | break; |
781 | ||
0a9d1385 | 782 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
783 | case SNDRV_PCM_FORMAT_S16_LE: |
784 | dma_params->data_type = 2; | |
ba764b3d | 785 | word_length = 16; |
b67f4487 C |
786 | break; |
787 | ||
21eb24d8 DM |
788 | case SNDRV_PCM_FORMAT_U24_3LE: |
789 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 790 | dma_params->data_type = 3; |
ba764b3d | 791 | word_length = 24; |
21eb24d8 DM |
792 | break; |
793 | ||
6b7fa011 DM |
794 | case SNDRV_PCM_FORMAT_U24_LE: |
795 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
796 | dma_params->data_type = 4; |
797 | word_length = 24; | |
798 | break; | |
799 | ||
0a9d1385 | 800 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
801 | case SNDRV_PCM_FORMAT_S32_LE: |
802 | dma_params->data_type = 4; | |
ba764b3d | 803 | word_length = 32; |
b67f4487 C |
804 | break; |
805 | ||
806 | default: | |
807 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
808 | return -EINVAL; | |
809 | } | |
6a99fb5f | 810 | |
5f04c603 | 811 | if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level) |
4fa9c1a5 C |
812 | dma_params->acnt = 4; |
813 | else | |
6a99fb5f C |
814 | dma_params->acnt = dma_params->data_type; |
815 | ||
70091a3e | 816 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 C |
817 | |
818 | return 0; | |
819 | } | |
820 | ||
821 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
822 | int cmd, struct snd_soc_dai *cpu_dai) | |
823 | { | |
70091a3e | 824 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
825 | int ret = 0; |
826 | ||
827 | switch (cmd) { | |
b67f4487 | 828 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
829 | case SNDRV_PCM_TRIGGER_START: |
830 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 831 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 832 | break; |
b67f4487 | 833 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 834 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 835 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 836 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
837 | break; |
838 | ||
839 | default: | |
840 | ret = -EINVAL; | |
841 | } | |
842 | ||
843 | return ret; | |
844 | } | |
845 | ||
85e7652d | 846 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
b67f4487 C |
847 | .trigger = davinci_mcasp_trigger, |
848 | .hw_params = davinci_mcasp_hw_params, | |
849 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 850 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 851 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
852 | }; |
853 | ||
d5902f69 PU |
854 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
855 | { | |
856 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
857 | ||
f3f9cfa8 | 858 | if (mcasp->version >= MCASP_VERSION_3) { |
d5902f69 PU |
859 | /* Using dmaengine PCM */ |
860 | dai->playback_dma_data = | |
861 | &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; | |
862 | dai->capture_dma_data = | |
863 | &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
864 | } else { | |
865 | /* Using davinci-pcm */ | |
866 | dai->playback_dma_data = mcasp->dma_params; | |
867 | dai->capture_dma_data = mcasp->dma_params; | |
868 | } | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
135014ad PU |
873 | #ifdef CONFIG_PM_SLEEP |
874 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
875 | { | |
876 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 877 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 878 | u32 reg; |
1cc0c054 | 879 | int i; |
135014ad | 880 | |
1cc0c054 PU |
881 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
882 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 883 | |
f114ce60 PU |
884 | if (mcasp->txnumevt) { |
885 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
886 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
887 | } | |
888 | if (mcasp->rxnumevt) { | |
889 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
890 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
891 | } | |
135014ad | 892 | |
f114ce60 PU |
893 | for (i = 0; i < mcasp->num_serializer; i++) |
894 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
895 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad PU |
896 | |
897 | return 0; | |
898 | } | |
899 | ||
900 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
901 | { | |
902 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 903 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 904 | u32 reg; |
1cc0c054 | 905 | int i; |
790bb94b | 906 | |
1cc0c054 PU |
907 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
908 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 909 | |
f114ce60 PU |
910 | if (mcasp->txnumevt) { |
911 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
912 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
913 | } | |
914 | if (mcasp->rxnumevt) { | |
915 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
916 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
917 | } | |
790bb94b | 918 | |
f114ce60 PU |
919 | for (i = 0; i < mcasp->num_serializer; i++) |
920 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
921 | context->xrsr_regs[i]); | |
135014ad PU |
922 | |
923 | return 0; | |
924 | } | |
925 | #else | |
926 | #define davinci_mcasp_suspend NULL | |
927 | #define davinci_mcasp_resume NULL | |
928 | #endif | |
929 | ||
ed29cd5e PU |
930 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
931 | ||
0a9d1385 BG |
932 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
933 | SNDRV_PCM_FMTBIT_U8 | \ | |
934 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
935 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
936 | SNDRV_PCM_FMTBIT_S24_LE | \ |
937 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
938 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
939 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
940 | SNDRV_PCM_FMTBIT_S32_LE | \ |
941 | SNDRV_PCM_FMTBIT_U32_LE) | |
942 | ||
f0fba2ad | 943 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 944 | { |
f0fba2ad | 945 | .name = "davinci-mcasp.0", |
d5902f69 | 946 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
947 | .suspend = davinci_mcasp_suspend, |
948 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
949 | .playback = { |
950 | .channels_min = 2, | |
2952b27e | 951 | .channels_max = 32 * 16, |
b67f4487 | 952 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 953 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
954 | }, |
955 | .capture = { | |
956 | .channels_min = 2, | |
2952b27e | 957 | .channels_max = 32 * 16, |
b67f4487 | 958 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 959 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
960 | }, |
961 | .ops = &davinci_mcasp_dai_ops, | |
962 | ||
963 | }, | |
964 | { | |
58e48d97 | 965 | .name = "davinci-mcasp.1", |
d5902f69 | 966 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
967 | .playback = { |
968 | .channels_min = 1, | |
969 | .channels_max = 384, | |
970 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 971 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
972 | }, |
973 | .ops = &davinci_mcasp_dai_ops, | |
974 | }, | |
975 | ||
976 | }; | |
b67f4487 | 977 | |
eeef0eda KM |
978 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
979 | .name = "davinci-mcasp", | |
980 | }; | |
981 | ||
256ba181 | 982 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 983 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
984 | .tx_dma_offset = 0x400, |
985 | .rx_dma_offset = 0x400, | |
986 | .asp_chan_q = EVENTQ_0, | |
987 | .version = MCASP_VERSION_1, | |
988 | }; | |
989 | ||
d1debafc | 990 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
991 | .tx_dma_offset = 0x2000, |
992 | .rx_dma_offset = 0x2000, | |
993 | .asp_chan_q = EVENTQ_0, | |
994 | .version = MCASP_VERSION_2, | |
995 | }; | |
996 | ||
d1debafc | 997 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
998 | .tx_dma_offset = 0, |
999 | .rx_dma_offset = 0, | |
1000 | .asp_chan_q = EVENTQ_0, | |
1001 | .version = MCASP_VERSION_3, | |
1002 | }; | |
1003 | ||
d1debafc | 1004 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
1005 | .tx_dma_offset = 0x200, |
1006 | .rx_dma_offset = 0x284, | |
1007 | .asp_chan_q = EVENTQ_0, | |
1008 | .version = MCASP_VERSION_4, | |
1009 | }; | |
1010 | ||
3e3b8c34 HG |
1011 | static const struct of_device_id mcasp_dt_ids[] = { |
1012 | { | |
1013 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1014 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1015 | }, |
1016 | { | |
1017 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1018 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1019 | }, |
e5ec69da | 1020 | { |
3af9e031 | 1021 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1022 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1023 | }, |
453c4990 PU |
1024 | { |
1025 | .compatible = "ti,dra7-mcasp-audio", | |
1026 | .data = &dra7_mcasp_pdata, | |
1027 | }, | |
3e3b8c34 HG |
1028 | { /* sentinel */ } |
1029 | }; | |
1030 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1031 | ||
ae726e93 PU |
1032 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1033 | { | |
1034 | struct device_node *node = pdev->dev.of_node; | |
1035 | struct clk *gfclk, *parent_clk; | |
1036 | const char *parent_name; | |
1037 | int ret; | |
1038 | ||
1039 | if (!node) | |
1040 | return 0; | |
1041 | ||
1042 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1043 | if (!parent_name) | |
1044 | return 0; | |
1045 | ||
1046 | gfclk = clk_get(&pdev->dev, "fck"); | |
1047 | if (IS_ERR(gfclk)) { | |
1048 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1049 | return PTR_ERR(gfclk); | |
1050 | } | |
1051 | ||
1052 | parent_clk = clk_get(NULL, parent_name); | |
1053 | if (IS_ERR(parent_clk)) { | |
1054 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1055 | ret = PTR_ERR(parent_clk); | |
1056 | goto err1; | |
1057 | } | |
1058 | ||
1059 | ret = clk_set_parent(gfclk, parent_clk); | |
1060 | if (ret) { | |
1061 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1062 | goto err2; | |
1063 | } | |
1064 | ||
1065 | err2: | |
1066 | clk_put(parent_clk); | |
1067 | err1: | |
1068 | clk_put(gfclk); | |
1069 | return ret; | |
1070 | } | |
1071 | ||
d1debafc | 1072 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1073 | struct platform_device *pdev) |
1074 | { | |
1075 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1076 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1077 | const struct of_device_id *match = |
ea421eb1 | 1078 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1079 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1080 | |
1081 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1082 | u32 val; |
1083 | int i, ret = 0; | |
1084 | ||
1085 | if (pdev->dev.platform_data) { | |
1086 | pdata = pdev->dev.platform_data; | |
1087 | return pdata; | |
1088 | } else if (match) { | |
d1debafc | 1089 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1090 | } else { |
1091 | /* control shouldn't reach here. something is wrong */ | |
1092 | ret = -EINVAL; | |
1093 | goto nodata; | |
1094 | } | |
1095 | ||
3e3b8c34 HG |
1096 | ret = of_property_read_u32(np, "op-mode", &val); |
1097 | if (ret >= 0) | |
1098 | pdata->op_mode = val; | |
1099 | ||
1100 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1101 | if (ret >= 0) { |
1102 | if (val < 2 || val > 32) { | |
1103 | dev_err(&pdev->dev, | |
1104 | "tdm-slots must be in rage [2-32]\n"); | |
1105 | ret = -EINVAL; | |
1106 | goto nodata; | |
1107 | } | |
1108 | ||
3e3b8c34 | 1109 | pdata->tdm_slots = val; |
2952b27e | 1110 | } |
3e3b8c34 | 1111 | |
3e3b8c34 HG |
1112 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1113 | val /= sizeof(u32); | |
3e3b8c34 | 1114 | if (of_serial_dir32) { |
1427e660 PU |
1115 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1116 | (sizeof(*of_serial_dir) * val), | |
1117 | GFP_KERNEL); | |
3e3b8c34 HG |
1118 | if (!of_serial_dir) { |
1119 | ret = -ENOMEM; | |
1120 | goto nodata; | |
1121 | } | |
1122 | ||
1427e660 | 1123 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1124 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1125 | ||
1427e660 | 1126 | pdata->num_serializer = val; |
3e3b8c34 HG |
1127 | pdata->serial_dir = of_serial_dir; |
1128 | } | |
1129 | ||
4023fe6f JS |
1130 | ret = of_property_match_string(np, "dma-names", "tx"); |
1131 | if (ret < 0) | |
1132 | goto nodata; | |
1133 | ||
1134 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1135 | &dma_spec); | |
1136 | if (ret < 0) | |
1137 | goto nodata; | |
1138 | ||
1139 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1140 | ||
1141 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1142 | if (ret < 0) | |
1143 | goto nodata; | |
1144 | ||
1145 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1146 | &dma_spec); | |
1147 | if (ret < 0) | |
1148 | goto nodata; | |
1149 | ||
1150 | pdata->rx_dma_channel = dma_spec.args[0]; | |
1151 | ||
3e3b8c34 HG |
1152 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1153 | if (ret >= 0) | |
1154 | pdata->txnumevt = val; | |
1155 | ||
1156 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1157 | if (ret >= 0) | |
1158 | pdata->rxnumevt = val; | |
1159 | ||
1160 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1161 | if (ret >= 0) | |
1162 | pdata->sram_size_playback = val; | |
1163 | ||
1164 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1165 | if (ret >= 0) | |
1166 | pdata->sram_size_capture = val; | |
1167 | ||
1168 | return pdata; | |
1169 | ||
1170 | nodata: | |
1171 | if (ret < 0) { | |
1172 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1173 | ret); | |
1174 | pdata = NULL; | |
1175 | } | |
1176 | return pdata; | |
1177 | } | |
1178 | ||
b67f4487 C |
1179 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1180 | { | |
64ebdec3 | 1181 | struct davinci_pcm_dma_params *dma_params; |
8de131f2 | 1182 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1183 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1184 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1185 | struct davinci_mcasp *mcasp; |
96d31e2b | 1186 | int ret; |
b67f4487 | 1187 | |
3e3b8c34 HG |
1188 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1189 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1190 | return -EINVAL; | |
1191 | } | |
1192 | ||
70091a3e | 1193 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1194 | GFP_KERNEL); |
70091a3e | 1195 | if (!mcasp) |
b67f4487 C |
1196 | return -ENOMEM; |
1197 | ||
3e3b8c34 HG |
1198 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1199 | if (!pdata) { | |
1200 | dev_err(&pdev->dev, "no platform data\n"); | |
1201 | return -EINVAL; | |
1202 | } | |
1203 | ||
256ba181 | 1204 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1205 | if (!mem) { |
70091a3e | 1206 | dev_warn(mcasp->dev, |
256ba181 JS |
1207 | "\"mpu\" mem resource not found, using index 0\n"); |
1208 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1209 | if (!mem) { | |
1210 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1211 | return -ENODEV; | |
1212 | } | |
b67f4487 C |
1213 | } |
1214 | ||
96d31e2b | 1215 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1216 | resource_size(mem), pdev->name); |
b67f4487 C |
1217 | if (!ioarea) { |
1218 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1219 | return -EBUSY; |
b67f4487 C |
1220 | } |
1221 | ||
10884347 | 1222 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1223 | |
10884347 HG |
1224 | ret = pm_runtime_get_sync(&pdev->dev); |
1225 | if (IS_ERR_VALUE(ret)) { | |
1226 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
1227 | return ret; | |
1228 | } | |
b67f4487 | 1229 | |
70091a3e PU |
1230 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1231 | if (!mcasp->base) { | |
4f82f028 VB |
1232 | dev_err(&pdev->dev, "ioremap failed\n"); |
1233 | ret = -ENOMEM; | |
b6bb3709 | 1234 | goto err; |
4f82f028 VB |
1235 | } |
1236 | ||
70091a3e PU |
1237 | mcasp->op_mode = pdata->op_mode; |
1238 | mcasp->tdm_slots = pdata->tdm_slots; | |
1239 | mcasp->num_serializer = pdata->num_serializer; | |
f114ce60 PU |
1240 | #ifdef CONFIG_PM_SLEEP |
1241 | mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, | |
1242 | sizeof(u32) * mcasp->num_serializer, | |
1243 | GFP_KERNEL); | |
1244 | #endif | |
70091a3e PU |
1245 | mcasp->serial_dir = pdata->serial_dir; |
1246 | mcasp->version = pdata->version; | |
1247 | mcasp->txnumevt = pdata->txnumevt; | |
1248 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1249 | |
70091a3e | 1250 | mcasp->dev = &pdev->dev; |
b67f4487 | 1251 | |
256ba181 | 1252 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1253 | if (dat) |
1254 | mcasp->dat_port = true; | |
256ba181 | 1255 | |
64ebdec3 | 1256 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
8de131f2 | 1257 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
64ebdec3 PU |
1258 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1259 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1260 | dma_params->sram_pool = pdata->sram_pool; | |
1261 | dma_params->sram_size = pdata->sram_size_playback; | |
cbc7956c | 1262 | if (dat) |
64ebdec3 | 1263 | dma_params->dma_addr = dat->start; |
cbc7956c | 1264 | else |
64ebdec3 | 1265 | dma_params->dma_addr = mem->start + pdata->tx_dma_offset; |
b67f4487 | 1266 | |
453c4990 | 1267 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1268 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1269 | |
b67f4487 | 1270 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1271 | if (res) |
64ebdec3 | 1272 | dma_params->channel = res->start; |
4023fe6f | 1273 | else |
64ebdec3 | 1274 | dma_params->channel = pdata->tx_dma_channel; |
92e2a6f6 | 1275 | |
8de131f2 PU |
1276 | /* dmaengine filter data for DT and non-DT boot */ |
1277 | if (pdev->dev.of_node) | |
1278 | dma_data->filter_data = "tx"; | |
1279 | else | |
1280 | dma_data->filter_data = &dma_params->channel; | |
1281 | ||
64ebdec3 | 1282 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
8de131f2 | 1283 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
64ebdec3 PU |
1284 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1285 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1286 | dma_params->sram_pool = pdata->sram_pool; | |
1287 | dma_params->sram_size = pdata->sram_size_capture; | |
cbc7956c | 1288 | if (dat) |
64ebdec3 | 1289 | dma_params->dma_addr = dat->start; |
cbc7956c | 1290 | else |
64ebdec3 | 1291 | dma_params->dma_addr = mem->start + pdata->rx_dma_offset; |
cbc7956c | 1292 | |
453c4990 | 1293 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1294 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1295 | |
cbc7956c PU |
1296 | if (mcasp->version < MCASP_VERSION_3) { |
1297 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1298 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1299 | mcasp->dat_port = true; |
1300 | } else { | |
1301 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1302 | } | |
b67f4487 C |
1303 | |
1304 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
4023fe6f | 1305 | if (res) |
64ebdec3 | 1306 | dma_params->channel = res->start; |
4023fe6f | 1307 | else |
64ebdec3 | 1308 | dma_params->channel = pdata->rx_dma_channel; |
b67f4487 | 1309 | |
8de131f2 PU |
1310 | /* dmaengine filter data for DT and non-DT boot */ |
1311 | if (pdev->dev.of_node) | |
1312 | dma_data->filter_data = "rx"; | |
1313 | else | |
1314 | dma_data->filter_data = &dma_params->channel; | |
453c4990 | 1315 | |
70091a3e | 1316 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1317 | |
1318 | mcasp_reparent_fck(pdev); | |
1319 | ||
b6bb3709 PU |
1320 | ret = devm_snd_soc_register_component(&pdev->dev, |
1321 | &davinci_mcasp_component, | |
1322 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1323 | |
1324 | if (ret != 0) | |
b6bb3709 | 1325 | goto err; |
f08095a4 | 1326 | |
d5c6c59a | 1327 | switch (mcasp->version) { |
7f28f357 JS |
1328 | #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \ |
1329 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1330 | IS_MODULE(CONFIG_SND_DAVINCI_SOC)) | |
d5c6c59a PU |
1331 | case MCASP_VERSION_1: |
1332 | case MCASP_VERSION_2: | |
453c4990 | 1333 | ret = davinci_soc_platform_register(&pdev->dev); |
d5c6c59a | 1334 | break; |
7f28f357 | 1335 | #endif |
f3f9cfa8 PU |
1336 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1337 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1338 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
1339 | case MCASP_VERSION_3: | |
1340 | ret = edma_pcm_platform_register(&pdev->dev); | |
1341 | break; | |
1342 | #endif | |
7f28f357 JS |
1343 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
1344 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1345 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a PU |
1346 | case MCASP_VERSION_4: |
1347 | ret = omap_pcm_platform_register(&pdev->dev); | |
1348 | break; | |
7f28f357 | 1349 | #endif |
d5c6c59a PU |
1350 | default: |
1351 | dev_err(&pdev->dev, "Invalid McASP version: %d\n", | |
1352 | mcasp->version); | |
1353 | ret = -EINVAL; | |
1354 | break; | |
1355 | } | |
1356 | ||
1357 | if (ret) { | |
1358 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 1359 | goto err; |
f08095a4 HG |
1360 | } |
1361 | ||
b67f4487 C |
1362 | return 0; |
1363 | ||
b6bb3709 | 1364 | err: |
10884347 HG |
1365 | pm_runtime_put_sync(&pdev->dev); |
1366 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1367 | return ret; |
1368 | } | |
1369 | ||
1370 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1371 | { | |
10884347 HG |
1372 | pm_runtime_put_sync(&pdev->dev); |
1373 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1374 | |
b67f4487 C |
1375 | return 0; |
1376 | } | |
1377 | ||
1378 | static struct platform_driver davinci_mcasp_driver = { | |
1379 | .probe = davinci_mcasp_probe, | |
1380 | .remove = davinci_mcasp_remove, | |
1381 | .driver = { | |
1382 | .name = "davinci-mcasp", | |
1383 | .owner = THIS_MODULE, | |
ea421eb1 | 1384 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1385 | }, |
1386 | }; | |
1387 | ||
f9b8a514 | 1388 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1389 | |
1390 | MODULE_AUTHOR("Steve Chen"); | |
1391 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1392 | MODULE_LICENSE("GPL"); |