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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
b67f4487 C |
29 | |
30 | #include <sound/core.h> | |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/initval.h> | |
34 | #include <sound/soc.h> | |
453c4990 | 35 | #include <sound/dmaengine_pcm.h> |
b67f4487 C |
36 | |
37 | #include "davinci-pcm.h" | |
38 | #include "davinci-mcasp.h" | |
39 | ||
0bf0e8ae PU |
40 | #define MCASP_MAX_AFIFO_DEPTH 64 |
41 | ||
790bb94b PU |
42 | struct davinci_mcasp_context { |
43 | u32 txfmtctl; | |
44 | u32 rxfmtctl; | |
45 | u32 txfmt; | |
46 | u32 rxfmt; | |
47 | u32 aclkxctl; | |
48 | u32 aclkrctl; | |
49 | u32 pdir; | |
50 | }; | |
51 | ||
70091a3e | 52 | struct davinci_mcasp { |
21400a72 | 53 | struct davinci_pcm_dma_params dma_params[2]; |
453c4990 | 54 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 55 | void __iomem *base; |
487dce88 | 56 | u32 fifo_base; |
21400a72 PU |
57 | struct device *dev; |
58 | ||
59 | /* McASP specific data */ | |
60 | int tdm_slots; | |
61 | u8 op_mode; | |
62 | u8 num_serializer; | |
63 | u8 *serial_dir; | |
64 | u8 version; | |
65 | u16 bclk_lrclk_ratio; | |
4dcb5a0b | 66 | int streams; |
21400a72 | 67 | |
ab8b14b6 JS |
68 | int sysclk_freq; |
69 | bool bclk_master; | |
70 | ||
21400a72 PU |
71 | /* McASP FIFO related */ |
72 | u8 txnumevt; | |
73 | u8 rxnumevt; | |
74 | ||
cbc7956c PU |
75 | bool dat_port; |
76 | ||
21400a72 | 77 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 78 | struct davinci_mcasp_context context; |
21400a72 PU |
79 | #endif |
80 | }; | |
81 | ||
f68205a7 PU |
82 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
83 | u32 val) | |
b67f4487 | 84 | { |
f68205a7 | 85 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
86 | __raw_writel(__raw_readl(reg) | val, reg); |
87 | } | |
88 | ||
f68205a7 PU |
89 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
90 | u32 val) | |
b67f4487 | 91 | { |
f68205a7 | 92 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
93 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
94 | } | |
95 | ||
f68205a7 PU |
96 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
97 | u32 val, u32 mask) | |
b67f4487 | 98 | { |
f68205a7 | 99 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
100 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
101 | } | |
102 | ||
f68205a7 PU |
103 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
104 | u32 val) | |
b67f4487 | 105 | { |
f68205a7 | 106 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
107 | } |
108 | ||
f68205a7 | 109 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 110 | { |
f68205a7 | 111 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
112 | } |
113 | ||
f68205a7 | 114 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
115 | { |
116 | int i = 0; | |
117 | ||
f68205a7 | 118 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
119 | |
120 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
121 | /* loop count is to avoid the lock-up */ | |
122 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 123 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
124 | break; |
125 | } | |
126 | ||
f68205a7 | 127 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
128 | printk(KERN_ERR "GBLCTL write error\n"); |
129 | } | |
130 | ||
4dcb5a0b PU |
131 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
132 | { | |
f68205a7 PU |
133 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
134 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
135 | |
136 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
137 | } | |
138 | ||
70091a3e | 139 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 140 | { |
f68205a7 PU |
141 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
142 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
143 | |
144 | /* | |
145 | * When ASYNC == 0 the transmit and receive sections operate | |
146 | * synchronously from the transmit clock and frame sync. We need to make | |
147 | * sure that the TX signlas are enabled when starting reception. | |
148 | */ | |
149 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
150 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
151 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
152 | } |
153 | ||
f68205a7 PU |
154 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
155 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); | |
b67f4487 | 156 | |
f68205a7 PU |
157 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
158 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
159 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); | |
b67f4487 | 160 | |
f68205a7 PU |
161 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
162 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
4dcb5a0b PU |
163 | |
164 | if (mcasp_is_synchronous(mcasp)) | |
f68205a7 | 165 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
b67f4487 C |
166 | } |
167 | ||
70091a3e | 168 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 169 | { |
6a99fb5f C |
170 | u8 offset = 0, i; |
171 | u32 cnt; | |
172 | ||
f68205a7 PU |
173 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
174 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
175 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); | |
176 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); | |
b67f4487 | 177 | |
f68205a7 PU |
178 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); |
179 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
180 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); | |
70091a3e PU |
181 | for (i = 0; i < mcasp->num_serializer; i++) { |
182 | if (mcasp->serial_dir[i] == TX_MODE) { | |
6a99fb5f C |
183 | offset = i; |
184 | break; | |
185 | } | |
186 | } | |
187 | ||
188 | /* wait for TX ready */ | |
189 | cnt = 0; | |
f68205a7 | 190 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) & |
6a99fb5f C |
191 | TXSTATE) && (cnt < 100000)) |
192 | cnt++; | |
193 | ||
f68205a7 | 194 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
b67f4487 C |
195 | } |
196 | ||
70091a3e | 197 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 198 | { |
487dce88 PU |
199 | u32 reg; |
200 | ||
4dcb5a0b PU |
201 | mcasp->streams++; |
202 | ||
539d3d8c | 203 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 204 | if (mcasp->txnumevt) { /* enable FIFO */ |
487dce88 | 205 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 PU |
206 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
207 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 208 | } |
70091a3e | 209 | mcasp_start_tx(mcasp); |
539d3d8c | 210 | } else { |
70091a3e | 211 | if (mcasp->rxnumevt) { /* enable FIFO */ |
487dce88 | 212 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 PU |
213 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
214 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 215 | } |
70091a3e | 216 | mcasp_start_rx(mcasp); |
539d3d8c | 217 | } |
b67f4487 C |
218 | } |
219 | ||
70091a3e | 220 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 221 | { |
4dcb5a0b PU |
222 | /* |
223 | * In synchronous mode stop the TX clocks if no other stream is | |
224 | * running | |
225 | */ | |
226 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 227 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 228 | |
f68205a7 PU |
229 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
230 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
231 | } |
232 | ||
70091a3e | 233 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 234 | { |
4dcb5a0b PU |
235 | u32 val = 0; |
236 | ||
237 | /* | |
238 | * In synchronous mode keep TX clocks running if the capture stream is | |
239 | * still running. | |
240 | */ | |
241 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
242 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
243 | ||
f68205a7 PU |
244 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
245 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
246 | } |
247 | ||
70091a3e | 248 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 249 | { |
487dce88 PU |
250 | u32 reg; |
251 | ||
4dcb5a0b PU |
252 | mcasp->streams--; |
253 | ||
539d3d8c | 254 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 255 | if (mcasp->txnumevt) { /* disable FIFO */ |
487dce88 | 256 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 | 257 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 258 | } |
70091a3e | 259 | mcasp_stop_tx(mcasp); |
539d3d8c | 260 | } else { |
70091a3e | 261 | if (mcasp->rxnumevt) { /* disable FIFO */ |
487dce88 | 262 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 | 263 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 264 | } |
70091a3e | 265 | mcasp_stop_rx(mcasp); |
539d3d8c | 266 | } |
b67f4487 C |
267 | } |
268 | ||
269 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
270 | unsigned int fmt) | |
271 | { | |
70091a3e | 272 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 273 | int ret = 0; |
6dfa9a4e | 274 | u32 data_delay; |
83f12503 | 275 | bool fs_pol_rising; |
b67f4487 | 276 | |
1d17a04e | 277 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 278 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
279 | case SND_SOC_DAIFMT_DSP_A: |
280 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
281 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
282 | ||
283 | /* 1st data bit occur one ACLK cycle after the frame sync */ | |
284 | data_delay = 1; | |
285 | break; | |
5296cf2d DM |
286 | case SND_SOC_DAIFMT_DSP_B: |
287 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
288 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
289 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
290 | |
291 | /* No delay after FS */ | |
292 | data_delay = 0; | |
5296cf2d DM |
293 | break; |
294 | default: | |
295 | /* configure a full-word SYNC pulse (LRCLK) */ | |
f68205a7 PU |
296 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
297 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
5296cf2d | 298 | |
6dfa9a4e PU |
299 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
300 | data_delay = 1; | |
5296cf2d DM |
301 | break; |
302 | } | |
303 | ||
6dfa9a4e PU |
304 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
305 | FSXDLY(3)); | |
306 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
307 | FSRDLY(3)); | |
308 | ||
b67f4487 C |
309 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
310 | case SND_SOC_DAIFMT_CBS_CFS: | |
311 | /* codec is clock and frame slave */ | |
f68205a7 PU |
312 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
313 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 314 | |
f68205a7 PU |
315 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
316 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 317 | |
f68205a7 PU |
318 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
319 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 320 | mcasp->bclk_master = 1; |
b67f4487 | 321 | break; |
517ee6cf C |
322 | case SND_SOC_DAIFMT_CBM_CFS: |
323 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
324 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
325 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 326 | |
f68205a7 PU |
327 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
328 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 329 | |
f68205a7 PU |
330 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
331 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 332 | mcasp->bclk_master = 0; |
517ee6cf | 333 | break; |
b67f4487 C |
334 | case SND_SOC_DAIFMT_CBM_CFM: |
335 | /* codec is clock and frame master */ | |
f68205a7 PU |
336 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
337 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 338 | |
f68205a7 PU |
339 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
340 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 341 | |
f68205a7 PU |
342 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
343 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 344 | mcasp->bclk_master = 0; |
b67f4487 C |
345 | break; |
346 | ||
347 | default: | |
1d17a04e PU |
348 | ret = -EINVAL; |
349 | goto out; | |
b67f4487 C |
350 | } |
351 | ||
352 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
353 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 354 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 355 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 356 | fs_pol_rising = true; |
b67f4487 C |
357 | break; |
358 | ||
359 | case SND_SOC_DAIFMT_NB_IF: | |
f68205a7 | 360 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 361 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 362 | fs_pol_rising = false; |
b67f4487 C |
363 | break; |
364 | ||
365 | case SND_SOC_DAIFMT_IB_IF: | |
f68205a7 | 366 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 367 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 368 | fs_pol_rising = false; |
b67f4487 C |
369 | break; |
370 | ||
371 | case SND_SOC_DAIFMT_NB_NF: | |
f68205a7 | 372 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 373 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 374 | fs_pol_rising = true; |
b67f4487 C |
375 | break; |
376 | ||
377 | default: | |
1d17a04e | 378 | ret = -EINVAL; |
83f12503 PU |
379 | goto out; |
380 | } | |
381 | ||
382 | if (fs_pol_rising) { | |
383 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
384 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
385 | } else { | |
386 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
387 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 388 | } |
1d17a04e PU |
389 | out: |
390 | pm_runtime_put_sync(mcasp->dev); | |
391 | return ret; | |
b67f4487 C |
392 | } |
393 | ||
4ed8c9b7 DM |
394 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) |
395 | { | |
70091a3e | 396 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
397 | |
398 | switch (div_id) { | |
399 | case 0: /* MCLK divider */ | |
f68205a7 | 400 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 401 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 402 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
403 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
404 | break; | |
405 | ||
406 | case 1: /* BCLK divider */ | |
f68205a7 | 407 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 408 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 409 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 DM |
410 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
411 | break; | |
412 | ||
1b3bc060 | 413 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 414 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
415 | break; |
416 | ||
4ed8c9b7 DM |
417 | default: |
418 | return -EINVAL; | |
419 | } | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
5b66aa2d DM |
424 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
425 | unsigned int freq, int dir) | |
426 | { | |
70091a3e | 427 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
428 | |
429 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
430 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
431 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
432 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 433 | } else { |
f68205a7 PU |
434 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
435 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
436 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
437 | } |
438 | ||
ab8b14b6 JS |
439 | mcasp->sysclk_freq = freq; |
440 | ||
5b66aa2d DM |
441 | return 0; |
442 | } | |
443 | ||
70091a3e | 444 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 445 | int word_length) |
b67f4487 | 446 | { |
ba764b3d | 447 | u32 fmt; |
79671892 DM |
448 | u32 tx_rotate = (word_length / 4) & 0x7; |
449 | u32 rx_rotate = (32 - word_length) / 4; | |
ba764b3d | 450 | u32 mask = (1ULL << word_length) - 1; |
b67f4487 | 451 | |
1b3bc060 DM |
452 | /* |
453 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
454 | * callback, take it into account here. That allows us to for example | |
455 | * send 32 bits per channel to the codec, while only 16 of them carry | |
456 | * audio payload. | |
d486fea6 MB |
457 | * The clock ratio is given for a full period of data (for I2S format |
458 | * both left and right channels), so it has to be divided by number of | |
459 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 460 | */ |
70091a3e PU |
461 | if (mcasp->bclk_lrclk_ratio) |
462 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
1b3bc060 | 463 | |
ba764b3d DM |
464 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
465 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 466 | |
70091a3e | 467 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
468 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
469 | RXSSZ(0x0F)); | |
470 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
471 | TXSSZ(0x0F)); | |
472 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
473 | TXROT(7)); | |
474 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
475 | RXROT(7)); | |
476 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
477 | } |
478 | ||
f68205a7 | 479 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 480 | |
b67f4487 C |
481 | return 0; |
482 | } | |
483 | ||
662ffae9 | 484 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 485 | int period_words, int channels) |
b67f4487 | 486 | { |
5f04c603 PU |
487 | struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream]; |
488 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; | |
b67f4487 | 489 | int i; |
6a99fb5f C |
490 | u8 tx_ser = 0; |
491 | u8 rx_ser = 0; | |
70091a3e | 492 | u8 slots = mcasp->tdm_slots; |
2952b27e | 493 | u8 max_active_serializers = (channels + slots - 1) / slots; |
dd093a0f | 494 | int active_serializers, numevt, n; |
487dce88 | 495 | u32 reg; |
b67f4487 | 496 | /* Default configuration */ |
453c4990 | 497 | if (mcasp->version != MCASP_VERSION_4) |
f68205a7 | 498 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
499 | |
500 | /* All PINS as McASP */ | |
f68205a7 | 501 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
502 | |
503 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
504 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
505 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 506 | } else { |
f68205a7 PU |
507 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
508 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
509 | } |
510 | ||
70091a3e | 511 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
512 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
513 | mcasp->serial_dir[i]); | |
70091a3e | 514 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 515 | tx_ser < max_active_serializers) { |
f68205a7 | 516 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 517 | tx_ser++; |
70091a3e | 518 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 519 | rx_ser < max_active_serializers) { |
f68205a7 | 520 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 521 | rx_ser++; |
2952b27e | 522 | } else { |
f68205a7 PU |
523 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
524 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
525 | } |
526 | } | |
527 | ||
0bf0e8ae PU |
528 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
529 | active_serializers = tx_ser; | |
530 | numevt = mcasp->txnumevt; | |
531 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
532 | } else { | |
533 | active_serializers = rx_ser; | |
534 | numevt = mcasp->rxnumevt; | |
535 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
536 | } | |
ecf327c7 | 537 | |
0bf0e8ae | 538 | if (active_serializers < max_active_serializers) { |
70091a3e | 539 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
540 | "enabled in mcasp (%d)\n", channels, |
541 | active_serializers * slots); | |
ecf327c7 DM |
542 | return -EINVAL; |
543 | } | |
544 | ||
0bf0e8ae | 545 | /* AFIFO is not in use */ |
5f04c603 PU |
546 | if (!numevt) { |
547 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
548 | if (active_serializers > 1) { |
549 | /* | |
550 | * If more than one serializers are in use we have one | |
551 | * DMA request to provide data for all serializers. | |
552 | * For example if three serializers are enabled the DMA | |
553 | * need to transfer three words per DMA request. | |
554 | */ | |
555 | dma_params->fifo_level = active_serializers; | |
556 | dma_data->maxburst = active_serializers; | |
557 | } else { | |
558 | dma_params->fifo_level = 0; | |
559 | dma_data->maxburst = 0; | |
560 | } | |
0bf0e8ae | 561 | return 0; |
5f04c603 | 562 | } |
6a99fb5f | 563 | |
dd093a0f PU |
564 | if (period_words % active_serializers) { |
565 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
566 | "active serializers: %d, %d\n", period_words, | |
567 | active_serializers); | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
571 | /* | |
572 | * Calculate the optimal AFIFO depth for platform side: | |
573 | * The number of words for numevt need to be in steps of active | |
574 | * serializers. | |
575 | */ | |
576 | n = numevt % active_serializers; | |
577 | if (n) | |
578 | numevt += (active_serializers - n); | |
579 | while (period_words % numevt && numevt > 0) | |
580 | numevt -= active_serializers; | |
581 | if (numevt <= 0) | |
0bf0e8ae | 582 | numevt = active_serializers; |
487dce88 | 583 | |
0bf0e8ae PU |
584 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
585 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 586 | |
5f04c603 | 587 | /* Configure the burst size for platform drivers */ |
33445643 PU |
588 | if (numevt == 1) |
589 | numevt = 0; | |
5f04c603 PU |
590 | dma_params->fifo_level = numevt; |
591 | dma_data->maxburst = numevt; | |
592 | ||
2952b27e | 593 | return 0; |
b67f4487 C |
594 | } |
595 | ||
2c56c4c2 | 596 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
b67f4487 C |
597 | { |
598 | int i, active_slots; | |
599 | u32 mask = 0; | |
cbc7956c | 600 | u32 busel = 0; |
b67f4487 | 601 | |
2c56c4c2 PU |
602 | if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) { |
603 | dev_err(mcasp->dev, "tdm slot %d not supported\n", | |
604 | mcasp->tdm_slots); | |
605 | return -EINVAL; | |
606 | } | |
607 | ||
70091a3e | 608 | active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; |
b67f4487 C |
609 | for (i = 0; i < active_slots; i++) |
610 | mask |= (1 << i); | |
611 | ||
f68205a7 | 612 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 613 | |
cbc7956c PU |
614 | if (!mcasp->dat_port) |
615 | busel = TXSEL; | |
616 | ||
2c56c4c2 PU |
617 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
618 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
619 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
620 | FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); | |
621 | ||
622 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
623 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
624 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
625 | FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); | |
626 | ||
627 | return 0; | |
b67f4487 C |
628 | } |
629 | ||
630 | /* S/PDIF */ | |
2c56c4c2 | 631 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp) |
b67f4487 | 632 | { |
b67f4487 C |
633 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
634 | and LSB first */ | |
f68205a7 | 635 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
636 | |
637 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 638 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
639 | |
640 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 641 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
642 | |
643 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 644 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 645 | |
f68205a7 | 646 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
647 | |
648 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 649 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
650 | |
651 | /* Enable the DIT */ | |
f68205a7 | 652 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 PU |
653 | |
654 | return 0; | |
b67f4487 C |
655 | } |
656 | ||
657 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
658 | struct snd_pcm_hw_params *params, | |
659 | struct snd_soc_dai *cpu_dai) | |
660 | { | |
70091a3e | 661 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 662 | struct davinci_pcm_dma_params *dma_params = |
70091a3e | 663 | &mcasp->dma_params[substream->stream]; |
b67f4487 | 664 | int word_length; |
a7e46bd9 | 665 | int channels = params_channels(params); |
dd093a0f | 666 | int period_size = params_period_size(params); |
2c56c4c2 | 667 | int ret; |
ab8b14b6 JS |
668 | |
669 | /* If mcasp is BCLK master we need to set BCLK divider */ | |
670 | if (mcasp->bclk_master) { | |
671 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); | |
672 | if (mcasp->sysclk_freq % bclk_freq != 0) { | |
f5b02b4a | 673 | dev_err(mcasp->dev, "Can't produce required BCLK\n"); |
ab8b14b6 JS |
674 | return -EINVAL; |
675 | } | |
676 | davinci_mcasp_set_clkdiv( | |
677 | cpu_dai, 1, mcasp->sysclk_freq / bclk_freq); | |
678 | } | |
679 | ||
dd093a0f PU |
680 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
681 | period_size * channels, channels); | |
0f7d9a63 PU |
682 | if (ret) |
683 | return ret; | |
684 | ||
70091a3e | 685 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
2c56c4c2 | 686 | ret = mcasp_dit_hw_param(mcasp); |
b67f4487 | 687 | else |
2c56c4c2 PU |
688 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
689 | ||
690 | if (ret) | |
691 | return ret; | |
b67f4487 C |
692 | |
693 | switch (params_format(params)) { | |
0a9d1385 | 694 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
695 | case SNDRV_PCM_FORMAT_S8: |
696 | dma_params->data_type = 1; | |
ba764b3d | 697 | word_length = 8; |
b67f4487 C |
698 | break; |
699 | ||
0a9d1385 | 700 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
701 | case SNDRV_PCM_FORMAT_S16_LE: |
702 | dma_params->data_type = 2; | |
ba764b3d | 703 | word_length = 16; |
b67f4487 C |
704 | break; |
705 | ||
21eb24d8 DM |
706 | case SNDRV_PCM_FORMAT_U24_3LE: |
707 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 708 | dma_params->data_type = 3; |
ba764b3d | 709 | word_length = 24; |
21eb24d8 DM |
710 | break; |
711 | ||
6b7fa011 DM |
712 | case SNDRV_PCM_FORMAT_U24_LE: |
713 | case SNDRV_PCM_FORMAT_S24_LE: | |
0a9d1385 | 714 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
715 | case SNDRV_PCM_FORMAT_S32_LE: |
716 | dma_params->data_type = 4; | |
ba764b3d | 717 | word_length = 32; |
b67f4487 C |
718 | break; |
719 | ||
720 | default: | |
721 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
722 | return -EINVAL; | |
723 | } | |
6a99fb5f | 724 | |
5f04c603 | 725 | if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level) |
4fa9c1a5 C |
726 | dma_params->acnt = 4; |
727 | else | |
6a99fb5f C |
728 | dma_params->acnt = dma_params->data_type; |
729 | ||
70091a3e | 730 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 C |
731 | |
732 | return 0; | |
733 | } | |
734 | ||
735 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
736 | int cmd, struct snd_soc_dai *cpu_dai) | |
737 | { | |
70091a3e | 738 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
739 | int ret = 0; |
740 | ||
741 | switch (cmd) { | |
b67f4487 | 742 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
743 | case SNDRV_PCM_TRIGGER_START: |
744 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 745 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 746 | break; |
b67f4487 | 747 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 748 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 749 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 750 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
751 | break; |
752 | ||
753 | default: | |
754 | ret = -EINVAL; | |
755 | } | |
756 | ||
757 | return ret; | |
758 | } | |
759 | ||
85e7652d | 760 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
b67f4487 C |
761 | .trigger = davinci_mcasp_trigger, |
762 | .hw_params = davinci_mcasp_hw_params, | |
763 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 764 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 765 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
766 | }; |
767 | ||
d5902f69 PU |
768 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
769 | { | |
770 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
771 | ||
772 | if (mcasp->version == MCASP_VERSION_4) { | |
773 | /* Using dmaengine PCM */ | |
774 | dai->playback_dma_data = | |
775 | &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; | |
776 | dai->capture_dma_data = | |
777 | &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
778 | } else { | |
779 | /* Using davinci-pcm */ | |
780 | dai->playback_dma_data = mcasp->dma_params; | |
781 | dai->capture_dma_data = mcasp->dma_params; | |
782 | } | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
135014ad PU |
787 | #ifdef CONFIG_PM_SLEEP |
788 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
789 | { | |
790 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 791 | struct davinci_mcasp_context *context = &mcasp->context; |
135014ad | 792 | |
790bb94b PU |
793 | context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG); |
794 | context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); | |
795 | context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG); | |
796 | context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG); | |
797 | context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
798 | context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG); | |
799 | context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); | |
135014ad PU |
800 | |
801 | return 0; | |
802 | } | |
803 | ||
804 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
805 | { | |
806 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b PU |
807 | struct davinci_mcasp_context *context = &mcasp->context; |
808 | ||
809 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl); | |
810 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl); | |
811 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt); | |
812 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt); | |
813 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl); | |
814 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl); | |
815 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir); | |
135014ad PU |
816 | |
817 | return 0; | |
818 | } | |
819 | #else | |
820 | #define davinci_mcasp_suspend NULL | |
821 | #define davinci_mcasp_resume NULL | |
822 | #endif | |
823 | ||
ed29cd5e PU |
824 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
825 | ||
0a9d1385 BG |
826 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
827 | SNDRV_PCM_FMTBIT_U8 | \ | |
828 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
829 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
830 | SNDRV_PCM_FMTBIT_S24_LE | \ |
831 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
832 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
833 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
834 | SNDRV_PCM_FMTBIT_S32_LE | \ |
835 | SNDRV_PCM_FMTBIT_U32_LE) | |
836 | ||
f0fba2ad | 837 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 838 | { |
f0fba2ad | 839 | .name = "davinci-mcasp.0", |
d5902f69 | 840 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
841 | .suspend = davinci_mcasp_suspend, |
842 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
843 | .playback = { |
844 | .channels_min = 2, | |
2952b27e | 845 | .channels_max = 32 * 16, |
b67f4487 | 846 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 847 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
848 | }, |
849 | .capture = { | |
850 | .channels_min = 2, | |
2952b27e | 851 | .channels_max = 32 * 16, |
b67f4487 | 852 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 853 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
854 | }, |
855 | .ops = &davinci_mcasp_dai_ops, | |
856 | ||
857 | }, | |
858 | { | |
58e48d97 | 859 | .name = "davinci-mcasp.1", |
d5902f69 | 860 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
861 | .playback = { |
862 | .channels_min = 1, | |
863 | .channels_max = 384, | |
864 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 865 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
866 | }, |
867 | .ops = &davinci_mcasp_dai_ops, | |
868 | }, | |
869 | ||
870 | }; | |
b67f4487 | 871 | |
eeef0eda KM |
872 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
873 | .name = "davinci-mcasp", | |
874 | }; | |
875 | ||
256ba181 | 876 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 877 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
878 | .tx_dma_offset = 0x400, |
879 | .rx_dma_offset = 0x400, | |
880 | .asp_chan_q = EVENTQ_0, | |
881 | .version = MCASP_VERSION_1, | |
882 | }; | |
883 | ||
d1debafc | 884 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
885 | .tx_dma_offset = 0x2000, |
886 | .rx_dma_offset = 0x2000, | |
887 | .asp_chan_q = EVENTQ_0, | |
888 | .version = MCASP_VERSION_2, | |
889 | }; | |
890 | ||
d1debafc | 891 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
892 | .tx_dma_offset = 0, |
893 | .rx_dma_offset = 0, | |
894 | .asp_chan_q = EVENTQ_0, | |
895 | .version = MCASP_VERSION_3, | |
896 | }; | |
897 | ||
d1debafc | 898 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
899 | .tx_dma_offset = 0x200, |
900 | .rx_dma_offset = 0x284, | |
901 | .asp_chan_q = EVENTQ_0, | |
902 | .version = MCASP_VERSION_4, | |
903 | }; | |
904 | ||
3e3b8c34 HG |
905 | static const struct of_device_id mcasp_dt_ids[] = { |
906 | { | |
907 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 908 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
909 | }, |
910 | { | |
911 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 912 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 913 | }, |
e5ec69da | 914 | { |
3af9e031 | 915 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 916 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 917 | }, |
453c4990 PU |
918 | { |
919 | .compatible = "ti,dra7-mcasp-audio", | |
920 | .data = &dra7_mcasp_pdata, | |
921 | }, | |
3e3b8c34 HG |
922 | { /* sentinel */ } |
923 | }; | |
924 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
925 | ||
ae726e93 PU |
926 | static int mcasp_reparent_fck(struct platform_device *pdev) |
927 | { | |
928 | struct device_node *node = pdev->dev.of_node; | |
929 | struct clk *gfclk, *parent_clk; | |
930 | const char *parent_name; | |
931 | int ret; | |
932 | ||
933 | if (!node) | |
934 | return 0; | |
935 | ||
936 | parent_name = of_get_property(node, "fck_parent", NULL); | |
937 | if (!parent_name) | |
938 | return 0; | |
939 | ||
940 | gfclk = clk_get(&pdev->dev, "fck"); | |
941 | if (IS_ERR(gfclk)) { | |
942 | dev_err(&pdev->dev, "failed to get fck\n"); | |
943 | return PTR_ERR(gfclk); | |
944 | } | |
945 | ||
946 | parent_clk = clk_get(NULL, parent_name); | |
947 | if (IS_ERR(parent_clk)) { | |
948 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
949 | ret = PTR_ERR(parent_clk); | |
950 | goto err1; | |
951 | } | |
952 | ||
953 | ret = clk_set_parent(gfclk, parent_clk); | |
954 | if (ret) { | |
955 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
956 | goto err2; | |
957 | } | |
958 | ||
959 | err2: | |
960 | clk_put(parent_clk); | |
961 | err1: | |
962 | clk_put(gfclk); | |
963 | return ret; | |
964 | } | |
965 | ||
d1debafc | 966 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
967 | struct platform_device *pdev) |
968 | { | |
969 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 970 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 971 | const struct of_device_id *match = |
ea421eb1 | 972 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 973 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
974 | |
975 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
976 | u32 val; |
977 | int i, ret = 0; | |
978 | ||
979 | if (pdev->dev.platform_data) { | |
980 | pdata = pdev->dev.platform_data; | |
981 | return pdata; | |
982 | } else if (match) { | |
d1debafc | 983 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
984 | } else { |
985 | /* control shouldn't reach here. something is wrong */ | |
986 | ret = -EINVAL; | |
987 | goto nodata; | |
988 | } | |
989 | ||
3e3b8c34 HG |
990 | ret = of_property_read_u32(np, "op-mode", &val); |
991 | if (ret >= 0) | |
992 | pdata->op_mode = val; | |
993 | ||
994 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
995 | if (ret >= 0) { |
996 | if (val < 2 || val > 32) { | |
997 | dev_err(&pdev->dev, | |
998 | "tdm-slots must be in rage [2-32]\n"); | |
999 | ret = -EINVAL; | |
1000 | goto nodata; | |
1001 | } | |
1002 | ||
3e3b8c34 | 1003 | pdata->tdm_slots = val; |
2952b27e | 1004 | } |
3e3b8c34 | 1005 | |
3e3b8c34 HG |
1006 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1007 | val /= sizeof(u32); | |
3e3b8c34 | 1008 | if (of_serial_dir32) { |
1427e660 PU |
1009 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1010 | (sizeof(*of_serial_dir) * val), | |
1011 | GFP_KERNEL); | |
3e3b8c34 HG |
1012 | if (!of_serial_dir) { |
1013 | ret = -ENOMEM; | |
1014 | goto nodata; | |
1015 | } | |
1016 | ||
1427e660 | 1017 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1018 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1019 | ||
1427e660 | 1020 | pdata->num_serializer = val; |
3e3b8c34 HG |
1021 | pdata->serial_dir = of_serial_dir; |
1022 | } | |
1023 | ||
4023fe6f JS |
1024 | ret = of_property_match_string(np, "dma-names", "tx"); |
1025 | if (ret < 0) | |
1026 | goto nodata; | |
1027 | ||
1028 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1029 | &dma_spec); | |
1030 | if (ret < 0) | |
1031 | goto nodata; | |
1032 | ||
1033 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1034 | ||
1035 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1036 | if (ret < 0) | |
1037 | goto nodata; | |
1038 | ||
1039 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1040 | &dma_spec); | |
1041 | if (ret < 0) | |
1042 | goto nodata; | |
1043 | ||
1044 | pdata->rx_dma_channel = dma_spec.args[0]; | |
1045 | ||
3e3b8c34 HG |
1046 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1047 | if (ret >= 0) | |
1048 | pdata->txnumevt = val; | |
1049 | ||
1050 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1051 | if (ret >= 0) | |
1052 | pdata->rxnumevt = val; | |
1053 | ||
1054 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1055 | if (ret >= 0) | |
1056 | pdata->sram_size_playback = val; | |
1057 | ||
1058 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1059 | if (ret >= 0) | |
1060 | pdata->sram_size_capture = val; | |
1061 | ||
1062 | return pdata; | |
1063 | ||
1064 | nodata: | |
1065 | if (ret < 0) { | |
1066 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1067 | ret); | |
1068 | pdata = NULL; | |
1069 | } | |
1070 | return pdata; | |
1071 | } | |
1072 | ||
b67f4487 C |
1073 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1074 | { | |
64ebdec3 | 1075 | struct davinci_pcm_dma_params *dma_params; |
8de131f2 | 1076 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1077 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1078 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1079 | struct davinci_mcasp *mcasp; |
96d31e2b | 1080 | int ret; |
b67f4487 | 1081 | |
3e3b8c34 HG |
1082 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1083 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1084 | return -EINVAL; | |
1085 | } | |
1086 | ||
70091a3e | 1087 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1088 | GFP_KERNEL); |
70091a3e | 1089 | if (!mcasp) |
b67f4487 C |
1090 | return -ENOMEM; |
1091 | ||
3e3b8c34 HG |
1092 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1093 | if (!pdata) { | |
1094 | dev_err(&pdev->dev, "no platform data\n"); | |
1095 | return -EINVAL; | |
1096 | } | |
1097 | ||
256ba181 | 1098 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1099 | if (!mem) { |
70091a3e | 1100 | dev_warn(mcasp->dev, |
256ba181 JS |
1101 | "\"mpu\" mem resource not found, using index 0\n"); |
1102 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1103 | if (!mem) { | |
1104 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1105 | return -ENODEV; | |
1106 | } | |
b67f4487 C |
1107 | } |
1108 | ||
96d31e2b | 1109 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1110 | resource_size(mem), pdev->name); |
b67f4487 C |
1111 | if (!ioarea) { |
1112 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1113 | return -EBUSY; |
b67f4487 C |
1114 | } |
1115 | ||
10884347 | 1116 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1117 | |
10884347 HG |
1118 | ret = pm_runtime_get_sync(&pdev->dev); |
1119 | if (IS_ERR_VALUE(ret)) { | |
1120 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
1121 | return ret; | |
1122 | } | |
b67f4487 | 1123 | |
70091a3e PU |
1124 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1125 | if (!mcasp->base) { | |
4f82f028 VB |
1126 | dev_err(&pdev->dev, "ioremap failed\n"); |
1127 | ret = -ENOMEM; | |
1128 | goto err_release_clk; | |
1129 | } | |
1130 | ||
70091a3e PU |
1131 | mcasp->op_mode = pdata->op_mode; |
1132 | mcasp->tdm_slots = pdata->tdm_slots; | |
1133 | mcasp->num_serializer = pdata->num_serializer; | |
1134 | mcasp->serial_dir = pdata->serial_dir; | |
1135 | mcasp->version = pdata->version; | |
1136 | mcasp->txnumevt = pdata->txnumevt; | |
1137 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1138 | |
70091a3e | 1139 | mcasp->dev = &pdev->dev; |
b67f4487 | 1140 | |
256ba181 | 1141 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1142 | if (dat) |
1143 | mcasp->dat_port = true; | |
256ba181 | 1144 | |
64ebdec3 | 1145 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
8de131f2 | 1146 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
64ebdec3 PU |
1147 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1148 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1149 | dma_params->sram_pool = pdata->sram_pool; | |
1150 | dma_params->sram_size = pdata->sram_size_playback; | |
cbc7956c | 1151 | if (dat) |
64ebdec3 | 1152 | dma_params->dma_addr = dat->start; |
cbc7956c | 1153 | else |
64ebdec3 | 1154 | dma_params->dma_addr = mem->start + pdata->tx_dma_offset; |
b67f4487 | 1155 | |
453c4990 | 1156 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1157 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1158 | |
b67f4487 | 1159 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1160 | if (res) |
64ebdec3 | 1161 | dma_params->channel = res->start; |
4023fe6f | 1162 | else |
64ebdec3 | 1163 | dma_params->channel = pdata->tx_dma_channel; |
92e2a6f6 | 1164 | |
8de131f2 PU |
1165 | /* dmaengine filter data for DT and non-DT boot */ |
1166 | if (pdev->dev.of_node) | |
1167 | dma_data->filter_data = "tx"; | |
1168 | else | |
1169 | dma_data->filter_data = &dma_params->channel; | |
1170 | ||
64ebdec3 | 1171 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
8de131f2 | 1172 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
64ebdec3 PU |
1173 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1174 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1175 | dma_params->sram_pool = pdata->sram_pool; | |
1176 | dma_params->sram_size = pdata->sram_size_capture; | |
cbc7956c | 1177 | if (dat) |
64ebdec3 | 1178 | dma_params->dma_addr = dat->start; |
cbc7956c | 1179 | else |
64ebdec3 | 1180 | dma_params->dma_addr = mem->start + pdata->rx_dma_offset; |
cbc7956c | 1181 | |
453c4990 | 1182 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1183 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1184 | |
cbc7956c PU |
1185 | if (mcasp->version < MCASP_VERSION_3) { |
1186 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1187 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1188 | mcasp->dat_port = true; |
1189 | } else { | |
1190 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1191 | } | |
b67f4487 C |
1192 | |
1193 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
4023fe6f | 1194 | if (res) |
64ebdec3 | 1195 | dma_params->channel = res->start; |
4023fe6f | 1196 | else |
64ebdec3 | 1197 | dma_params->channel = pdata->rx_dma_channel; |
b67f4487 | 1198 | |
8de131f2 PU |
1199 | /* dmaengine filter data for DT and non-DT boot */ |
1200 | if (pdev->dev.of_node) | |
1201 | dma_data->filter_data = "rx"; | |
1202 | else | |
1203 | dma_data->filter_data = &dma_params->channel; | |
453c4990 | 1204 | |
70091a3e | 1205 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1206 | |
1207 | mcasp_reparent_fck(pdev); | |
1208 | ||
eeef0eda KM |
1209 | ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, |
1210 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1211 | |
1212 | if (ret != 0) | |
96d31e2b | 1213 | goto err_release_clk; |
f08095a4 | 1214 | |
453c4990 PU |
1215 | if (mcasp->version != MCASP_VERSION_4) { |
1216 | ret = davinci_soc_platform_register(&pdev->dev); | |
1217 | if (ret) { | |
1218 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
1219 | goto err_unregister_component; | |
1220 | } | |
f08095a4 HG |
1221 | } |
1222 | ||
b67f4487 C |
1223 | return 0; |
1224 | ||
eeef0eda KM |
1225 | err_unregister_component: |
1226 | snd_soc_unregister_component(&pdev->dev); | |
eef6d7b8 | 1227 | err_release_clk: |
10884347 HG |
1228 | pm_runtime_put_sync(&pdev->dev); |
1229 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1230 | return ret; |
1231 | } | |
1232 | ||
1233 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1234 | { | |
453c4990 | 1235 | struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev); |
b67f4487 | 1236 | |
eeef0eda | 1237 | snd_soc_unregister_component(&pdev->dev); |
453c4990 PU |
1238 | if (mcasp->version != MCASP_VERSION_4) |
1239 | davinci_soc_platform_unregister(&pdev->dev); | |
10884347 HG |
1240 | |
1241 | pm_runtime_put_sync(&pdev->dev); | |
1242 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1243 | |
b67f4487 C |
1244 | return 0; |
1245 | } | |
1246 | ||
1247 | static struct platform_driver davinci_mcasp_driver = { | |
1248 | .probe = davinci_mcasp_probe, | |
1249 | .remove = davinci_mcasp_remove, | |
1250 | .driver = { | |
1251 | .name = "davinci-mcasp", | |
1252 | .owner = THIS_MODULE, | |
ea421eb1 | 1253 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1254 | }, |
1255 | }; | |
1256 | ||
f9b8a514 | 1257 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1258 | |
1259 | MODULE_AUTHOR("Steve Chen"); | |
1260 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1261 | MODULE_LICENSE("GPL"); |