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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
b67f4487 C |
29 | |
30 | #include <sound/core.h> | |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/initval.h> | |
34 | #include <sound/soc.h> | |
453c4990 | 35 | #include <sound/dmaengine_pcm.h> |
b67f4487 C |
36 | |
37 | #include "davinci-pcm.h" | |
38 | #include "davinci-mcasp.h" | |
39 | ||
70091a3e | 40 | struct davinci_mcasp { |
21400a72 | 41 | struct davinci_pcm_dma_params dma_params[2]; |
453c4990 | 42 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 43 | void __iomem *base; |
487dce88 | 44 | u32 fifo_base; |
21400a72 PU |
45 | struct device *dev; |
46 | ||
47 | /* McASP specific data */ | |
48 | int tdm_slots; | |
49 | u8 op_mode; | |
50 | u8 num_serializer; | |
51 | u8 *serial_dir; | |
52 | u8 version; | |
53 | u16 bclk_lrclk_ratio; | |
4dcb5a0b | 54 | int streams; |
21400a72 | 55 | |
ab8b14b6 JS |
56 | int sysclk_freq; |
57 | bool bclk_master; | |
58 | ||
21400a72 PU |
59 | /* McASP FIFO related */ |
60 | u8 txnumevt; | |
61 | u8 rxnumevt; | |
62 | ||
cbc7956c PU |
63 | bool dat_port; |
64 | ||
21400a72 PU |
65 | #ifdef CONFIG_PM_SLEEP |
66 | struct { | |
67 | u32 txfmtctl; | |
68 | u32 rxfmtctl; | |
69 | u32 txfmt; | |
70 | u32 rxfmt; | |
71 | u32 aclkxctl; | |
72 | u32 aclkrctl; | |
73 | u32 pdir; | |
74 | } context; | |
75 | #endif | |
76 | }; | |
77 | ||
f68205a7 PU |
78 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
79 | u32 val) | |
b67f4487 | 80 | { |
f68205a7 | 81 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
82 | __raw_writel(__raw_readl(reg) | val, reg); |
83 | } | |
84 | ||
f68205a7 PU |
85 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
86 | u32 val) | |
b67f4487 | 87 | { |
f68205a7 | 88 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
89 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
90 | } | |
91 | ||
f68205a7 PU |
92 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
93 | u32 val, u32 mask) | |
b67f4487 | 94 | { |
f68205a7 | 95 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
96 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
97 | } | |
98 | ||
f68205a7 PU |
99 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
100 | u32 val) | |
b67f4487 | 101 | { |
f68205a7 | 102 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
103 | } |
104 | ||
f68205a7 | 105 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 106 | { |
f68205a7 | 107 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
108 | } |
109 | ||
f68205a7 | 110 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
111 | { |
112 | int i = 0; | |
113 | ||
f68205a7 | 114 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
115 | |
116 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
117 | /* loop count is to avoid the lock-up */ | |
118 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 119 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
120 | break; |
121 | } | |
122 | ||
f68205a7 | 123 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
124 | printk(KERN_ERR "GBLCTL write error\n"); |
125 | } | |
126 | ||
4dcb5a0b PU |
127 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
128 | { | |
f68205a7 PU |
129 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
130 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
131 | |
132 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
133 | } | |
134 | ||
70091a3e | 135 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 136 | { |
f68205a7 PU |
137 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
138 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
139 | |
140 | /* | |
141 | * When ASYNC == 0 the transmit and receive sections operate | |
142 | * synchronously from the transmit clock and frame sync. We need to make | |
143 | * sure that the TX signlas are enabled when starting reception. | |
144 | */ | |
145 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
146 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
147 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
148 | } |
149 | ||
f68205a7 PU |
150 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
151 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); | |
b67f4487 | 152 | |
f68205a7 PU |
153 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
154 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
155 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); | |
b67f4487 | 156 | |
f68205a7 PU |
157 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
158 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
4dcb5a0b PU |
159 | |
160 | if (mcasp_is_synchronous(mcasp)) | |
f68205a7 | 161 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
b67f4487 C |
162 | } |
163 | ||
70091a3e | 164 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 165 | { |
6a99fb5f C |
166 | u8 offset = 0, i; |
167 | u32 cnt; | |
168 | ||
f68205a7 PU |
169 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
170 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
171 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); | |
172 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); | |
b67f4487 | 173 | |
f68205a7 PU |
174 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); |
175 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
176 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); | |
70091a3e PU |
177 | for (i = 0; i < mcasp->num_serializer; i++) { |
178 | if (mcasp->serial_dir[i] == TX_MODE) { | |
6a99fb5f C |
179 | offset = i; |
180 | break; | |
181 | } | |
182 | } | |
183 | ||
184 | /* wait for TX ready */ | |
185 | cnt = 0; | |
f68205a7 | 186 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) & |
6a99fb5f C |
187 | TXSTATE) && (cnt < 100000)) |
188 | cnt++; | |
189 | ||
f68205a7 | 190 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
b67f4487 C |
191 | } |
192 | ||
70091a3e | 193 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 194 | { |
487dce88 PU |
195 | u32 reg; |
196 | ||
4dcb5a0b PU |
197 | mcasp->streams++; |
198 | ||
539d3d8c | 199 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 200 | if (mcasp->txnumevt) { /* enable FIFO */ |
487dce88 | 201 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 PU |
202 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
203 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 204 | } |
70091a3e | 205 | mcasp_start_tx(mcasp); |
539d3d8c | 206 | } else { |
70091a3e | 207 | if (mcasp->rxnumevt) { /* enable FIFO */ |
487dce88 | 208 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 PU |
209 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
210 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 211 | } |
70091a3e | 212 | mcasp_start_rx(mcasp); |
539d3d8c | 213 | } |
b67f4487 C |
214 | } |
215 | ||
70091a3e | 216 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 217 | { |
4dcb5a0b PU |
218 | /* |
219 | * In synchronous mode stop the TX clocks if no other stream is | |
220 | * running | |
221 | */ | |
222 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 223 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 224 | |
f68205a7 PU |
225 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
226 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
227 | } |
228 | ||
70091a3e | 229 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 230 | { |
4dcb5a0b PU |
231 | u32 val = 0; |
232 | ||
233 | /* | |
234 | * In synchronous mode keep TX clocks running if the capture stream is | |
235 | * still running. | |
236 | */ | |
237 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
238 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
239 | ||
f68205a7 PU |
240 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
241 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
242 | } |
243 | ||
70091a3e | 244 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 245 | { |
487dce88 PU |
246 | u32 reg; |
247 | ||
4dcb5a0b PU |
248 | mcasp->streams--; |
249 | ||
539d3d8c | 250 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 251 | if (mcasp->txnumevt) { /* disable FIFO */ |
487dce88 | 252 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 | 253 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 254 | } |
70091a3e | 255 | mcasp_stop_tx(mcasp); |
539d3d8c | 256 | } else { |
70091a3e | 257 | if (mcasp->rxnumevt) { /* disable FIFO */ |
487dce88 | 258 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 | 259 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 260 | } |
70091a3e | 261 | mcasp_stop_rx(mcasp); |
539d3d8c | 262 | } |
b67f4487 C |
263 | } |
264 | ||
265 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
266 | unsigned int fmt) | |
267 | { | |
70091a3e | 268 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 269 | int ret = 0; |
b67f4487 | 270 | |
1d17a04e | 271 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d DM |
272 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
273 | case SND_SOC_DAIFMT_DSP_B: | |
274 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
275 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
276 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
5296cf2d DM |
277 | break; |
278 | default: | |
279 | /* configure a full-word SYNC pulse (LRCLK) */ | |
f68205a7 PU |
280 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
281 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
5296cf2d DM |
282 | |
283 | /* make 1st data bit occur one ACLK cycle after the frame sync */ | |
f68205a7 PU |
284 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1)); |
285 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1)); | |
5296cf2d DM |
286 | break; |
287 | } | |
288 | ||
b67f4487 C |
289 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
290 | case SND_SOC_DAIFMT_CBS_CFS: | |
291 | /* codec is clock and frame slave */ | |
f68205a7 PU |
292 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
293 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 294 | |
f68205a7 PU |
295 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
296 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 297 | |
f68205a7 PU |
298 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
299 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 300 | mcasp->bclk_master = 1; |
b67f4487 | 301 | break; |
517ee6cf C |
302 | case SND_SOC_DAIFMT_CBM_CFS: |
303 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
304 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
305 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 306 | |
f68205a7 PU |
307 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
308 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 309 | |
f68205a7 PU |
310 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
311 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 312 | mcasp->bclk_master = 0; |
517ee6cf | 313 | break; |
b67f4487 C |
314 | case SND_SOC_DAIFMT_CBM_CFM: |
315 | /* codec is clock and frame master */ | |
f68205a7 PU |
316 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
317 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 318 | |
f68205a7 PU |
319 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
320 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 321 | |
f68205a7 PU |
322 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
323 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 324 | mcasp->bclk_master = 0; |
b67f4487 C |
325 | break; |
326 | ||
327 | default: | |
1d17a04e PU |
328 | ret = -EINVAL; |
329 | goto out; | |
b67f4487 C |
330 | } |
331 | ||
332 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
333 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 PU |
334 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
335 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
b67f4487 | 336 | |
f68205a7 PU |
337 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
338 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 C |
339 | break; |
340 | ||
341 | case SND_SOC_DAIFMT_NB_IF: | |
f68205a7 PU |
342 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
343 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
b67f4487 | 344 | |
f68205a7 PU |
345 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
346 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 C |
347 | break; |
348 | ||
349 | case SND_SOC_DAIFMT_IB_IF: | |
f68205a7 PU |
350 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
351 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
b67f4487 | 352 | |
f68205a7 PU |
353 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
354 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 C |
355 | break; |
356 | ||
357 | case SND_SOC_DAIFMT_NB_NF: | |
f68205a7 PU |
358 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
359 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
b67f4487 | 360 | |
f68205a7 PU |
361 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
362 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 C |
363 | break; |
364 | ||
365 | default: | |
1d17a04e PU |
366 | ret = -EINVAL; |
367 | break; | |
b67f4487 | 368 | } |
1d17a04e PU |
369 | out: |
370 | pm_runtime_put_sync(mcasp->dev); | |
371 | return ret; | |
b67f4487 C |
372 | } |
373 | ||
4ed8c9b7 DM |
374 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) |
375 | { | |
70091a3e | 376 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
377 | |
378 | switch (div_id) { | |
379 | case 0: /* MCLK divider */ | |
f68205a7 | 380 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 381 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 382 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
383 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
384 | break; | |
385 | ||
386 | case 1: /* BCLK divider */ | |
f68205a7 | 387 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 388 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 389 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 DM |
390 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
391 | break; | |
392 | ||
1b3bc060 | 393 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 394 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
395 | break; |
396 | ||
4ed8c9b7 DM |
397 | default: |
398 | return -EINVAL; | |
399 | } | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
5b66aa2d DM |
404 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
405 | unsigned int freq, int dir) | |
406 | { | |
70091a3e | 407 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
408 | |
409 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
410 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
411 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
412 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 413 | } else { |
f68205a7 PU |
414 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
415 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
416 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
417 | } |
418 | ||
ab8b14b6 JS |
419 | mcasp->sysclk_freq = freq; |
420 | ||
5b66aa2d DM |
421 | return 0; |
422 | } | |
423 | ||
70091a3e | 424 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 425 | int word_length) |
b67f4487 | 426 | { |
ba764b3d | 427 | u32 fmt; |
79671892 DM |
428 | u32 tx_rotate = (word_length / 4) & 0x7; |
429 | u32 rx_rotate = (32 - word_length) / 4; | |
ba764b3d | 430 | u32 mask = (1ULL << word_length) - 1; |
b67f4487 | 431 | |
1b3bc060 DM |
432 | /* |
433 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
434 | * callback, take it into account here. That allows us to for example | |
435 | * send 32 bits per channel to the codec, while only 16 of them carry | |
436 | * audio payload. | |
d486fea6 MB |
437 | * The clock ratio is given for a full period of data (for I2S format |
438 | * both left and right channels), so it has to be divided by number of | |
439 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 440 | */ |
70091a3e PU |
441 | if (mcasp->bclk_lrclk_ratio) |
442 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
1b3bc060 | 443 | |
ba764b3d DM |
444 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
445 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 446 | |
70091a3e | 447 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
448 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
449 | RXSSZ(0x0F)); | |
450 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
451 | TXSSZ(0x0F)); | |
452 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
453 | TXROT(7)); | |
454 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
455 | RXROT(7)); | |
456 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
457 | } |
458 | ||
f68205a7 | 459 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 460 | |
b67f4487 C |
461 | return 0; |
462 | } | |
463 | ||
662ffae9 | 464 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
2952b27e | 465 | int channels) |
b67f4487 C |
466 | { |
467 | int i; | |
6a99fb5f C |
468 | u8 tx_ser = 0; |
469 | u8 rx_ser = 0; | |
2952b27e | 470 | u8 ser; |
70091a3e | 471 | u8 slots = mcasp->tdm_slots; |
2952b27e | 472 | u8 max_active_serializers = (channels + slots - 1) / slots; |
487dce88 | 473 | u32 reg; |
b67f4487 | 474 | /* Default configuration */ |
453c4990 | 475 | if (mcasp->version != MCASP_VERSION_4) |
f68205a7 | 476 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
477 | |
478 | /* All PINS as McASP */ | |
f68205a7 | 479 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
480 | |
481 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
482 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
483 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 484 | } else { |
f68205a7 PU |
485 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
486 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
487 | } |
488 | ||
70091a3e | 489 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
490 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
491 | mcasp->serial_dir[i]); | |
70091a3e | 492 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 493 | tx_ser < max_active_serializers) { |
f68205a7 | 494 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 495 | tx_ser++; |
70091a3e | 496 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 497 | rx_ser < max_active_serializers) { |
f68205a7 | 498 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 499 | rx_ser++; |
2952b27e | 500 | } else { |
f68205a7 PU |
501 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
502 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
503 | } |
504 | } | |
505 | ||
ecf327c7 DM |
506 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
507 | ser = tx_ser; | |
508 | else | |
509 | ser = rx_ser; | |
510 | ||
511 | if (ser < max_active_serializers) { | |
70091a3e | 512 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
ecf327c7 DM |
513 | "enabled in mcasp (%d)\n", channels, ser * slots); |
514 | return -EINVAL; | |
515 | } | |
516 | ||
70091a3e PU |
517 | if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) { |
518 | if (mcasp->txnumevt * tx_ser > 64) | |
519 | mcasp->txnumevt = 1; | |
6a99fb5f | 520 | |
487dce88 | 521 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 PU |
522 | mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK); |
523 | mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8), | |
524 | NUMEVT_MASK); | |
6a99fb5f C |
525 | } |
526 | ||
70091a3e PU |
527 | if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) { |
528 | if (mcasp->rxnumevt * rx_ser > 64) | |
529 | mcasp->rxnumevt = 1; | |
487dce88 PU |
530 | |
531 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
f68205a7 PU |
532 | mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK); |
533 | mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8), | |
534 | NUMEVT_MASK); | |
b67f4487 | 535 | } |
2952b27e MB |
536 | |
537 | return 0; | |
b67f4487 C |
538 | } |
539 | ||
2c56c4c2 | 540 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
b67f4487 C |
541 | { |
542 | int i, active_slots; | |
543 | u32 mask = 0; | |
cbc7956c | 544 | u32 busel = 0; |
b67f4487 | 545 | |
2c56c4c2 PU |
546 | if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) { |
547 | dev_err(mcasp->dev, "tdm slot %d not supported\n", | |
548 | mcasp->tdm_slots); | |
549 | return -EINVAL; | |
550 | } | |
551 | ||
70091a3e | 552 | active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; |
b67f4487 C |
553 | for (i = 0; i < active_slots; i++) |
554 | mask |= (1 << i); | |
555 | ||
f68205a7 | 556 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 557 | |
cbc7956c PU |
558 | if (!mcasp->dat_port) |
559 | busel = TXSEL; | |
560 | ||
2c56c4c2 PU |
561 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
562 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
563 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
564 | FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); | |
565 | ||
566 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
567 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
568 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
569 | FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); | |
570 | ||
571 | return 0; | |
b67f4487 C |
572 | } |
573 | ||
574 | /* S/PDIF */ | |
2c56c4c2 | 575 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp) |
b67f4487 | 576 | { |
b67f4487 C |
577 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
578 | and LSB first */ | |
f68205a7 | 579 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
580 | |
581 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 582 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
583 | |
584 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 585 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
586 | |
587 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 588 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 589 | |
f68205a7 | 590 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
591 | |
592 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 593 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
594 | |
595 | /* Enable the DIT */ | |
f68205a7 | 596 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 PU |
597 | |
598 | return 0; | |
b67f4487 C |
599 | } |
600 | ||
601 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
602 | struct snd_pcm_hw_params *params, | |
603 | struct snd_soc_dai *cpu_dai) | |
604 | { | |
70091a3e | 605 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 606 | struct davinci_pcm_dma_params *dma_params = |
70091a3e | 607 | &mcasp->dma_params[substream->stream]; |
453c4990 PU |
608 | struct snd_dmaengine_dai_dma_data *dma_data = |
609 | &mcasp->dma_data[substream->stream]; | |
b67f4487 | 610 | int word_length; |
4fa9c1a5 | 611 | u8 fifo_level; |
70091a3e | 612 | u8 slots = mcasp->tdm_slots; |
7c21a781 | 613 | u8 active_serializers; |
a7e46bd9 | 614 | int channels = params_channels(params); |
2c56c4c2 | 615 | int ret; |
ab8b14b6 JS |
616 | |
617 | /* If mcasp is BCLK master we need to set BCLK divider */ | |
618 | if (mcasp->bclk_master) { | |
619 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); | |
620 | if (mcasp->sysclk_freq % bclk_freq != 0) { | |
621 | dev_err(mcasp->dev, "Can't produce requred BCLK\n"); | |
622 | return -EINVAL; | |
623 | } | |
624 | davinci_mcasp_set_clkdiv( | |
625 | cpu_dai, 1, mcasp->sysclk_freq / bclk_freq); | |
626 | } | |
627 | ||
0f7d9a63 PU |
628 | ret = mcasp_common_hw_param(mcasp, substream->stream, channels); |
629 | if (ret) | |
630 | return ret; | |
631 | ||
70091a3e | 632 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
2c56c4c2 | 633 | ret = mcasp_dit_hw_param(mcasp); |
b67f4487 | 634 | else |
2c56c4c2 PU |
635 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
636 | ||
637 | if (ret) | |
638 | return ret; | |
b67f4487 C |
639 | |
640 | switch (params_format(params)) { | |
0a9d1385 | 641 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
642 | case SNDRV_PCM_FORMAT_S8: |
643 | dma_params->data_type = 1; | |
ba764b3d | 644 | word_length = 8; |
b67f4487 C |
645 | break; |
646 | ||
0a9d1385 | 647 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
648 | case SNDRV_PCM_FORMAT_S16_LE: |
649 | dma_params->data_type = 2; | |
ba764b3d | 650 | word_length = 16; |
b67f4487 C |
651 | break; |
652 | ||
21eb24d8 DM |
653 | case SNDRV_PCM_FORMAT_U24_3LE: |
654 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 655 | dma_params->data_type = 3; |
ba764b3d | 656 | word_length = 24; |
21eb24d8 DM |
657 | break; |
658 | ||
6b7fa011 DM |
659 | case SNDRV_PCM_FORMAT_U24_LE: |
660 | case SNDRV_PCM_FORMAT_S24_LE: | |
0a9d1385 | 661 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
662 | case SNDRV_PCM_FORMAT_S32_LE: |
663 | dma_params->data_type = 4; | |
ba764b3d | 664 | word_length = 32; |
b67f4487 C |
665 | break; |
666 | ||
667 | default: | |
668 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
669 | return -EINVAL; | |
670 | } | |
6a99fb5f | 671 | |
a7e46bd9 PU |
672 | /* Calculate FIFO level */ |
673 | active_serializers = (channels + slots - 1) / slots; | |
674 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
675 | fifo_level = mcasp->txnumevt * active_serializers; | |
676 | else | |
677 | fifo_level = mcasp->rxnumevt * active_serializers; | |
678 | ||
70091a3e | 679 | if (mcasp->version == MCASP_VERSION_2 && !fifo_level) |
4fa9c1a5 C |
680 | dma_params->acnt = 4; |
681 | else | |
6a99fb5f C |
682 | dma_params->acnt = dma_params->data_type; |
683 | ||
4fa9c1a5 | 684 | dma_params->fifo_level = fifo_level; |
453c4990 PU |
685 | dma_data->maxburst = fifo_level; |
686 | ||
70091a3e | 687 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 C |
688 | |
689 | return 0; | |
690 | } | |
691 | ||
692 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
693 | int cmd, struct snd_soc_dai *cpu_dai) | |
694 | { | |
70091a3e | 695 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
696 | int ret = 0; |
697 | ||
698 | switch (cmd) { | |
b67f4487 | 699 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
700 | case SNDRV_PCM_TRIGGER_START: |
701 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 702 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 703 | break; |
b67f4487 | 704 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 705 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 706 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 707 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
708 | break; |
709 | ||
710 | default: | |
711 | ret = -EINVAL; | |
712 | } | |
713 | ||
714 | return ret; | |
715 | } | |
716 | ||
bedad0ca CPE |
717 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
718 | struct snd_soc_dai *dai) | |
719 | { | |
70091a3e | 720 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
bedad0ca | 721 | |
453c4990 PU |
722 | if (mcasp->version == MCASP_VERSION_4) |
723 | snd_soc_dai_set_dma_data(dai, substream, | |
724 | &mcasp->dma_data[substream->stream]); | |
725 | else | |
726 | snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params); | |
727 | ||
bedad0ca CPE |
728 | return 0; |
729 | } | |
730 | ||
85e7652d | 731 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
bedad0ca | 732 | .startup = davinci_mcasp_startup, |
b67f4487 C |
733 | .trigger = davinci_mcasp_trigger, |
734 | .hw_params = davinci_mcasp_hw_params, | |
735 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 736 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 737 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
738 | }; |
739 | ||
135014ad PU |
740 | #ifdef CONFIG_PM_SLEEP |
741 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
742 | { | |
743 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
744 | ||
745 | mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG); | |
746 | mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); | |
747 | mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG); | |
748 | mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG); | |
749 | mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
750 | mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG); | |
751 | mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); | |
752 | ||
753 | return 0; | |
754 | } | |
755 | ||
756 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
757 | { | |
758 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
759 | ||
760 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl); | |
761 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl); | |
762 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt); | |
763 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt); | |
764 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl); | |
765 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl); | |
766 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir); | |
767 | ||
768 | return 0; | |
769 | } | |
770 | #else | |
771 | #define davinci_mcasp_suspend NULL | |
772 | #define davinci_mcasp_resume NULL | |
773 | #endif | |
774 | ||
ed29cd5e PU |
775 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
776 | ||
0a9d1385 BG |
777 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
778 | SNDRV_PCM_FMTBIT_U8 | \ | |
779 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
780 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
781 | SNDRV_PCM_FMTBIT_S24_LE | \ |
782 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
783 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
784 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
785 | SNDRV_PCM_FMTBIT_S32_LE | \ |
786 | SNDRV_PCM_FMTBIT_U32_LE) | |
787 | ||
f0fba2ad | 788 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 789 | { |
f0fba2ad | 790 | .name = "davinci-mcasp.0", |
135014ad PU |
791 | .suspend = davinci_mcasp_suspend, |
792 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
793 | .playback = { |
794 | .channels_min = 2, | |
2952b27e | 795 | .channels_max = 32 * 16, |
b67f4487 | 796 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 797 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
798 | }, |
799 | .capture = { | |
800 | .channels_min = 2, | |
2952b27e | 801 | .channels_max = 32 * 16, |
b67f4487 | 802 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 803 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
804 | }, |
805 | .ops = &davinci_mcasp_dai_ops, | |
806 | ||
807 | }, | |
808 | { | |
58e48d97 | 809 | .name = "davinci-mcasp.1", |
b67f4487 C |
810 | .playback = { |
811 | .channels_min = 1, | |
812 | .channels_max = 384, | |
813 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 814 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
815 | }, |
816 | .ops = &davinci_mcasp_dai_ops, | |
817 | }, | |
818 | ||
819 | }; | |
b67f4487 | 820 | |
eeef0eda KM |
821 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
822 | .name = "davinci-mcasp", | |
823 | }; | |
824 | ||
256ba181 JS |
825 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
826 | static struct snd_platform_data dm646x_mcasp_pdata = { | |
827 | .tx_dma_offset = 0x400, | |
828 | .rx_dma_offset = 0x400, | |
829 | .asp_chan_q = EVENTQ_0, | |
830 | .version = MCASP_VERSION_1, | |
831 | }; | |
832 | ||
833 | static struct snd_platform_data da830_mcasp_pdata = { | |
834 | .tx_dma_offset = 0x2000, | |
835 | .rx_dma_offset = 0x2000, | |
836 | .asp_chan_q = EVENTQ_0, | |
837 | .version = MCASP_VERSION_2, | |
838 | }; | |
839 | ||
b14899da | 840 | static struct snd_platform_data am33xx_mcasp_pdata = { |
256ba181 JS |
841 | .tx_dma_offset = 0, |
842 | .rx_dma_offset = 0, | |
843 | .asp_chan_q = EVENTQ_0, | |
844 | .version = MCASP_VERSION_3, | |
845 | }; | |
846 | ||
453c4990 PU |
847 | static struct snd_platform_data dra7_mcasp_pdata = { |
848 | .tx_dma_offset = 0x200, | |
849 | .rx_dma_offset = 0x284, | |
850 | .asp_chan_q = EVENTQ_0, | |
851 | .version = MCASP_VERSION_4, | |
852 | }; | |
853 | ||
3e3b8c34 HG |
854 | static const struct of_device_id mcasp_dt_ids[] = { |
855 | { | |
856 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 857 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
858 | }, |
859 | { | |
860 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 861 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 862 | }, |
e5ec69da | 863 | { |
3af9e031 | 864 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 865 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 866 | }, |
453c4990 PU |
867 | { |
868 | .compatible = "ti,dra7-mcasp-audio", | |
869 | .data = &dra7_mcasp_pdata, | |
870 | }, | |
3e3b8c34 HG |
871 | { /* sentinel */ } |
872 | }; | |
873 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
874 | ||
ae726e93 PU |
875 | static int mcasp_reparent_fck(struct platform_device *pdev) |
876 | { | |
877 | struct device_node *node = pdev->dev.of_node; | |
878 | struct clk *gfclk, *parent_clk; | |
879 | const char *parent_name; | |
880 | int ret; | |
881 | ||
882 | if (!node) | |
883 | return 0; | |
884 | ||
885 | parent_name = of_get_property(node, "fck_parent", NULL); | |
886 | if (!parent_name) | |
887 | return 0; | |
888 | ||
889 | gfclk = clk_get(&pdev->dev, "fck"); | |
890 | if (IS_ERR(gfclk)) { | |
891 | dev_err(&pdev->dev, "failed to get fck\n"); | |
892 | return PTR_ERR(gfclk); | |
893 | } | |
894 | ||
895 | parent_clk = clk_get(NULL, parent_name); | |
896 | if (IS_ERR(parent_clk)) { | |
897 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
898 | ret = PTR_ERR(parent_clk); | |
899 | goto err1; | |
900 | } | |
901 | ||
902 | ret = clk_set_parent(gfclk, parent_clk); | |
903 | if (ret) { | |
904 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
905 | goto err2; | |
906 | } | |
907 | ||
908 | err2: | |
909 | clk_put(parent_clk); | |
910 | err1: | |
911 | clk_put(gfclk); | |
912 | return ret; | |
913 | } | |
914 | ||
3e3b8c34 HG |
915 | static struct snd_platform_data *davinci_mcasp_set_pdata_from_of( |
916 | struct platform_device *pdev) | |
917 | { | |
918 | struct device_node *np = pdev->dev.of_node; | |
919 | struct snd_platform_data *pdata = NULL; | |
920 | const struct of_device_id *match = | |
ea421eb1 | 921 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 922 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
923 | |
924 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
925 | u32 val; |
926 | int i, ret = 0; | |
927 | ||
928 | if (pdev->dev.platform_data) { | |
929 | pdata = pdev->dev.platform_data; | |
930 | return pdata; | |
931 | } else if (match) { | |
256ba181 | 932 | pdata = (struct snd_platform_data *) match->data; |
3e3b8c34 HG |
933 | } else { |
934 | /* control shouldn't reach here. something is wrong */ | |
935 | ret = -EINVAL; | |
936 | goto nodata; | |
937 | } | |
938 | ||
3e3b8c34 HG |
939 | ret = of_property_read_u32(np, "op-mode", &val); |
940 | if (ret >= 0) | |
941 | pdata->op_mode = val; | |
942 | ||
943 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
944 | if (ret >= 0) { |
945 | if (val < 2 || val > 32) { | |
946 | dev_err(&pdev->dev, | |
947 | "tdm-slots must be in rage [2-32]\n"); | |
948 | ret = -EINVAL; | |
949 | goto nodata; | |
950 | } | |
951 | ||
3e3b8c34 | 952 | pdata->tdm_slots = val; |
2952b27e | 953 | } |
3e3b8c34 | 954 | |
3e3b8c34 HG |
955 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
956 | val /= sizeof(u32); | |
3e3b8c34 | 957 | if (of_serial_dir32) { |
1427e660 PU |
958 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
959 | (sizeof(*of_serial_dir) * val), | |
960 | GFP_KERNEL); | |
3e3b8c34 HG |
961 | if (!of_serial_dir) { |
962 | ret = -ENOMEM; | |
963 | goto nodata; | |
964 | } | |
965 | ||
1427e660 | 966 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
967 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
968 | ||
1427e660 | 969 | pdata->num_serializer = val; |
3e3b8c34 HG |
970 | pdata->serial_dir = of_serial_dir; |
971 | } | |
972 | ||
4023fe6f JS |
973 | ret = of_property_match_string(np, "dma-names", "tx"); |
974 | if (ret < 0) | |
975 | goto nodata; | |
976 | ||
977 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
978 | &dma_spec); | |
979 | if (ret < 0) | |
980 | goto nodata; | |
981 | ||
982 | pdata->tx_dma_channel = dma_spec.args[0]; | |
983 | ||
984 | ret = of_property_match_string(np, "dma-names", "rx"); | |
985 | if (ret < 0) | |
986 | goto nodata; | |
987 | ||
988 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
989 | &dma_spec); | |
990 | if (ret < 0) | |
991 | goto nodata; | |
992 | ||
993 | pdata->rx_dma_channel = dma_spec.args[0]; | |
994 | ||
3e3b8c34 HG |
995 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
996 | if (ret >= 0) | |
997 | pdata->txnumevt = val; | |
998 | ||
999 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1000 | if (ret >= 0) | |
1001 | pdata->rxnumevt = val; | |
1002 | ||
1003 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1004 | if (ret >= 0) | |
1005 | pdata->sram_size_playback = val; | |
1006 | ||
1007 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1008 | if (ret >= 0) | |
1009 | pdata->sram_size_capture = val; | |
1010 | ||
1011 | return pdata; | |
1012 | ||
1013 | nodata: | |
1014 | if (ret < 0) { | |
1015 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1016 | ret); | |
1017 | pdata = NULL; | |
1018 | } | |
1019 | return pdata; | |
1020 | } | |
1021 | ||
b67f4487 C |
1022 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1023 | { | |
1024 | struct davinci_pcm_dma_params *dma_data; | |
256ba181 | 1025 | struct resource *mem, *ioarea, *res, *dat; |
b67f4487 | 1026 | struct snd_platform_data *pdata; |
70091a3e | 1027 | struct davinci_mcasp *mcasp; |
96d31e2b | 1028 | int ret; |
b67f4487 | 1029 | |
3e3b8c34 HG |
1030 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1031 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1032 | return -EINVAL; | |
1033 | } | |
1034 | ||
70091a3e | 1035 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1036 | GFP_KERNEL); |
70091a3e | 1037 | if (!mcasp) |
b67f4487 C |
1038 | return -ENOMEM; |
1039 | ||
3e3b8c34 HG |
1040 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1041 | if (!pdata) { | |
1042 | dev_err(&pdev->dev, "no platform data\n"); | |
1043 | return -EINVAL; | |
1044 | } | |
1045 | ||
256ba181 | 1046 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1047 | if (!mem) { |
70091a3e | 1048 | dev_warn(mcasp->dev, |
256ba181 JS |
1049 | "\"mpu\" mem resource not found, using index 0\n"); |
1050 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1051 | if (!mem) { | |
1052 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1053 | return -ENODEV; | |
1054 | } | |
b67f4487 C |
1055 | } |
1056 | ||
96d31e2b | 1057 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1058 | resource_size(mem), pdev->name); |
b67f4487 C |
1059 | if (!ioarea) { |
1060 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1061 | return -EBUSY; |
b67f4487 C |
1062 | } |
1063 | ||
10884347 | 1064 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1065 | |
10884347 HG |
1066 | ret = pm_runtime_get_sync(&pdev->dev); |
1067 | if (IS_ERR_VALUE(ret)) { | |
1068 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
1069 | return ret; | |
1070 | } | |
b67f4487 | 1071 | |
70091a3e PU |
1072 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1073 | if (!mcasp->base) { | |
4f82f028 VB |
1074 | dev_err(&pdev->dev, "ioremap failed\n"); |
1075 | ret = -ENOMEM; | |
1076 | goto err_release_clk; | |
1077 | } | |
1078 | ||
70091a3e PU |
1079 | mcasp->op_mode = pdata->op_mode; |
1080 | mcasp->tdm_slots = pdata->tdm_slots; | |
1081 | mcasp->num_serializer = pdata->num_serializer; | |
1082 | mcasp->serial_dir = pdata->serial_dir; | |
1083 | mcasp->version = pdata->version; | |
1084 | mcasp->txnumevt = pdata->txnumevt; | |
1085 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1086 | |
70091a3e | 1087 | mcasp->dev = &pdev->dev; |
b67f4487 | 1088 | |
256ba181 | 1089 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1090 | if (dat) |
1091 | mcasp->dat_port = true; | |
256ba181 | 1092 | |
70091a3e | 1093 | dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
48519f0a SN |
1094 | dma_data->asp_chan_q = pdata->asp_chan_q; |
1095 | dma_data->ram_chan_q = pdata->ram_chan_q; | |
b8ec56d8 | 1096 | dma_data->sram_pool = pdata->sram_pool; |
a0c83263 | 1097 | dma_data->sram_size = pdata->sram_size_playback; |
cbc7956c PU |
1098 | if (dat) |
1099 | dma_data->dma_addr = dat->start; | |
1100 | else | |
1101 | dma_data->dma_addr = mem->start + pdata->tx_dma_offset; | |
b67f4487 | 1102 | |
453c4990 PU |
1103 | /* Unconditional dmaengine stuff */ |
1104 | mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr; | |
1105 | ||
b67f4487 | 1106 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f JS |
1107 | if (res) |
1108 | dma_data->channel = res->start; | |
1109 | else | |
1110 | dma_data->channel = pdata->tx_dma_channel; | |
92e2a6f6 | 1111 | |
70091a3e | 1112 | dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
48519f0a SN |
1113 | dma_data->asp_chan_q = pdata->asp_chan_q; |
1114 | dma_data->ram_chan_q = pdata->ram_chan_q; | |
b8ec56d8 | 1115 | dma_data->sram_pool = pdata->sram_pool; |
a0c83263 | 1116 | dma_data->sram_size = pdata->sram_size_capture; |
cbc7956c PU |
1117 | if (dat) |
1118 | dma_data->dma_addr = dat->start; | |
1119 | else | |
1120 | dma_data->dma_addr = mem->start + pdata->rx_dma_offset; | |
1121 | ||
453c4990 PU |
1122 | /* Unconditional dmaengine stuff */ |
1123 | mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr; | |
1124 | ||
cbc7956c PU |
1125 | if (mcasp->version < MCASP_VERSION_3) { |
1126 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
1127 | /* dma_data->dma_addr is pointing to the data port address */ | |
1128 | mcasp->dat_port = true; | |
1129 | } else { | |
1130 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1131 | } | |
b67f4487 C |
1132 | |
1133 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
4023fe6f JS |
1134 | if (res) |
1135 | dma_data->channel = res->start; | |
1136 | else | |
1137 | dma_data->channel = pdata->rx_dma_channel; | |
b67f4487 | 1138 | |
453c4990 PU |
1139 | /* Unconditional dmaengine stuff */ |
1140 | mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx"; | |
1141 | mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx"; | |
1142 | ||
70091a3e | 1143 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1144 | |
1145 | mcasp_reparent_fck(pdev); | |
1146 | ||
eeef0eda KM |
1147 | ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, |
1148 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1149 | |
1150 | if (ret != 0) | |
96d31e2b | 1151 | goto err_release_clk; |
f08095a4 | 1152 | |
453c4990 PU |
1153 | if (mcasp->version != MCASP_VERSION_4) { |
1154 | ret = davinci_soc_platform_register(&pdev->dev); | |
1155 | if (ret) { | |
1156 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
1157 | goto err_unregister_component; | |
1158 | } | |
f08095a4 HG |
1159 | } |
1160 | ||
b67f4487 C |
1161 | return 0; |
1162 | ||
eeef0eda KM |
1163 | err_unregister_component: |
1164 | snd_soc_unregister_component(&pdev->dev); | |
eef6d7b8 | 1165 | err_release_clk: |
10884347 HG |
1166 | pm_runtime_put_sync(&pdev->dev); |
1167 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1168 | return ret; |
1169 | } | |
1170 | ||
1171 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1172 | { | |
453c4990 | 1173 | struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev); |
b67f4487 | 1174 | |
eeef0eda | 1175 | snd_soc_unregister_component(&pdev->dev); |
453c4990 PU |
1176 | if (mcasp->version != MCASP_VERSION_4) |
1177 | davinci_soc_platform_unregister(&pdev->dev); | |
10884347 HG |
1178 | |
1179 | pm_runtime_put_sync(&pdev->dev); | |
1180 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1181 | |
b67f4487 C |
1182 | return 0; |
1183 | } | |
1184 | ||
1185 | static struct platform_driver davinci_mcasp_driver = { | |
1186 | .probe = davinci_mcasp_probe, | |
1187 | .remove = davinci_mcasp_remove, | |
1188 | .driver = { | |
1189 | .name = "davinci-mcasp", | |
1190 | .owner = THIS_MODULE, | |
ea421eb1 | 1191 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1192 | }, |
1193 | }; | |
1194 | ||
f9b8a514 | 1195 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1196 | |
1197 | MODULE_AUTHOR("Steve Chen"); | |
1198 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1199 | MODULE_LICENSE("GPL"); |