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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
9759e7ef | 29 | #include <linux/platform_data/davinci_asp.h> |
a75a053f | 30 | #include <linux/math64.h> |
b67f4487 | 31 | |
6479285d | 32 | #include <sound/asoundef.h> |
b67f4487 C |
33 | #include <sound/core.h> |
34 | #include <sound/pcm.h> | |
35 | #include <sound/pcm_params.h> | |
36 | #include <sound/initval.h> | |
37 | #include <sound/soc.h> | |
453c4990 | 38 | #include <sound/dmaengine_pcm.h> |
87c19364 | 39 | #include <sound/omap-pcm.h> |
b67f4487 | 40 | |
f3f9cfa8 | 41 | #include "edma-pcm.h" |
b67f4487 C |
42 | #include "davinci-mcasp.h" |
43 | ||
0bf0e8ae PU |
44 | #define MCASP_MAX_AFIFO_DEPTH 64 |
45 | ||
1cc0c054 PU |
46 | static u32 context_regs[] = { |
47 | DAVINCI_MCASP_TXFMCTL_REG, | |
48 | DAVINCI_MCASP_RXFMCTL_REG, | |
49 | DAVINCI_MCASP_TXFMT_REG, | |
50 | DAVINCI_MCASP_RXFMT_REG, | |
51 | DAVINCI_MCASP_ACLKXCTL_REG, | |
52 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
53 | DAVINCI_MCASP_AHCLKXCTL_REG, |
54 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 55 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
56 | DAVINCI_MCASP_RXMASK_REG, |
57 | DAVINCI_MCASP_TXMASK_REG, | |
58 | DAVINCI_MCASP_RXTDM_REG, | |
59 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
60 | }; |
61 | ||
790bb94b | 62 | struct davinci_mcasp_context { |
1cc0c054 | 63 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
64 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
65 | u32 *xrsr_regs; /* for serializer configuration */ | |
6afda7f5 | 66 | bool pm_state; |
790bb94b PU |
67 | }; |
68 | ||
a75a053f JS |
69 | struct davinci_mcasp_ruledata { |
70 | struct davinci_mcasp *mcasp; | |
71 | int serializers; | |
72 | }; | |
73 | ||
70091a3e | 74 | struct davinci_mcasp { |
453c4990 | 75 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 76 | void __iomem *base; |
487dce88 | 77 | u32 fifo_base; |
21400a72 | 78 | struct device *dev; |
a7a3324a | 79 | struct snd_pcm_substream *substreams[2]; |
21400a72 PU |
80 | |
81 | /* McASP specific data */ | |
82 | int tdm_slots; | |
dd55ff83 JS |
83 | u32 tdm_mask[2]; |
84 | int slot_width; | |
21400a72 PU |
85 | u8 op_mode; |
86 | u8 num_serializer; | |
87 | u8 *serial_dir; | |
88 | u8 version; | |
8267525c | 89 | u8 bclk_div; |
4dcb5a0b | 90 | int streams; |
a7a3324a | 91 | u32 irq_request[2]; |
9759e7ef | 92 | int dma_request[2]; |
21400a72 | 93 | |
ab8b14b6 JS |
94 | int sysclk_freq; |
95 | bool bclk_master; | |
96 | ||
21400a72 PU |
97 | /* McASP FIFO related */ |
98 | u8 txnumevt; | |
99 | u8 rxnumevt; | |
100 | ||
cbc7956c PU |
101 | bool dat_port; |
102 | ||
11277833 PU |
103 | /* Used for comstraint setting on the second stream */ |
104 | u32 channels; | |
105 | ||
21400a72 | 106 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 107 | struct davinci_mcasp_context context; |
21400a72 | 108 | #endif |
a75a053f JS |
109 | |
110 | struct davinci_mcasp_ruledata ruledata[2]; | |
5935a056 | 111 | struct snd_pcm_hw_constraint_list chconstr[2]; |
21400a72 PU |
112 | }; |
113 | ||
f68205a7 PU |
114 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
115 | u32 val) | |
b67f4487 | 116 | { |
f68205a7 | 117 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
118 | __raw_writel(__raw_readl(reg) | val, reg); |
119 | } | |
120 | ||
f68205a7 PU |
121 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
122 | u32 val) | |
b67f4487 | 123 | { |
f68205a7 | 124 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
125 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
126 | } | |
127 | ||
f68205a7 PU |
128 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
129 | u32 val, u32 mask) | |
b67f4487 | 130 | { |
f68205a7 | 131 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
132 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
133 | } | |
134 | ||
f68205a7 PU |
135 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
136 | u32 val) | |
b67f4487 | 137 | { |
f68205a7 | 138 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
139 | } |
140 | ||
f68205a7 | 141 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 142 | { |
f68205a7 | 143 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
144 | } |
145 | ||
f68205a7 | 146 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
147 | { |
148 | int i = 0; | |
149 | ||
f68205a7 | 150 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
151 | |
152 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
153 | /* loop count is to avoid the lock-up */ | |
154 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 155 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
156 | break; |
157 | } | |
158 | ||
f68205a7 | 159 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
160 | printk(KERN_ERR "GBLCTL write error\n"); |
161 | } | |
162 | ||
4dcb5a0b PU |
163 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
164 | { | |
f68205a7 PU |
165 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
166 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
167 | |
168 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
169 | } | |
170 | ||
70091a3e | 171 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 172 | { |
bb372af0 PU |
173 | if (mcasp->rxnumevt) { /* enable FIFO */ |
174 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
175 | ||
176 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
177 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
178 | } | |
179 | ||
44982735 | 180 | /* Start clocks */ |
f68205a7 PU |
181 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
182 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
183 | /* |
184 | * When ASYNC == 0 the transmit and receive sections operate | |
185 | * synchronously from the transmit clock and frame sync. We need to make | |
186 | * sure that the TX signlas are enabled when starting reception. | |
187 | */ | |
188 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
189 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
190 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
191 | } |
192 | ||
44982735 | 193 | /* Activate serializer(s) */ |
f68205a7 | 194 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 195 | /* Release RX state machine */ |
f68205a7 | 196 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 197 | /* Release Frame Sync generator */ |
f68205a7 | 198 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 199 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 200 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
a7a3324a MLC |
201 | |
202 | /* enable receive IRQs */ | |
203 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
204 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
b67f4487 C |
205 | } |
206 | ||
70091a3e | 207 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 208 | { |
6a99fb5f C |
209 | u32 cnt; |
210 | ||
bb372af0 PU |
211 | if (mcasp->txnumevt) { /* enable FIFO */ |
212 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
213 | ||
214 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
215 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
216 | } | |
217 | ||
36bcecd0 | 218 | /* Start clocks */ |
f68205a7 PU |
219 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
220 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
36bcecd0 | 221 | /* Activate serializer(s) */ |
f68205a7 | 222 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 223 | |
36bcecd0 | 224 | /* wait for XDATA to be cleared */ |
6a99fb5f | 225 | cnt = 0; |
36bcecd0 PU |
226 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & |
227 | ~XRDATA) && (cnt < 100000)) | |
6a99fb5f C |
228 | cnt++; |
229 | ||
36bcecd0 PU |
230 | /* Release TX state machine */ |
231 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
232 | /* Release Frame Sync generator */ | |
233 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
a7a3324a MLC |
234 | |
235 | /* enable transmit IRQs */ | |
236 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
237 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
b67f4487 C |
238 | } |
239 | ||
70091a3e | 240 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 241 | { |
4dcb5a0b PU |
242 | mcasp->streams++; |
243 | ||
bb372af0 | 244 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 245 | mcasp_start_tx(mcasp); |
bb372af0 | 246 | else |
70091a3e | 247 | mcasp_start_rx(mcasp); |
b67f4487 C |
248 | } |
249 | ||
70091a3e | 250 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 251 | { |
a7a3324a MLC |
252 | /* disable IRQ sources */ |
253 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
254 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
255 | ||
4dcb5a0b PU |
256 | /* |
257 | * In synchronous mode stop the TX clocks if no other stream is | |
258 | * running | |
259 | */ | |
260 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 261 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 262 | |
f68205a7 PU |
263 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
264 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
265 | |
266 | if (mcasp->rxnumevt) { /* disable FIFO */ | |
267 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
268 | ||
269 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
270 | } | |
b67f4487 C |
271 | } |
272 | ||
70091a3e | 273 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 274 | { |
4dcb5a0b PU |
275 | u32 val = 0; |
276 | ||
a7a3324a MLC |
277 | /* disable IRQ sources */ |
278 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
279 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
280 | ||
4dcb5a0b PU |
281 | /* |
282 | * In synchronous mode keep TX clocks running if the capture stream is | |
283 | * still running. | |
284 | */ | |
285 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
286 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
287 | ||
f68205a7 PU |
288 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
289 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
290 | |
291 | if (mcasp->txnumevt) { /* disable FIFO */ | |
292 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
293 | ||
294 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
295 | } | |
b67f4487 C |
296 | } |
297 | ||
70091a3e | 298 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 299 | { |
4dcb5a0b PU |
300 | mcasp->streams--; |
301 | ||
0380866a | 302 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 303 | mcasp_stop_tx(mcasp); |
0380866a | 304 | else |
70091a3e | 305 | mcasp_stop_rx(mcasp); |
b67f4487 C |
306 | } |
307 | ||
a7a3324a MLC |
308 | static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) |
309 | { | |
310 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
311 | struct snd_pcm_substream *substream; | |
312 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; | |
313 | u32 handled_mask = 0; | |
314 | u32 stat; | |
315 | ||
316 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); | |
317 | if (stat & XUNDRN & irq_mask) { | |
318 | dev_warn(mcasp->dev, "Transmit buffer underflow\n"); | |
319 | handled_mask |= XUNDRN; | |
320 | ||
321 | substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; | |
322 | if (substream) { | |
323 | snd_pcm_stream_lock_irq(substream); | |
324 | if (snd_pcm_running(substream)) | |
325 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
326 | snd_pcm_stream_unlock_irq(substream); | |
327 | } | |
328 | } | |
329 | ||
330 | if (!handled_mask) | |
331 | dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", | |
332 | stat); | |
333 | ||
334 | if (stat & XRERR) | |
335 | handled_mask |= XRERR; | |
336 | ||
337 | /* Ack the handled event only */ | |
338 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); | |
339 | ||
340 | return IRQ_RETVAL(handled_mask); | |
341 | } | |
342 | ||
343 | static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) | |
344 | { | |
345 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
346 | struct snd_pcm_substream *substream; | |
347 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; | |
348 | u32 handled_mask = 0; | |
349 | u32 stat; | |
350 | ||
351 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); | |
352 | if (stat & ROVRN & irq_mask) { | |
353 | dev_warn(mcasp->dev, "Receive buffer overflow\n"); | |
354 | handled_mask |= ROVRN; | |
355 | ||
356 | substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; | |
357 | if (substream) { | |
358 | snd_pcm_stream_lock_irq(substream); | |
359 | if (snd_pcm_running(substream)) | |
360 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
361 | snd_pcm_stream_unlock_irq(substream); | |
362 | } | |
363 | } | |
364 | ||
365 | if (!handled_mask) | |
366 | dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", | |
367 | stat); | |
368 | ||
369 | if (stat & XRERR) | |
370 | handled_mask |= XRERR; | |
371 | ||
372 | /* Ack the handled event only */ | |
373 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); | |
374 | ||
375 | return IRQ_RETVAL(handled_mask); | |
376 | } | |
377 | ||
5a1b8a80 PU |
378 | static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) |
379 | { | |
380 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
381 | irqreturn_t ret = IRQ_NONE; | |
382 | ||
383 | if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) | |
384 | ret = davinci_mcasp_tx_irq_handler(irq, data); | |
385 | ||
386 | if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) | |
387 | ret |= davinci_mcasp_rx_irq_handler(irq, data); | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
b67f4487 C |
392 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
393 | unsigned int fmt) | |
394 | { | |
70091a3e | 395 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 396 | int ret = 0; |
6dfa9a4e | 397 | u32 data_delay; |
83f12503 | 398 | bool fs_pol_rising; |
ffd950f7 | 399 | bool inv_fs = false; |
b67f4487 | 400 | |
1d17a04e | 401 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 402 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
403 | case SND_SOC_DAIFMT_DSP_A: |
404 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
405 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
406 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
407 | data_delay = 1; | |
408 | break; | |
5296cf2d DM |
409 | case SND_SOC_DAIFMT_DSP_B: |
410 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
411 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
412 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
413 | /* No delay after FS */ |
414 | data_delay = 0; | |
5296cf2d | 415 | break; |
ffd950f7 | 416 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 417 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
418 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
419 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
420 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
421 | data_delay = 1; | |
ffd950f7 PU |
422 | /* FS need to be inverted */ |
423 | inv_fs = true; | |
5296cf2d | 424 | break; |
423761e0 PU |
425 | case SND_SOC_DAIFMT_LEFT_J: |
426 | /* configure a full-word SYNC pulse (LRCLK) */ | |
427 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
428 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
429 | /* No delay after FS */ | |
430 | data_delay = 0; | |
431 | break; | |
ffd950f7 PU |
432 | default: |
433 | ret = -EINVAL; | |
434 | goto out; | |
5296cf2d DM |
435 | } |
436 | ||
6dfa9a4e PU |
437 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
438 | FSXDLY(3)); | |
439 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
440 | FSRDLY(3)); | |
441 | ||
b67f4487 C |
442 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
443 | case SND_SOC_DAIFMT_CBS_CFS: | |
444 | /* codec is clock and frame slave */ | |
f68205a7 PU |
445 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
446 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 447 | |
f68205a7 PU |
448 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
449 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 450 | |
f68205a7 PU |
451 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
452 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 453 | mcasp->bclk_master = 1; |
b67f4487 | 454 | break; |
226e2f1b PU |
455 | case SND_SOC_DAIFMT_CBS_CFM: |
456 | /* codec is clock slave and frame master */ | |
457 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); | |
458 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
459 | ||
460 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | |
461 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
462 | ||
463 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); | |
464 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
465 | mcasp->bclk_master = 1; | |
466 | break; | |
517ee6cf C |
467 | case SND_SOC_DAIFMT_CBM_CFS: |
468 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
469 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
470 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 471 | |
f68205a7 PU |
472 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
473 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 474 | |
f68205a7 PU |
475 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
476 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 477 | mcasp->bclk_master = 0; |
517ee6cf | 478 | break; |
b67f4487 C |
479 | case SND_SOC_DAIFMT_CBM_CFM: |
480 | /* codec is clock and frame master */ | |
f68205a7 PU |
481 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
482 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 483 | |
f68205a7 PU |
484 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
485 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 486 | |
f68205a7 PU |
487 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
488 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 489 | mcasp->bclk_master = 0; |
b67f4487 | 490 | break; |
b67f4487 | 491 | default: |
1d17a04e PU |
492 | ret = -EINVAL; |
493 | goto out; | |
b67f4487 C |
494 | } |
495 | ||
496 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
497 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 498 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 499 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 500 | fs_pol_rising = true; |
b67f4487 | 501 | break; |
b67f4487 | 502 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 503 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 504 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 505 | fs_pol_rising = false; |
b67f4487 | 506 | break; |
b67f4487 | 507 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 508 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 509 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 510 | fs_pol_rising = false; |
b67f4487 | 511 | break; |
b67f4487 | 512 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 513 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 514 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 515 | fs_pol_rising = true; |
b67f4487 | 516 | break; |
b67f4487 | 517 | default: |
1d17a04e | 518 | ret = -EINVAL; |
83f12503 PU |
519 | goto out; |
520 | } | |
521 | ||
ffd950f7 PU |
522 | if (inv_fs) |
523 | fs_pol_rising = !fs_pol_rising; | |
524 | ||
83f12503 PU |
525 | if (fs_pol_rising) { |
526 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
527 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
528 | } else { | |
529 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
530 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 531 | } |
1d17a04e | 532 | out: |
6afda7f5 | 533 | pm_runtime_put(mcasp->dev); |
1d17a04e | 534 | return ret; |
b67f4487 C |
535 | } |
536 | ||
8813543e JS |
537 | static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
538 | int div, bool explicit) | |
4ed8c9b7 | 539 | { |
70091a3e | 540 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 | 541 | |
6afda7f5 | 542 | pm_runtime_get_sync(mcasp->dev); |
4ed8c9b7 DM |
543 | switch (div_id) { |
544 | case 0: /* MCLK divider */ | |
f68205a7 | 545 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 546 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 547 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
548 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
549 | break; | |
550 | ||
551 | case 1: /* BCLK divider */ | |
f68205a7 | 552 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 553 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 554 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 555 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
556 | if (explicit) |
557 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
558 | break; |
559 | ||
14a998be JS |
560 | case 2: /* |
561 | * BCLK/LRCLK ratio descries how many bit-clock cycles | |
562 | * fit into one frame. The clock ratio is given for a | |
563 | * full period of data (for I2S format both left and | |
564 | * right channels), so it has to be divided by number | |
565 | * of tdm-slots (for I2S - divided by 2). | |
566 | * Instead of storing this ratio, we calculate a new | |
567 | * tdm_slot width by dividing the the ratio by the | |
568 | * number of configured tdm slots. | |
569 | */ | |
570 | mcasp->slot_width = div / mcasp->tdm_slots; | |
571 | if (div % mcasp->tdm_slots) | |
572 | dev_warn(mcasp->dev, | |
573 | "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", | |
574 | __func__, div, mcasp->tdm_slots); | |
1b3bc060 DM |
575 | break; |
576 | ||
4ed8c9b7 DM |
577 | default: |
578 | return -EINVAL; | |
579 | } | |
580 | ||
6afda7f5 | 581 | pm_runtime_put(mcasp->dev); |
4ed8c9b7 DM |
582 | return 0; |
583 | } | |
584 | ||
8813543e JS |
585 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
586 | int div) | |
587 | { | |
588 | return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1); | |
589 | } | |
590 | ||
5b66aa2d DM |
591 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
592 | unsigned int freq, int dir) | |
593 | { | |
70091a3e | 594 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d | 595 | |
6afda7f5 | 596 | pm_runtime_get_sync(mcasp->dev); |
5b66aa2d | 597 | if (dir == SND_SOC_CLOCK_OUT) { |
f68205a7 PU |
598 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
599 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
600 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 601 | } else { |
f68205a7 PU |
602 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
603 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
604 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
605 | } |
606 | ||
ab8b14b6 JS |
607 | mcasp->sysclk_freq = freq; |
608 | ||
6afda7f5 | 609 | pm_runtime_put(mcasp->dev); |
5b66aa2d DM |
610 | return 0; |
611 | } | |
612 | ||
dd55ff83 JS |
613 | /* All serializers must have equal number of channels */ |
614 | static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, | |
615 | int serializers) | |
616 | { | |
617 | struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; | |
618 | unsigned int *list = (unsigned int *) cl->list; | |
619 | int slots = mcasp->tdm_slots; | |
620 | int i, count = 0; | |
621 | ||
622 | if (mcasp->tdm_mask[stream]) | |
623 | slots = hweight32(mcasp->tdm_mask[stream]); | |
624 | ||
625 | for (i = 2; i <= slots; i++) | |
626 | list[count++] = i; | |
627 | ||
628 | for (i = 2; i <= serializers; i++) | |
629 | list[count++] = i*slots; | |
630 | ||
631 | cl->count = count; | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) | |
637 | { | |
638 | int rx_serializers = 0, tx_serializers = 0, ret, i; | |
639 | ||
640 | for (i = 0; i < mcasp->num_serializer; i++) | |
641 | if (mcasp->serial_dir[i] == TX_MODE) | |
642 | tx_serializers++; | |
643 | else if (mcasp->serial_dir[i] == RX_MODE) | |
644 | rx_serializers++; | |
645 | ||
646 | ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, | |
647 | tx_serializers); | |
648 | if (ret) | |
649 | return ret; | |
650 | ||
651 | ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, | |
652 | rx_serializers); | |
653 | ||
654 | return ret; | |
655 | } | |
656 | ||
657 | ||
658 | static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, | |
659 | unsigned int tx_mask, | |
660 | unsigned int rx_mask, | |
661 | int slots, int slot_width) | |
662 | { | |
663 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
664 | ||
665 | dev_dbg(mcasp->dev, | |
666 | "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", | |
667 | __func__, tx_mask, rx_mask, slots, slot_width); | |
668 | ||
669 | if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { | |
670 | dev_err(mcasp->dev, | |
671 | "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", | |
672 | tx_mask, rx_mask, slots); | |
673 | return -EINVAL; | |
674 | } | |
675 | ||
676 | if (slot_width && | |
677 | (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { | |
678 | dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", | |
679 | __func__, slot_width); | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
683 | mcasp->tdm_slots = slots; | |
684 | mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = rx_mask; | |
685 | mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = tx_mask; | |
686 | mcasp->slot_width = slot_width; | |
687 | ||
688 | return davinci_mcasp_set_ch_constraints(mcasp); | |
689 | } | |
690 | ||
70091a3e | 691 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
14a998be | 692 | int sample_width) |
b67f4487 | 693 | { |
ba764b3d | 694 | u32 fmt; |
14a998be JS |
695 | u32 tx_rotate = (sample_width / 4) & 0x7; |
696 | u32 mask = (1ULL << sample_width) - 1; | |
697 | u32 slot_width = sample_width; | |
698 | ||
fe0a29e1 PU |
699 | /* |
700 | * For captured data we should not rotate, inversion and masking is | |
701 | * enoguh to get the data to the right position: | |
702 | * Format data from bus after reverse (XRBUF) | |
703 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
704 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
705 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
706 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
707 | */ | |
708 | u32 rx_rotate = 0; | |
b67f4487 | 709 | |
1b3bc060 | 710 | /* |
14a998be JS |
711 | * Setting the tdm slot width either with set_clkdiv() or |
712 | * set_tdm_slot() allows us to for example send 32 bits per | |
713 | * channel to the codec, while only 16 of them carry audio | |
714 | * payload. | |
1b3bc060 | 715 | */ |
14a998be | 716 | if (mcasp->slot_width) { |
d742b925 | 717 | /* |
14a998be JS |
718 | * When we have more bclk then it is needed for the |
719 | * data, we need to use the rotation to move the | |
720 | * received samples to have correct alignment. | |
d742b925 | 721 | */ |
14a998be JS |
722 | slot_width = mcasp->slot_width; |
723 | rx_rotate = (slot_width - sample_width) / 4; | |
d742b925 | 724 | } |
1b3bc060 | 725 | |
ba764b3d | 726 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
14a998be | 727 | fmt = (slot_width >> 1) - 1; |
b67f4487 | 728 | |
70091a3e | 729 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
730 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
731 | RXSSZ(0x0F)); | |
732 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
733 | TXSSZ(0x0F)); | |
734 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
735 | TXROT(7)); | |
736 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
737 | RXROT(7)); | |
738 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
739 | } |
740 | ||
f68205a7 | 741 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 742 | |
b67f4487 C |
743 | return 0; |
744 | } | |
745 | ||
662ffae9 | 746 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 747 | int period_words, int channels) |
b67f4487 | 748 | { |
5f04c603 | 749 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; |
b67f4487 | 750 | int i; |
6a99fb5f C |
751 | u8 tx_ser = 0; |
752 | u8 rx_ser = 0; | |
70091a3e | 753 | u8 slots = mcasp->tdm_slots; |
2952b27e | 754 | u8 max_active_serializers = (channels + slots - 1) / slots; |
72383192 | 755 | int active_serializers, numevt; |
487dce88 | 756 | u32 reg; |
b67f4487 | 757 | /* Default configuration */ |
40448e5e | 758 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 759 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
760 | |
761 | /* All PINS as McASP */ | |
f68205a7 | 762 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
763 | |
764 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
765 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
766 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 767 | } else { |
f68205a7 PU |
768 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
769 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
770 | } |
771 | ||
70091a3e | 772 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
773 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
774 | mcasp->serial_dir[i]); | |
70091a3e | 775 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 776 | tx_ser < max_active_serializers) { |
f68205a7 | 777 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
19db62ea MLC |
778 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
779 | DISMOD_LOW, DISMOD_MASK); | |
6a99fb5f | 780 | tx_ser++; |
70091a3e | 781 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 782 | rx_ser < max_active_serializers) { |
f68205a7 | 783 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 784 | rx_ser++; |
2952b27e | 785 | } else { |
f68205a7 PU |
786 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
787 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
788 | } |
789 | } | |
790 | ||
0bf0e8ae PU |
791 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
792 | active_serializers = tx_ser; | |
793 | numevt = mcasp->txnumevt; | |
794 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
795 | } else { | |
796 | active_serializers = rx_ser; | |
797 | numevt = mcasp->rxnumevt; | |
798 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
799 | } | |
ecf327c7 | 800 | |
0bf0e8ae | 801 | if (active_serializers < max_active_serializers) { |
70091a3e | 802 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
803 | "enabled in mcasp (%d)\n", channels, |
804 | active_serializers * slots); | |
ecf327c7 DM |
805 | return -EINVAL; |
806 | } | |
807 | ||
0bf0e8ae | 808 | /* AFIFO is not in use */ |
5f04c603 PU |
809 | if (!numevt) { |
810 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
811 | if (active_serializers > 1) { |
812 | /* | |
813 | * If more than one serializers are in use we have one | |
814 | * DMA request to provide data for all serializers. | |
815 | * For example if three serializers are enabled the DMA | |
816 | * need to transfer three words per DMA request. | |
817 | */ | |
33445643 PU |
818 | dma_data->maxburst = active_serializers; |
819 | } else { | |
33445643 PU |
820 | dma_data->maxburst = 0; |
821 | } | |
0bf0e8ae | 822 | return 0; |
5f04c603 | 823 | } |
6a99fb5f | 824 | |
dd093a0f PU |
825 | if (period_words % active_serializers) { |
826 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
827 | "active serializers: %d, %d\n", period_words, | |
828 | active_serializers); | |
829 | return -EINVAL; | |
830 | } | |
831 | ||
832 | /* | |
833 | * Calculate the optimal AFIFO depth for platform side: | |
834 | * The number of words for numevt need to be in steps of active | |
835 | * serializers. | |
836 | */ | |
72383192 PU |
837 | numevt = (numevt / active_serializers) * active_serializers; |
838 | ||
dd093a0f PU |
839 | while (period_words % numevt && numevt > 0) |
840 | numevt -= active_serializers; | |
841 | if (numevt <= 0) | |
0bf0e8ae | 842 | numevt = active_serializers; |
487dce88 | 843 | |
0bf0e8ae PU |
844 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
845 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 846 | |
5f04c603 | 847 | /* Configure the burst size for platform drivers */ |
33445643 PU |
848 | if (numevt == 1) |
849 | numevt = 0; | |
5f04c603 PU |
850 | dma_data->maxburst = numevt; |
851 | ||
2952b27e | 852 | return 0; |
b67f4487 C |
853 | } |
854 | ||
18a4f557 MLC |
855 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, |
856 | int channels) | |
b67f4487 C |
857 | { |
858 | int i, active_slots; | |
18a4f557 MLC |
859 | int total_slots; |
860 | int active_serializers; | |
b67f4487 | 861 | u32 mask = 0; |
cbc7956c | 862 | u32 busel = 0; |
b67f4487 | 863 | |
18a4f557 MLC |
864 | total_slots = mcasp->tdm_slots; |
865 | ||
866 | /* | |
867 | * If more than one serializer is needed, then use them with | |
dd55ff83 JS |
868 | * all the specified tdm_slots. Otherwise, one serializer can |
869 | * cope with the transaction using just as many slots as there | |
870 | * are channels in the stream. | |
18a4f557 | 871 | */ |
dd55ff83 JS |
872 | if (mcasp->tdm_mask[stream]) { |
873 | active_slots = hweight32(mcasp->tdm_mask[stream]); | |
874 | active_serializers = (channels + active_slots - 1) / | |
875 | active_slots; | |
876 | if (active_serializers == 1) { | |
877 | active_slots = channels; | |
878 | for (i = 0; i < total_slots; i++) { | |
879 | if ((1 << i) & mcasp->tdm_mask[stream]) { | |
880 | mask |= (1 << i); | |
881 | if (--active_slots <= 0) | |
882 | break; | |
883 | } | |
884 | } | |
885 | } | |
886 | } else { | |
887 | active_serializers = (channels + total_slots - 1) / total_slots; | |
888 | if (active_serializers == 1) | |
889 | active_slots = channels; | |
890 | else | |
891 | active_slots = total_slots; | |
b67f4487 | 892 | |
dd55ff83 JS |
893 | for (i = 0; i < active_slots; i++) |
894 | mask |= (1 << i); | |
895 | } | |
f68205a7 | 896 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 897 | |
cbc7956c PU |
898 | if (!mcasp->dat_port) |
899 | busel = TXSEL; | |
900 | ||
dd55ff83 JS |
901 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
902 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); | |
903 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
904 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
905 | FSXMOD(total_slots), FSXMOD(0x1FF)); | |
906 | } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { | |
907 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
908 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
909 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
910 | FSRMOD(total_slots), FSRMOD(0x1FF)); | |
911 | } | |
2c56c4c2 PU |
912 | |
913 | return 0; | |
b67f4487 C |
914 | } |
915 | ||
916 | /* S/PDIF */ | |
6479285d DM |
917 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
918 | unsigned int rate) | |
b67f4487 | 919 | { |
6479285d DM |
920 | u32 cs_value = 0; |
921 | u8 *cs_bytes = (u8*) &cs_value; | |
922 | ||
b67f4487 C |
923 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
924 | and LSB first */ | |
f68205a7 | 925 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
926 | |
927 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 928 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
929 | |
930 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 931 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
932 | |
933 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 934 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 935 | |
f68205a7 | 936 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
937 | |
938 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 939 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
940 | |
941 | /* Enable the DIT */ | |
f68205a7 | 942 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 943 | |
6479285d DM |
944 | /* Set S/PDIF channel status bits */ |
945 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
946 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
947 | ||
948 | switch (rate) { | |
949 | case 22050: | |
950 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
951 | break; | |
952 | case 24000: | |
953 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
954 | break; | |
955 | case 32000: | |
956 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
957 | break; | |
958 | case 44100: | |
959 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
960 | break; | |
961 | case 48000: | |
962 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
963 | break; | |
964 | case 88200: | |
965 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
966 | break; | |
967 | case 96000: | |
968 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
969 | break; | |
970 | case 176400: | |
971 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
972 | break; | |
973 | case 192000: | |
974 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
975 | break; | |
976 | default: | |
977 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
978 | return -EINVAL; | |
979 | } | |
980 | ||
981 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
982 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
983 | ||
2c56c4c2 | 984 | return 0; |
b67f4487 C |
985 | } |
986 | ||
a75a053f JS |
987 | static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, |
988 | unsigned int bclk_freq, | |
989 | int *error_ppm) | |
990 | { | |
991 | int div = mcasp->sysclk_freq / bclk_freq; | |
992 | int rem = mcasp->sysclk_freq % bclk_freq; | |
993 | ||
994 | if (rem != 0) { | |
995 | if (div == 0 || | |
996 | ((mcasp->sysclk_freq / div) - bclk_freq) > | |
997 | (bclk_freq - (mcasp->sysclk_freq / (div+1)))) { | |
998 | div++; | |
999 | rem = rem - bclk_freq; | |
1000 | } | |
1001 | } | |
1002 | if (error_ppm) | |
1003 | *error_ppm = | |
1004 | (div*1000000 + (int)div64_long(1000000LL*rem, | |
1005 | (int)bclk_freq)) | |
1006 | /div - 1000000; | |
1007 | ||
1008 | return div; | |
1009 | } | |
1010 | ||
b67f4487 C |
1011 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, |
1012 | struct snd_pcm_hw_params *params, | |
1013 | struct snd_soc_dai *cpu_dai) | |
1014 | { | |
70091a3e | 1015 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 1016 | int word_length; |
a7e46bd9 | 1017 | int channels = params_channels(params); |
dd093a0f | 1018 | int period_size = params_period_size(params); |
2c56c4c2 | 1019 | int ret; |
ab8b14b6 | 1020 | |
8267525c DM |
1021 | /* |
1022 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
1023 | * the machine driver, we need to calculate the ratio. | |
1024 | */ | |
1025 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
1f114f77 | 1026 | int slots = mcasp->tdm_slots; |
a75a053f JS |
1027 | int rate = params_rate(params); |
1028 | int sbits = params_width(params); | |
1029 | int ppm, div; | |
1030 | ||
dd55ff83 JS |
1031 | if (mcasp->slot_width) |
1032 | sbits = mcasp->slot_width; | |
1033 | ||
1f114f77 | 1034 | div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots, |
a75a053f JS |
1035 | &ppm); |
1036 | if (ppm) | |
1037 | dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", | |
1038 | ppm); | |
1039 | ||
8813543e | 1040 | __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0); |
ab8b14b6 JS |
1041 | } |
1042 | ||
dd093a0f PU |
1043 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
1044 | period_size * channels, channels); | |
0f7d9a63 PU |
1045 | if (ret) |
1046 | return ret; | |
1047 | ||
70091a3e | 1048 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 1049 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 1050 | else |
18a4f557 MLC |
1051 | ret = mcasp_i2s_hw_param(mcasp, substream->stream, |
1052 | channels); | |
2c56c4c2 PU |
1053 | |
1054 | if (ret) | |
1055 | return ret; | |
b67f4487 C |
1056 | |
1057 | switch (params_format(params)) { | |
0a9d1385 | 1058 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 | 1059 | case SNDRV_PCM_FORMAT_S8: |
ba764b3d | 1060 | word_length = 8; |
b67f4487 C |
1061 | break; |
1062 | ||
0a9d1385 | 1063 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 | 1064 | case SNDRV_PCM_FORMAT_S16_LE: |
ba764b3d | 1065 | word_length = 16; |
b67f4487 C |
1066 | break; |
1067 | ||
21eb24d8 DM |
1068 | case SNDRV_PCM_FORMAT_U24_3LE: |
1069 | case SNDRV_PCM_FORMAT_S24_3LE: | |
ba764b3d | 1070 | word_length = 24; |
21eb24d8 DM |
1071 | break; |
1072 | ||
6b7fa011 DM |
1073 | case SNDRV_PCM_FORMAT_U24_LE: |
1074 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
1075 | word_length = 24; |
1076 | break; | |
1077 | ||
0a9d1385 | 1078 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 | 1079 | case SNDRV_PCM_FORMAT_S32_LE: |
ba764b3d | 1080 | word_length = 32; |
b67f4487 C |
1081 | break; |
1082 | ||
1083 | default: | |
1084 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
1085 | return -EINVAL; | |
1086 | } | |
6a99fb5f | 1087 | |
70091a3e | 1088 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 | 1089 | |
11277833 PU |
1090 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) |
1091 | mcasp->channels = channels; | |
1092 | ||
b67f4487 C |
1093 | return 0; |
1094 | } | |
1095 | ||
1096 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
1097 | int cmd, struct snd_soc_dai *cpu_dai) | |
1098 | { | |
70091a3e | 1099 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
1100 | int ret = 0; |
1101 | ||
1102 | switch (cmd) { | |
b67f4487 | 1103 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
1104 | case SNDRV_PCM_TRIGGER_START: |
1105 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 1106 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 1107 | break; |
b67f4487 | 1108 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 1109 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 1110 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 1111 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
1112 | break; |
1113 | ||
1114 | default: | |
1115 | ret = -EINVAL; | |
1116 | } | |
1117 | ||
1118 | return ret; | |
1119 | } | |
1120 | ||
a75a053f JS |
1121 | static const unsigned int davinci_mcasp_dai_rates[] = { |
1122 | 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, | |
1123 | 88200, 96000, 176400, 192000, | |
1124 | }; | |
1125 | ||
1126 | #define DAVINCI_MAX_RATE_ERROR_PPM 1000 | |
1127 | ||
1128 | static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, | |
1129 | struct snd_pcm_hw_rule *rule) | |
1130 | { | |
1131 | struct davinci_mcasp_ruledata *rd = rule->private; | |
1132 | struct snd_interval *ri = | |
1133 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1134 | int sbits = params_width(params); | |
1f114f77 | 1135 | int slots = rd->mcasp->tdm_slots; |
518f6bab JS |
1136 | struct snd_interval range; |
1137 | int i; | |
a75a053f | 1138 | |
dd55ff83 JS |
1139 | if (rd->mcasp->slot_width) |
1140 | sbits = rd->mcasp->slot_width; | |
1141 | ||
518f6bab JS |
1142 | snd_interval_any(&range); |
1143 | range.empty = 1; | |
a75a053f JS |
1144 | |
1145 | for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { | |
518f6bab | 1146 | if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { |
1f114f77 | 1147 | uint bclk_freq = sbits*slots* |
a75a053f JS |
1148 | davinci_mcasp_dai_rates[i]; |
1149 | int ppm; | |
1150 | ||
1151 | davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm); | |
518f6bab JS |
1152 | if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { |
1153 | if (range.empty) { | |
1154 | range.min = davinci_mcasp_dai_rates[i]; | |
1155 | range.empty = 0; | |
1156 | } | |
1157 | range.max = davinci_mcasp_dai_rates[i]; | |
1158 | } | |
a75a053f JS |
1159 | } |
1160 | } | |
518f6bab | 1161 | |
a75a053f | 1162 | dev_dbg(rd->mcasp->dev, |
518f6bab JS |
1163 | "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", |
1164 | ri->min, ri->max, range.min, range.max, sbits, slots); | |
a75a053f | 1165 | |
518f6bab JS |
1166 | return snd_interval_refine(hw_param_interval(params, rule->var), |
1167 | &range); | |
a75a053f JS |
1168 | } |
1169 | ||
1170 | static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, | |
1171 | struct snd_pcm_hw_rule *rule) | |
1172 | { | |
1173 | struct davinci_mcasp_ruledata *rd = rule->private; | |
1174 | struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); | |
1175 | struct snd_mask nfmt; | |
1176 | int rate = params_rate(params); | |
1f114f77 | 1177 | int slots = rd->mcasp->tdm_slots; |
a75a053f JS |
1178 | int i, count = 0; |
1179 | ||
1180 | snd_mask_none(&nfmt); | |
1181 | ||
a75a053f JS |
1182 | for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) { |
1183 | if (snd_mask_test(fmt, i)) { | |
dd55ff83 | 1184 | uint sbits = snd_pcm_format_width(i); |
a75a053f JS |
1185 | int ppm; |
1186 | ||
dd55ff83 JS |
1187 | if (rd->mcasp->slot_width) |
1188 | sbits = rd->mcasp->slot_width; | |
1189 | ||
1190 | davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate, | |
1191 | &ppm); | |
a75a053f JS |
1192 | if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { |
1193 | snd_mask_set(&nfmt, i); | |
1194 | count++; | |
1195 | } | |
1196 | } | |
1197 | } | |
1198 | dev_dbg(rd->mcasp->dev, | |
1f114f77 JS |
1199 | "%d possible sample format for %d Hz and %d tdm slots\n", |
1200 | count, rate, slots); | |
a75a053f JS |
1201 | |
1202 | return snd_mask_refine(fmt, &nfmt); | |
1203 | } | |
1204 | ||
11277833 PU |
1205 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
1206 | struct snd_soc_dai *cpu_dai) | |
1207 | { | |
1208 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
4cd9db08 PU |
1209 | struct davinci_mcasp_ruledata *ruledata = |
1210 | &mcasp->ruledata[substream->stream]; | |
11277833 PU |
1211 | u32 max_channels = 0; |
1212 | int i, dir; | |
dd55ff83 JS |
1213 | int tdm_slots = mcasp->tdm_slots; |
1214 | ||
1215 | if (mcasp->tdm_mask[substream->stream]) | |
1216 | tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); | |
11277833 | 1217 | |
a7a3324a MLC |
1218 | mcasp->substreams[substream->stream] = substream; |
1219 | ||
11277833 PU |
1220 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1221 | return 0; | |
1222 | ||
1223 | /* | |
1224 | * Limit the maximum allowed channels for the first stream: | |
1225 | * number of serializers for the direction * tdm slots per serializer | |
1226 | */ | |
1227 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1228 | dir = TX_MODE; | |
1229 | else | |
1230 | dir = RX_MODE; | |
1231 | ||
1232 | for (i = 0; i < mcasp->num_serializer; i++) { | |
1233 | if (mcasp->serial_dir[i] == dir) | |
1234 | max_channels++; | |
1235 | } | |
4cd9db08 | 1236 | ruledata->serializers = max_channels; |
dd55ff83 | 1237 | max_channels *= tdm_slots; |
11277833 PU |
1238 | /* |
1239 | * If the already active stream has less channels than the calculated | |
1240 | * limnit based on the seirializers * tdm_slots, we need to use that as | |
1241 | * a constraint for the second stream. | |
1242 | * Otherwise (first stream or less allowed channels) we use the | |
1243 | * calculated constraint. | |
1244 | */ | |
1245 | if (mcasp->channels && mcasp->channels < max_channels) | |
1246 | max_channels = mcasp->channels; | |
dd55ff83 JS |
1247 | /* |
1248 | * But we can always allow channels upto the amount of | |
1249 | * the available tdm_slots. | |
1250 | */ | |
1251 | if (max_channels < tdm_slots) | |
1252 | max_channels = tdm_slots; | |
11277833 PU |
1253 | |
1254 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1255 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1256 | 2, max_channels); | |
a75a053f | 1257 | |
dd55ff83 JS |
1258 | snd_pcm_hw_constraint_list(substream->runtime, |
1259 | 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
1260 | &mcasp->chconstr[substream->stream]); | |
1261 | ||
1262 | if (mcasp->slot_width) | |
1263 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1264 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1265 | 8, mcasp->slot_width); | |
5935a056 | 1266 | |
a75a053f JS |
1267 | /* |
1268 | * If we rely on implicit BCLK divider setting we should | |
1269 | * set constraints based on what we can provide. | |
1270 | */ | |
1271 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
1272 | int ret; | |
1273 | ||
4cd9db08 | 1274 | ruledata->mcasp = mcasp; |
a75a053f JS |
1275 | |
1276 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
1277 | SNDRV_PCM_HW_PARAM_RATE, | |
1278 | davinci_mcasp_hw_rule_rate, | |
4cd9db08 | 1279 | ruledata, |
1f114f77 | 1280 | SNDRV_PCM_HW_PARAM_FORMAT, -1); |
a75a053f JS |
1281 | if (ret) |
1282 | return ret; | |
1283 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
1284 | SNDRV_PCM_HW_PARAM_FORMAT, | |
1285 | davinci_mcasp_hw_rule_format, | |
4cd9db08 | 1286 | ruledata, |
1f114f77 | 1287 | SNDRV_PCM_HW_PARAM_RATE, -1); |
a75a053f JS |
1288 | if (ret) |
1289 | return ret; | |
1290 | } | |
1291 | ||
11277833 PU |
1292 | return 0; |
1293 | } | |
1294 | ||
1295 | static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, | |
1296 | struct snd_soc_dai *cpu_dai) | |
1297 | { | |
1298 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
1299 | ||
a7a3324a MLC |
1300 | mcasp->substreams[substream->stream] = NULL; |
1301 | ||
11277833 PU |
1302 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1303 | return; | |
1304 | ||
1305 | if (!cpu_dai->active) | |
1306 | mcasp->channels = 0; | |
1307 | } | |
1308 | ||
85e7652d | 1309 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
11277833 PU |
1310 | .startup = davinci_mcasp_startup, |
1311 | .shutdown = davinci_mcasp_shutdown, | |
b67f4487 C |
1312 | .trigger = davinci_mcasp_trigger, |
1313 | .hw_params = davinci_mcasp_hw_params, | |
1314 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 1315 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 1316 | .set_sysclk = davinci_mcasp_set_sysclk, |
dd55ff83 | 1317 | .set_tdm_slot = davinci_mcasp_set_tdm_slot, |
b67f4487 C |
1318 | }; |
1319 | ||
d5902f69 PU |
1320 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
1321 | { | |
1322 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
1323 | ||
9759e7ef PU |
1324 | dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
1325 | dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
d5902f69 PU |
1326 | |
1327 | return 0; | |
1328 | } | |
1329 | ||
135014ad PU |
1330 | #ifdef CONFIG_PM_SLEEP |
1331 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
1332 | { | |
1333 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1334 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1335 | u32 reg; |
1cc0c054 | 1336 | int i; |
135014ad | 1337 | |
27796e75 | 1338 | context->pm_state = pm_runtime_active(mcasp->dev); |
6afda7f5 PU |
1339 | if (!context->pm_state) |
1340 | pm_runtime_get_sync(mcasp->dev); | |
1341 | ||
1cc0c054 PU |
1342 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1343 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 1344 | |
f114ce60 PU |
1345 | if (mcasp->txnumevt) { |
1346 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1347 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
1348 | } | |
1349 | if (mcasp->rxnumevt) { | |
1350 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1351 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
1352 | } | |
135014ad | 1353 | |
f114ce60 PU |
1354 | for (i = 0; i < mcasp->num_serializer; i++) |
1355 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
1356 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad | 1357 | |
6afda7f5 PU |
1358 | pm_runtime_put_sync(mcasp->dev); |
1359 | ||
135014ad PU |
1360 | return 0; |
1361 | } | |
1362 | ||
1363 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
1364 | { | |
1365 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1366 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1367 | u32 reg; |
1cc0c054 | 1368 | int i; |
790bb94b | 1369 | |
6afda7f5 PU |
1370 | pm_runtime_get_sync(mcasp->dev); |
1371 | ||
1cc0c054 PU |
1372 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1373 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 1374 | |
f114ce60 PU |
1375 | if (mcasp->txnumevt) { |
1376 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1377 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
1378 | } | |
1379 | if (mcasp->rxnumevt) { | |
1380 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1381 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
1382 | } | |
790bb94b | 1383 | |
f114ce60 PU |
1384 | for (i = 0; i < mcasp->num_serializer; i++) |
1385 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
1386 | context->xrsr_regs[i]); | |
135014ad | 1387 | |
6afda7f5 PU |
1388 | if (!context->pm_state) |
1389 | pm_runtime_put_sync(mcasp->dev); | |
1390 | ||
135014ad PU |
1391 | return 0; |
1392 | } | |
1393 | #else | |
1394 | #define davinci_mcasp_suspend NULL | |
1395 | #define davinci_mcasp_resume NULL | |
1396 | #endif | |
1397 | ||
ed29cd5e PU |
1398 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
1399 | ||
0a9d1385 BG |
1400 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
1401 | SNDRV_PCM_FMTBIT_U8 | \ | |
1402 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
1403 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
1404 | SNDRV_PCM_FMTBIT_S24_LE | \ |
1405 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
1406 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
1407 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
1408 | SNDRV_PCM_FMTBIT_S32_LE | \ |
1409 | SNDRV_PCM_FMTBIT_U32_LE) | |
1410 | ||
f0fba2ad | 1411 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 1412 | { |
f0fba2ad | 1413 | .name = "davinci-mcasp.0", |
d5902f69 | 1414 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
1415 | .suspend = davinci_mcasp_suspend, |
1416 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
1417 | .playback = { |
1418 | .channels_min = 2, | |
2952b27e | 1419 | .channels_max = 32 * 16, |
b67f4487 | 1420 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1421 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1422 | }, |
1423 | .capture = { | |
1424 | .channels_min = 2, | |
2952b27e | 1425 | .channels_max = 32 * 16, |
b67f4487 | 1426 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1427 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1428 | }, |
1429 | .ops = &davinci_mcasp_dai_ops, | |
1430 | ||
d75249f5 | 1431 | .symmetric_samplebits = 1, |
295c3405 | 1432 | .symmetric_rates = 1, |
b67f4487 C |
1433 | }, |
1434 | { | |
58e48d97 | 1435 | .name = "davinci-mcasp.1", |
d5902f69 | 1436 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
1437 | .playback = { |
1438 | .channels_min = 1, | |
1439 | .channels_max = 384, | |
1440 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 1441 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1442 | }, |
1443 | .ops = &davinci_mcasp_dai_ops, | |
1444 | }, | |
1445 | ||
1446 | }; | |
b67f4487 | 1447 | |
eeef0eda KM |
1448 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
1449 | .name = "davinci-mcasp", | |
1450 | }; | |
1451 | ||
256ba181 | 1452 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 1453 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
1454 | .tx_dma_offset = 0x400, |
1455 | .rx_dma_offset = 0x400, | |
256ba181 JS |
1456 | .version = MCASP_VERSION_1, |
1457 | }; | |
1458 | ||
d1debafc | 1459 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
1460 | .tx_dma_offset = 0x2000, |
1461 | .rx_dma_offset = 0x2000, | |
256ba181 JS |
1462 | .version = MCASP_VERSION_2, |
1463 | }; | |
1464 | ||
d1debafc | 1465 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
1466 | .tx_dma_offset = 0, |
1467 | .rx_dma_offset = 0, | |
256ba181 JS |
1468 | .version = MCASP_VERSION_3, |
1469 | }; | |
1470 | ||
d1debafc | 1471 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
1472 | .tx_dma_offset = 0x200, |
1473 | .rx_dma_offset = 0x284, | |
453c4990 PU |
1474 | .version = MCASP_VERSION_4, |
1475 | }; | |
1476 | ||
3e3b8c34 HG |
1477 | static const struct of_device_id mcasp_dt_ids[] = { |
1478 | { | |
1479 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1480 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1481 | }, |
1482 | { | |
1483 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1484 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1485 | }, |
e5ec69da | 1486 | { |
3af9e031 | 1487 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1488 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1489 | }, |
453c4990 PU |
1490 | { |
1491 | .compatible = "ti,dra7-mcasp-audio", | |
1492 | .data = &dra7_mcasp_pdata, | |
1493 | }, | |
3e3b8c34 HG |
1494 | { /* sentinel */ } |
1495 | }; | |
1496 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1497 | ||
ae726e93 PU |
1498 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1499 | { | |
1500 | struct device_node *node = pdev->dev.of_node; | |
1501 | struct clk *gfclk, *parent_clk; | |
1502 | const char *parent_name; | |
1503 | int ret; | |
1504 | ||
1505 | if (!node) | |
1506 | return 0; | |
1507 | ||
1508 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1509 | if (!parent_name) | |
1510 | return 0; | |
1511 | ||
1512 | gfclk = clk_get(&pdev->dev, "fck"); | |
1513 | if (IS_ERR(gfclk)) { | |
1514 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1515 | return PTR_ERR(gfclk); | |
1516 | } | |
1517 | ||
1518 | parent_clk = clk_get(NULL, parent_name); | |
1519 | if (IS_ERR(parent_clk)) { | |
1520 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1521 | ret = PTR_ERR(parent_clk); | |
1522 | goto err1; | |
1523 | } | |
1524 | ||
1525 | ret = clk_set_parent(gfclk, parent_clk); | |
1526 | if (ret) { | |
1527 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1528 | goto err2; | |
1529 | } | |
1530 | ||
1531 | err2: | |
1532 | clk_put(parent_clk); | |
1533 | err1: | |
1534 | clk_put(gfclk); | |
1535 | return ret; | |
1536 | } | |
1537 | ||
d1debafc | 1538 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1539 | struct platform_device *pdev) |
1540 | { | |
1541 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1542 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1543 | const struct of_device_id *match = |
ea421eb1 | 1544 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1545 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1546 | |
1547 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1548 | u32 val; |
1549 | int i, ret = 0; | |
1550 | ||
1551 | if (pdev->dev.platform_data) { | |
1552 | pdata = pdev->dev.platform_data; | |
1553 | return pdata; | |
1554 | } else if (match) { | |
d1debafc | 1555 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1556 | } else { |
1557 | /* control shouldn't reach here. something is wrong */ | |
1558 | ret = -EINVAL; | |
1559 | goto nodata; | |
1560 | } | |
1561 | ||
3e3b8c34 HG |
1562 | ret = of_property_read_u32(np, "op-mode", &val); |
1563 | if (ret >= 0) | |
1564 | pdata->op_mode = val; | |
1565 | ||
1566 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1567 | if (ret >= 0) { |
1568 | if (val < 2 || val > 32) { | |
1569 | dev_err(&pdev->dev, | |
1570 | "tdm-slots must be in rage [2-32]\n"); | |
1571 | ret = -EINVAL; | |
1572 | goto nodata; | |
1573 | } | |
1574 | ||
3e3b8c34 | 1575 | pdata->tdm_slots = val; |
2952b27e | 1576 | } |
3e3b8c34 | 1577 | |
3e3b8c34 HG |
1578 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1579 | val /= sizeof(u32); | |
3e3b8c34 | 1580 | if (of_serial_dir32) { |
1427e660 PU |
1581 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1582 | (sizeof(*of_serial_dir) * val), | |
1583 | GFP_KERNEL); | |
3e3b8c34 HG |
1584 | if (!of_serial_dir) { |
1585 | ret = -ENOMEM; | |
1586 | goto nodata; | |
1587 | } | |
1588 | ||
1427e660 | 1589 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1590 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1591 | ||
1427e660 | 1592 | pdata->num_serializer = val; |
3e3b8c34 HG |
1593 | pdata->serial_dir = of_serial_dir; |
1594 | } | |
1595 | ||
4023fe6f JS |
1596 | ret = of_property_match_string(np, "dma-names", "tx"); |
1597 | if (ret < 0) | |
1598 | goto nodata; | |
1599 | ||
1600 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1601 | &dma_spec); | |
1602 | if (ret < 0) | |
1603 | goto nodata; | |
1604 | ||
1605 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1606 | ||
caa1d794 PU |
1607 | /* RX is not valid in DIT mode */ |
1608 | if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
1609 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1610 | if (ret < 0) | |
1611 | goto nodata; | |
4023fe6f | 1612 | |
caa1d794 PU |
1613 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
1614 | &dma_spec); | |
1615 | if (ret < 0) | |
1616 | goto nodata; | |
4023fe6f | 1617 | |
caa1d794 PU |
1618 | pdata->rx_dma_channel = dma_spec.args[0]; |
1619 | } | |
4023fe6f | 1620 | |
3e3b8c34 HG |
1621 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1622 | if (ret >= 0) | |
1623 | pdata->txnumevt = val; | |
1624 | ||
1625 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1626 | if (ret >= 0) | |
1627 | pdata->rxnumevt = val; | |
1628 | ||
1629 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1630 | if (ret >= 0) | |
1631 | pdata->sram_size_playback = val; | |
1632 | ||
1633 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1634 | if (ret >= 0) | |
1635 | pdata->sram_size_capture = val; | |
1636 | ||
1637 | return pdata; | |
1638 | ||
1639 | nodata: | |
1640 | if (ret < 0) { | |
1641 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1642 | ret); | |
1643 | pdata = NULL; | |
1644 | } | |
1645 | return pdata; | |
1646 | } | |
1647 | ||
9fbd58cf JS |
1648 | enum { |
1649 | PCM_EDMA, | |
1650 | PCM_SDMA, | |
1651 | }; | |
1652 | static const char *sdma_prefix = "ti,omap"; | |
1653 | ||
1654 | static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) | |
1655 | { | |
1656 | struct dma_chan *chan; | |
1657 | const char *tmp; | |
1658 | int ret = PCM_EDMA; | |
1659 | ||
1660 | if (!mcasp->dev->of_node) | |
1661 | return PCM_EDMA; | |
1662 | ||
1663 | tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; | |
1664 | chan = dma_request_slave_channel_reason(mcasp->dev, tmp); | |
1665 | if (IS_ERR(chan)) { | |
1666 | if (PTR_ERR(chan) != -EPROBE_DEFER) | |
1667 | dev_err(mcasp->dev, | |
1668 | "Can't verify DMA configuration (%ld)\n", | |
1669 | PTR_ERR(chan)); | |
1670 | return PTR_ERR(chan); | |
1671 | } | |
1672 | BUG_ON(!chan->device || !chan->device->dev); | |
1673 | ||
1674 | if (chan->device->dev->of_node) | |
1675 | ret = of_property_read_string(chan->device->dev->of_node, | |
1676 | "compatible", &tmp); | |
1677 | else | |
1678 | dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); | |
1679 | ||
1680 | dma_release_channel(chan); | |
1681 | if (ret) | |
1682 | return ret; | |
1683 | ||
1684 | dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); | |
1685 | if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) | |
1686 | return PCM_SDMA; | |
1687 | ||
1688 | return PCM_EDMA; | |
1689 | } | |
1690 | ||
b67f4487 C |
1691 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1692 | { | |
8de131f2 | 1693 | struct snd_dmaengine_dai_dma_data *dma_data; |
508a43fd | 1694 | struct resource *mem, *res, *dat; |
d1debafc | 1695 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1696 | struct davinci_mcasp *mcasp; |
a7a3324a | 1697 | char *irq_name; |
9759e7ef | 1698 | int *dma; |
a7a3324a | 1699 | int irq; |
96d31e2b | 1700 | int ret; |
b67f4487 | 1701 | |
3e3b8c34 HG |
1702 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1703 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1704 | return -EINVAL; | |
1705 | } | |
1706 | ||
70091a3e | 1707 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1708 | GFP_KERNEL); |
70091a3e | 1709 | if (!mcasp) |
b67f4487 C |
1710 | return -ENOMEM; |
1711 | ||
3e3b8c34 HG |
1712 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1713 | if (!pdata) { | |
1714 | dev_err(&pdev->dev, "no platform data\n"); | |
1715 | return -EINVAL; | |
1716 | } | |
1717 | ||
256ba181 | 1718 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1719 | if (!mem) { |
70091a3e | 1720 | dev_warn(mcasp->dev, |
256ba181 JS |
1721 | "\"mpu\" mem resource not found, using index 0\n"); |
1722 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1723 | if (!mem) { | |
1724 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1725 | return -ENODEV; | |
1726 | } | |
b67f4487 C |
1727 | } |
1728 | ||
508a43fd AL |
1729 | mcasp->base = devm_ioremap_resource(&pdev->dev, mem); |
1730 | if (IS_ERR(mcasp->base)) | |
1731 | return PTR_ERR(mcasp->base); | |
b67f4487 | 1732 | |
10884347 | 1733 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1734 | |
70091a3e | 1735 | mcasp->op_mode = pdata->op_mode; |
1a5923da PU |
1736 | /* sanity check for tdm slots parameter */ |
1737 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { | |
1738 | if (pdata->tdm_slots < 2) { | |
1739 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1740 | pdata->tdm_slots); | |
1741 | mcasp->tdm_slots = 2; | |
1742 | } else if (pdata->tdm_slots > 32) { | |
1743 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1744 | pdata->tdm_slots); | |
1745 | mcasp->tdm_slots = 32; | |
1746 | } else { | |
1747 | mcasp->tdm_slots = pdata->tdm_slots; | |
1748 | } | |
1749 | } | |
1750 | ||
70091a3e | 1751 | mcasp->num_serializer = pdata->num_serializer; |
f114ce60 PU |
1752 | #ifdef CONFIG_PM_SLEEP |
1753 | mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, | |
1754 | sizeof(u32) * mcasp->num_serializer, | |
1755 | GFP_KERNEL); | |
1756 | #endif | |
70091a3e PU |
1757 | mcasp->serial_dir = pdata->serial_dir; |
1758 | mcasp->version = pdata->version; | |
1759 | mcasp->txnumevt = pdata->txnumevt; | |
1760 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1761 | |
70091a3e | 1762 | mcasp->dev = &pdev->dev; |
b67f4487 | 1763 | |
5a1b8a80 PU |
1764 | irq = platform_get_irq_byname(pdev, "common"); |
1765 | if (irq >= 0) { | |
ab1fffe3 | 1766 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", |
5a1b8a80 PU |
1767 | dev_name(&pdev->dev)); |
1768 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1769 | davinci_mcasp_common_irq_handler, | |
8f511ffb PU |
1770 | IRQF_ONESHOT | IRQF_SHARED, |
1771 | irq_name, mcasp); | |
5a1b8a80 PU |
1772 | if (ret) { |
1773 | dev_err(&pdev->dev, "common IRQ request failed\n"); | |
1774 | goto err; | |
1775 | } | |
1776 | ||
1777 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1778 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1779 | } | |
1780 | ||
a7a3324a MLC |
1781 | irq = platform_get_irq_byname(pdev, "rx"); |
1782 | if (irq >= 0) { | |
ab1fffe3 | 1783 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", |
a7a3324a MLC |
1784 | dev_name(&pdev->dev)); |
1785 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1786 | davinci_mcasp_rx_irq_handler, | |
1787 | IRQF_ONESHOT, irq_name, mcasp); | |
1788 | if (ret) { | |
1789 | dev_err(&pdev->dev, "RX IRQ request failed\n"); | |
1790 | goto err; | |
1791 | } | |
1792 | ||
1793 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1794 | } | |
1795 | ||
1796 | irq = platform_get_irq_byname(pdev, "tx"); | |
1797 | if (irq >= 0) { | |
ab1fffe3 | 1798 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", |
a7a3324a MLC |
1799 | dev_name(&pdev->dev)); |
1800 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1801 | davinci_mcasp_tx_irq_handler, | |
1802 | IRQF_ONESHOT, irq_name, mcasp); | |
1803 | if (ret) { | |
1804 | dev_err(&pdev->dev, "TX IRQ request failed\n"); | |
1805 | goto err; | |
1806 | } | |
1807 | ||
1808 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1809 | } | |
1810 | ||
256ba181 | 1811 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1812 | if (dat) |
1813 | mcasp->dat_port = true; | |
256ba181 | 1814 | |
8de131f2 | 1815 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
cbc7956c | 1816 | if (dat) |
9759e7ef | 1817 | dma_data->addr = dat->start; |
cbc7956c | 1818 | else |
9759e7ef | 1819 | dma_data->addr = mem->start + pdata->tx_dma_offset; |
453c4990 | 1820 | |
9759e7ef | 1821 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; |
b67f4487 | 1822 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1823 | if (res) |
9759e7ef | 1824 | *dma = res->start; |
4023fe6f | 1825 | else |
9759e7ef | 1826 | *dma = pdata->tx_dma_channel; |
92e2a6f6 | 1827 | |
8de131f2 PU |
1828 | /* dmaengine filter data for DT and non-DT boot */ |
1829 | if (pdev->dev.of_node) | |
1830 | dma_data->filter_data = "tx"; | |
1831 | else | |
9759e7ef | 1832 | dma_data->filter_data = dma; |
8de131f2 | 1833 | |
caa1d794 PU |
1834 | /* RX is not valid in DIT mode */ |
1835 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
caa1d794 | 1836 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 | 1837 | if (dat) |
9759e7ef | 1838 | dma_data->addr = dat->start; |
caa1d794 | 1839 | else |
9759e7ef | 1840 | dma_data->addr = mem->start + pdata->rx_dma_offset; |
caa1d794 | 1841 | |
9759e7ef | 1842 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 PU |
1843 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
1844 | if (res) | |
9759e7ef | 1845 | *dma = res->start; |
caa1d794 | 1846 | else |
9759e7ef | 1847 | *dma = pdata->rx_dma_channel; |
caa1d794 PU |
1848 | |
1849 | /* dmaengine filter data for DT and non-DT boot */ | |
1850 | if (pdev->dev.of_node) | |
1851 | dma_data->filter_data = "rx"; | |
1852 | else | |
9759e7ef | 1853 | dma_data->filter_data = dma; |
caa1d794 | 1854 | } |
453c4990 | 1855 | |
cbc7956c PU |
1856 | if (mcasp->version < MCASP_VERSION_3) { |
1857 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1858 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1859 | mcasp->dat_port = true; |
1860 | } else { | |
1861 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1862 | } | |
b67f4487 | 1863 | |
dd55ff83 JS |
1864 | /* Allocate memory for long enough list for all possible |
1865 | * scenarios. Maximum number tdm slots is 32 and there cannot | |
1866 | * be more serializers than given in the configuration. The | |
1867 | * serializer directions could be taken into account, but it | |
1868 | * would make code much more complex and save only couple of | |
1869 | * bytes. | |
1870 | */ | |
1871 | mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = | |
1872 | devm_kzalloc(mcasp->dev, sizeof(unsigned int) * | |
1873 | (32 + mcasp->num_serializer - 2), | |
1874 | GFP_KERNEL); | |
1875 | ||
1876 | mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = | |
1877 | devm_kzalloc(mcasp->dev, sizeof(unsigned int) * | |
1878 | (32 + mcasp->num_serializer - 2), | |
1879 | GFP_KERNEL); | |
1880 | ||
1881 | if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || | |
1882 | !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) | |
1883 | return -ENOMEM; | |
1884 | ||
1885 | ret = davinci_mcasp_set_ch_constraints(mcasp); | |
5935a056 JS |
1886 | if (ret) |
1887 | goto err; | |
1888 | ||
70091a3e | 1889 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1890 | |
1891 | mcasp_reparent_fck(pdev); | |
1892 | ||
b6bb3709 PU |
1893 | ret = devm_snd_soc_register_component(&pdev->dev, |
1894 | &davinci_mcasp_component, | |
1895 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1896 | |
1897 | if (ret != 0) | |
b6bb3709 | 1898 | goto err; |
f08095a4 | 1899 | |
9fbd58cf JS |
1900 | ret = davinci_mcasp_get_dma_type(mcasp); |
1901 | switch (ret) { | |
1902 | case PCM_EDMA: | |
f3f9cfa8 PU |
1903 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1904 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1905 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
f3f9cfa8 | 1906 | ret = edma_pcm_platform_register(&pdev->dev); |
9fbd58cf JS |
1907 | #else |
1908 | dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n"); | |
1909 | ret = -EINVAL; | |
1910 | goto err; | |
f3f9cfa8 | 1911 | #endif |
9fbd58cf JS |
1912 | break; |
1913 | case PCM_SDMA: | |
7f28f357 JS |
1914 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
1915 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1916 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a | 1917 | ret = omap_pcm_platform_register(&pdev->dev); |
9fbd58cf JS |
1918 | #else |
1919 | dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n"); | |
1920 | ret = -EINVAL; | |
1921 | goto err; | |
7f28f357 | 1922 | #endif |
9fbd58cf | 1923 | break; |
d5c6c59a | 1924 | default: |
9fbd58cf JS |
1925 | dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); |
1926 | case -EPROBE_DEFER: | |
1927 | goto err; | |
d5c6c59a PU |
1928 | break; |
1929 | } | |
1930 | ||
1931 | if (ret) { | |
1932 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 1933 | goto err; |
f08095a4 HG |
1934 | } |
1935 | ||
b67f4487 C |
1936 | return 0; |
1937 | ||
b6bb3709 | 1938 | err: |
10884347 | 1939 | pm_runtime_disable(&pdev->dev); |
b67f4487 C |
1940 | return ret; |
1941 | } | |
1942 | ||
1943 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1944 | { | |
10884347 | 1945 | pm_runtime_disable(&pdev->dev); |
b67f4487 | 1946 | |
b67f4487 C |
1947 | return 0; |
1948 | } | |
1949 | ||
1950 | static struct platform_driver davinci_mcasp_driver = { | |
1951 | .probe = davinci_mcasp_probe, | |
1952 | .remove = davinci_mcasp_remove, | |
1953 | .driver = { | |
1954 | .name = "davinci-mcasp", | |
ea421eb1 | 1955 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1956 | }, |
1957 | }; | |
1958 | ||
f9b8a514 | 1959 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1960 | |
1961 | MODULE_AUTHOR("Steve Chen"); | |
1962 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1963 | MODULE_LICENSE("GPL"); |