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Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
b67f4487 C |
29 | |
30 | #include <sound/core.h> | |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/initval.h> | |
34 | #include <sound/soc.h> | |
453c4990 | 35 | #include <sound/dmaengine_pcm.h> |
b67f4487 C |
36 | |
37 | #include "davinci-pcm.h" | |
38 | #include "davinci-mcasp.h" | |
39 | ||
790bb94b PU |
40 | struct davinci_mcasp_context { |
41 | u32 txfmtctl; | |
42 | u32 rxfmtctl; | |
43 | u32 txfmt; | |
44 | u32 rxfmt; | |
45 | u32 aclkxctl; | |
46 | u32 aclkrctl; | |
47 | u32 pdir; | |
48 | }; | |
49 | ||
70091a3e | 50 | struct davinci_mcasp { |
21400a72 | 51 | struct davinci_pcm_dma_params dma_params[2]; |
453c4990 | 52 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 53 | void __iomem *base; |
487dce88 | 54 | u32 fifo_base; |
21400a72 PU |
55 | struct device *dev; |
56 | ||
57 | /* McASP specific data */ | |
58 | int tdm_slots; | |
59 | u8 op_mode; | |
60 | u8 num_serializer; | |
61 | u8 *serial_dir; | |
62 | u8 version; | |
63 | u16 bclk_lrclk_ratio; | |
4dcb5a0b | 64 | int streams; |
21400a72 | 65 | |
ab8b14b6 JS |
66 | int sysclk_freq; |
67 | bool bclk_master; | |
68 | ||
21400a72 PU |
69 | /* McASP FIFO related */ |
70 | u8 txnumevt; | |
71 | u8 rxnumevt; | |
72 | ||
cbc7956c PU |
73 | bool dat_port; |
74 | ||
21400a72 | 75 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 76 | struct davinci_mcasp_context context; |
21400a72 PU |
77 | #endif |
78 | }; | |
79 | ||
f68205a7 PU |
80 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
81 | u32 val) | |
b67f4487 | 82 | { |
f68205a7 | 83 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
84 | __raw_writel(__raw_readl(reg) | val, reg); |
85 | } | |
86 | ||
f68205a7 PU |
87 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
88 | u32 val) | |
b67f4487 | 89 | { |
f68205a7 | 90 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
91 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
92 | } | |
93 | ||
f68205a7 PU |
94 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
95 | u32 val, u32 mask) | |
b67f4487 | 96 | { |
f68205a7 | 97 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
98 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
99 | } | |
100 | ||
f68205a7 PU |
101 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
102 | u32 val) | |
b67f4487 | 103 | { |
f68205a7 | 104 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
105 | } |
106 | ||
f68205a7 | 107 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 108 | { |
f68205a7 | 109 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
110 | } |
111 | ||
f68205a7 | 112 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
113 | { |
114 | int i = 0; | |
115 | ||
f68205a7 | 116 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
117 | |
118 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
119 | /* loop count is to avoid the lock-up */ | |
120 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 121 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
122 | break; |
123 | } | |
124 | ||
f68205a7 | 125 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
126 | printk(KERN_ERR "GBLCTL write error\n"); |
127 | } | |
128 | ||
4dcb5a0b PU |
129 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
130 | { | |
f68205a7 PU |
131 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
132 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
133 | |
134 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
135 | } | |
136 | ||
70091a3e | 137 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 138 | { |
f68205a7 PU |
139 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
140 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
141 | |
142 | /* | |
143 | * When ASYNC == 0 the transmit and receive sections operate | |
144 | * synchronously from the transmit clock and frame sync. We need to make | |
145 | * sure that the TX signlas are enabled when starting reception. | |
146 | */ | |
147 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
148 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
149 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
150 | } |
151 | ||
f68205a7 PU |
152 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
153 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); | |
b67f4487 | 154 | |
f68205a7 PU |
155 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
156 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
157 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); | |
b67f4487 | 158 | |
f68205a7 PU |
159 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
160 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
4dcb5a0b PU |
161 | |
162 | if (mcasp_is_synchronous(mcasp)) | |
f68205a7 | 163 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
b67f4487 C |
164 | } |
165 | ||
70091a3e | 166 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 167 | { |
6a99fb5f C |
168 | u8 offset = 0, i; |
169 | u32 cnt; | |
170 | ||
f68205a7 PU |
171 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
172 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
173 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); | |
174 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); | |
b67f4487 | 175 | |
f68205a7 PU |
176 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); |
177 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
178 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); | |
70091a3e PU |
179 | for (i = 0; i < mcasp->num_serializer; i++) { |
180 | if (mcasp->serial_dir[i] == TX_MODE) { | |
6a99fb5f C |
181 | offset = i; |
182 | break; | |
183 | } | |
184 | } | |
185 | ||
186 | /* wait for TX ready */ | |
187 | cnt = 0; | |
f68205a7 | 188 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) & |
6a99fb5f C |
189 | TXSTATE) && (cnt < 100000)) |
190 | cnt++; | |
191 | ||
f68205a7 | 192 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
b67f4487 C |
193 | } |
194 | ||
70091a3e | 195 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 196 | { |
487dce88 PU |
197 | u32 reg; |
198 | ||
4dcb5a0b PU |
199 | mcasp->streams++; |
200 | ||
539d3d8c | 201 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 202 | if (mcasp->txnumevt) { /* enable FIFO */ |
487dce88 | 203 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 PU |
204 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
205 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 206 | } |
70091a3e | 207 | mcasp_start_tx(mcasp); |
539d3d8c | 208 | } else { |
70091a3e | 209 | if (mcasp->rxnumevt) { /* enable FIFO */ |
487dce88 | 210 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 PU |
211 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
212 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
0d624275 | 213 | } |
70091a3e | 214 | mcasp_start_rx(mcasp); |
539d3d8c | 215 | } |
b67f4487 C |
216 | } |
217 | ||
70091a3e | 218 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 219 | { |
4dcb5a0b PU |
220 | /* |
221 | * In synchronous mode stop the TX clocks if no other stream is | |
222 | * running | |
223 | */ | |
224 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 225 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 226 | |
f68205a7 PU |
227 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
228 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
229 | } |
230 | ||
70091a3e | 231 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 232 | { |
4dcb5a0b PU |
233 | u32 val = 0; |
234 | ||
235 | /* | |
236 | * In synchronous mode keep TX clocks running if the capture stream is | |
237 | * still running. | |
238 | */ | |
239 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
240 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
241 | ||
f68205a7 PU |
242 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
243 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
b67f4487 C |
244 | } |
245 | ||
70091a3e | 246 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 247 | { |
487dce88 PU |
248 | u32 reg; |
249 | ||
4dcb5a0b PU |
250 | mcasp->streams--; |
251 | ||
539d3d8c | 252 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
70091a3e | 253 | if (mcasp->txnumevt) { /* disable FIFO */ |
487dce88 | 254 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 | 255 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 256 | } |
70091a3e | 257 | mcasp_stop_tx(mcasp); |
539d3d8c | 258 | } else { |
70091a3e | 259 | if (mcasp->rxnumevt) { /* disable FIFO */ |
487dce88 | 260 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
f68205a7 | 261 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
e5ec69da | 262 | } |
70091a3e | 263 | mcasp_stop_rx(mcasp); |
539d3d8c | 264 | } |
b67f4487 C |
265 | } |
266 | ||
267 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
268 | unsigned int fmt) | |
269 | { | |
70091a3e | 270 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 271 | int ret = 0; |
b67f4487 | 272 | |
1d17a04e | 273 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d DM |
274 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
275 | case SND_SOC_DAIFMT_DSP_B: | |
276 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
277 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
278 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
5296cf2d DM |
279 | break; |
280 | default: | |
281 | /* configure a full-word SYNC pulse (LRCLK) */ | |
f68205a7 PU |
282 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
283 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
5296cf2d DM |
284 | |
285 | /* make 1st data bit occur one ACLK cycle after the frame sync */ | |
f68205a7 PU |
286 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1)); |
287 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1)); | |
5296cf2d DM |
288 | break; |
289 | } | |
290 | ||
b67f4487 C |
291 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
292 | case SND_SOC_DAIFMT_CBS_CFS: | |
293 | /* codec is clock and frame slave */ | |
f68205a7 PU |
294 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
295 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 296 | |
f68205a7 PU |
297 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
298 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 299 | |
f68205a7 PU |
300 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
301 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 302 | mcasp->bclk_master = 1; |
b67f4487 | 303 | break; |
517ee6cf C |
304 | case SND_SOC_DAIFMT_CBM_CFS: |
305 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
306 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
307 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 308 | |
f68205a7 PU |
309 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
310 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 311 | |
f68205a7 PU |
312 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
313 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 314 | mcasp->bclk_master = 0; |
517ee6cf | 315 | break; |
b67f4487 C |
316 | case SND_SOC_DAIFMT_CBM_CFM: |
317 | /* codec is clock and frame master */ | |
f68205a7 PU |
318 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
319 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 320 | |
f68205a7 PU |
321 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
322 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 323 | |
f68205a7 PU |
324 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
325 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 326 | mcasp->bclk_master = 0; |
b67f4487 C |
327 | break; |
328 | ||
329 | default: | |
1d17a04e PU |
330 | ret = -EINVAL; |
331 | goto out; | |
b67f4487 C |
332 | } |
333 | ||
334 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
335 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 PU |
336 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
337 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
b67f4487 | 338 | |
f68205a7 PU |
339 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
340 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 C |
341 | break; |
342 | ||
343 | case SND_SOC_DAIFMT_NB_IF: | |
f68205a7 PU |
344 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
345 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
b67f4487 | 346 | |
f68205a7 PU |
347 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
348 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 C |
349 | break; |
350 | ||
351 | case SND_SOC_DAIFMT_IB_IF: | |
f68205a7 PU |
352 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
353 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
b67f4487 | 354 | |
f68205a7 PU |
355 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
356 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 C |
357 | break; |
358 | ||
359 | case SND_SOC_DAIFMT_NB_NF: | |
f68205a7 PU |
360 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
361 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
b67f4487 | 362 | |
f68205a7 PU |
363 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
364 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 C |
365 | break; |
366 | ||
367 | default: | |
1d17a04e PU |
368 | ret = -EINVAL; |
369 | break; | |
b67f4487 | 370 | } |
1d17a04e PU |
371 | out: |
372 | pm_runtime_put_sync(mcasp->dev); | |
373 | return ret; | |
b67f4487 C |
374 | } |
375 | ||
4ed8c9b7 DM |
376 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) |
377 | { | |
70091a3e | 378 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
379 | |
380 | switch (div_id) { | |
381 | case 0: /* MCLK divider */ | |
f68205a7 | 382 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 383 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 384 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
385 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
386 | break; | |
387 | ||
388 | case 1: /* BCLK divider */ | |
f68205a7 | 389 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 390 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 391 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 DM |
392 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
393 | break; | |
394 | ||
1b3bc060 | 395 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 396 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
397 | break; |
398 | ||
4ed8c9b7 DM |
399 | default: |
400 | return -EINVAL; | |
401 | } | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
5b66aa2d DM |
406 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
407 | unsigned int freq, int dir) | |
408 | { | |
70091a3e | 409 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
410 | |
411 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
412 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
413 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
414 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 415 | } else { |
f68205a7 PU |
416 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
417 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
418 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
419 | } |
420 | ||
ab8b14b6 JS |
421 | mcasp->sysclk_freq = freq; |
422 | ||
5b66aa2d DM |
423 | return 0; |
424 | } | |
425 | ||
70091a3e | 426 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 427 | int word_length) |
b67f4487 | 428 | { |
ba764b3d | 429 | u32 fmt; |
79671892 DM |
430 | u32 tx_rotate = (word_length / 4) & 0x7; |
431 | u32 rx_rotate = (32 - word_length) / 4; | |
ba764b3d | 432 | u32 mask = (1ULL << word_length) - 1; |
b67f4487 | 433 | |
1b3bc060 DM |
434 | /* |
435 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
436 | * callback, take it into account here. That allows us to for example | |
437 | * send 32 bits per channel to the codec, while only 16 of them carry | |
438 | * audio payload. | |
d486fea6 MB |
439 | * The clock ratio is given for a full period of data (for I2S format |
440 | * both left and right channels), so it has to be divided by number of | |
441 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 442 | */ |
70091a3e PU |
443 | if (mcasp->bclk_lrclk_ratio) |
444 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
1b3bc060 | 445 | |
ba764b3d DM |
446 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
447 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 448 | |
70091a3e | 449 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
450 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
451 | RXSSZ(0x0F)); | |
452 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
453 | TXSSZ(0x0F)); | |
454 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
455 | TXROT(7)); | |
456 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
457 | RXROT(7)); | |
458 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
459 | } |
460 | ||
f68205a7 | 461 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 462 | |
b67f4487 C |
463 | return 0; |
464 | } | |
465 | ||
662ffae9 | 466 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
2952b27e | 467 | int channels) |
b67f4487 C |
468 | { |
469 | int i; | |
6a99fb5f C |
470 | u8 tx_ser = 0; |
471 | u8 rx_ser = 0; | |
2952b27e | 472 | u8 ser; |
70091a3e | 473 | u8 slots = mcasp->tdm_slots; |
2952b27e | 474 | u8 max_active_serializers = (channels + slots - 1) / slots; |
487dce88 | 475 | u32 reg; |
b67f4487 | 476 | /* Default configuration */ |
453c4990 | 477 | if (mcasp->version != MCASP_VERSION_4) |
f68205a7 | 478 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
479 | |
480 | /* All PINS as McASP */ | |
f68205a7 | 481 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
482 | |
483 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
484 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
485 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 486 | } else { |
f68205a7 PU |
487 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
488 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
489 | } |
490 | ||
70091a3e | 491 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
492 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
493 | mcasp->serial_dir[i]); | |
70091a3e | 494 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 495 | tx_ser < max_active_serializers) { |
f68205a7 | 496 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 497 | tx_ser++; |
70091a3e | 498 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 499 | rx_ser < max_active_serializers) { |
f68205a7 | 500 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 501 | rx_ser++; |
2952b27e | 502 | } else { |
f68205a7 PU |
503 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
504 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
505 | } |
506 | } | |
507 | ||
ecf327c7 DM |
508 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
509 | ser = tx_ser; | |
510 | else | |
511 | ser = rx_ser; | |
512 | ||
513 | if (ser < max_active_serializers) { | |
70091a3e | 514 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
ecf327c7 DM |
515 | "enabled in mcasp (%d)\n", channels, ser * slots); |
516 | return -EINVAL; | |
517 | } | |
518 | ||
70091a3e PU |
519 | if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) { |
520 | if (mcasp->txnumevt * tx_ser > 64) | |
521 | mcasp->txnumevt = 1; | |
6a99fb5f | 522 | |
487dce88 | 523 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
f68205a7 PU |
524 | mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK); |
525 | mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8), | |
526 | NUMEVT_MASK); | |
6a99fb5f C |
527 | } |
528 | ||
70091a3e PU |
529 | if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) { |
530 | if (mcasp->rxnumevt * rx_ser > 64) | |
531 | mcasp->rxnumevt = 1; | |
487dce88 PU |
532 | |
533 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
f68205a7 PU |
534 | mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK); |
535 | mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8), | |
536 | NUMEVT_MASK); | |
b67f4487 | 537 | } |
2952b27e MB |
538 | |
539 | return 0; | |
b67f4487 C |
540 | } |
541 | ||
2c56c4c2 | 542 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
b67f4487 C |
543 | { |
544 | int i, active_slots; | |
545 | u32 mask = 0; | |
cbc7956c | 546 | u32 busel = 0; |
b67f4487 | 547 | |
2c56c4c2 PU |
548 | if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) { |
549 | dev_err(mcasp->dev, "tdm slot %d not supported\n", | |
550 | mcasp->tdm_slots); | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
70091a3e | 554 | active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; |
b67f4487 C |
555 | for (i = 0; i < active_slots; i++) |
556 | mask |= (1 << i); | |
557 | ||
f68205a7 | 558 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 559 | |
cbc7956c PU |
560 | if (!mcasp->dat_port) |
561 | busel = TXSEL; | |
562 | ||
2c56c4c2 PU |
563 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
564 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
565 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
566 | FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); | |
567 | ||
568 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
569 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
570 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
571 | FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); | |
572 | ||
573 | return 0; | |
b67f4487 C |
574 | } |
575 | ||
576 | /* S/PDIF */ | |
2c56c4c2 | 577 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp) |
b67f4487 | 578 | { |
b67f4487 C |
579 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
580 | and LSB first */ | |
f68205a7 | 581 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
582 | |
583 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 584 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
585 | |
586 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 587 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
588 | |
589 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 590 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 591 | |
f68205a7 | 592 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
593 | |
594 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 595 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
596 | |
597 | /* Enable the DIT */ | |
f68205a7 | 598 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 PU |
599 | |
600 | return 0; | |
b67f4487 C |
601 | } |
602 | ||
603 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
604 | struct snd_pcm_hw_params *params, | |
605 | struct snd_soc_dai *cpu_dai) | |
606 | { | |
70091a3e | 607 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 608 | struct davinci_pcm_dma_params *dma_params = |
70091a3e | 609 | &mcasp->dma_params[substream->stream]; |
453c4990 PU |
610 | struct snd_dmaengine_dai_dma_data *dma_data = |
611 | &mcasp->dma_data[substream->stream]; | |
b67f4487 | 612 | int word_length; |
4fa9c1a5 | 613 | u8 fifo_level; |
70091a3e | 614 | u8 slots = mcasp->tdm_slots; |
7c21a781 | 615 | u8 active_serializers; |
a7e46bd9 | 616 | int channels = params_channels(params); |
2c56c4c2 | 617 | int ret; |
ab8b14b6 JS |
618 | |
619 | /* If mcasp is BCLK master we need to set BCLK divider */ | |
620 | if (mcasp->bclk_master) { | |
621 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); | |
622 | if (mcasp->sysclk_freq % bclk_freq != 0) { | |
623 | dev_err(mcasp->dev, "Can't produce requred BCLK\n"); | |
624 | return -EINVAL; | |
625 | } | |
626 | davinci_mcasp_set_clkdiv( | |
627 | cpu_dai, 1, mcasp->sysclk_freq / bclk_freq); | |
628 | } | |
629 | ||
0f7d9a63 PU |
630 | ret = mcasp_common_hw_param(mcasp, substream->stream, channels); |
631 | if (ret) | |
632 | return ret; | |
633 | ||
70091a3e | 634 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
2c56c4c2 | 635 | ret = mcasp_dit_hw_param(mcasp); |
b67f4487 | 636 | else |
2c56c4c2 PU |
637 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
638 | ||
639 | if (ret) | |
640 | return ret; | |
b67f4487 C |
641 | |
642 | switch (params_format(params)) { | |
0a9d1385 | 643 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
644 | case SNDRV_PCM_FORMAT_S8: |
645 | dma_params->data_type = 1; | |
ba764b3d | 646 | word_length = 8; |
b67f4487 C |
647 | break; |
648 | ||
0a9d1385 | 649 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
650 | case SNDRV_PCM_FORMAT_S16_LE: |
651 | dma_params->data_type = 2; | |
ba764b3d | 652 | word_length = 16; |
b67f4487 C |
653 | break; |
654 | ||
21eb24d8 DM |
655 | case SNDRV_PCM_FORMAT_U24_3LE: |
656 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 657 | dma_params->data_type = 3; |
ba764b3d | 658 | word_length = 24; |
21eb24d8 DM |
659 | break; |
660 | ||
6b7fa011 DM |
661 | case SNDRV_PCM_FORMAT_U24_LE: |
662 | case SNDRV_PCM_FORMAT_S24_LE: | |
0a9d1385 | 663 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
664 | case SNDRV_PCM_FORMAT_S32_LE: |
665 | dma_params->data_type = 4; | |
ba764b3d | 666 | word_length = 32; |
b67f4487 C |
667 | break; |
668 | ||
669 | default: | |
670 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
671 | return -EINVAL; | |
672 | } | |
6a99fb5f | 673 | |
a7e46bd9 PU |
674 | /* Calculate FIFO level */ |
675 | active_serializers = (channels + slots - 1) / slots; | |
676 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
677 | fifo_level = mcasp->txnumevt * active_serializers; | |
678 | else | |
679 | fifo_level = mcasp->rxnumevt * active_serializers; | |
680 | ||
70091a3e | 681 | if (mcasp->version == MCASP_VERSION_2 && !fifo_level) |
4fa9c1a5 C |
682 | dma_params->acnt = 4; |
683 | else | |
6a99fb5f C |
684 | dma_params->acnt = dma_params->data_type; |
685 | ||
4fa9c1a5 | 686 | dma_params->fifo_level = fifo_level; |
453c4990 PU |
687 | dma_data->maxburst = fifo_level; |
688 | ||
70091a3e | 689 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 C |
690 | |
691 | return 0; | |
692 | } | |
693 | ||
694 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
695 | int cmd, struct snd_soc_dai *cpu_dai) | |
696 | { | |
70091a3e | 697 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
698 | int ret = 0; |
699 | ||
700 | switch (cmd) { | |
b67f4487 | 701 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
702 | case SNDRV_PCM_TRIGGER_START: |
703 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 704 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 705 | break; |
b67f4487 | 706 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 707 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 708 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 709 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
710 | break; |
711 | ||
712 | default: | |
713 | ret = -EINVAL; | |
714 | } | |
715 | ||
716 | return ret; | |
717 | } | |
718 | ||
bedad0ca CPE |
719 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
720 | struct snd_soc_dai *dai) | |
721 | { | |
70091a3e | 722 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
bedad0ca | 723 | |
453c4990 PU |
724 | if (mcasp->version == MCASP_VERSION_4) |
725 | snd_soc_dai_set_dma_data(dai, substream, | |
726 | &mcasp->dma_data[substream->stream]); | |
727 | else | |
728 | snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params); | |
729 | ||
bedad0ca CPE |
730 | return 0; |
731 | } | |
732 | ||
85e7652d | 733 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
bedad0ca | 734 | .startup = davinci_mcasp_startup, |
b67f4487 C |
735 | .trigger = davinci_mcasp_trigger, |
736 | .hw_params = davinci_mcasp_hw_params, | |
737 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 738 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 739 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
740 | }; |
741 | ||
135014ad PU |
742 | #ifdef CONFIG_PM_SLEEP |
743 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
744 | { | |
745 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 746 | struct davinci_mcasp_context *context = &mcasp->context; |
135014ad | 747 | |
790bb94b PU |
748 | context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG); |
749 | context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); | |
750 | context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG); | |
751 | context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG); | |
752 | context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
753 | context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG); | |
754 | context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); | |
135014ad PU |
755 | |
756 | return 0; | |
757 | } | |
758 | ||
759 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
760 | { | |
761 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b PU |
762 | struct davinci_mcasp_context *context = &mcasp->context; |
763 | ||
764 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl); | |
765 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl); | |
766 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt); | |
767 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt); | |
768 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl); | |
769 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl); | |
770 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir); | |
135014ad PU |
771 | |
772 | return 0; | |
773 | } | |
774 | #else | |
775 | #define davinci_mcasp_suspend NULL | |
776 | #define davinci_mcasp_resume NULL | |
777 | #endif | |
778 | ||
ed29cd5e PU |
779 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
780 | ||
0a9d1385 BG |
781 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
782 | SNDRV_PCM_FMTBIT_U8 | \ | |
783 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
784 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
785 | SNDRV_PCM_FMTBIT_S24_LE | \ |
786 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
787 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
788 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
789 | SNDRV_PCM_FMTBIT_S32_LE | \ |
790 | SNDRV_PCM_FMTBIT_U32_LE) | |
791 | ||
f0fba2ad | 792 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 793 | { |
f0fba2ad | 794 | .name = "davinci-mcasp.0", |
135014ad PU |
795 | .suspend = davinci_mcasp_suspend, |
796 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
797 | .playback = { |
798 | .channels_min = 2, | |
2952b27e | 799 | .channels_max = 32 * 16, |
b67f4487 | 800 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 801 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
802 | }, |
803 | .capture = { | |
804 | .channels_min = 2, | |
2952b27e | 805 | .channels_max = 32 * 16, |
b67f4487 | 806 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 807 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
808 | }, |
809 | .ops = &davinci_mcasp_dai_ops, | |
810 | ||
811 | }, | |
812 | { | |
58e48d97 | 813 | .name = "davinci-mcasp.1", |
b67f4487 C |
814 | .playback = { |
815 | .channels_min = 1, | |
816 | .channels_max = 384, | |
817 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 818 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
819 | }, |
820 | .ops = &davinci_mcasp_dai_ops, | |
821 | }, | |
822 | ||
823 | }; | |
b67f4487 | 824 | |
eeef0eda KM |
825 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
826 | .name = "davinci-mcasp", | |
827 | }; | |
828 | ||
256ba181 | 829 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 830 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
831 | .tx_dma_offset = 0x400, |
832 | .rx_dma_offset = 0x400, | |
833 | .asp_chan_q = EVENTQ_0, | |
834 | .version = MCASP_VERSION_1, | |
835 | }; | |
836 | ||
d1debafc | 837 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
838 | .tx_dma_offset = 0x2000, |
839 | .rx_dma_offset = 0x2000, | |
840 | .asp_chan_q = EVENTQ_0, | |
841 | .version = MCASP_VERSION_2, | |
842 | }; | |
843 | ||
d1debafc | 844 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
845 | .tx_dma_offset = 0, |
846 | .rx_dma_offset = 0, | |
847 | .asp_chan_q = EVENTQ_0, | |
848 | .version = MCASP_VERSION_3, | |
849 | }; | |
850 | ||
d1debafc | 851 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
852 | .tx_dma_offset = 0x200, |
853 | .rx_dma_offset = 0x284, | |
854 | .asp_chan_q = EVENTQ_0, | |
855 | .version = MCASP_VERSION_4, | |
856 | }; | |
857 | ||
3e3b8c34 HG |
858 | static const struct of_device_id mcasp_dt_ids[] = { |
859 | { | |
860 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 861 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
862 | }, |
863 | { | |
864 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 865 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 866 | }, |
e5ec69da | 867 | { |
3af9e031 | 868 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 869 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 870 | }, |
453c4990 PU |
871 | { |
872 | .compatible = "ti,dra7-mcasp-audio", | |
873 | .data = &dra7_mcasp_pdata, | |
874 | }, | |
3e3b8c34 HG |
875 | { /* sentinel */ } |
876 | }; | |
877 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
878 | ||
ae726e93 PU |
879 | static int mcasp_reparent_fck(struct platform_device *pdev) |
880 | { | |
881 | struct device_node *node = pdev->dev.of_node; | |
882 | struct clk *gfclk, *parent_clk; | |
883 | const char *parent_name; | |
884 | int ret; | |
885 | ||
886 | if (!node) | |
887 | return 0; | |
888 | ||
889 | parent_name = of_get_property(node, "fck_parent", NULL); | |
890 | if (!parent_name) | |
891 | return 0; | |
892 | ||
893 | gfclk = clk_get(&pdev->dev, "fck"); | |
894 | if (IS_ERR(gfclk)) { | |
895 | dev_err(&pdev->dev, "failed to get fck\n"); | |
896 | return PTR_ERR(gfclk); | |
897 | } | |
898 | ||
899 | parent_clk = clk_get(NULL, parent_name); | |
900 | if (IS_ERR(parent_clk)) { | |
901 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
902 | ret = PTR_ERR(parent_clk); | |
903 | goto err1; | |
904 | } | |
905 | ||
906 | ret = clk_set_parent(gfclk, parent_clk); | |
907 | if (ret) { | |
908 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
909 | goto err2; | |
910 | } | |
911 | ||
912 | err2: | |
913 | clk_put(parent_clk); | |
914 | err1: | |
915 | clk_put(gfclk); | |
916 | return ret; | |
917 | } | |
918 | ||
d1debafc | 919 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
920 | struct platform_device *pdev) |
921 | { | |
922 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 923 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 924 | const struct of_device_id *match = |
ea421eb1 | 925 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 926 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
927 | |
928 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
929 | u32 val; |
930 | int i, ret = 0; | |
931 | ||
932 | if (pdev->dev.platform_data) { | |
933 | pdata = pdev->dev.platform_data; | |
934 | return pdata; | |
935 | } else if (match) { | |
d1debafc | 936 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
937 | } else { |
938 | /* control shouldn't reach here. something is wrong */ | |
939 | ret = -EINVAL; | |
940 | goto nodata; | |
941 | } | |
942 | ||
3e3b8c34 HG |
943 | ret = of_property_read_u32(np, "op-mode", &val); |
944 | if (ret >= 0) | |
945 | pdata->op_mode = val; | |
946 | ||
947 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
948 | if (ret >= 0) { |
949 | if (val < 2 || val > 32) { | |
950 | dev_err(&pdev->dev, | |
951 | "tdm-slots must be in rage [2-32]\n"); | |
952 | ret = -EINVAL; | |
953 | goto nodata; | |
954 | } | |
955 | ||
3e3b8c34 | 956 | pdata->tdm_slots = val; |
2952b27e | 957 | } |
3e3b8c34 | 958 | |
3e3b8c34 HG |
959 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
960 | val /= sizeof(u32); | |
3e3b8c34 | 961 | if (of_serial_dir32) { |
1427e660 PU |
962 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
963 | (sizeof(*of_serial_dir) * val), | |
964 | GFP_KERNEL); | |
3e3b8c34 HG |
965 | if (!of_serial_dir) { |
966 | ret = -ENOMEM; | |
967 | goto nodata; | |
968 | } | |
969 | ||
1427e660 | 970 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
971 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
972 | ||
1427e660 | 973 | pdata->num_serializer = val; |
3e3b8c34 HG |
974 | pdata->serial_dir = of_serial_dir; |
975 | } | |
976 | ||
4023fe6f JS |
977 | ret = of_property_match_string(np, "dma-names", "tx"); |
978 | if (ret < 0) | |
979 | goto nodata; | |
980 | ||
981 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
982 | &dma_spec); | |
983 | if (ret < 0) | |
984 | goto nodata; | |
985 | ||
986 | pdata->tx_dma_channel = dma_spec.args[0]; | |
987 | ||
988 | ret = of_property_match_string(np, "dma-names", "rx"); | |
989 | if (ret < 0) | |
990 | goto nodata; | |
991 | ||
992 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
993 | &dma_spec); | |
994 | if (ret < 0) | |
995 | goto nodata; | |
996 | ||
997 | pdata->rx_dma_channel = dma_spec.args[0]; | |
998 | ||
3e3b8c34 HG |
999 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1000 | if (ret >= 0) | |
1001 | pdata->txnumevt = val; | |
1002 | ||
1003 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1004 | if (ret >= 0) | |
1005 | pdata->rxnumevt = val; | |
1006 | ||
1007 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1008 | if (ret >= 0) | |
1009 | pdata->sram_size_playback = val; | |
1010 | ||
1011 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1012 | if (ret >= 0) | |
1013 | pdata->sram_size_capture = val; | |
1014 | ||
1015 | return pdata; | |
1016 | ||
1017 | nodata: | |
1018 | if (ret < 0) { | |
1019 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1020 | ret); | |
1021 | pdata = NULL; | |
1022 | } | |
1023 | return pdata; | |
1024 | } | |
1025 | ||
b67f4487 C |
1026 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1027 | { | |
64ebdec3 | 1028 | struct davinci_pcm_dma_params *dma_params; |
8de131f2 | 1029 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1030 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1031 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1032 | struct davinci_mcasp *mcasp; |
96d31e2b | 1033 | int ret; |
b67f4487 | 1034 | |
3e3b8c34 HG |
1035 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1036 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1037 | return -EINVAL; | |
1038 | } | |
1039 | ||
70091a3e | 1040 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1041 | GFP_KERNEL); |
70091a3e | 1042 | if (!mcasp) |
b67f4487 C |
1043 | return -ENOMEM; |
1044 | ||
3e3b8c34 HG |
1045 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1046 | if (!pdata) { | |
1047 | dev_err(&pdev->dev, "no platform data\n"); | |
1048 | return -EINVAL; | |
1049 | } | |
1050 | ||
256ba181 | 1051 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1052 | if (!mem) { |
70091a3e | 1053 | dev_warn(mcasp->dev, |
256ba181 JS |
1054 | "\"mpu\" mem resource not found, using index 0\n"); |
1055 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1056 | if (!mem) { | |
1057 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1058 | return -ENODEV; | |
1059 | } | |
b67f4487 C |
1060 | } |
1061 | ||
96d31e2b | 1062 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1063 | resource_size(mem), pdev->name); |
b67f4487 C |
1064 | if (!ioarea) { |
1065 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1066 | return -EBUSY; |
b67f4487 C |
1067 | } |
1068 | ||
10884347 | 1069 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1070 | |
10884347 HG |
1071 | ret = pm_runtime_get_sync(&pdev->dev); |
1072 | if (IS_ERR_VALUE(ret)) { | |
1073 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
1074 | return ret; | |
1075 | } | |
b67f4487 | 1076 | |
70091a3e PU |
1077 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1078 | if (!mcasp->base) { | |
4f82f028 VB |
1079 | dev_err(&pdev->dev, "ioremap failed\n"); |
1080 | ret = -ENOMEM; | |
1081 | goto err_release_clk; | |
1082 | } | |
1083 | ||
70091a3e PU |
1084 | mcasp->op_mode = pdata->op_mode; |
1085 | mcasp->tdm_slots = pdata->tdm_slots; | |
1086 | mcasp->num_serializer = pdata->num_serializer; | |
1087 | mcasp->serial_dir = pdata->serial_dir; | |
1088 | mcasp->version = pdata->version; | |
1089 | mcasp->txnumevt = pdata->txnumevt; | |
1090 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1091 | |
70091a3e | 1092 | mcasp->dev = &pdev->dev; |
b67f4487 | 1093 | |
256ba181 | 1094 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1095 | if (dat) |
1096 | mcasp->dat_port = true; | |
256ba181 | 1097 | |
64ebdec3 | 1098 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
8de131f2 | 1099 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
64ebdec3 PU |
1100 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1101 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1102 | dma_params->sram_pool = pdata->sram_pool; | |
1103 | dma_params->sram_size = pdata->sram_size_playback; | |
cbc7956c | 1104 | if (dat) |
64ebdec3 | 1105 | dma_params->dma_addr = dat->start; |
cbc7956c | 1106 | else |
64ebdec3 | 1107 | dma_params->dma_addr = mem->start + pdata->tx_dma_offset; |
b67f4487 | 1108 | |
453c4990 | 1109 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1110 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1111 | |
b67f4487 | 1112 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1113 | if (res) |
64ebdec3 | 1114 | dma_params->channel = res->start; |
4023fe6f | 1115 | else |
64ebdec3 | 1116 | dma_params->channel = pdata->tx_dma_channel; |
92e2a6f6 | 1117 | |
8de131f2 PU |
1118 | /* dmaengine filter data for DT and non-DT boot */ |
1119 | if (pdev->dev.of_node) | |
1120 | dma_data->filter_data = "tx"; | |
1121 | else | |
1122 | dma_data->filter_data = &dma_params->channel; | |
1123 | ||
64ebdec3 | 1124 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
8de131f2 | 1125 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
64ebdec3 PU |
1126 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1127 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1128 | dma_params->sram_pool = pdata->sram_pool; | |
1129 | dma_params->sram_size = pdata->sram_size_capture; | |
cbc7956c | 1130 | if (dat) |
64ebdec3 | 1131 | dma_params->dma_addr = dat->start; |
cbc7956c | 1132 | else |
64ebdec3 | 1133 | dma_params->dma_addr = mem->start + pdata->rx_dma_offset; |
cbc7956c | 1134 | |
453c4990 | 1135 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1136 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1137 | |
cbc7956c PU |
1138 | if (mcasp->version < MCASP_VERSION_3) { |
1139 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1140 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1141 | mcasp->dat_port = true; |
1142 | } else { | |
1143 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1144 | } | |
b67f4487 C |
1145 | |
1146 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
4023fe6f | 1147 | if (res) |
64ebdec3 | 1148 | dma_params->channel = res->start; |
4023fe6f | 1149 | else |
64ebdec3 | 1150 | dma_params->channel = pdata->rx_dma_channel; |
b67f4487 | 1151 | |
8de131f2 PU |
1152 | /* dmaengine filter data for DT and non-DT boot */ |
1153 | if (pdev->dev.of_node) | |
1154 | dma_data->filter_data = "rx"; | |
1155 | else | |
1156 | dma_data->filter_data = &dma_params->channel; | |
453c4990 | 1157 | |
70091a3e | 1158 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1159 | |
1160 | mcasp_reparent_fck(pdev); | |
1161 | ||
eeef0eda KM |
1162 | ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, |
1163 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1164 | |
1165 | if (ret != 0) | |
96d31e2b | 1166 | goto err_release_clk; |
f08095a4 | 1167 | |
453c4990 PU |
1168 | if (mcasp->version != MCASP_VERSION_4) { |
1169 | ret = davinci_soc_platform_register(&pdev->dev); | |
1170 | if (ret) { | |
1171 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
1172 | goto err_unregister_component; | |
1173 | } | |
f08095a4 HG |
1174 | } |
1175 | ||
b67f4487 C |
1176 | return 0; |
1177 | ||
eeef0eda KM |
1178 | err_unregister_component: |
1179 | snd_soc_unregister_component(&pdev->dev); | |
eef6d7b8 | 1180 | err_release_clk: |
10884347 HG |
1181 | pm_runtime_put_sync(&pdev->dev); |
1182 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1183 | return ret; |
1184 | } | |
1185 | ||
1186 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1187 | { | |
453c4990 | 1188 | struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev); |
b67f4487 | 1189 | |
eeef0eda | 1190 | snd_soc_unregister_component(&pdev->dev); |
453c4990 PU |
1191 | if (mcasp->version != MCASP_VERSION_4) |
1192 | davinci_soc_platform_unregister(&pdev->dev); | |
10884347 HG |
1193 | |
1194 | pm_runtime_put_sync(&pdev->dev); | |
1195 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1196 | |
b67f4487 C |
1197 | return 0; |
1198 | } | |
1199 | ||
1200 | static struct platform_driver davinci_mcasp_driver = { | |
1201 | .probe = davinci_mcasp_probe, | |
1202 | .remove = davinci_mcasp_remove, | |
1203 | .driver = { | |
1204 | .name = "davinci-mcasp", | |
1205 | .owner = THIS_MODULE, | |
ea421eb1 | 1206 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1207 | }, |
1208 | }; | |
1209 | ||
f9b8a514 | 1210 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1211 | |
1212 | MODULE_AUTHOR("Steve Chen"); | |
1213 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1214 | MODULE_LICENSE("GPL"); |