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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
10884347 | 24 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
25 | #include <linux/of.h> |
26 | #include <linux/of_platform.h> | |
27 | #include <linux/of_device.h> | |
b67f4487 C |
28 | |
29 | #include <sound/core.h> | |
30 | #include <sound/pcm.h> | |
31 | #include <sound/pcm_params.h> | |
32 | #include <sound/initval.h> | |
33 | #include <sound/soc.h> | |
34 | ||
35 | #include "davinci-pcm.h" | |
36 | #include "davinci-mcasp.h" | |
37 | ||
38 | /* | |
39 | * McASP register definitions | |
40 | */ | |
41 | #define DAVINCI_MCASP_PID_REG 0x00 | |
42 | #define DAVINCI_MCASP_PWREMUMGT_REG 0x04 | |
43 | ||
44 | #define DAVINCI_MCASP_PFUNC_REG 0x10 | |
45 | #define DAVINCI_MCASP_PDIR_REG 0x14 | |
46 | #define DAVINCI_MCASP_PDOUT_REG 0x18 | |
47 | #define DAVINCI_MCASP_PDSET_REG 0x1c | |
48 | ||
49 | #define DAVINCI_MCASP_PDCLR_REG 0x20 | |
50 | ||
51 | #define DAVINCI_MCASP_TLGC_REG 0x30 | |
52 | #define DAVINCI_MCASP_TLMR_REG 0x34 | |
53 | ||
54 | #define DAVINCI_MCASP_GBLCTL_REG 0x44 | |
55 | #define DAVINCI_MCASP_AMUTE_REG 0x48 | |
56 | #define DAVINCI_MCASP_LBCTL_REG 0x4c | |
57 | ||
58 | #define DAVINCI_MCASP_TXDITCTL_REG 0x50 | |
59 | ||
60 | #define DAVINCI_MCASP_GBLCTLR_REG 0x60 | |
61 | #define DAVINCI_MCASP_RXMASK_REG 0x64 | |
62 | #define DAVINCI_MCASP_RXFMT_REG 0x68 | |
63 | #define DAVINCI_MCASP_RXFMCTL_REG 0x6c | |
64 | ||
65 | #define DAVINCI_MCASP_ACLKRCTL_REG 0x70 | |
66 | #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74 | |
67 | #define DAVINCI_MCASP_RXTDM_REG 0x78 | |
68 | #define DAVINCI_MCASP_EVTCTLR_REG 0x7c | |
69 | ||
70 | #define DAVINCI_MCASP_RXSTAT_REG 0x80 | |
71 | #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84 | |
72 | #define DAVINCI_MCASP_RXCLKCHK_REG 0x88 | |
73 | #define DAVINCI_MCASP_REVTCTL_REG 0x8c | |
74 | ||
75 | #define DAVINCI_MCASP_GBLCTLX_REG 0xa0 | |
76 | #define DAVINCI_MCASP_TXMASK_REG 0xa4 | |
77 | #define DAVINCI_MCASP_TXFMT_REG 0xa8 | |
78 | #define DAVINCI_MCASP_TXFMCTL_REG 0xac | |
79 | ||
80 | #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0 | |
81 | #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4 | |
82 | #define DAVINCI_MCASP_TXTDM_REG 0xb8 | |
83 | #define DAVINCI_MCASP_EVTCTLX_REG 0xbc | |
84 | ||
85 | #define DAVINCI_MCASP_TXSTAT_REG 0xc0 | |
86 | #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4 | |
87 | #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8 | |
88 | #define DAVINCI_MCASP_XEVTCTL_REG 0xcc | |
89 | ||
90 | /* Left(even TDM Slot) Channel Status Register File */ | |
91 | #define DAVINCI_MCASP_DITCSRA_REG 0x100 | |
92 | /* Right(odd TDM slot) Channel Status Register File */ | |
93 | #define DAVINCI_MCASP_DITCSRB_REG 0x118 | |
94 | /* Left(even TDM slot) User Data Register File */ | |
95 | #define DAVINCI_MCASP_DITUDRA_REG 0x130 | |
96 | /* Right(odd TDM Slot) User Data Register File */ | |
97 | #define DAVINCI_MCASP_DITUDRB_REG 0x148 | |
98 | ||
99 | /* Serializer n Control Register */ | |
100 | #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180 | |
101 | #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \ | |
102 | (n << 2)) | |
103 | ||
104 | /* Transmit Buffer for Serializer n */ | |
105 | #define DAVINCI_MCASP_TXBUF_REG 0x200 | |
106 | /* Receive Buffer for Serializer n */ | |
107 | #define DAVINCI_MCASP_RXBUF_REG 0x280 | |
108 | ||
6a99fb5f C |
109 | /* McASP FIFO Registers */ |
110 | #define DAVINCI_MCASP_WFIFOCTL (0x1010) | |
111 | #define DAVINCI_MCASP_WFIFOSTS (0x1014) | |
112 | #define DAVINCI_MCASP_RFIFOCTL (0x1018) | |
113 | #define DAVINCI_MCASP_RFIFOSTS (0x101C) | |
e5ec69da HG |
114 | #define MCASP_VER3_WFIFOCTL (0x1000) |
115 | #define MCASP_VER3_WFIFOSTS (0x1004) | |
116 | #define MCASP_VER3_RFIFOCTL (0x1008) | |
117 | #define MCASP_VER3_RFIFOSTS (0x100C) | |
b67f4487 C |
118 | |
119 | /* | |
120 | * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management | |
121 | * Register Bits | |
122 | */ | |
123 | #define MCASP_FREE BIT(0) | |
124 | #define MCASP_SOFT BIT(1) | |
125 | ||
126 | /* | |
127 | * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits | |
128 | */ | |
129 | #define AXR(n) (1<<n) | |
130 | #define PFUNC_AMUTE BIT(25) | |
131 | #define ACLKX BIT(26) | |
132 | #define AHCLKX BIT(27) | |
133 | #define AFSX BIT(28) | |
134 | #define ACLKR BIT(29) | |
135 | #define AHCLKR BIT(30) | |
136 | #define AFSR BIT(31) | |
137 | ||
138 | /* | |
139 | * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits | |
140 | */ | |
141 | #define AXR(n) (1<<n) | |
142 | #define PDIR_AMUTE BIT(25) | |
143 | #define ACLKX BIT(26) | |
144 | #define AHCLKX BIT(27) | |
145 | #define AFSX BIT(28) | |
146 | #define ACLKR BIT(29) | |
147 | #define AHCLKR BIT(30) | |
148 | #define AFSR BIT(31) | |
149 | ||
150 | /* | |
151 | * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits | |
152 | */ | |
153 | #define DITEN BIT(0) /* Transmit DIT mode enable/disable */ | |
154 | #define VA BIT(2) | |
155 | #define VB BIT(3) | |
156 | ||
157 | /* | |
158 | * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits | |
159 | */ | |
160 | #define TXROT(val) (val) | |
161 | #define TXSEL BIT(3) | |
162 | #define TXSSZ(val) (val<<4) | |
163 | #define TXPBIT(val) (val<<8) | |
164 | #define TXPAD(val) (val<<13) | |
165 | #define TXORD BIT(15) | |
166 | #define FSXDLY(val) (val<<16) | |
167 | ||
168 | /* | |
169 | * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits | |
170 | */ | |
171 | #define RXROT(val) (val) | |
172 | #define RXSEL BIT(3) | |
173 | #define RXSSZ(val) (val<<4) | |
174 | #define RXPBIT(val) (val<<8) | |
175 | #define RXPAD(val) (val<<13) | |
176 | #define RXORD BIT(15) | |
177 | #define FSRDLY(val) (val<<16) | |
178 | ||
179 | /* | |
180 | * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits | |
181 | */ | |
182 | #define FSXPOL BIT(0) | |
183 | #define AFSXE BIT(1) | |
184 | #define FSXDUR BIT(4) | |
185 | #define FSXMOD(val) (val<<7) | |
186 | ||
187 | /* | |
188 | * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits | |
189 | */ | |
190 | #define FSRPOL BIT(0) | |
191 | #define AFSRE BIT(1) | |
192 | #define FSRDUR BIT(4) | |
193 | #define FSRMOD(val) (val<<7) | |
194 | ||
195 | /* | |
196 | * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits | |
197 | */ | |
198 | #define ACLKXDIV(val) (val) | |
199 | #define ACLKXE BIT(5) | |
200 | #define TX_ASYNC BIT(6) | |
201 | #define ACLKXPOL BIT(7) | |
4ed8c9b7 | 202 | #define ACLKXDIV_MASK 0x1f |
b67f4487 C |
203 | |
204 | /* | |
205 | * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits | |
206 | */ | |
207 | #define ACLKRDIV(val) (val) | |
208 | #define ACLKRE BIT(5) | |
209 | #define RX_ASYNC BIT(6) | |
210 | #define ACLKRPOL BIT(7) | |
4ed8c9b7 | 211 | #define ACLKRDIV_MASK 0x1f |
b67f4487 C |
212 | |
213 | /* | |
214 | * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control | |
215 | * Register Bits | |
216 | */ | |
217 | #define AHCLKXDIV(val) (val) | |
218 | #define AHCLKXPOL BIT(14) | |
219 | #define AHCLKXE BIT(15) | |
4ed8c9b7 | 220 | #define AHCLKXDIV_MASK 0xfff |
b67f4487 C |
221 | |
222 | /* | |
223 | * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control | |
224 | * Register Bits | |
225 | */ | |
226 | #define AHCLKRDIV(val) (val) | |
227 | #define AHCLKRPOL BIT(14) | |
228 | #define AHCLKRE BIT(15) | |
4ed8c9b7 | 229 | #define AHCLKRDIV_MASK 0xfff |
b67f4487 C |
230 | |
231 | /* | |
232 | * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits | |
233 | */ | |
234 | #define MODE(val) (val) | |
235 | #define DISMOD (val)(val<<2) | |
236 | #define TXSTATE BIT(4) | |
237 | #define RXSTATE BIT(5) | |
2952b27e MB |
238 | #define SRMOD_MASK 3 |
239 | #define SRMOD_INACTIVE 0 | |
b67f4487 C |
240 | |
241 | /* | |
242 | * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits | |
243 | */ | |
244 | #define LBEN BIT(0) | |
245 | #define LBORD BIT(1) | |
246 | #define LBGENMODE(val) (val<<2) | |
247 | ||
248 | /* | |
249 | * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration | |
250 | */ | |
251 | #define TXTDMS(n) (1<<n) | |
252 | ||
253 | /* | |
254 | * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration | |
255 | */ | |
256 | #define RXTDMS(n) (1<<n) | |
257 | ||
258 | /* | |
259 | * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits | |
260 | */ | |
261 | #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */ | |
262 | #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */ | |
263 | #define RXSERCLR BIT(2) /* Receiver Serializer Clear */ | |
264 | #define RXSMRST BIT(3) /* Receiver State Machine Reset */ | |
265 | #define RXFSRST BIT(4) /* Frame Sync Generator Reset */ | |
266 | #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */ | |
267 | #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/ | |
268 | #define TXSERCLR BIT(10) /* Transmit Serializer Clear */ | |
269 | #define TXSMRST BIT(11) /* Transmitter State Machine Reset */ | |
270 | #define TXFSRST BIT(12) /* Frame Sync Generator Reset */ | |
271 | ||
272 | /* | |
273 | * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits | |
274 | */ | |
275 | #define MUTENA(val) (val) | |
276 | #define MUTEINPOL BIT(2) | |
277 | #define MUTEINENA BIT(3) | |
278 | #define MUTEIN BIT(4) | |
279 | #define MUTER BIT(5) | |
280 | #define MUTEX BIT(6) | |
281 | #define MUTEFSR BIT(7) | |
282 | #define MUTEFSX BIT(8) | |
283 | #define MUTEBADCLKR BIT(9) | |
284 | #define MUTEBADCLKX BIT(10) | |
285 | #define MUTERXDMAERR BIT(11) | |
286 | #define MUTETXDMAERR BIT(12) | |
287 | ||
288 | /* | |
289 | * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits | |
290 | */ | |
291 | #define RXDATADMADIS BIT(0) | |
292 | ||
293 | /* | |
294 | * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits | |
295 | */ | |
296 | #define TXDATADMADIS BIT(0) | |
297 | ||
6a99fb5f C |
298 | /* |
299 | * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits | |
300 | */ | |
301 | #define FIFO_ENABLE BIT(16) | |
302 | #define NUMEVT_MASK (0xFF << 8) | |
303 | #define NUMDMA_MASK (0xFF) | |
304 | ||
b67f4487 C |
305 | #define DAVINCI_MCASP_NUM_SERIALIZER 16 |
306 | ||
307 | static inline void mcasp_set_bits(void __iomem *reg, u32 val) | |
308 | { | |
309 | __raw_writel(__raw_readl(reg) | val, reg); | |
310 | } | |
311 | ||
312 | static inline void mcasp_clr_bits(void __iomem *reg, u32 val) | |
313 | { | |
314 | __raw_writel((__raw_readl(reg) & ~(val)), reg); | |
315 | } | |
316 | ||
317 | static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask) | |
318 | { | |
319 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); | |
320 | } | |
321 | ||
322 | static inline void mcasp_set_reg(void __iomem *reg, u32 val) | |
323 | { | |
324 | __raw_writel(val, reg); | |
325 | } | |
326 | ||
327 | static inline u32 mcasp_get_reg(void __iomem *reg) | |
328 | { | |
329 | return (unsigned int)__raw_readl(reg); | |
330 | } | |
331 | ||
332 | static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val) | |
333 | { | |
334 | int i = 0; | |
335 | ||
336 | mcasp_set_bits(regs, val); | |
337 | ||
338 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
339 | /* loop count is to avoid the lock-up */ | |
340 | for (i = 0; i < 1000; i++) { | |
341 | if ((mcasp_get_reg(regs) & val) == val) | |
342 | break; | |
343 | } | |
344 | ||
345 | if (i == 1000 && ((mcasp_get_reg(regs) & val) != val)) | |
346 | printk(KERN_ERR "GBLCTL write error\n"); | |
347 | } | |
348 | ||
b67f4487 C |
349 | static void mcasp_start_rx(struct davinci_audio_dev *dev) |
350 | { | |
351 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); | |
352 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
353 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); | |
354 | mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0); | |
355 | ||
356 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); | |
357 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
358 | mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0); | |
359 | ||
360 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); | |
361 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); | |
362 | } | |
363 | ||
364 | static void mcasp_start_tx(struct davinci_audio_dev *dev) | |
365 | { | |
6a99fb5f C |
366 | u8 offset = 0, i; |
367 | u32 cnt; | |
368 | ||
b67f4487 C |
369 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
370 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
371 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); | |
372 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); | |
373 | ||
374 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
375 | mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
376 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); | |
6a99fb5f C |
377 | for (i = 0; i < dev->num_serializer; i++) { |
378 | if (dev->serial_dir[i] == TX_MODE) { | |
379 | offset = i; | |
380 | break; | |
381 | } | |
382 | } | |
383 | ||
384 | /* wait for TX ready */ | |
385 | cnt = 0; | |
386 | while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) & | |
387 | TXSTATE) && (cnt < 100000)) | |
388 | cnt++; | |
389 | ||
b67f4487 C |
390 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); |
391 | } | |
392 | ||
393 | static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream) | |
394 | { | |
539d3d8c | 395 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
0d624275 | 396 | if (dev->txnumevt) { /* enable FIFO */ |
e5ec69da HG |
397 | switch (dev->version) { |
398 | case MCASP_VERSION_3: | |
399 | mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL, | |
0d624275 | 400 | FIFO_ENABLE); |
e5ec69da | 401 | mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL, |
539d3d8c | 402 | FIFO_ENABLE); |
e5ec69da HG |
403 | break; |
404 | default: | |
405 | mcasp_clr_bits(dev->base + | |
406 | DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); | |
407 | mcasp_set_bits(dev->base + | |
408 | DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); | |
409 | } | |
0d624275 | 410 | } |
b67f4487 | 411 | mcasp_start_tx(dev); |
539d3d8c | 412 | } else { |
0d624275 | 413 | if (dev->rxnumevt) { /* enable FIFO */ |
e5ec69da HG |
414 | switch (dev->version) { |
415 | case MCASP_VERSION_3: | |
416 | mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL, | |
0d624275 | 417 | FIFO_ENABLE); |
e5ec69da | 418 | mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL, |
539d3d8c | 419 | FIFO_ENABLE); |
e5ec69da HG |
420 | break; |
421 | default: | |
422 | mcasp_clr_bits(dev->base + | |
423 | DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); | |
424 | mcasp_set_bits(dev->base + | |
425 | DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); | |
426 | } | |
0d624275 | 427 | } |
b67f4487 | 428 | mcasp_start_rx(dev); |
539d3d8c | 429 | } |
b67f4487 C |
430 | } |
431 | ||
432 | static void mcasp_stop_rx(struct davinci_audio_dev *dev) | |
433 | { | |
434 | mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0); | |
435 | mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
436 | } | |
437 | ||
438 | static void mcasp_stop_tx(struct davinci_audio_dev *dev) | |
439 | { | |
440 | mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0); | |
441 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
442 | } | |
443 | ||
444 | static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream) | |
445 | { | |
539d3d8c | 446 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
e5ec69da HG |
447 | if (dev->txnumevt) { /* disable FIFO */ |
448 | switch (dev->version) { | |
449 | case MCASP_VERSION_3: | |
450 | mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL, | |
539d3d8c | 451 | FIFO_ENABLE); |
e5ec69da HG |
452 | break; |
453 | default: | |
454 | mcasp_clr_bits(dev->base + | |
455 | DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); | |
456 | } | |
457 | } | |
b67f4487 | 458 | mcasp_stop_tx(dev); |
539d3d8c | 459 | } else { |
e5ec69da HG |
460 | if (dev->rxnumevt) { /* disable FIFO */ |
461 | switch (dev->version) { | |
462 | case MCASP_VERSION_3: | |
463 | mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL, | |
539d3d8c | 464 | FIFO_ENABLE); |
e5ec69da HG |
465 | break; |
466 | ||
467 | default: | |
468 | mcasp_clr_bits(dev->base + | |
469 | DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); | |
470 | } | |
471 | } | |
b67f4487 | 472 | mcasp_stop_rx(dev); |
539d3d8c | 473 | } |
b67f4487 C |
474 | } |
475 | ||
476 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
477 | unsigned int fmt) | |
478 | { | |
f0fba2ad | 479 | struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
480 | void __iomem *base = dev->base; |
481 | ||
5296cf2d DM |
482 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
483 | case SND_SOC_DAIFMT_DSP_B: | |
484 | case SND_SOC_DAIFMT_AC97: | |
485 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
486 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
487 | break; | |
488 | default: | |
489 | /* configure a full-word SYNC pulse (LRCLK) */ | |
490 | mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
491 | mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
492 | ||
493 | /* make 1st data bit occur one ACLK cycle after the frame sync */ | |
494 | mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1)); | |
495 | mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1)); | |
496 | break; | |
497 | } | |
498 | ||
b67f4487 C |
499 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
500 | case SND_SOC_DAIFMT_CBS_CFS: | |
501 | /* codec is clock and frame slave */ | |
502 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); | |
503 | mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
504 | ||
505 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | |
506 | mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
507 | ||
81ee6833 MB |
508 | mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, |
509 | ACLKX | ACLKR); | |
510 | mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, | |
511 | AFSX | AFSR); | |
b67f4487 | 512 | break; |
517ee6cf C |
513 | case SND_SOC_DAIFMT_CBM_CFS: |
514 | /* codec is clock master and frame slave */ | |
a90f549e | 515 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
517ee6cf C |
516 | mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); |
517 | ||
a90f549e | 518 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
517ee6cf C |
519 | mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
520 | ||
db92f437 BG |
521 | mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, |
522 | ACLKX | ACLKR); | |
9595c8f0 | 523 | mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, |
db92f437 | 524 | AFSX | AFSR); |
517ee6cf | 525 | break; |
b67f4487 C |
526 | case SND_SOC_DAIFMT_CBM_CFM: |
527 | /* codec is clock and frame master */ | |
528 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); | |
529 | mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
530 | ||
531 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | |
532 | mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
533 | ||
9595c8f0 BG |
534 | mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, |
535 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
b67f4487 C |
536 | break; |
537 | ||
538 | default: | |
539 | return -EINVAL; | |
540 | } | |
541 | ||
542 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
543 | case SND_SOC_DAIFMT_IB_NF: | |
544 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); | |
545 | mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
546 | ||
547 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); | |
548 | mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
549 | break; | |
550 | ||
551 | case SND_SOC_DAIFMT_NB_IF: | |
552 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); | |
553 | mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
554 | ||
555 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); | |
556 | mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
557 | break; | |
558 | ||
559 | case SND_SOC_DAIFMT_IB_IF: | |
560 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); | |
561 | mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
562 | ||
563 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); | |
564 | mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
565 | break; | |
566 | ||
567 | case SND_SOC_DAIFMT_NB_NF: | |
568 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); | |
569 | mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
570 | ||
df4a4eec | 571 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
b67f4487 C |
572 | mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
573 | break; | |
574 | ||
575 | default: | |
576 | return -EINVAL; | |
577 | } | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
4ed8c9b7 DM |
582 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) |
583 | { | |
584 | struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); | |
585 | ||
586 | switch (div_id) { | |
587 | case 0: /* MCLK divider */ | |
588 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, | |
589 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); | |
590 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, | |
591 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); | |
592 | break; | |
593 | ||
594 | case 1: /* BCLK divider */ | |
595 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, | |
596 | ACLKXDIV(div - 1), ACLKXDIV_MASK); | |
597 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG, | |
598 | ACLKRDIV(div - 1), ACLKRDIV_MASK); | |
599 | break; | |
600 | ||
1b3bc060 DM |
601 | case 2: /* BCLK/LRCLK ratio */ |
602 | dev->bclk_lrclk_ratio = div; | |
603 | break; | |
604 | ||
4ed8c9b7 DM |
605 | default: |
606 | return -EINVAL; | |
607 | } | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
5b66aa2d DM |
612 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
613 | unsigned int freq, int dir) | |
614 | { | |
615 | struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); | |
616 | ||
617 | if (dir == SND_SOC_CLOCK_OUT) { | |
618 | mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); | |
619 | mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
620 | mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
621 | } else { | |
622 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); | |
623 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
624 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
625 | } | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
b67f4487 | 630 | static int davinci_config_channel_size(struct davinci_audio_dev *dev, |
ba764b3d | 631 | int word_length) |
b67f4487 | 632 | { |
ba764b3d | 633 | u32 fmt; |
dde109fb | 634 | u32 rotate = (word_length / 4) & 0x7; |
ba764b3d | 635 | u32 mask = (1ULL << word_length) - 1; |
b67f4487 | 636 | |
1b3bc060 DM |
637 | /* |
638 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
639 | * callback, take it into account here. That allows us to for example | |
640 | * send 32 bits per channel to the codec, while only 16 of them carry | |
641 | * audio payload. | |
d486fea6 MB |
642 | * The clock ratio is given for a full period of data (for I2S format |
643 | * both left and right channels), so it has to be divided by number of | |
644 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 DM |
645 | */ |
646 | if (dev->bclk_lrclk_ratio) | |
d486fea6 | 647 | word_length = dev->bclk_lrclk_ratio / dev->tdm_slots; |
1b3bc060 | 648 | |
ba764b3d DM |
649 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
650 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 651 | |
f5023af6 YY |
652 | if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) { |
653 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, | |
654 | RXSSZ(fmt), RXSSZ(0x0F)); | |
655 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, | |
656 | TXSSZ(fmt), TXSSZ(0x0F)); | |
657 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, | |
658 | TXROT(rotate), TXROT(7)); | |
659 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, | |
660 | RXROT(rotate), RXROT(7)); | |
661 | mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, | |
662 | mask); | |
663 | } | |
664 | ||
0c31cf3e | 665 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 666 | |
b67f4487 C |
667 | return 0; |
668 | } | |
669 | ||
2952b27e MB |
670 | static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream, |
671 | int channels) | |
b67f4487 C |
672 | { |
673 | int i; | |
6a99fb5f C |
674 | u8 tx_ser = 0; |
675 | u8 rx_ser = 0; | |
2952b27e MB |
676 | u8 ser; |
677 | u8 slots = dev->tdm_slots; | |
678 | u8 max_active_serializers = (channels + slots - 1) / slots; | |
b67f4487 C |
679 | /* Default configuration */ |
680 | mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); | |
681 | ||
682 | /* All PINS as McASP */ | |
683 | mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000); | |
684 | ||
685 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
686 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
687 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, | |
688 | TXDATADMADIS); | |
689 | } else { | |
690 | mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
691 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG, | |
692 | RXDATADMADIS); | |
693 | } | |
694 | ||
695 | for (i = 0; i < dev->num_serializer; i++) { | |
696 | mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i), | |
697 | dev->serial_dir[i]); | |
2952b27e MB |
698 | if (dev->serial_dir[i] == TX_MODE && |
699 | tx_ser < max_active_serializers) { | |
b67f4487 C |
700 | mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, |
701 | AXR(i)); | |
6a99fb5f | 702 | tx_ser++; |
2952b27e MB |
703 | } else if (dev->serial_dir[i] == RX_MODE && |
704 | rx_ser < max_active_serializers) { | |
b67f4487 C |
705 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, |
706 | AXR(i)); | |
6a99fb5f | 707 | rx_ser++; |
2952b27e MB |
708 | } else { |
709 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i), | |
710 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
711 | } |
712 | } | |
713 | ||
ecf327c7 DM |
714 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
715 | ser = tx_ser; | |
716 | else | |
717 | ser = rx_ser; | |
718 | ||
719 | if (ser < max_active_serializers) { | |
720 | dev_warn(dev->dev, "stream has more channels (%d) than are " | |
721 | "enabled in mcasp (%d)\n", channels, ser * slots); | |
722 | return -EINVAL; | |
723 | } | |
724 | ||
6a99fb5f C |
725 | if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) { |
726 | if (dev->txnumevt * tx_ser > 64) | |
727 | dev->txnumevt = 1; | |
728 | ||
e5ec69da HG |
729 | switch (dev->version) { |
730 | case MCASP_VERSION_3: | |
731 | mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser, | |
6a99fb5f | 732 | NUMDMA_MASK); |
e5ec69da | 733 | mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, |
6a99fb5f | 734 | ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK); |
e5ec69da HG |
735 | break; |
736 | default: | |
737 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, | |
738 | tx_ser, NUMDMA_MASK); | |
739 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, | |
740 | ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK); | |
741 | } | |
6a99fb5f C |
742 | } |
743 | ||
744 | if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) { | |
745 | if (dev->rxnumevt * rx_ser > 64) | |
746 | dev->rxnumevt = 1; | |
e5ec69da HG |
747 | switch (dev->version) { |
748 | case MCASP_VERSION_3: | |
749 | mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser, | |
6a99fb5f | 750 | NUMDMA_MASK); |
e5ec69da HG |
751 | mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, |
752 | ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK); | |
753 | break; | |
754 | default: | |
755 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, | |
756 | rx_ser, NUMDMA_MASK); | |
757 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, | |
6a99fb5f | 758 | ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK); |
e5ec69da | 759 | } |
b67f4487 | 760 | } |
2952b27e MB |
761 | |
762 | return 0; | |
b67f4487 C |
763 | } |
764 | ||
765 | static void davinci_hw_param(struct davinci_audio_dev *dev, int stream) | |
766 | { | |
767 | int i, active_slots; | |
768 | u32 mask = 0; | |
769 | ||
770 | active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots; | |
771 | for (i = 0; i < active_slots; i++) | |
772 | mask |= (1 << i); | |
773 | ||
6a99fb5f C |
774 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
775 | ||
b67f4487 C |
776 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
777 | /* bit stream is MSB first with no delay */ | |
778 | /* DSP_B mode */ | |
b67f4487 C |
779 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask); |
780 | mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD); | |
781 | ||
049cfaaa | 782 | if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32)) |
b67f4487 C |
783 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, |
784 | FSXMOD(dev->tdm_slots), FSXMOD(0x1FF)); | |
785 | else | |
786 | printk(KERN_ERR "playback tdm slot %d not supported\n", | |
787 | dev->tdm_slots); | |
b67f4487 C |
788 | } else { |
789 | /* bit stream is MSB first with no delay */ | |
790 | /* DSP_B mode */ | |
791 | mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD); | |
b67f4487 C |
792 | mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask); |
793 | ||
049cfaaa | 794 | if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32)) |
b67f4487 C |
795 | mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, |
796 | FSRMOD(dev->tdm_slots), FSRMOD(0x1FF)); | |
797 | else | |
798 | printk(KERN_ERR "capture tdm slot %d not supported\n", | |
799 | dev->tdm_slots); | |
b67f4487 C |
800 | } |
801 | } | |
802 | ||
803 | /* S/PDIF */ | |
804 | static void davinci_hw_dit_param(struct davinci_audio_dev *dev) | |
805 | { | |
b67f4487 C |
806 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
807 | and LSB first */ | |
808 | mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, | |
809 | TXROT(6) | TXSSZ(15)); | |
810 | ||
811 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
812 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG, | |
813 | AFSXE | FSXMOD(0x180)); | |
814 | ||
815 | /* Set the TX tdm : for all the slots */ | |
816 | mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); | |
817 | ||
818 | /* Set the TX clock controls : div = 1 and internal */ | |
819 | mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, | |
820 | ACLKXE | TX_ASYNC); | |
821 | ||
822 | mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
823 | ||
824 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
825 | mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); | |
826 | ||
827 | /* Enable the DIT */ | |
828 | mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN); | |
829 | } | |
830 | ||
831 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
832 | struct snd_pcm_hw_params *params, | |
833 | struct snd_soc_dai *cpu_dai) | |
834 | { | |
f0fba2ad | 835 | struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 836 | struct davinci_pcm_dma_params *dma_params = |
92e2a6f6 | 837 | &dev->dma_params[substream->stream]; |
b67f4487 | 838 | int word_length; |
4fa9c1a5 | 839 | u8 fifo_level; |
2952b27e | 840 | u8 slots = dev->tdm_slots; |
7c21a781 | 841 | u8 active_serializers; |
2952b27e MB |
842 | int channels; |
843 | struct snd_interval *pcm_channels = hw_param_interval(params, | |
844 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
845 | channels = pcm_channels->min; | |
b67f4487 | 846 | |
7c21a781 MB |
847 | active_serializers = (channels + slots - 1) / slots; |
848 | ||
2952b27e MB |
849 | if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL) |
850 | return -EINVAL; | |
6a99fb5f | 851 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
7c21a781 | 852 | fifo_level = dev->txnumevt * active_serializers; |
6a99fb5f | 853 | else |
7c21a781 | 854 | fifo_level = dev->rxnumevt * active_serializers; |
b67f4487 C |
855 | |
856 | if (dev->op_mode == DAVINCI_MCASP_DIT_MODE) | |
857 | davinci_hw_dit_param(dev); | |
858 | else | |
859 | davinci_hw_param(dev, substream->stream); | |
860 | ||
861 | switch (params_format(params)) { | |
0a9d1385 | 862 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
863 | case SNDRV_PCM_FORMAT_S8: |
864 | dma_params->data_type = 1; | |
ba764b3d | 865 | word_length = 8; |
b67f4487 C |
866 | break; |
867 | ||
0a9d1385 | 868 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
869 | case SNDRV_PCM_FORMAT_S16_LE: |
870 | dma_params->data_type = 2; | |
ba764b3d | 871 | word_length = 16; |
b67f4487 C |
872 | break; |
873 | ||
21eb24d8 DM |
874 | case SNDRV_PCM_FORMAT_U24_3LE: |
875 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 876 | dma_params->data_type = 3; |
ba764b3d | 877 | word_length = 24; |
21eb24d8 DM |
878 | break; |
879 | ||
6b7fa011 DM |
880 | case SNDRV_PCM_FORMAT_U24_LE: |
881 | case SNDRV_PCM_FORMAT_S24_LE: | |
0a9d1385 | 882 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
883 | case SNDRV_PCM_FORMAT_S32_LE: |
884 | dma_params->data_type = 4; | |
ba764b3d | 885 | word_length = 32; |
b67f4487 C |
886 | break; |
887 | ||
888 | default: | |
889 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
890 | return -EINVAL; | |
891 | } | |
6a99fb5f | 892 | |
4fa9c1a5 C |
893 | if (dev->version == MCASP_VERSION_2 && !fifo_level) |
894 | dma_params->acnt = 4; | |
895 | else | |
6a99fb5f C |
896 | dma_params->acnt = dma_params->data_type; |
897 | ||
4fa9c1a5 | 898 | dma_params->fifo_level = fifo_level; |
b67f4487 C |
899 | davinci_config_channel_size(dev, word_length); |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
904 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
905 | int cmd, struct snd_soc_dai *cpu_dai) | |
906 | { | |
f0fba2ad | 907 | struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
908 | int ret = 0; |
909 | ||
910 | switch (cmd) { | |
b67f4487 | 911 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
912 | case SNDRV_PCM_TRIGGER_START: |
913 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
10884347 HG |
914 | ret = pm_runtime_get_sync(dev->dev); |
915 | if (IS_ERR_VALUE(ret)) | |
916 | dev_err(dev->dev, "pm_runtime_get_sync() failed\n"); | |
b67f4487 C |
917 | davinci_mcasp_start(dev, substream->stream); |
918 | break; | |
919 | ||
b67f4487 | 920 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 921 | davinci_mcasp_stop(dev, substream->stream); |
10884347 HG |
922 | ret = pm_runtime_put_sync(dev->dev); |
923 | if (IS_ERR_VALUE(ret)) | |
924 | dev_err(dev->dev, "pm_runtime_put_sync() failed\n"); | |
a47979b5 C |
925 | break; |
926 | ||
927 | case SNDRV_PCM_TRIGGER_STOP: | |
b67f4487 C |
928 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
929 | davinci_mcasp_stop(dev, substream->stream); | |
930 | break; | |
931 | ||
932 | default: | |
933 | ret = -EINVAL; | |
934 | } | |
935 | ||
936 | return ret; | |
937 | } | |
938 | ||
bedad0ca CPE |
939 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
940 | struct snd_soc_dai *dai) | |
941 | { | |
942 | struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); | |
943 | ||
944 | snd_soc_dai_set_dma_data(dai, substream, dev->dma_params); | |
945 | return 0; | |
946 | } | |
947 | ||
85e7652d | 948 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
bedad0ca | 949 | .startup = davinci_mcasp_startup, |
b67f4487 C |
950 | .trigger = davinci_mcasp_trigger, |
951 | .hw_params = davinci_mcasp_hw_params, | |
952 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 953 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 954 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
955 | }; |
956 | ||
0a9d1385 BG |
957 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
958 | SNDRV_PCM_FMTBIT_U8 | \ | |
959 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
960 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
961 | SNDRV_PCM_FMTBIT_S24_LE | \ |
962 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
963 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
964 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
965 | SNDRV_PCM_FMTBIT_S32_LE | \ |
966 | SNDRV_PCM_FMTBIT_U32_LE) | |
967 | ||
f0fba2ad | 968 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 969 | { |
f0fba2ad | 970 | .name = "davinci-mcasp.0", |
b67f4487 C |
971 | .playback = { |
972 | .channels_min = 2, | |
2952b27e | 973 | .channels_max = 32 * 16, |
b67f4487 | 974 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 975 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
976 | }, |
977 | .capture = { | |
978 | .channels_min = 2, | |
2952b27e | 979 | .channels_max = 32 * 16, |
b67f4487 | 980 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 981 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
982 | }, |
983 | .ops = &davinci_mcasp_dai_ops, | |
984 | ||
985 | }, | |
986 | { | |
f0fba2ad | 987 | "davinci-mcasp.1", |
b67f4487 C |
988 | .playback = { |
989 | .channels_min = 1, | |
990 | .channels_max = 384, | |
991 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 992 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
993 | }, |
994 | .ops = &davinci_mcasp_dai_ops, | |
995 | }, | |
996 | ||
997 | }; | |
b67f4487 | 998 | |
eeef0eda KM |
999 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
1000 | .name = "davinci-mcasp", | |
1001 | }; | |
1002 | ||
3e3b8c34 HG |
1003 | static const struct of_device_id mcasp_dt_ids[] = { |
1004 | { | |
1005 | .compatible = "ti,dm646x-mcasp-audio", | |
1006 | .data = (void *)MCASP_VERSION_1, | |
1007 | }, | |
1008 | { | |
1009 | .compatible = "ti,da830-mcasp-audio", | |
1010 | .data = (void *)MCASP_VERSION_2, | |
1011 | }, | |
e5ec69da HG |
1012 | { |
1013 | .compatible = "ti,omap2-mcasp-audio", | |
1014 | .data = (void *)MCASP_VERSION_3, | |
1015 | }, | |
3e3b8c34 HG |
1016 | { /* sentinel */ } |
1017 | }; | |
1018 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1019 | ||
1020 | static struct snd_platform_data *davinci_mcasp_set_pdata_from_of( | |
1021 | struct platform_device *pdev) | |
1022 | { | |
1023 | struct device_node *np = pdev->dev.of_node; | |
1024 | struct snd_platform_data *pdata = NULL; | |
1025 | const struct of_device_id *match = | |
1026 | of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev); | |
1027 | ||
1028 | const u32 *of_serial_dir32; | |
1029 | u8 *of_serial_dir; | |
1030 | u32 val; | |
1031 | int i, ret = 0; | |
1032 | ||
1033 | if (pdev->dev.platform_data) { | |
1034 | pdata = pdev->dev.platform_data; | |
1035 | return pdata; | |
1036 | } else if (match) { | |
1037 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1038 | if (!pdata) { | |
1039 | ret = -ENOMEM; | |
1040 | goto nodata; | |
1041 | } | |
1042 | } else { | |
1043 | /* control shouldn't reach here. something is wrong */ | |
1044 | ret = -EINVAL; | |
1045 | goto nodata; | |
1046 | } | |
1047 | ||
1048 | if (match->data) | |
1049 | pdata->version = (u8)((int)match->data); | |
1050 | ||
1051 | ret = of_property_read_u32(np, "op-mode", &val); | |
1052 | if (ret >= 0) | |
1053 | pdata->op_mode = val; | |
1054 | ||
1055 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1056 | if (ret >= 0) { |
1057 | if (val < 2 || val > 32) { | |
1058 | dev_err(&pdev->dev, | |
1059 | "tdm-slots must be in rage [2-32]\n"); | |
1060 | ret = -EINVAL; | |
1061 | goto nodata; | |
1062 | } | |
1063 | ||
3e3b8c34 | 1064 | pdata->tdm_slots = val; |
2952b27e | 1065 | } |
3e3b8c34 HG |
1066 | |
1067 | ret = of_property_read_u32(np, "num-serializer", &val); | |
1068 | if (ret >= 0) | |
1069 | pdata->num_serializer = val; | |
1070 | ||
1071 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); | |
1072 | val /= sizeof(u32); | |
1073 | if (val != pdata->num_serializer) { | |
1074 | dev_err(&pdev->dev, | |
1075 | "num-serializer(%d) != serial-dir size(%d)\n", | |
1076 | pdata->num_serializer, val); | |
1077 | ret = -EINVAL; | |
1078 | goto nodata; | |
1079 | } | |
1080 | ||
1081 | if (of_serial_dir32) { | |
1082 | of_serial_dir = devm_kzalloc(&pdev->dev, | |
1083 | (sizeof(*of_serial_dir) * val), | |
1084 | GFP_KERNEL); | |
1085 | if (!of_serial_dir) { | |
1086 | ret = -ENOMEM; | |
1087 | goto nodata; | |
1088 | } | |
1089 | ||
1090 | for (i = 0; i < pdata->num_serializer; i++) | |
1091 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); | |
1092 | ||
1093 | pdata->serial_dir = of_serial_dir; | |
1094 | } | |
1095 | ||
1096 | ret = of_property_read_u32(np, "tx-num-evt", &val); | |
1097 | if (ret >= 0) | |
1098 | pdata->txnumevt = val; | |
1099 | ||
1100 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1101 | if (ret >= 0) | |
1102 | pdata->rxnumevt = val; | |
1103 | ||
1104 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1105 | if (ret >= 0) | |
1106 | pdata->sram_size_playback = val; | |
1107 | ||
1108 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1109 | if (ret >= 0) | |
1110 | pdata->sram_size_capture = val; | |
1111 | ||
1112 | return pdata; | |
1113 | ||
1114 | nodata: | |
1115 | if (ret < 0) { | |
1116 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1117 | ret); | |
1118 | pdata = NULL; | |
1119 | } | |
1120 | return pdata; | |
1121 | } | |
1122 | ||
b67f4487 C |
1123 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1124 | { | |
1125 | struct davinci_pcm_dma_params *dma_data; | |
1126 | struct resource *mem, *ioarea, *res; | |
1127 | struct snd_platform_data *pdata; | |
1128 | struct davinci_audio_dev *dev; | |
96d31e2b | 1129 | int ret; |
b67f4487 | 1130 | |
3e3b8c34 HG |
1131 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1132 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1133 | return -EINVAL; | |
1134 | } | |
1135 | ||
96d31e2b JL |
1136 | dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev), |
1137 | GFP_KERNEL); | |
b67f4487 C |
1138 | if (!dev) |
1139 | return -ENOMEM; | |
1140 | ||
3e3b8c34 HG |
1141 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1142 | if (!pdata) { | |
1143 | dev_err(&pdev->dev, "no platform data\n"); | |
1144 | return -EINVAL; | |
1145 | } | |
1146 | ||
b67f4487 C |
1147 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1148 | if (!mem) { | |
1149 | dev_err(&pdev->dev, "no mem resource?\n"); | |
96d31e2b | 1150 | return -ENODEV; |
b67f4487 C |
1151 | } |
1152 | ||
96d31e2b | 1153 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1154 | resource_size(mem), pdev->name); |
b67f4487 C |
1155 | if (!ioarea) { |
1156 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1157 | return -EBUSY; |
b67f4487 C |
1158 | } |
1159 | ||
10884347 | 1160 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1161 | |
10884347 HG |
1162 | ret = pm_runtime_get_sync(&pdev->dev); |
1163 | if (IS_ERR_VALUE(ret)) { | |
1164 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
1165 | return ret; | |
1166 | } | |
b67f4487 | 1167 | |
96d31e2b | 1168 | dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
4f82f028 VB |
1169 | if (!dev->base) { |
1170 | dev_err(&pdev->dev, "ioremap failed\n"); | |
1171 | ret = -ENOMEM; | |
1172 | goto err_release_clk; | |
1173 | } | |
1174 | ||
b67f4487 C |
1175 | dev->op_mode = pdata->op_mode; |
1176 | dev->tdm_slots = pdata->tdm_slots; | |
1177 | dev->num_serializer = pdata->num_serializer; | |
1178 | dev->serial_dir = pdata->serial_dir; | |
6a99fb5f C |
1179 | dev->version = pdata->version; |
1180 | dev->txnumevt = pdata->txnumevt; | |
1181 | dev->rxnumevt = pdata->rxnumevt; | |
10884347 | 1182 | dev->dev = &pdev->dev; |
b67f4487 | 1183 | |
92e2a6f6 | 1184 | dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
48519f0a SN |
1185 | dma_data->asp_chan_q = pdata->asp_chan_q; |
1186 | dma_data->ram_chan_q = pdata->ram_chan_q; | |
b8ec56d8 | 1187 | dma_data->sram_pool = pdata->sram_pool; |
a0c83263 | 1188 | dma_data->sram_size = pdata->sram_size_playback; |
92e2a6f6 | 1189 | dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset + |
4f82f028 | 1190 | mem->start); |
b67f4487 C |
1191 | |
1192 | /* first TX, then RX */ | |
1193 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1194 | if (!res) { | |
1195 | dev_err(&pdev->dev, "no DMA resource\n"); | |
02ffc5f3 | 1196 | ret = -ENODEV; |
96d31e2b | 1197 | goto err_release_clk; |
b67f4487 C |
1198 | } |
1199 | ||
92e2a6f6 TK |
1200 | dma_data->channel = res->start; |
1201 | ||
1202 | dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]; | |
48519f0a SN |
1203 | dma_data->asp_chan_q = pdata->asp_chan_q; |
1204 | dma_data->ram_chan_q = pdata->ram_chan_q; | |
b8ec56d8 | 1205 | dma_data->sram_pool = pdata->sram_pool; |
a0c83263 | 1206 | dma_data->sram_size = pdata->sram_size_capture; |
92e2a6f6 | 1207 | dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset + |
4f82f028 | 1208 | mem->start); |
b67f4487 C |
1209 | |
1210 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1211 | if (!res) { | |
1212 | dev_err(&pdev->dev, "no DMA resource\n"); | |
02ffc5f3 | 1213 | ret = -ENODEV; |
96d31e2b | 1214 | goto err_release_clk; |
b67f4487 C |
1215 | } |
1216 | ||
92e2a6f6 | 1217 | dma_data->channel = res->start; |
f0fba2ad | 1218 | dev_set_drvdata(&pdev->dev, dev); |
eeef0eda KM |
1219 | ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, |
1220 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1221 | |
1222 | if (ret != 0) | |
96d31e2b | 1223 | goto err_release_clk; |
f08095a4 HG |
1224 | |
1225 | ret = davinci_soc_platform_register(&pdev->dev); | |
1226 | if (ret) { | |
1227 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
eeef0eda | 1228 | goto err_unregister_component; |
f08095a4 HG |
1229 | } |
1230 | ||
b67f4487 C |
1231 | return 0; |
1232 | ||
eeef0eda KM |
1233 | err_unregister_component: |
1234 | snd_soc_unregister_component(&pdev->dev); | |
eef6d7b8 | 1235 | err_release_clk: |
10884347 HG |
1236 | pm_runtime_put_sync(&pdev->dev); |
1237 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1238 | return ret; |
1239 | } | |
1240 | ||
1241 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1242 | { | |
b67f4487 | 1243 | |
eeef0eda | 1244 | snd_soc_unregister_component(&pdev->dev); |
f08095a4 | 1245 | davinci_soc_platform_unregister(&pdev->dev); |
10884347 HG |
1246 | |
1247 | pm_runtime_put_sync(&pdev->dev); | |
1248 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1249 | |
b67f4487 C |
1250 | return 0; |
1251 | } | |
1252 | ||
1253 | static struct platform_driver davinci_mcasp_driver = { | |
1254 | .probe = davinci_mcasp_probe, | |
1255 | .remove = davinci_mcasp_remove, | |
1256 | .driver = { | |
1257 | .name = "davinci-mcasp", | |
1258 | .owner = THIS_MODULE, | |
3e3b8c34 | 1259 | .of_match_table = of_match_ptr(mcasp_dt_ids), |
b67f4487 C |
1260 | }, |
1261 | }; | |
1262 | ||
f9b8a514 | 1263 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1264 | |
1265 | MODULE_AUTHOR("Steve Chen"); | |
1266 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1267 | MODULE_LICENSE("GPL"); | |
1268 |