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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * MCASP related definitions | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #ifndef DAVINCI_MCASP_H | |
19 | #define DAVINCI_MCASP_H | |
20 | ||
02e08d9b PU |
21 | /* |
22 | * McASP register definitions | |
23 | */ | |
24 | #define DAVINCI_MCASP_PID_REG 0x00 | |
25 | #define DAVINCI_MCASP_PWREMUMGT_REG 0x04 | |
26 | ||
27 | #define DAVINCI_MCASP_PFUNC_REG 0x10 | |
28 | #define DAVINCI_MCASP_PDIR_REG 0x14 | |
29 | #define DAVINCI_MCASP_PDOUT_REG 0x18 | |
30 | #define DAVINCI_MCASP_PDSET_REG 0x1c | |
31 | ||
32 | #define DAVINCI_MCASP_PDCLR_REG 0x20 | |
33 | ||
34 | #define DAVINCI_MCASP_TLGC_REG 0x30 | |
35 | #define DAVINCI_MCASP_TLMR_REG 0x34 | |
36 | ||
37 | #define DAVINCI_MCASP_GBLCTL_REG 0x44 | |
38 | #define DAVINCI_MCASP_AMUTE_REG 0x48 | |
39 | #define DAVINCI_MCASP_LBCTL_REG 0x4c | |
40 | ||
41 | #define DAVINCI_MCASP_TXDITCTL_REG 0x50 | |
42 | ||
43 | #define DAVINCI_MCASP_GBLCTLR_REG 0x60 | |
44 | #define DAVINCI_MCASP_RXMASK_REG 0x64 | |
45 | #define DAVINCI_MCASP_RXFMT_REG 0x68 | |
46 | #define DAVINCI_MCASP_RXFMCTL_REG 0x6c | |
47 | ||
48 | #define DAVINCI_MCASP_ACLKRCTL_REG 0x70 | |
49 | #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74 | |
50 | #define DAVINCI_MCASP_RXTDM_REG 0x78 | |
51 | #define DAVINCI_MCASP_EVTCTLR_REG 0x7c | |
52 | ||
53 | #define DAVINCI_MCASP_RXSTAT_REG 0x80 | |
54 | #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84 | |
55 | #define DAVINCI_MCASP_RXCLKCHK_REG 0x88 | |
56 | #define DAVINCI_MCASP_REVTCTL_REG 0x8c | |
57 | ||
58 | #define DAVINCI_MCASP_GBLCTLX_REG 0xa0 | |
59 | #define DAVINCI_MCASP_TXMASK_REG 0xa4 | |
60 | #define DAVINCI_MCASP_TXFMT_REG 0xa8 | |
61 | #define DAVINCI_MCASP_TXFMCTL_REG 0xac | |
62 | ||
63 | #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0 | |
64 | #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4 | |
65 | #define DAVINCI_MCASP_TXTDM_REG 0xb8 | |
66 | #define DAVINCI_MCASP_EVTCTLX_REG 0xbc | |
67 | ||
68 | #define DAVINCI_MCASP_TXSTAT_REG 0xc0 | |
69 | #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4 | |
70 | #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8 | |
71 | #define DAVINCI_MCASP_XEVTCTL_REG 0xcc | |
72 | ||
73 | /* Left(even TDM Slot) Channel Status Register File */ | |
74 | #define DAVINCI_MCASP_DITCSRA_REG 0x100 | |
75 | /* Right(odd TDM slot) Channel Status Register File */ | |
76 | #define DAVINCI_MCASP_DITCSRB_REG 0x118 | |
77 | /* Left(even TDM slot) User Data Register File */ | |
78 | #define DAVINCI_MCASP_DITUDRA_REG 0x130 | |
79 | /* Right(odd TDM Slot) User Data Register File */ | |
80 | #define DAVINCI_MCASP_DITUDRB_REG 0x148 | |
81 | ||
82 | /* Serializer n Control Register */ | |
83 | #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180 | |
84 | #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \ | |
85 | (n << 2)) | |
86 | ||
87 | /* Transmit Buffer for Serializer n */ | |
8e1cc0e4 | 88 | #define DAVINCI_MCASP_TXBUF_REG(n) (0x200 + (n << 2)) |
02e08d9b | 89 | /* Receive Buffer for Serializer n */ |
8e1cc0e4 | 90 | #define DAVINCI_MCASP_RXBUF_REG(n) (0x280 + (n << 2)) |
02e08d9b PU |
91 | |
92 | /* McASP FIFO Registers */ | |
487dce88 PU |
93 | #define DAVINCI_MCASP_V2_AFIFO_BASE (0x1010) |
94 | #define DAVINCI_MCASP_V3_AFIFO_BASE (0x1000) | |
95 | ||
96 | /* FIFO register offsets from AFIFO base */ | |
97 | #define MCASP_WFIFOCTL_OFFSET (0x0) | |
98 | #define MCASP_WFIFOSTS_OFFSET (0x4) | |
99 | #define MCASP_RFIFOCTL_OFFSET (0x8) | |
100 | #define MCASP_RFIFOSTS_OFFSET (0xc) | |
02e08d9b PU |
101 | |
102 | /* | |
103 | * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management | |
104 | * Register Bits | |
105 | */ | |
106 | #define MCASP_FREE BIT(0) | |
107 | #define MCASP_SOFT BIT(1) | |
108 | ||
109 | /* | |
110 | * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits | |
111 | */ | |
112 | #define AXR(n) (1<<n) | |
113 | #define PFUNC_AMUTE BIT(25) | |
114 | #define ACLKX BIT(26) | |
115 | #define AHCLKX BIT(27) | |
116 | #define AFSX BIT(28) | |
117 | #define ACLKR BIT(29) | |
118 | #define AHCLKR BIT(30) | |
119 | #define AFSR BIT(31) | |
120 | ||
121 | /* | |
122 | * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits | |
123 | */ | |
124 | #define AXR(n) (1<<n) | |
125 | #define PDIR_AMUTE BIT(25) | |
126 | #define ACLKX BIT(26) | |
127 | #define AHCLKX BIT(27) | |
128 | #define AFSX BIT(28) | |
129 | #define ACLKR BIT(29) | |
130 | #define AHCLKR BIT(30) | |
131 | #define AFSR BIT(31) | |
132 | ||
133 | /* | |
134 | * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits | |
135 | */ | |
136 | #define DITEN BIT(0) /* Transmit DIT mode enable/disable */ | |
137 | #define VA BIT(2) | |
138 | #define VB BIT(3) | |
139 | ||
140 | /* | |
141 | * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits | |
142 | */ | |
143 | #define TXROT(val) (val) | |
144 | #define TXSEL BIT(3) | |
145 | #define TXSSZ(val) (val<<4) | |
146 | #define TXPBIT(val) (val<<8) | |
147 | #define TXPAD(val) (val<<13) | |
148 | #define TXORD BIT(15) | |
149 | #define FSXDLY(val) (val<<16) | |
150 | ||
151 | /* | |
152 | * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits | |
153 | */ | |
154 | #define RXROT(val) (val) | |
155 | #define RXSEL BIT(3) | |
156 | #define RXSSZ(val) (val<<4) | |
157 | #define RXPBIT(val) (val<<8) | |
158 | #define RXPAD(val) (val<<13) | |
159 | #define RXORD BIT(15) | |
160 | #define FSRDLY(val) (val<<16) | |
161 | ||
162 | /* | |
163 | * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits | |
164 | */ | |
165 | #define FSXPOL BIT(0) | |
166 | #define AFSXE BIT(1) | |
167 | #define FSXDUR BIT(4) | |
168 | #define FSXMOD(val) (val<<7) | |
169 | ||
170 | /* | |
171 | * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits | |
172 | */ | |
173 | #define FSRPOL BIT(0) | |
174 | #define AFSRE BIT(1) | |
175 | #define FSRDUR BIT(4) | |
176 | #define FSRMOD(val) (val<<7) | |
177 | ||
178 | /* | |
179 | * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits | |
180 | */ | |
181 | #define ACLKXDIV(val) (val) | |
182 | #define ACLKXE BIT(5) | |
183 | #define TX_ASYNC BIT(6) | |
184 | #define ACLKXPOL BIT(7) | |
185 | #define ACLKXDIV_MASK 0x1f | |
186 | ||
187 | /* | |
188 | * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits | |
189 | */ | |
190 | #define ACLKRDIV(val) (val) | |
191 | #define ACLKRE BIT(5) | |
192 | #define RX_ASYNC BIT(6) | |
193 | #define ACLKRPOL BIT(7) | |
194 | #define ACLKRDIV_MASK 0x1f | |
195 | ||
196 | /* | |
197 | * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control | |
198 | * Register Bits | |
199 | */ | |
200 | #define AHCLKXDIV(val) (val) | |
201 | #define AHCLKXPOL BIT(14) | |
202 | #define AHCLKXE BIT(15) | |
203 | #define AHCLKXDIV_MASK 0xfff | |
204 | ||
205 | /* | |
206 | * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control | |
207 | * Register Bits | |
208 | */ | |
209 | #define AHCLKRDIV(val) (val) | |
210 | #define AHCLKRPOL BIT(14) | |
211 | #define AHCLKRE BIT(15) | |
212 | #define AHCLKRDIV_MASK 0xfff | |
213 | ||
214 | /* | |
215 | * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits | |
216 | */ | |
217 | #define MODE(val) (val) | |
19db62ea MLC |
218 | #define DISMOD_3STATE (0x0) |
219 | #define DISMOD_LOW (0x2 << 2) | |
220 | #define DISMOD_HIGH (0x3 << 2) | |
221 | #define DISMOD_MASK DISMOD_HIGH | |
02e08d9b PU |
222 | #define TXSTATE BIT(4) |
223 | #define RXSTATE BIT(5) | |
224 | #define SRMOD_MASK 3 | |
225 | #define SRMOD_INACTIVE 0 | |
226 | ||
227 | /* | |
228 | * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits | |
229 | */ | |
230 | #define LBEN BIT(0) | |
231 | #define LBORD BIT(1) | |
232 | #define LBGENMODE(val) (val<<2) | |
233 | ||
234 | /* | |
235 | * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration | |
236 | */ | |
237 | #define TXTDMS(n) (1<<n) | |
238 | ||
239 | /* | |
240 | * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration | |
241 | */ | |
242 | #define RXTDMS(n) (1<<n) | |
243 | ||
244 | /* | |
245 | * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits | |
246 | */ | |
247 | #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */ | |
248 | #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */ | |
249 | #define RXSERCLR BIT(2) /* Receiver Serializer Clear */ | |
250 | #define RXSMRST BIT(3) /* Receiver State Machine Reset */ | |
251 | #define RXFSRST BIT(4) /* Frame Sync Generator Reset */ | |
252 | #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */ | |
253 | #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/ | |
254 | #define TXSERCLR BIT(10) /* Transmit Serializer Clear */ | |
255 | #define TXSMRST BIT(11) /* Transmitter State Machine Reset */ | |
256 | #define TXFSRST BIT(12) /* Frame Sync Generator Reset */ | |
257 | ||
36bcecd0 PU |
258 | /* |
259 | * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits | |
260 | * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits | |
261 | */ | |
a7a3324a | 262 | #define XRERR BIT(8) /* Transmit/Receive error */ |
36bcecd0 PU |
263 | #define XRDATA BIT(5) /* Transmit/Receive data ready */ |
264 | ||
02e08d9b PU |
265 | /* |
266 | * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits | |
267 | */ | |
268 | #define MUTENA(val) (val) | |
269 | #define MUTEINPOL BIT(2) | |
270 | #define MUTEINENA BIT(3) | |
271 | #define MUTEIN BIT(4) | |
272 | #define MUTER BIT(5) | |
273 | #define MUTEX BIT(6) | |
274 | #define MUTEFSR BIT(7) | |
275 | #define MUTEFSX BIT(8) | |
276 | #define MUTEBADCLKR BIT(9) | |
277 | #define MUTEBADCLKX BIT(10) | |
278 | #define MUTERXDMAERR BIT(11) | |
279 | #define MUTETXDMAERR BIT(12) | |
280 | ||
281 | /* | |
282 | * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits | |
283 | */ | |
284 | #define RXDATADMADIS BIT(0) | |
285 | ||
286 | /* | |
287 | * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits | |
288 | */ | |
289 | #define TXDATADMADIS BIT(0) | |
290 | ||
a7a3324a MLC |
291 | /* |
292 | * DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits | |
293 | */ | |
294 | #define ROVRN BIT(0) | |
295 | ||
296 | /* | |
297 | * DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits | |
298 | */ | |
299 | #define XUNDRN BIT(0) | |
300 | ||
02e08d9b PU |
301 | /* |
302 | * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits | |
303 | */ | |
304 | #define FIFO_ENABLE BIT(16) | |
305 | #define NUMEVT_MASK (0xFF << 8) | |
0bf0e8ae | 306 | #define NUMEVT(x) (((x) & 0xFF) << 8) |
02e08d9b PU |
307 | #define NUMDMA_MASK (0xFF) |
308 | ||
20d4b107 PU |
309 | /* clock divider IDs */ |
310 | #define MCASP_CLKDIV_AUXCLK 0 /* HCLK divider from AUXCLK */ | |
311 | #define MCASP_CLKDIV_BCLK 1 /* BCLK divider from HCLK */ | |
312 | #define MCASP_CLKDIV_BCLK_FS_RATIO 2 /* to set BCLK FS ration */ | |
313 | ||
b67f4487 | 314 | #endif /* DAVINCI_MCASP_H */ |