]>
Commit | Line | Data |
---|---|---|
3a9cf8ef RK |
1 | /* |
2 | * ALSA SoC Synopsys I2S Audio Layer | |
3 | * | |
22a4adf2 | 4 | * sound/soc/dwc/designware_i2s.c |
3a9cf8ef RK |
5 | * |
6 | * Copyright (C) 2010 ST Microelectronics | |
9a302c32 | 7 | * Rajeev Kumar <rajeevkumar.linux@gmail.com> |
3a9cf8ef RK |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/slab.h> | |
f4830312 | 21 | #include <linux/pm_runtime.h> |
3a9cf8ef RK |
22 | #include <sound/designware_i2s.h> |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
0d274544 | 26 | #include <sound/dmaengine_pcm.h> |
3a9cf8ef RK |
27 | |
28 | /* common register for all channel */ | |
29 | #define IER 0x000 | |
30 | #define IRER 0x004 | |
31 | #define ITER 0x008 | |
32 | #define CER 0x00C | |
33 | #define CCR 0x010 | |
34 | #define RXFFR 0x014 | |
35 | #define TXFFR 0x018 | |
36 | ||
37 | /* I2STxRxRegisters for all channels */ | |
38 | #define LRBR_LTHR(x) (0x40 * x + 0x020) | |
39 | #define RRBR_RTHR(x) (0x40 * x + 0x024) | |
40 | #define RER(x) (0x40 * x + 0x028) | |
41 | #define TER(x) (0x40 * x + 0x02C) | |
42 | #define RCR(x) (0x40 * x + 0x030) | |
43 | #define TCR(x) (0x40 * x + 0x034) | |
44 | #define ISR(x) (0x40 * x + 0x038) | |
45 | #define IMR(x) (0x40 * x + 0x03C) | |
46 | #define ROR(x) (0x40 * x + 0x040) | |
47 | #define TOR(x) (0x40 * x + 0x044) | |
48 | #define RFCR(x) (0x40 * x + 0x048) | |
49 | #define TFCR(x) (0x40 * x + 0x04C) | |
50 | #define RFF(x) (0x40 * x + 0x050) | |
51 | #define TFF(x) (0x40 * x + 0x054) | |
52 | ||
53 | /* I2SCOMPRegisters */ | |
54 | #define I2S_COMP_PARAM_2 0x01F0 | |
55 | #define I2S_COMP_PARAM_1 0x01F4 | |
56 | #define I2S_COMP_VERSION 0x01F8 | |
57 | #define I2S_COMP_TYPE 0x01FC | |
58 | ||
b226efe5 AJ |
59 | /* |
60 | * Component parameter register fields - define the I2S block's | |
61 | * configuration. | |
62 | */ | |
63 | #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25) | |
64 | #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22) | |
65 | #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19) | |
66 | #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16) | |
67 | #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9) | |
68 | #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7) | |
69 | #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6) | |
70 | #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5) | |
71 | #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4) | |
72 | #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2) | |
73 | #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0) | |
74 | ||
75 | #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10) | |
76 | #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7) | |
77 | #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3) | |
78 | #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0) | |
79 | ||
80 | /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */ | |
81 | #define COMP_MAX_WORDSIZE (1 << 3) | |
82 | #define COMP_MAX_DATA_WIDTH (1 << 2) | |
83 | ||
3a9cf8ef RK |
84 | #define MAX_CHANNEL_NUM 8 |
85 | #define MIN_CHANNEL_NUM 2 | |
86 | ||
0d274544 AJ |
87 | union dw_i2s_snd_dma_data { |
88 | struct i2s_dma_data pd; | |
89 | struct snd_dmaengine_dai_dma_data dt; | |
90 | }; | |
91 | ||
3a9cf8ef RK |
92 | struct dw_i2s_dev { |
93 | void __iomem *i2s_base; | |
94 | struct clk *clk; | |
95 | int active; | |
96 | unsigned int capability; | |
e164835a MSB |
97 | unsigned int quirks; |
98 | unsigned int i2s_reg_comp1; | |
99 | unsigned int i2s_reg_comp2; | |
3a9cf8ef | 100 | struct device *dev; |
0032e9db MSB |
101 | u32 ccr; |
102 | u32 xfer_resolution; | |
3a9cf8ef RK |
103 | |
104 | /* data related to DMA transfers b/w i2s and DMAC */ | |
0d274544 AJ |
105 | union dw_i2s_snd_dma_data play_dma_data; |
106 | union dw_i2s_snd_dma_data capture_dma_data; | |
3a9cf8ef RK |
107 | struct i2s_clk_config_data config; |
108 | int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); | |
109 | }; | |
110 | ||
6b4a21b6 | 111 | static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) |
3a9cf8ef RK |
112 | { |
113 | writel(val, io_base + reg); | |
114 | } | |
115 | ||
6b4a21b6 | 116 | static inline u32 i2s_read_reg(void __iomem *io_base, int reg) |
3a9cf8ef RK |
117 | { |
118 | return readl(io_base + reg); | |
119 | } | |
120 | ||
121 | static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) | |
122 | { | |
123 | u32 i = 0; | |
124 | ||
125 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
126 | for (i = 0; i < 4; i++) | |
127 | i2s_write_reg(dev->i2s_base, TER(i), 0); | |
128 | } else { | |
129 | for (i = 0; i < 4; i++) | |
130 | i2s_write_reg(dev->i2s_base, RER(i), 0); | |
131 | } | |
132 | } | |
133 | ||
134 | static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) | |
135 | { | |
136 | u32 i = 0; | |
137 | ||
138 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
139 | for (i = 0; i < 4; i++) | |
4873867e | 140 | i2s_read_reg(dev->i2s_base, TOR(i)); |
3a9cf8ef RK |
141 | } else { |
142 | for (i = 0; i < 4; i++) | |
4873867e | 143 | i2s_read_reg(dev->i2s_base, ROR(i)); |
3a9cf8ef RK |
144 | } |
145 | } | |
146 | ||
1520ffd2 MB |
147 | static void i2s_start(struct dw_i2s_dev *dev, |
148 | struct snd_pcm_substream *substream) | |
3a9cf8ef | 149 | { |
924eb475 | 150 | u32 i, irq; |
3a9cf8ef RK |
151 | i2s_write_reg(dev->i2s_base, IER, 1); |
152 | ||
924eb475 | 153 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
154 | for (i = 0; i < 4; i++) { | |
155 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); | |
156 | i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); | |
157 | } | |
3a9cf8ef | 158 | i2s_write_reg(dev->i2s_base, ITER, 1); |
924eb475 | 159 | } else { |
160 | for (i = 0; i < 4; i++) { | |
161 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); | |
162 | i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); | |
163 | } | |
3a9cf8ef | 164 | i2s_write_reg(dev->i2s_base, IRER, 1); |
924eb475 | 165 | } |
3a9cf8ef RK |
166 | |
167 | i2s_write_reg(dev->i2s_base, CER, 1); | |
168 | } | |
169 | ||
170 | static void i2s_stop(struct dw_i2s_dev *dev, | |
171 | struct snd_pcm_substream *substream) | |
172 | { | |
173 | u32 i = 0, irq; | |
174 | ||
175 | i2s_clear_irqs(dev, substream->stream); | |
176 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
177 | i2s_write_reg(dev->i2s_base, ITER, 0); | |
178 | ||
179 | for (i = 0; i < 4; i++) { | |
180 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); | |
181 | i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); | |
182 | } | |
183 | } else { | |
184 | i2s_write_reg(dev->i2s_base, IRER, 0); | |
185 | ||
186 | for (i = 0; i < 4; i++) { | |
187 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); | |
188 | i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); | |
189 | } | |
190 | } | |
191 | ||
192 | if (!dev->active) { | |
193 | i2s_write_reg(dev->i2s_base, CER, 0); | |
194 | i2s_write_reg(dev->i2s_base, IER, 0); | |
195 | } | |
196 | } | |
197 | ||
198 | static int dw_i2s_startup(struct snd_pcm_substream *substream, | |
199 | struct snd_soc_dai *cpu_dai) | |
200 | { | |
201 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); | |
0d274544 | 202 | union dw_i2s_snd_dma_data *dma_data = NULL; |
3a9cf8ef RK |
203 | |
204 | if (!(dev->capability & DWC_I2S_RECORD) && | |
205 | (substream->stream == SNDRV_PCM_STREAM_CAPTURE)) | |
206 | return -EINVAL; | |
207 | ||
208 | if (!(dev->capability & DWC_I2S_PLAY) && | |
209 | (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) | |
210 | return -EINVAL; | |
211 | ||
212 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
213 | dma_data = &dev->play_dma_data; | |
214 | else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
215 | dma_data = &dev->capture_dma_data; | |
216 | ||
217 | snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data); | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
0032e9db MSB |
222 | static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) |
223 | { | |
224 | u32 ch_reg, irq; | |
225 | struct i2s_clk_config_data *config = &dev->config; | |
226 | ||
227 | ||
228 | i2s_disable_channels(dev, stream); | |
229 | ||
230 | for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { | |
231 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
232 | i2s_write_reg(dev->i2s_base, TCR(ch_reg), | |
233 | dev->xfer_resolution); | |
234 | i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); | |
235 | irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); | |
236 | i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); | |
237 | i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); | |
238 | } else { | |
239 | i2s_write_reg(dev->i2s_base, RCR(ch_reg), | |
240 | dev->xfer_resolution); | |
241 | i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); | |
242 | irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); | |
243 | i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); | |
244 | i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); | |
245 | } | |
246 | ||
247 | } | |
248 | } | |
249 | ||
3a9cf8ef RK |
250 | static int dw_i2s_hw_params(struct snd_pcm_substream *substream, |
251 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
252 | { | |
253 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
254 | struct i2s_clk_config_data *config = &dev->config; | |
3a9cf8ef RK |
255 | int ret; |
256 | ||
257 | switch (params_format(params)) { | |
258 | case SNDRV_PCM_FORMAT_S16_LE: | |
259 | config->data_width = 16; | |
0032e9db MSB |
260 | dev->ccr = 0x00; |
261 | dev->xfer_resolution = 0x02; | |
3a9cf8ef RK |
262 | break; |
263 | ||
264 | case SNDRV_PCM_FORMAT_S24_LE: | |
265 | config->data_width = 24; | |
0032e9db MSB |
266 | dev->ccr = 0x08; |
267 | dev->xfer_resolution = 0x04; | |
3a9cf8ef RK |
268 | break; |
269 | ||
270 | case SNDRV_PCM_FORMAT_S32_LE: | |
271 | config->data_width = 32; | |
0032e9db MSB |
272 | dev->ccr = 0x10; |
273 | dev->xfer_resolution = 0x05; | |
3a9cf8ef RK |
274 | break; |
275 | ||
276 | default: | |
277 | dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt"); | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
281 | config->chan_nr = params_channels(params); | |
282 | ||
283 | switch (config->chan_nr) { | |
284 | case EIGHT_CHANNEL_SUPPORT: | |
3a9cf8ef | 285 | case SIX_CHANNEL_SUPPORT: |
3a9cf8ef | 286 | case FOUR_CHANNEL_SUPPORT: |
3a9cf8ef | 287 | case TWO_CHANNEL_SUPPORT: |
3a9cf8ef RK |
288 | break; |
289 | default: | |
290 | dev_err(dev->dev, "channel not supported\n"); | |
0099d24c | 291 | return -EINVAL; |
3a9cf8ef RK |
292 | } |
293 | ||
0032e9db | 294 | dw_i2s_config(dev, substream->stream); |
3a9cf8ef | 295 | |
0032e9db | 296 | i2s_write_reg(dev->i2s_base, CCR, dev->ccr); |
3a9cf8ef RK |
297 | |
298 | config->sample_rate = params_rate(params); | |
299 | ||
1d957d86 MSB |
300 | if (dev->capability & DW_I2S_MASTER) { |
301 | if (dev->i2s_clk_cfg) { | |
302 | ret = dev->i2s_clk_cfg(config); | |
303 | if (ret < 0) { | |
304 | dev_err(dev->dev, "runtime audio clk config fail\n"); | |
305 | return ret; | |
306 | } | |
307 | } else { | |
308 | u32 bitclk = config->sample_rate * | |
309 | config->data_width * 2; | |
310 | ||
311 | ret = clk_set_rate(dev->clk, bitclk); | |
312 | if (ret) { | |
313 | dev_err(dev->dev, "Can't set I2S clock rate: %d\n", | |
314 | ret); | |
315 | return ret; | |
316 | } | |
0d274544 | 317 | } |
3a9cf8ef | 318 | } |
3a9cf8ef RK |
319 | return 0; |
320 | } | |
321 | ||
322 | static void dw_i2s_shutdown(struct snd_pcm_substream *substream, | |
323 | struct snd_soc_dai *dai) | |
324 | { | |
325 | snd_soc_dai_set_dma_data(dai, substream, NULL); | |
326 | } | |
327 | ||
3475c3d0 AJ |
328 | static int dw_i2s_prepare(struct snd_pcm_substream *substream, |
329 | struct snd_soc_dai *dai) | |
330 | { | |
331 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
332 | ||
333 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
334 | i2s_write_reg(dev->i2s_base, TXFFR, 1); | |
335 | else | |
336 | i2s_write_reg(dev->i2s_base, RXFFR, 1); | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
3a9cf8ef RK |
341 | static int dw_i2s_trigger(struct snd_pcm_substream *substream, |
342 | int cmd, struct snd_soc_dai *dai) | |
343 | { | |
344 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
345 | int ret = 0; | |
346 | ||
347 | switch (cmd) { | |
348 | case SNDRV_PCM_TRIGGER_START: | |
349 | case SNDRV_PCM_TRIGGER_RESUME: | |
350 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
351 | dev->active++; | |
352 | i2s_start(dev, substream); | |
353 | break; | |
354 | ||
355 | case SNDRV_PCM_TRIGGER_STOP: | |
356 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
357 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
358 | dev->active--; | |
359 | i2s_stop(dev, substream); | |
360 | break; | |
361 | default: | |
362 | ret = -EINVAL; | |
363 | break; | |
364 | } | |
365 | return ret; | |
366 | } | |
367 | ||
ab57b8e9 MSB |
368 | static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) |
369 | { | |
370 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); | |
371 | int ret = 0; | |
372 | ||
373 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
374 | case SND_SOC_DAIFMT_CBM_CFM: | |
375 | if (dev->capability & DW_I2S_SLAVE) | |
376 | ret = 0; | |
377 | else | |
378 | ret = -EINVAL; | |
379 | break; | |
380 | case SND_SOC_DAIFMT_CBS_CFS: | |
381 | if (dev->capability & DW_I2S_MASTER) | |
382 | ret = 0; | |
383 | else | |
384 | ret = -EINVAL; | |
385 | break; | |
386 | case SND_SOC_DAIFMT_CBM_CFS: | |
387 | case SND_SOC_DAIFMT_CBS_CFM: | |
388 | ret = -EINVAL; | |
389 | break; | |
390 | default: | |
391 | dev_dbg(dev->dev, "dwc : Invalid master/slave format\n"); | |
392 | ret = -EINVAL; | |
393 | break; | |
394 | } | |
395 | return ret; | |
396 | } | |
397 | ||
3a9cf8ef RK |
398 | static struct snd_soc_dai_ops dw_i2s_dai_ops = { |
399 | .startup = dw_i2s_startup, | |
400 | .shutdown = dw_i2s_shutdown, | |
401 | .hw_params = dw_i2s_hw_params, | |
3475c3d0 | 402 | .prepare = dw_i2s_prepare, |
3a9cf8ef | 403 | .trigger = dw_i2s_trigger, |
ab57b8e9 | 404 | .set_fmt = dw_i2s_set_fmt, |
3a9cf8ef RK |
405 | }; |
406 | ||
92eaa328 KM |
407 | static const struct snd_soc_component_driver dw_i2s_component = { |
408 | .name = "dw-i2s", | |
409 | }; | |
410 | ||
3a9cf8ef | 411 | #ifdef CONFIG_PM |
f4830312 MSB |
412 | static int dw_i2s_runtime_suspend(struct device *dev) |
413 | { | |
414 | struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); | |
415 | ||
416 | if (dw_dev->capability & DW_I2S_MASTER) | |
417 | clk_disable(dw_dev->clk); | |
418 | return 0; | |
419 | } | |
420 | ||
421 | static int dw_i2s_runtime_resume(struct device *dev) | |
422 | { | |
423 | struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); | |
424 | ||
425 | if (dw_dev->capability & DW_I2S_MASTER) | |
426 | clk_enable(dw_dev->clk); | |
427 | return 0; | |
428 | } | |
3a9cf8ef RK |
429 | |
430 | static int dw_i2s_suspend(struct snd_soc_dai *dai) | |
431 | { | |
432 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
433 | ||
1d957d86 MSB |
434 | if (dev->capability & DW_I2S_MASTER) |
435 | clk_disable(dev->clk); | |
3a9cf8ef RK |
436 | return 0; |
437 | } | |
438 | ||
439 | static int dw_i2s_resume(struct snd_soc_dai *dai) | |
440 | { | |
441 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
442 | ||
1d957d86 MSB |
443 | if (dev->capability & DW_I2S_MASTER) |
444 | clk_enable(dev->clk); | |
0032e9db MSB |
445 | |
446 | if (dai->playback_active) | |
447 | dw_i2s_config(dev, SNDRV_PCM_STREAM_PLAYBACK); | |
448 | if (dai->capture_active) | |
449 | dw_i2s_config(dev, SNDRV_PCM_STREAM_CAPTURE); | |
3a9cf8ef RK |
450 | return 0; |
451 | } | |
452 | ||
453 | #else | |
454 | #define dw_i2s_suspend NULL | |
455 | #define dw_i2s_resume NULL | |
456 | #endif | |
457 | ||
b226efe5 AJ |
458 | /* |
459 | * The following tables allow a direct lookup of various parameters | |
460 | * defined in the I2S block's configuration in terms of sound system | |
461 | * parameters. Each table is sized to the number of entries possible | |
462 | * according to the number of configuration bits describing an I2S | |
463 | * block parameter. | |
464 | */ | |
465 | ||
0d274544 AJ |
466 | /* Maximum bit resolution of a channel - not uniformly spaced */ |
467 | static const u32 fifo_width[COMP_MAX_WORDSIZE] = { | |
468 | 12, 16, 20, 24, 32, 0, 0, 0 | |
469 | }; | |
470 | ||
b226efe5 AJ |
471 | /* Width of (DMA) bus */ |
472 | static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = { | |
473 | DMA_SLAVE_BUSWIDTH_1_BYTE, | |
474 | DMA_SLAVE_BUSWIDTH_2_BYTES, | |
475 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
476 | DMA_SLAVE_BUSWIDTH_UNDEFINED | |
477 | }; | |
478 | ||
479 | /* PCM format to support channel resolution */ | |
480 | static const u32 formats[COMP_MAX_WORDSIZE] = { | |
481 | SNDRV_PCM_FMTBIT_S16_LE, | |
482 | SNDRV_PCM_FMTBIT_S16_LE, | |
483 | SNDRV_PCM_FMTBIT_S24_LE, | |
484 | SNDRV_PCM_FMTBIT_S24_LE, | |
485 | SNDRV_PCM_FMTBIT_S32_LE, | |
486 | 0, | |
487 | 0, | |
488 | 0 | |
489 | }; | |
490 | ||
0d274544 | 491 | static int dw_configure_dai(struct dw_i2s_dev *dev, |
afa8603c | 492 | struct snd_soc_dai_driver *dw_i2s_dai, |
0d274544 | 493 | unsigned int rates) |
afa8603c | 494 | { |
b226efe5 AJ |
495 | /* |
496 | * Read component parameter registers to extract | |
497 | * the I2S block's configuration. | |
498 | */ | |
e164835a MSB |
499 | u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); |
500 | u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); | |
0d274544 | 501 | u32 idx; |
afa8603c | 502 | |
a242cac1 MSB |
503 | if (dev->capability & DWC_I2S_RECORD && |
504 | dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) | |
505 | comp1 = comp1 & ~BIT(5); | |
506 | ||
b226efe5 | 507 | if (COMP1_TX_ENABLED(comp1)) { |
afa8603c | 508 | dev_dbg(dev->dev, " designware: play supported\n"); |
b226efe5 AJ |
509 | idx = COMP1_TX_WORDSIZE_0(comp1); |
510 | if (WARN_ON(idx >= ARRAY_SIZE(formats))) | |
511 | return -EINVAL; | |
afa8603c | 512 | dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; |
b226efe5 AJ |
513 | dw_i2s_dai->playback.channels_max = |
514 | 1 << (COMP1_TX_CHANNELS(comp1) + 1); | |
515 | dw_i2s_dai->playback.formats = formats[idx]; | |
0d274544 | 516 | dw_i2s_dai->playback.rates = rates; |
afa8603c AJ |
517 | } |
518 | ||
b226efe5 | 519 | if (COMP1_RX_ENABLED(comp1)) { |
afa8603c | 520 | dev_dbg(dev->dev, "designware: record supported\n"); |
b226efe5 AJ |
521 | idx = COMP2_RX_WORDSIZE_0(comp2); |
522 | if (WARN_ON(idx >= ARRAY_SIZE(formats))) | |
523 | return -EINVAL; | |
afa8603c | 524 | dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; |
b226efe5 AJ |
525 | dw_i2s_dai->capture.channels_max = |
526 | 1 << (COMP1_RX_CHANNELS(comp1) + 1); | |
527 | dw_i2s_dai->capture.formats = formats[idx]; | |
0d274544 AJ |
528 | dw_i2s_dai->capture.rates = rates; |
529 | } | |
530 | ||
1d957d86 MSB |
531 | if (COMP1_MODE_EN(comp1)) { |
532 | dev_dbg(dev->dev, "designware: i2s master mode supported\n"); | |
533 | dev->capability |= DW_I2S_MASTER; | |
534 | } else { | |
535 | dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); | |
536 | dev->capability |= DW_I2S_SLAVE; | |
537 | } | |
538 | ||
0d274544 AJ |
539 | return 0; |
540 | } | |
541 | ||
542 | static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, | |
543 | struct snd_soc_dai_driver *dw_i2s_dai, | |
544 | struct resource *res, | |
545 | const struct i2s_platform_data *pdata) | |
546 | { | |
e164835a | 547 | u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); |
0d274544 AJ |
548 | u32 idx = COMP1_APB_DATA_WIDTH(comp1); |
549 | int ret; | |
550 | ||
551 | if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) | |
552 | return -EINVAL; | |
553 | ||
554 | ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); | |
555 | if (ret < 0) | |
556 | return ret; | |
557 | ||
558 | /* Set DMA slaves info */ | |
559 | dev->play_dma_data.pd.data = pdata->play_dma_data; | |
560 | dev->capture_dma_data.pd.data = pdata->capture_dma_data; | |
561 | dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; | |
562 | dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; | |
563 | dev->play_dma_data.pd.max_burst = 16; | |
564 | dev->capture_dma_data.pd.max_burst = 16; | |
565 | dev->play_dma_data.pd.addr_width = bus_widths[idx]; | |
566 | dev->capture_dma_data.pd.addr_width = bus_widths[idx]; | |
567 | dev->play_dma_data.pd.filter = pdata->filter; | |
568 | dev->capture_dma_data.pd.filter = pdata->filter; | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, | |
574 | struct snd_soc_dai_driver *dw_i2s_dai, | |
575 | struct resource *res) | |
576 | { | |
577 | u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); | |
578 | u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); | |
579 | u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); | |
580 | u32 idx = COMP1_APB_DATA_WIDTH(comp1); | |
581 | u32 idx2; | |
582 | int ret; | |
583 | ||
584 | if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) | |
585 | return -EINVAL; | |
586 | ||
587 | ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); | |
588 | if (ret < 0) | |
589 | return ret; | |
590 | ||
591 | if (COMP1_TX_ENABLED(comp1)) { | |
592 | idx2 = COMP1_TX_WORDSIZE_0(comp1); | |
593 | ||
594 | dev->capability |= DWC_I2S_PLAY; | |
595 | dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; | |
596 | dev->play_dma_data.dt.addr_width = bus_widths[idx]; | |
597 | dev->play_dma_data.dt.chan_name = "TX"; | |
598 | dev->play_dma_data.dt.fifo_size = fifo_depth * | |
599 | (fifo_width[idx2]) >> 8; | |
600 | dev->play_dma_data.dt.maxburst = 16; | |
601 | } | |
602 | if (COMP1_RX_ENABLED(comp1)) { | |
603 | idx2 = COMP2_RX_WORDSIZE_0(comp2); | |
604 | ||
605 | dev->capability |= DWC_I2S_RECORD; | |
606 | dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; | |
607 | dev->capture_dma_data.dt.addr_width = bus_widths[idx]; | |
608 | dev->capture_dma_data.dt.chan_name = "RX"; | |
609 | dev->capture_dma_data.dt.fifo_size = fifo_depth * | |
610 | (fifo_width[idx2] >> 8); | |
611 | dev->capture_dma_data.dt.maxburst = 16; | |
afa8603c | 612 | } |
b226efe5 AJ |
613 | |
614 | return 0; | |
0d274544 | 615 | |
afa8603c AJ |
616 | } |
617 | ||
3a9cf8ef RK |
618 | static int dw_i2s_probe(struct platform_device *pdev) |
619 | { | |
620 | const struct i2s_platform_data *pdata = pdev->dev.platform_data; | |
621 | struct dw_i2s_dev *dev; | |
622 | struct resource *res; | |
623 | int ret; | |
3a9cf8ef | 624 | struct snd_soc_dai_driver *dw_i2s_dai; |
1d957d86 | 625 | const char *clk_id; |
3a9cf8ef | 626 | |
3a9cf8ef RK |
627 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); |
628 | if (!dev) { | |
629 | dev_warn(&pdev->dev, "kzalloc fail\n"); | |
630 | return -ENOMEM; | |
631 | } | |
632 | ||
b163be4c | 633 | dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); |
be33465e | 634 | if (!dw_i2s_dai) |
3a9cf8ef | 635 | return -ENOMEM; |
3a9cf8ef | 636 | |
b163be4c AJ |
637 | dw_i2s_dai->ops = &dw_i2s_dai_ops; |
638 | dw_i2s_dai->suspend = dw_i2s_suspend; | |
639 | dw_i2s_dai->resume = dw_i2s_resume; | |
640 | ||
641 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b163be4c | 642 | dev->i2s_base = devm_ioremap_resource(&pdev->dev, res); |
be33465e | 643 | if (IS_ERR(dev->i2s_base)) |
b163be4c | 644 | return PTR_ERR(dev->i2s_base); |
b163be4c | 645 | |
afa8603c | 646 | dev->dev = &pdev->dev; |
1d957d86 | 647 | |
d2f916aa JMT |
648 | dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; |
649 | dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; | |
0d274544 | 650 | if (pdata) { |
1d957d86 MSB |
651 | dev->capability = pdata->cap; |
652 | clk_id = NULL; | |
e164835a MSB |
653 | dev->quirks = pdata->quirks; |
654 | if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { | |
655 | dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; | |
656 | dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; | |
e164835a | 657 | } |
0d274544 | 658 | ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); |
1d957d86 MSB |
659 | } else { |
660 | clk_id = "i2sclk"; | |
661 | ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); | |
662 | } | |
663 | if (ret < 0) | |
664 | return ret; | |
0d274544 | 665 | |
1d957d86 MSB |
666 | if (dev->capability & DW_I2S_MASTER) { |
667 | if (pdata) { | |
668 | dev->i2s_clk_cfg = pdata->i2s_clk_cfg; | |
669 | if (!dev->i2s_clk_cfg) { | |
670 | dev_err(&pdev->dev, "no clock configure method\n"); | |
671 | return -ENODEV; | |
672 | } | |
0d274544 | 673 | } |
1d957d86 | 674 | dev->clk = devm_clk_get(&pdev->dev, clk_id); |
3a9cf8ef | 675 | |
1d957d86 MSB |
676 | if (IS_ERR(dev->clk)) |
677 | return PTR_ERR(dev->clk); | |
678 | ||
679 | ret = clk_prepare_enable(dev->clk); | |
0d274544 AJ |
680 | if (ret < 0) |
681 | return ret; | |
0d274544 | 682 | } |
3a9cf8ef | 683 | |
3a9cf8ef | 684 | dev_set_drvdata(&pdev->dev, dev); |
758c2deb | 685 | ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, |
92eaa328 | 686 | dw_i2s_dai, 1); |
3a9cf8ef RK |
687 | if (ret != 0) { |
688 | dev_err(&pdev->dev, "not able to register dai\n"); | |
e925a6b1 | 689 | goto err_clk_disable; |
3a9cf8ef RK |
690 | } |
691 | ||
0d274544 AJ |
692 | if (!pdata) { |
693 | ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); | |
694 | if (ret) { | |
695 | dev_err(&pdev->dev, | |
696 | "Could not register PCM: %d\n", ret); | |
697 | goto err_clk_disable; | |
698 | } | |
699 | } | |
f4830312 | 700 | pm_runtime_enable(&pdev->dev); |
3a9cf8ef RK |
701 | return 0; |
702 | ||
3a9cf8ef | 703 | err_clk_disable: |
1d957d86 MSB |
704 | if (dev->capability & DW_I2S_MASTER) |
705 | clk_disable_unprepare(dev->clk); | |
3a9cf8ef RK |
706 | return ret; |
707 | } | |
708 | ||
709 | static int dw_i2s_remove(struct platform_device *pdev) | |
710 | { | |
711 | struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); | |
712 | ||
1d957d86 MSB |
713 | if (dev->capability & DW_I2S_MASTER) |
714 | clk_disable_unprepare(dev->clk); | |
3a9cf8ef | 715 | |
f4830312 | 716 | pm_runtime_disable(&pdev->dev); |
3a9cf8ef RK |
717 | return 0; |
718 | } | |
719 | ||
0d274544 AJ |
720 | #ifdef CONFIG_OF |
721 | static const struct of_device_id dw_i2s_of_match[] = { | |
722 | { .compatible = "snps,designware-i2s", }, | |
723 | {}, | |
724 | }; | |
725 | ||
726 | MODULE_DEVICE_TABLE(of, dw_i2s_of_match); | |
727 | #endif | |
728 | ||
f4830312 MSB |
729 | static const struct dev_pm_ops dwc_pm_ops = { |
730 | SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL) | |
731 | }; | |
732 | ||
3a9cf8ef RK |
733 | static struct platform_driver dw_i2s_driver = { |
734 | .probe = dw_i2s_probe, | |
735 | .remove = dw_i2s_remove, | |
736 | .driver = { | |
737 | .name = "designware-i2s", | |
0d274544 | 738 | .of_match_table = of_match_ptr(dw_i2s_of_match), |
f4830312 | 739 | .pm = &dwc_pm_ops, |
3a9cf8ef RK |
740 | }, |
741 | }; | |
742 | ||
743 | module_platform_driver(dw_i2s_driver); | |
744 | ||
b794dbcd | 745 | MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>"); |
3a9cf8ef RK |
746 | MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface"); |
747 | MODULE_LICENSE("GPL"); | |
748 | MODULE_ALIAS("platform:designware_i2s"); |