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Commit | Line | Data |
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3a9cf8ef RK |
1 | /* |
2 | * ALSA SoC Synopsys I2S Audio Layer | |
3 | * | |
22a4adf2 | 4 | * sound/soc/dwc/designware_i2s.c |
3a9cf8ef RK |
5 | * |
6 | * Copyright (C) 2010 ST Microelectronics | |
9a302c32 | 7 | * Rajeev Kumar <rajeevkumar.linux@gmail.com> |
3a9cf8ef RK |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/slab.h> | |
21 | #include <sound/designware_i2s.h> | |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/soc.h> | |
0d274544 | 25 | #include <sound/dmaengine_pcm.h> |
3a9cf8ef RK |
26 | |
27 | /* common register for all channel */ | |
28 | #define IER 0x000 | |
29 | #define IRER 0x004 | |
30 | #define ITER 0x008 | |
31 | #define CER 0x00C | |
32 | #define CCR 0x010 | |
33 | #define RXFFR 0x014 | |
34 | #define TXFFR 0x018 | |
35 | ||
36 | /* I2STxRxRegisters for all channels */ | |
37 | #define LRBR_LTHR(x) (0x40 * x + 0x020) | |
38 | #define RRBR_RTHR(x) (0x40 * x + 0x024) | |
39 | #define RER(x) (0x40 * x + 0x028) | |
40 | #define TER(x) (0x40 * x + 0x02C) | |
41 | #define RCR(x) (0x40 * x + 0x030) | |
42 | #define TCR(x) (0x40 * x + 0x034) | |
43 | #define ISR(x) (0x40 * x + 0x038) | |
44 | #define IMR(x) (0x40 * x + 0x03C) | |
45 | #define ROR(x) (0x40 * x + 0x040) | |
46 | #define TOR(x) (0x40 * x + 0x044) | |
47 | #define RFCR(x) (0x40 * x + 0x048) | |
48 | #define TFCR(x) (0x40 * x + 0x04C) | |
49 | #define RFF(x) (0x40 * x + 0x050) | |
50 | #define TFF(x) (0x40 * x + 0x054) | |
51 | ||
52 | /* I2SCOMPRegisters */ | |
53 | #define I2S_COMP_PARAM_2 0x01F0 | |
54 | #define I2S_COMP_PARAM_1 0x01F4 | |
55 | #define I2S_COMP_VERSION 0x01F8 | |
56 | #define I2S_COMP_TYPE 0x01FC | |
57 | ||
b226efe5 AJ |
58 | /* |
59 | * Component parameter register fields - define the I2S block's | |
60 | * configuration. | |
61 | */ | |
62 | #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25) | |
63 | #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22) | |
64 | #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19) | |
65 | #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16) | |
66 | #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9) | |
67 | #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7) | |
68 | #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6) | |
69 | #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5) | |
70 | #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4) | |
71 | #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2) | |
72 | #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0) | |
73 | ||
74 | #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10) | |
75 | #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7) | |
76 | #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3) | |
77 | #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0) | |
78 | ||
79 | /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */ | |
80 | #define COMP_MAX_WORDSIZE (1 << 3) | |
81 | #define COMP_MAX_DATA_WIDTH (1 << 2) | |
82 | ||
3a9cf8ef RK |
83 | #define MAX_CHANNEL_NUM 8 |
84 | #define MIN_CHANNEL_NUM 2 | |
85 | ||
0d274544 AJ |
86 | union dw_i2s_snd_dma_data { |
87 | struct i2s_dma_data pd; | |
88 | struct snd_dmaengine_dai_dma_data dt; | |
89 | }; | |
90 | ||
3a9cf8ef RK |
91 | struct dw_i2s_dev { |
92 | void __iomem *i2s_base; | |
93 | struct clk *clk; | |
94 | int active; | |
95 | unsigned int capability; | |
96 | struct device *dev; | |
97 | ||
98 | /* data related to DMA transfers b/w i2s and DMAC */ | |
0d274544 AJ |
99 | union dw_i2s_snd_dma_data play_dma_data; |
100 | union dw_i2s_snd_dma_data capture_dma_data; | |
3a9cf8ef RK |
101 | struct i2s_clk_config_data config; |
102 | int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); | |
103 | }; | |
104 | ||
6b4a21b6 | 105 | static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) |
3a9cf8ef RK |
106 | { |
107 | writel(val, io_base + reg); | |
108 | } | |
109 | ||
6b4a21b6 | 110 | static inline u32 i2s_read_reg(void __iomem *io_base, int reg) |
3a9cf8ef RK |
111 | { |
112 | return readl(io_base + reg); | |
113 | } | |
114 | ||
115 | static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) | |
116 | { | |
117 | u32 i = 0; | |
118 | ||
119 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
120 | for (i = 0; i < 4; i++) | |
121 | i2s_write_reg(dev->i2s_base, TER(i), 0); | |
122 | } else { | |
123 | for (i = 0; i < 4; i++) | |
124 | i2s_write_reg(dev->i2s_base, RER(i), 0); | |
125 | } | |
126 | } | |
127 | ||
128 | static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) | |
129 | { | |
130 | u32 i = 0; | |
131 | ||
132 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
133 | for (i = 0; i < 4; i++) | |
134 | i2s_write_reg(dev->i2s_base, TOR(i), 0); | |
135 | } else { | |
136 | for (i = 0; i < 4; i++) | |
137 | i2s_write_reg(dev->i2s_base, ROR(i), 0); | |
138 | } | |
139 | } | |
140 | ||
1520ffd2 MB |
141 | static void i2s_start(struct dw_i2s_dev *dev, |
142 | struct snd_pcm_substream *substream) | |
3a9cf8ef RK |
143 | { |
144 | ||
145 | i2s_write_reg(dev->i2s_base, IER, 1); | |
146 | ||
147 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
148 | i2s_write_reg(dev->i2s_base, ITER, 1); | |
149 | else | |
150 | i2s_write_reg(dev->i2s_base, IRER, 1); | |
151 | ||
152 | i2s_write_reg(dev->i2s_base, CER, 1); | |
153 | } | |
154 | ||
155 | static void i2s_stop(struct dw_i2s_dev *dev, | |
156 | struct snd_pcm_substream *substream) | |
157 | { | |
158 | u32 i = 0, irq; | |
159 | ||
160 | i2s_clear_irqs(dev, substream->stream); | |
161 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
162 | i2s_write_reg(dev->i2s_base, ITER, 0); | |
163 | ||
164 | for (i = 0; i < 4; i++) { | |
165 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); | |
166 | i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); | |
167 | } | |
168 | } else { | |
169 | i2s_write_reg(dev->i2s_base, IRER, 0); | |
170 | ||
171 | for (i = 0; i < 4; i++) { | |
172 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); | |
173 | i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); | |
174 | } | |
175 | } | |
176 | ||
177 | if (!dev->active) { | |
178 | i2s_write_reg(dev->i2s_base, CER, 0); | |
179 | i2s_write_reg(dev->i2s_base, IER, 0); | |
180 | } | |
181 | } | |
182 | ||
183 | static int dw_i2s_startup(struct snd_pcm_substream *substream, | |
184 | struct snd_soc_dai *cpu_dai) | |
185 | { | |
186 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); | |
0d274544 | 187 | union dw_i2s_snd_dma_data *dma_data = NULL; |
3a9cf8ef RK |
188 | |
189 | if (!(dev->capability & DWC_I2S_RECORD) && | |
190 | (substream->stream == SNDRV_PCM_STREAM_CAPTURE)) | |
191 | return -EINVAL; | |
192 | ||
193 | if (!(dev->capability & DWC_I2S_PLAY) && | |
194 | (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) | |
195 | return -EINVAL; | |
196 | ||
197 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
198 | dma_data = &dev->play_dma_data; | |
199 | else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
200 | dma_data = &dev->capture_dma_data; | |
201 | ||
202 | snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data); | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | static int dw_i2s_hw_params(struct snd_pcm_substream *substream, | |
208 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
209 | { | |
210 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
211 | struct i2s_clk_config_data *config = &dev->config; | |
212 | u32 ccr, xfer_resolution, ch_reg, irq; | |
213 | int ret; | |
214 | ||
215 | switch (params_format(params)) { | |
216 | case SNDRV_PCM_FORMAT_S16_LE: | |
217 | config->data_width = 16; | |
218 | ccr = 0x00; | |
219 | xfer_resolution = 0x02; | |
220 | break; | |
221 | ||
222 | case SNDRV_PCM_FORMAT_S24_LE: | |
223 | config->data_width = 24; | |
224 | ccr = 0x08; | |
225 | xfer_resolution = 0x04; | |
226 | break; | |
227 | ||
228 | case SNDRV_PCM_FORMAT_S32_LE: | |
229 | config->data_width = 32; | |
230 | ccr = 0x10; | |
231 | xfer_resolution = 0x05; | |
232 | break; | |
233 | ||
234 | default: | |
235 | dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt"); | |
236 | return -EINVAL; | |
237 | } | |
238 | ||
239 | config->chan_nr = params_channels(params); | |
240 | ||
241 | switch (config->chan_nr) { | |
242 | case EIGHT_CHANNEL_SUPPORT: | |
3a9cf8ef | 243 | case SIX_CHANNEL_SUPPORT: |
3a9cf8ef | 244 | case FOUR_CHANNEL_SUPPORT: |
3a9cf8ef | 245 | case TWO_CHANNEL_SUPPORT: |
3a9cf8ef RK |
246 | break; |
247 | default: | |
248 | dev_err(dev->dev, "channel not supported\n"); | |
0099d24c | 249 | return -EINVAL; |
3a9cf8ef RK |
250 | } |
251 | ||
252 | i2s_disable_channels(dev, substream->stream); | |
253 | ||
db2c1f9e AJ |
254 | for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { |
255 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
256 | i2s_write_reg(dev->i2s_base, TCR(ch_reg), | |
257 | xfer_resolution); | |
258 | i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); | |
259 | irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); | |
260 | i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); | |
261 | i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); | |
262 | } else { | |
263 | i2s_write_reg(dev->i2s_base, RCR(ch_reg), | |
264 | xfer_resolution); | |
265 | i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); | |
266 | irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); | |
267 | i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); | |
268 | i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); | |
269 | } | |
3a9cf8ef RK |
270 | } |
271 | ||
272 | i2s_write_reg(dev->i2s_base, CCR, ccr); | |
273 | ||
274 | config->sample_rate = params_rate(params); | |
275 | ||
0d274544 AJ |
276 | if (dev->i2s_clk_cfg) { |
277 | ret = dev->i2s_clk_cfg(config); | |
278 | if (ret < 0) { | |
279 | dev_err(dev->dev, "runtime audio clk config fail\n"); | |
280 | return ret; | |
281 | } | |
282 | } else { | |
283 | u32 bitclk = config->sample_rate * config->data_width * 2; | |
3a9cf8ef | 284 | |
0d274544 AJ |
285 | ret = clk_set_rate(dev->clk, bitclk); |
286 | if (ret) { | |
287 | dev_err(dev->dev, "Can't set I2S clock rate: %d\n", | |
288 | ret); | |
289 | return ret; | |
290 | } | |
3a9cf8ef RK |
291 | } |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | static void dw_i2s_shutdown(struct snd_pcm_substream *substream, | |
297 | struct snd_soc_dai *dai) | |
298 | { | |
299 | snd_soc_dai_set_dma_data(dai, substream, NULL); | |
300 | } | |
301 | ||
3475c3d0 AJ |
302 | static int dw_i2s_prepare(struct snd_pcm_substream *substream, |
303 | struct snd_soc_dai *dai) | |
304 | { | |
305 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
306 | ||
307 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
308 | i2s_write_reg(dev->i2s_base, TXFFR, 1); | |
309 | else | |
310 | i2s_write_reg(dev->i2s_base, RXFFR, 1); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
3a9cf8ef RK |
315 | static int dw_i2s_trigger(struct snd_pcm_substream *substream, |
316 | int cmd, struct snd_soc_dai *dai) | |
317 | { | |
318 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
319 | int ret = 0; | |
320 | ||
321 | switch (cmd) { | |
322 | case SNDRV_PCM_TRIGGER_START: | |
323 | case SNDRV_PCM_TRIGGER_RESUME: | |
324 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
325 | dev->active++; | |
326 | i2s_start(dev, substream); | |
327 | break; | |
328 | ||
329 | case SNDRV_PCM_TRIGGER_STOP: | |
330 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
331 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
332 | dev->active--; | |
333 | i2s_stop(dev, substream); | |
334 | break; | |
335 | default: | |
336 | ret = -EINVAL; | |
337 | break; | |
338 | } | |
339 | return ret; | |
340 | } | |
341 | ||
342 | static struct snd_soc_dai_ops dw_i2s_dai_ops = { | |
343 | .startup = dw_i2s_startup, | |
344 | .shutdown = dw_i2s_shutdown, | |
345 | .hw_params = dw_i2s_hw_params, | |
3475c3d0 | 346 | .prepare = dw_i2s_prepare, |
3a9cf8ef RK |
347 | .trigger = dw_i2s_trigger, |
348 | }; | |
349 | ||
92eaa328 KM |
350 | static const struct snd_soc_component_driver dw_i2s_component = { |
351 | .name = "dw-i2s", | |
352 | }; | |
353 | ||
3a9cf8ef RK |
354 | #ifdef CONFIG_PM |
355 | ||
356 | static int dw_i2s_suspend(struct snd_soc_dai *dai) | |
357 | { | |
358 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
359 | ||
360 | clk_disable(dev->clk); | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static int dw_i2s_resume(struct snd_soc_dai *dai) | |
365 | { | |
366 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
367 | ||
368 | clk_enable(dev->clk); | |
369 | return 0; | |
370 | } | |
371 | ||
372 | #else | |
373 | #define dw_i2s_suspend NULL | |
374 | #define dw_i2s_resume NULL | |
375 | #endif | |
376 | ||
b226efe5 AJ |
377 | /* |
378 | * The following tables allow a direct lookup of various parameters | |
379 | * defined in the I2S block's configuration in terms of sound system | |
380 | * parameters. Each table is sized to the number of entries possible | |
381 | * according to the number of configuration bits describing an I2S | |
382 | * block parameter. | |
383 | */ | |
384 | ||
0d274544 AJ |
385 | /* Maximum bit resolution of a channel - not uniformly spaced */ |
386 | static const u32 fifo_width[COMP_MAX_WORDSIZE] = { | |
387 | 12, 16, 20, 24, 32, 0, 0, 0 | |
388 | }; | |
389 | ||
b226efe5 AJ |
390 | /* Width of (DMA) bus */ |
391 | static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = { | |
392 | DMA_SLAVE_BUSWIDTH_1_BYTE, | |
393 | DMA_SLAVE_BUSWIDTH_2_BYTES, | |
394 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
395 | DMA_SLAVE_BUSWIDTH_UNDEFINED | |
396 | }; | |
397 | ||
398 | /* PCM format to support channel resolution */ | |
399 | static const u32 formats[COMP_MAX_WORDSIZE] = { | |
400 | SNDRV_PCM_FMTBIT_S16_LE, | |
401 | SNDRV_PCM_FMTBIT_S16_LE, | |
402 | SNDRV_PCM_FMTBIT_S24_LE, | |
403 | SNDRV_PCM_FMTBIT_S24_LE, | |
404 | SNDRV_PCM_FMTBIT_S32_LE, | |
405 | 0, | |
406 | 0, | |
407 | 0 | |
408 | }; | |
409 | ||
0d274544 | 410 | static int dw_configure_dai(struct dw_i2s_dev *dev, |
afa8603c | 411 | struct snd_soc_dai_driver *dw_i2s_dai, |
0d274544 | 412 | unsigned int rates) |
afa8603c | 413 | { |
b226efe5 AJ |
414 | /* |
415 | * Read component parameter registers to extract | |
416 | * the I2S block's configuration. | |
417 | */ | |
418 | u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); | |
419 | u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); | |
0d274544 | 420 | u32 idx; |
afa8603c | 421 | |
b226efe5 | 422 | if (COMP1_TX_ENABLED(comp1)) { |
afa8603c | 423 | dev_dbg(dev->dev, " designware: play supported\n"); |
b226efe5 AJ |
424 | idx = COMP1_TX_WORDSIZE_0(comp1); |
425 | if (WARN_ON(idx >= ARRAY_SIZE(formats))) | |
426 | return -EINVAL; | |
afa8603c | 427 | dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; |
b226efe5 AJ |
428 | dw_i2s_dai->playback.channels_max = |
429 | 1 << (COMP1_TX_CHANNELS(comp1) + 1); | |
430 | dw_i2s_dai->playback.formats = formats[idx]; | |
0d274544 | 431 | dw_i2s_dai->playback.rates = rates; |
afa8603c AJ |
432 | } |
433 | ||
b226efe5 | 434 | if (COMP1_RX_ENABLED(comp1)) { |
afa8603c | 435 | dev_dbg(dev->dev, "designware: record supported\n"); |
b226efe5 AJ |
436 | idx = COMP2_RX_WORDSIZE_0(comp2); |
437 | if (WARN_ON(idx >= ARRAY_SIZE(formats))) | |
438 | return -EINVAL; | |
afa8603c | 439 | dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; |
b226efe5 AJ |
440 | dw_i2s_dai->capture.channels_max = |
441 | 1 << (COMP1_RX_CHANNELS(comp1) + 1); | |
442 | dw_i2s_dai->capture.formats = formats[idx]; | |
0d274544 AJ |
443 | dw_i2s_dai->capture.rates = rates; |
444 | } | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
449 | static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, | |
450 | struct snd_soc_dai_driver *dw_i2s_dai, | |
451 | struct resource *res, | |
452 | const struct i2s_platform_data *pdata) | |
453 | { | |
454 | u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); | |
455 | u32 idx = COMP1_APB_DATA_WIDTH(comp1); | |
456 | int ret; | |
457 | ||
458 | if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) | |
459 | return -EINVAL; | |
460 | ||
461 | ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); | |
462 | if (ret < 0) | |
463 | return ret; | |
464 | ||
465 | /* Set DMA slaves info */ | |
466 | dev->play_dma_data.pd.data = pdata->play_dma_data; | |
467 | dev->capture_dma_data.pd.data = pdata->capture_dma_data; | |
468 | dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; | |
469 | dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; | |
470 | dev->play_dma_data.pd.max_burst = 16; | |
471 | dev->capture_dma_data.pd.max_burst = 16; | |
472 | dev->play_dma_data.pd.addr_width = bus_widths[idx]; | |
473 | dev->capture_dma_data.pd.addr_width = bus_widths[idx]; | |
474 | dev->play_dma_data.pd.filter = pdata->filter; | |
475 | dev->capture_dma_data.pd.filter = pdata->filter; | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, | |
481 | struct snd_soc_dai_driver *dw_i2s_dai, | |
482 | struct resource *res) | |
483 | { | |
484 | u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); | |
485 | u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); | |
486 | u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); | |
487 | u32 idx = COMP1_APB_DATA_WIDTH(comp1); | |
488 | u32 idx2; | |
489 | int ret; | |
490 | ||
491 | if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) | |
492 | return -EINVAL; | |
493 | ||
494 | ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); | |
495 | if (ret < 0) | |
496 | return ret; | |
497 | ||
498 | if (COMP1_TX_ENABLED(comp1)) { | |
499 | idx2 = COMP1_TX_WORDSIZE_0(comp1); | |
500 | ||
501 | dev->capability |= DWC_I2S_PLAY; | |
502 | dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; | |
503 | dev->play_dma_data.dt.addr_width = bus_widths[idx]; | |
504 | dev->play_dma_data.dt.chan_name = "TX"; | |
505 | dev->play_dma_data.dt.fifo_size = fifo_depth * | |
506 | (fifo_width[idx2]) >> 8; | |
507 | dev->play_dma_data.dt.maxburst = 16; | |
508 | } | |
509 | if (COMP1_RX_ENABLED(comp1)) { | |
510 | idx2 = COMP2_RX_WORDSIZE_0(comp2); | |
511 | ||
512 | dev->capability |= DWC_I2S_RECORD; | |
513 | dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; | |
514 | dev->capture_dma_data.dt.addr_width = bus_widths[idx]; | |
515 | dev->capture_dma_data.dt.chan_name = "RX"; | |
516 | dev->capture_dma_data.dt.fifo_size = fifo_depth * | |
517 | (fifo_width[idx2] >> 8); | |
518 | dev->capture_dma_data.dt.maxburst = 16; | |
afa8603c | 519 | } |
b226efe5 AJ |
520 | |
521 | return 0; | |
0d274544 | 522 | |
afa8603c AJ |
523 | } |
524 | ||
3a9cf8ef RK |
525 | static int dw_i2s_probe(struct platform_device *pdev) |
526 | { | |
527 | const struct i2s_platform_data *pdata = pdev->dev.platform_data; | |
528 | struct dw_i2s_dev *dev; | |
529 | struct resource *res; | |
530 | int ret; | |
3a9cf8ef RK |
531 | struct snd_soc_dai_driver *dw_i2s_dai; |
532 | ||
3a9cf8ef RK |
533 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); |
534 | if (!dev) { | |
535 | dev_warn(&pdev->dev, "kzalloc fail\n"); | |
536 | return -ENOMEM; | |
537 | } | |
538 | ||
b163be4c | 539 | dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); |
be33465e | 540 | if (!dw_i2s_dai) |
3a9cf8ef | 541 | return -ENOMEM; |
3a9cf8ef | 542 | |
b163be4c AJ |
543 | dw_i2s_dai->ops = &dw_i2s_dai_ops; |
544 | dw_i2s_dai->suspend = dw_i2s_suspend; | |
545 | dw_i2s_dai->resume = dw_i2s_resume; | |
546 | ||
547 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b163be4c | 548 | dev->i2s_base = devm_ioremap_resource(&pdev->dev, res); |
be33465e | 549 | if (IS_ERR(dev->i2s_base)) |
b163be4c | 550 | return PTR_ERR(dev->i2s_base); |
b163be4c | 551 | |
afa8603c | 552 | dev->dev = &pdev->dev; |
0d274544 AJ |
553 | if (pdata) { |
554 | ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); | |
555 | if (ret < 0) | |
556 | return ret; | |
557 | ||
558 | dev->capability = pdata->cap; | |
559 | dev->i2s_clk_cfg = pdata->i2s_clk_cfg; | |
560 | if (!dev->i2s_clk_cfg) { | |
561 | dev_err(&pdev->dev, "no clock configure method\n"); | |
562 | return -ENODEV; | |
563 | } | |
3a9cf8ef | 564 | |
0d274544 AJ |
565 | dev->clk = devm_clk_get(&pdev->dev, NULL); |
566 | } else { | |
567 | ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); | |
568 | if (ret < 0) | |
569 | return ret; | |
3a9cf8ef | 570 | |
0d274544 AJ |
571 | dev->clk = devm_clk_get(&pdev->dev, "i2sclk"); |
572 | } | |
3a9cf8ef | 573 | if (IS_ERR(dev->clk)) |
0d274544 | 574 | return PTR_ERR(dev->clk); |
3a9cf8ef | 575 | |
3a19272a | 576 | ret = clk_prepare_enable(dev->clk); |
3a9cf8ef | 577 | if (ret < 0) |
a56257c6 | 578 | return ret; |
3a9cf8ef | 579 | |
3a9cf8ef | 580 | dev_set_drvdata(&pdev->dev, dev); |
758c2deb | 581 | ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, |
92eaa328 | 582 | dw_i2s_dai, 1); |
3a9cf8ef RK |
583 | if (ret != 0) { |
584 | dev_err(&pdev->dev, "not able to register dai\n"); | |
e925a6b1 | 585 | goto err_clk_disable; |
3a9cf8ef RK |
586 | } |
587 | ||
0d274544 AJ |
588 | if (!pdata) { |
589 | ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); | |
590 | if (ret) { | |
591 | dev_err(&pdev->dev, | |
592 | "Could not register PCM: %d\n", ret); | |
593 | goto err_clk_disable; | |
594 | } | |
595 | } | |
596 | ||
3a9cf8ef RK |
597 | return 0; |
598 | ||
3a9cf8ef | 599 | err_clk_disable: |
3a19272a | 600 | clk_disable_unprepare(dev->clk); |
3a9cf8ef RK |
601 | return ret; |
602 | } | |
603 | ||
604 | static int dw_i2s_remove(struct platform_device *pdev) | |
605 | { | |
606 | struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); | |
607 | ||
3a19272a | 608 | clk_disable_unprepare(dev->clk); |
3a9cf8ef RK |
609 | |
610 | return 0; | |
611 | } | |
612 | ||
0d274544 AJ |
613 | #ifdef CONFIG_OF |
614 | static const struct of_device_id dw_i2s_of_match[] = { | |
615 | { .compatible = "snps,designware-i2s", }, | |
616 | {}, | |
617 | }; | |
618 | ||
619 | MODULE_DEVICE_TABLE(of, dw_i2s_of_match); | |
620 | #endif | |
621 | ||
3a9cf8ef RK |
622 | static struct platform_driver dw_i2s_driver = { |
623 | .probe = dw_i2s_probe, | |
624 | .remove = dw_i2s_remove, | |
625 | .driver = { | |
626 | .name = "designware-i2s", | |
0d274544 | 627 | .of_match_table = of_match_ptr(dw_i2s_of_match), |
3a9cf8ef RK |
628 | }, |
629 | }; | |
630 | ||
631 | module_platform_driver(dw_i2s_driver); | |
632 | ||
b794dbcd | 633 | MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>"); |
3a9cf8ef RK |
634 | MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface"); |
635 | MODULE_LICENSE("GPL"); | |
636 | MODULE_ALIAS("platform:designware_i2s"); |