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Commit | Line | Data |
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3a9cf8ef RK |
1 | /* |
2 | * ALSA SoC Synopsys I2S Audio Layer | |
3 | * | |
22a4adf2 | 4 | * sound/soc/dwc/designware_i2s.c |
3a9cf8ef RK |
5 | * |
6 | * Copyright (C) 2010 ST Microelectronics | |
9a302c32 | 7 | * Rajeev Kumar <rajeevkumar.linux@gmail.com> |
3a9cf8ef RK |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/slab.h> | |
f4830312 | 21 | #include <linux/pm_runtime.h> |
3a9cf8ef RK |
22 | #include <sound/designware_i2s.h> |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
0d274544 | 26 | #include <sound/dmaengine_pcm.h> |
79361b2b | 27 | #include "local.h" |
3a9cf8ef | 28 | |
6b4a21b6 | 29 | static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) |
3a9cf8ef RK |
30 | { |
31 | writel(val, io_base + reg); | |
32 | } | |
33 | ||
6b4a21b6 | 34 | static inline u32 i2s_read_reg(void __iomem *io_base, int reg) |
3a9cf8ef RK |
35 | { |
36 | return readl(io_base + reg); | |
37 | } | |
38 | ||
39 | static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) | |
40 | { | |
41 | u32 i = 0; | |
42 | ||
43 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
44 | for (i = 0; i < 4; i++) | |
45 | i2s_write_reg(dev->i2s_base, TER(i), 0); | |
46 | } else { | |
47 | for (i = 0; i < 4; i++) | |
48 | i2s_write_reg(dev->i2s_base, RER(i), 0); | |
49 | } | |
50 | } | |
51 | ||
52 | static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) | |
53 | { | |
54 | u32 i = 0; | |
55 | ||
56 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
57 | for (i = 0; i < 4; i++) | |
4873867e | 58 | i2s_read_reg(dev->i2s_base, TOR(i)); |
3a9cf8ef RK |
59 | } else { |
60 | for (i = 0; i < 4; i++) | |
4873867e | 61 | i2s_read_reg(dev->i2s_base, ROR(i)); |
3a9cf8ef RK |
62 | } |
63 | } | |
64 | ||
b1d32feb JA |
65 | static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream, |
66 | int chan_nr) | |
3a9cf8ef | 67 | { |
924eb475 | 68 | u32 i, irq; |
3a9cf8ef | 69 | |
b1d32feb JA |
70 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
71 | for (i = 0; i < (chan_nr / 2); i++) { | |
72 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); | |
73 | i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); | |
74 | } | |
75 | } else { | |
76 | for (i = 0; i < (chan_nr / 2); i++) { | |
77 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); | |
78 | i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); | |
79 | } | |
80 | } | |
81 | } | |
82 | ||
83 | static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, | |
84 | int chan_nr) | |
85 | { | |
86 | u32 i, irq; | |
87 | ||
88 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
89 | for (i = 0; i < (chan_nr / 2); i++) { | |
924eb475 | 90 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); |
91 | i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); | |
92 | } | |
924eb475 | 93 | } else { |
b1d32feb | 94 | for (i = 0; i < (chan_nr / 2); i++) { |
924eb475 | 95 | irq = i2s_read_reg(dev->i2s_base, IMR(i)); |
96 | i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); | |
97 | } | |
924eb475 | 98 | } |
b1d32feb JA |
99 | } |
100 | ||
79361b2b JA |
101 | static irqreturn_t i2s_irq_handler(int irq, void *dev_id) |
102 | { | |
103 | struct dw_i2s_dev *dev = dev_id; | |
104 | bool irq_valid = false; | |
105 | u32 isr[4]; | |
106 | int i; | |
107 | ||
108 | for (i = 0; i < 4; i++) | |
109 | isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); | |
110 | ||
111 | i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK); | |
112 | i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE); | |
113 | ||
114 | for (i = 0; i < 4; i++) { | |
115 | /* | |
116 | * Check if TX fifo is empty. If empty fill FIFO with samples | |
117 | * NOTE: Only two channels supported | |
118 | */ | |
119 | if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { | |
120 | dw_pcm_push_tx(dev); | |
121 | irq_valid = true; | |
122 | } | |
123 | ||
124 | /* Data available. Record mode not supported in PIO mode */ | |
125 | if (isr[i] & ISR_RXDA) | |
126 | irq_valid = true; | |
127 | ||
128 | /* Error Handling: TX */ | |
129 | if (isr[i] & ISR_TXFO) { | |
130 | dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i); | |
131 | irq_valid = true; | |
132 | } | |
133 | ||
134 | /* Error Handling: TX */ | |
135 | if (isr[i] & ISR_RXFO) { | |
136 | dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i); | |
137 | irq_valid = true; | |
138 | } | |
139 | } | |
140 | ||
141 | if (irq_valid) | |
142 | return IRQ_HANDLED; | |
143 | else | |
144 | return IRQ_NONE; | |
145 | } | |
146 | ||
b1d32feb JA |
147 | static void i2s_start(struct dw_i2s_dev *dev, |
148 | struct snd_pcm_substream *substream) | |
149 | { | |
150 | struct i2s_clk_config_data *config = &dev->config; | |
151 | ||
152 | i2s_write_reg(dev->i2s_base, IER, 1); | |
153 | i2s_enable_irqs(dev, substream->stream, config->chan_nr); | |
154 | ||
155 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
156 | i2s_write_reg(dev->i2s_base, ITER, 1); | |
157 | else | |
158 | i2s_write_reg(dev->i2s_base, IRER, 1); | |
3a9cf8ef RK |
159 | |
160 | i2s_write_reg(dev->i2s_base, CER, 1); | |
161 | } | |
162 | ||
163 | static void i2s_stop(struct dw_i2s_dev *dev, | |
164 | struct snd_pcm_substream *substream) | |
165 | { | |
3a9cf8ef RK |
166 | |
167 | i2s_clear_irqs(dev, substream->stream); | |
b1d32feb | 168 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
3a9cf8ef | 169 | i2s_write_reg(dev->i2s_base, ITER, 0); |
b1d32feb | 170 | else |
3a9cf8ef RK |
171 | i2s_write_reg(dev->i2s_base, IRER, 0); |
172 | ||
b1d32feb | 173 | i2s_disable_irqs(dev, substream->stream, 8); |
3a9cf8ef RK |
174 | |
175 | if (!dev->active) { | |
176 | i2s_write_reg(dev->i2s_base, CER, 0); | |
177 | i2s_write_reg(dev->i2s_base, IER, 0); | |
178 | } | |
179 | } | |
180 | ||
181 | static int dw_i2s_startup(struct snd_pcm_substream *substream, | |
182 | struct snd_soc_dai *cpu_dai) | |
183 | { | |
184 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); | |
0d274544 | 185 | union dw_i2s_snd_dma_data *dma_data = NULL; |
3a9cf8ef RK |
186 | |
187 | if (!(dev->capability & DWC_I2S_RECORD) && | |
188 | (substream->stream == SNDRV_PCM_STREAM_CAPTURE)) | |
189 | return -EINVAL; | |
190 | ||
191 | if (!(dev->capability & DWC_I2S_PLAY) && | |
192 | (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) | |
193 | return -EINVAL; | |
194 | ||
195 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
196 | dma_data = &dev->play_dma_data; | |
197 | else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
198 | dma_data = &dev->capture_dma_data; | |
199 | ||
200 | snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data); | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
0032e9db MSB |
205 | static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) |
206 | { | |
b1d32feb | 207 | u32 ch_reg; |
0032e9db MSB |
208 | struct i2s_clk_config_data *config = &dev->config; |
209 | ||
210 | ||
211 | i2s_disable_channels(dev, stream); | |
212 | ||
213 | for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { | |
214 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
215 | i2s_write_reg(dev->i2s_base, TCR(ch_reg), | |
216 | dev->xfer_resolution); | |
3fafd14d JA |
217 | i2s_write_reg(dev->i2s_base, TFCR(ch_reg), |
218 | dev->fifo_th - 1); | |
0032e9db MSB |
219 | i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); |
220 | } else { | |
221 | i2s_write_reg(dev->i2s_base, RCR(ch_reg), | |
222 | dev->xfer_resolution); | |
3fafd14d JA |
223 | i2s_write_reg(dev->i2s_base, RFCR(ch_reg), |
224 | dev->fifo_th - 1); | |
0032e9db MSB |
225 | i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); |
226 | } | |
227 | ||
228 | } | |
229 | } | |
230 | ||
3a9cf8ef RK |
231 | static int dw_i2s_hw_params(struct snd_pcm_substream *substream, |
232 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
233 | { | |
234 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
235 | struct i2s_clk_config_data *config = &dev->config; | |
3a9cf8ef RK |
236 | int ret; |
237 | ||
238 | switch (params_format(params)) { | |
239 | case SNDRV_PCM_FORMAT_S16_LE: | |
240 | config->data_width = 16; | |
0032e9db MSB |
241 | dev->ccr = 0x00; |
242 | dev->xfer_resolution = 0x02; | |
3a9cf8ef RK |
243 | break; |
244 | ||
245 | case SNDRV_PCM_FORMAT_S24_LE: | |
246 | config->data_width = 24; | |
0032e9db MSB |
247 | dev->ccr = 0x08; |
248 | dev->xfer_resolution = 0x04; | |
3a9cf8ef RK |
249 | break; |
250 | ||
251 | case SNDRV_PCM_FORMAT_S32_LE: | |
252 | config->data_width = 32; | |
0032e9db MSB |
253 | dev->ccr = 0x10; |
254 | dev->xfer_resolution = 0x05; | |
3a9cf8ef RK |
255 | break; |
256 | ||
257 | default: | |
57072ae1 | 258 | dev_err(dev->dev, "designware-i2s: unsupported PCM fmt"); |
3a9cf8ef RK |
259 | return -EINVAL; |
260 | } | |
261 | ||
262 | config->chan_nr = params_channels(params); | |
263 | ||
264 | switch (config->chan_nr) { | |
265 | case EIGHT_CHANNEL_SUPPORT: | |
3a9cf8ef | 266 | case SIX_CHANNEL_SUPPORT: |
3a9cf8ef | 267 | case FOUR_CHANNEL_SUPPORT: |
3a9cf8ef | 268 | case TWO_CHANNEL_SUPPORT: |
3a9cf8ef RK |
269 | break; |
270 | default: | |
271 | dev_err(dev->dev, "channel not supported\n"); | |
0099d24c | 272 | return -EINVAL; |
3a9cf8ef RK |
273 | } |
274 | ||
0032e9db | 275 | dw_i2s_config(dev, substream->stream); |
3a9cf8ef | 276 | |
0032e9db | 277 | i2s_write_reg(dev->i2s_base, CCR, dev->ccr); |
3a9cf8ef RK |
278 | |
279 | config->sample_rate = params_rate(params); | |
280 | ||
1d957d86 MSB |
281 | if (dev->capability & DW_I2S_MASTER) { |
282 | if (dev->i2s_clk_cfg) { | |
283 | ret = dev->i2s_clk_cfg(config); | |
284 | if (ret < 0) { | |
285 | dev_err(dev->dev, "runtime audio clk config fail\n"); | |
286 | return ret; | |
287 | } | |
288 | } else { | |
289 | u32 bitclk = config->sample_rate * | |
290 | config->data_width * 2; | |
291 | ||
292 | ret = clk_set_rate(dev->clk, bitclk); | |
293 | if (ret) { | |
294 | dev_err(dev->dev, "Can't set I2S clock rate: %d\n", | |
295 | ret); | |
296 | return ret; | |
297 | } | |
0d274544 | 298 | } |
3a9cf8ef | 299 | } |
3a9cf8ef RK |
300 | return 0; |
301 | } | |
302 | ||
303 | static void dw_i2s_shutdown(struct snd_pcm_substream *substream, | |
304 | struct snd_soc_dai *dai) | |
305 | { | |
306 | snd_soc_dai_set_dma_data(dai, substream, NULL); | |
307 | } | |
308 | ||
3475c3d0 AJ |
309 | static int dw_i2s_prepare(struct snd_pcm_substream *substream, |
310 | struct snd_soc_dai *dai) | |
311 | { | |
312 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
313 | ||
314 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
315 | i2s_write_reg(dev->i2s_base, TXFFR, 1); | |
316 | else | |
317 | i2s_write_reg(dev->i2s_base, RXFFR, 1); | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
3a9cf8ef RK |
322 | static int dw_i2s_trigger(struct snd_pcm_substream *substream, |
323 | int cmd, struct snd_soc_dai *dai) | |
324 | { | |
325 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
326 | int ret = 0; | |
327 | ||
328 | switch (cmd) { | |
329 | case SNDRV_PCM_TRIGGER_START: | |
330 | case SNDRV_PCM_TRIGGER_RESUME: | |
331 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
332 | dev->active++; | |
333 | i2s_start(dev, substream); | |
334 | break; | |
335 | ||
336 | case SNDRV_PCM_TRIGGER_STOP: | |
337 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
338 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
339 | dev->active--; | |
340 | i2s_stop(dev, substream); | |
341 | break; | |
342 | default: | |
343 | ret = -EINVAL; | |
344 | break; | |
345 | } | |
346 | return ret; | |
347 | } | |
348 | ||
ab57b8e9 MSB |
349 | static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) |
350 | { | |
351 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); | |
352 | int ret = 0; | |
353 | ||
354 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
355 | case SND_SOC_DAIFMT_CBM_CFM: | |
356 | if (dev->capability & DW_I2S_SLAVE) | |
357 | ret = 0; | |
358 | else | |
359 | ret = -EINVAL; | |
360 | break; | |
361 | case SND_SOC_DAIFMT_CBS_CFS: | |
362 | if (dev->capability & DW_I2S_MASTER) | |
363 | ret = 0; | |
364 | else | |
365 | ret = -EINVAL; | |
366 | break; | |
367 | case SND_SOC_DAIFMT_CBM_CFS: | |
368 | case SND_SOC_DAIFMT_CBS_CFM: | |
369 | ret = -EINVAL; | |
370 | break; | |
371 | default: | |
372 | dev_dbg(dev->dev, "dwc : Invalid master/slave format\n"); | |
373 | ret = -EINVAL; | |
374 | break; | |
375 | } | |
376 | return ret; | |
377 | } | |
378 | ||
3a9cf8ef RK |
379 | static struct snd_soc_dai_ops dw_i2s_dai_ops = { |
380 | .startup = dw_i2s_startup, | |
381 | .shutdown = dw_i2s_shutdown, | |
382 | .hw_params = dw_i2s_hw_params, | |
3475c3d0 | 383 | .prepare = dw_i2s_prepare, |
3a9cf8ef | 384 | .trigger = dw_i2s_trigger, |
ab57b8e9 | 385 | .set_fmt = dw_i2s_set_fmt, |
3a9cf8ef RK |
386 | }; |
387 | ||
92eaa328 KM |
388 | static const struct snd_soc_component_driver dw_i2s_component = { |
389 | .name = "dw-i2s", | |
390 | }; | |
391 | ||
3a9cf8ef | 392 | #ifdef CONFIG_PM |
f4830312 MSB |
393 | static int dw_i2s_runtime_suspend(struct device *dev) |
394 | { | |
395 | struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); | |
396 | ||
397 | if (dw_dev->capability & DW_I2S_MASTER) | |
398 | clk_disable(dw_dev->clk); | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static int dw_i2s_runtime_resume(struct device *dev) | |
403 | { | |
404 | struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); | |
405 | ||
406 | if (dw_dev->capability & DW_I2S_MASTER) | |
407 | clk_enable(dw_dev->clk); | |
408 | return 0; | |
409 | } | |
3a9cf8ef RK |
410 | |
411 | static int dw_i2s_suspend(struct snd_soc_dai *dai) | |
412 | { | |
413 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
414 | ||
1d957d86 MSB |
415 | if (dev->capability & DW_I2S_MASTER) |
416 | clk_disable(dev->clk); | |
3a9cf8ef RK |
417 | return 0; |
418 | } | |
419 | ||
420 | static int dw_i2s_resume(struct snd_soc_dai *dai) | |
421 | { | |
422 | struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
423 | ||
1d957d86 MSB |
424 | if (dev->capability & DW_I2S_MASTER) |
425 | clk_enable(dev->clk); | |
0032e9db MSB |
426 | |
427 | if (dai->playback_active) | |
428 | dw_i2s_config(dev, SNDRV_PCM_STREAM_PLAYBACK); | |
429 | if (dai->capture_active) | |
430 | dw_i2s_config(dev, SNDRV_PCM_STREAM_CAPTURE); | |
3a9cf8ef RK |
431 | return 0; |
432 | } | |
433 | ||
434 | #else | |
435 | #define dw_i2s_suspend NULL | |
436 | #define dw_i2s_resume NULL | |
437 | #endif | |
438 | ||
b226efe5 AJ |
439 | /* |
440 | * The following tables allow a direct lookup of various parameters | |
441 | * defined in the I2S block's configuration in terms of sound system | |
442 | * parameters. Each table is sized to the number of entries possible | |
443 | * according to the number of configuration bits describing an I2S | |
444 | * block parameter. | |
445 | */ | |
446 | ||
0d274544 AJ |
447 | /* Maximum bit resolution of a channel - not uniformly spaced */ |
448 | static const u32 fifo_width[COMP_MAX_WORDSIZE] = { | |
449 | 12, 16, 20, 24, 32, 0, 0, 0 | |
450 | }; | |
451 | ||
b226efe5 AJ |
452 | /* Width of (DMA) bus */ |
453 | static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = { | |
454 | DMA_SLAVE_BUSWIDTH_1_BYTE, | |
455 | DMA_SLAVE_BUSWIDTH_2_BYTES, | |
456 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
457 | DMA_SLAVE_BUSWIDTH_UNDEFINED | |
458 | }; | |
459 | ||
460 | /* PCM format to support channel resolution */ | |
461 | static const u32 formats[COMP_MAX_WORDSIZE] = { | |
462 | SNDRV_PCM_FMTBIT_S16_LE, | |
463 | SNDRV_PCM_FMTBIT_S16_LE, | |
464 | SNDRV_PCM_FMTBIT_S24_LE, | |
465 | SNDRV_PCM_FMTBIT_S24_LE, | |
466 | SNDRV_PCM_FMTBIT_S32_LE, | |
467 | 0, | |
468 | 0, | |
469 | 0 | |
470 | }; | |
471 | ||
0d274544 | 472 | static int dw_configure_dai(struct dw_i2s_dev *dev, |
afa8603c | 473 | struct snd_soc_dai_driver *dw_i2s_dai, |
0d274544 | 474 | unsigned int rates) |
afa8603c | 475 | { |
b226efe5 AJ |
476 | /* |
477 | * Read component parameter registers to extract | |
478 | * the I2S block's configuration. | |
479 | */ | |
e164835a MSB |
480 | u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); |
481 | u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); | |
3fafd14d | 482 | u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); |
0d274544 | 483 | u32 idx; |
afa8603c | 484 | |
a242cac1 MSB |
485 | if (dev->capability & DWC_I2S_RECORD && |
486 | dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) | |
487 | comp1 = comp1 & ~BIT(5); | |
488 | ||
b226efe5 | 489 | if (COMP1_TX_ENABLED(comp1)) { |
afa8603c | 490 | dev_dbg(dev->dev, " designware: play supported\n"); |
b226efe5 AJ |
491 | idx = COMP1_TX_WORDSIZE_0(comp1); |
492 | if (WARN_ON(idx >= ARRAY_SIZE(formats))) | |
493 | return -EINVAL; | |
afa8603c | 494 | dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; |
b226efe5 AJ |
495 | dw_i2s_dai->playback.channels_max = |
496 | 1 << (COMP1_TX_CHANNELS(comp1) + 1); | |
497 | dw_i2s_dai->playback.formats = formats[idx]; | |
0d274544 | 498 | dw_i2s_dai->playback.rates = rates; |
afa8603c AJ |
499 | } |
500 | ||
b226efe5 | 501 | if (COMP1_RX_ENABLED(comp1)) { |
afa8603c | 502 | dev_dbg(dev->dev, "designware: record supported\n"); |
b226efe5 AJ |
503 | idx = COMP2_RX_WORDSIZE_0(comp2); |
504 | if (WARN_ON(idx >= ARRAY_SIZE(formats))) | |
505 | return -EINVAL; | |
afa8603c | 506 | dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; |
b226efe5 AJ |
507 | dw_i2s_dai->capture.channels_max = |
508 | 1 << (COMP1_RX_CHANNELS(comp1) + 1); | |
509 | dw_i2s_dai->capture.formats = formats[idx]; | |
0d274544 AJ |
510 | dw_i2s_dai->capture.rates = rates; |
511 | } | |
512 | ||
1d957d86 MSB |
513 | if (COMP1_MODE_EN(comp1)) { |
514 | dev_dbg(dev->dev, "designware: i2s master mode supported\n"); | |
515 | dev->capability |= DW_I2S_MASTER; | |
516 | } else { | |
517 | dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); | |
518 | dev->capability |= DW_I2S_SLAVE; | |
519 | } | |
520 | ||
3fafd14d | 521 | dev->fifo_th = fifo_depth / 2; |
0d274544 AJ |
522 | return 0; |
523 | } | |
524 | ||
525 | static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, | |
526 | struct snd_soc_dai_driver *dw_i2s_dai, | |
527 | struct resource *res, | |
528 | const struct i2s_platform_data *pdata) | |
529 | { | |
e164835a | 530 | u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); |
0d274544 AJ |
531 | u32 idx = COMP1_APB_DATA_WIDTH(comp1); |
532 | int ret; | |
533 | ||
534 | if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) | |
535 | return -EINVAL; | |
536 | ||
537 | ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); | |
538 | if (ret < 0) | |
539 | return ret; | |
540 | ||
541 | /* Set DMA slaves info */ | |
542 | dev->play_dma_data.pd.data = pdata->play_dma_data; | |
543 | dev->capture_dma_data.pd.data = pdata->capture_dma_data; | |
544 | dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; | |
545 | dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; | |
546 | dev->play_dma_data.pd.max_burst = 16; | |
547 | dev->capture_dma_data.pd.max_burst = 16; | |
548 | dev->play_dma_data.pd.addr_width = bus_widths[idx]; | |
549 | dev->capture_dma_data.pd.addr_width = bus_widths[idx]; | |
550 | dev->play_dma_data.pd.filter = pdata->filter; | |
551 | dev->capture_dma_data.pd.filter = pdata->filter; | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, | |
557 | struct snd_soc_dai_driver *dw_i2s_dai, | |
558 | struct resource *res) | |
559 | { | |
560 | u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); | |
561 | u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); | |
562 | u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); | |
563 | u32 idx = COMP1_APB_DATA_WIDTH(comp1); | |
564 | u32 idx2; | |
565 | int ret; | |
566 | ||
567 | if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) | |
568 | return -EINVAL; | |
569 | ||
570 | ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); | |
571 | if (ret < 0) | |
572 | return ret; | |
573 | ||
574 | if (COMP1_TX_ENABLED(comp1)) { | |
575 | idx2 = COMP1_TX_WORDSIZE_0(comp1); | |
576 | ||
577 | dev->capability |= DWC_I2S_PLAY; | |
578 | dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; | |
579 | dev->play_dma_data.dt.addr_width = bus_widths[idx]; | |
0d274544 AJ |
580 | dev->play_dma_data.dt.fifo_size = fifo_depth * |
581 | (fifo_width[idx2]) >> 8; | |
582 | dev->play_dma_data.dt.maxburst = 16; | |
583 | } | |
584 | if (COMP1_RX_ENABLED(comp1)) { | |
585 | idx2 = COMP2_RX_WORDSIZE_0(comp2); | |
586 | ||
587 | dev->capability |= DWC_I2S_RECORD; | |
588 | dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; | |
589 | dev->capture_dma_data.dt.addr_width = bus_widths[idx]; | |
0d274544 AJ |
590 | dev->capture_dma_data.dt.fifo_size = fifo_depth * |
591 | (fifo_width[idx2] >> 8); | |
592 | dev->capture_dma_data.dt.maxburst = 16; | |
afa8603c | 593 | } |
b226efe5 AJ |
594 | |
595 | return 0; | |
0d274544 | 596 | |
afa8603c AJ |
597 | } |
598 | ||
3a9cf8ef RK |
599 | static int dw_i2s_probe(struct platform_device *pdev) |
600 | { | |
601 | const struct i2s_platform_data *pdata = pdev->dev.platform_data; | |
602 | struct dw_i2s_dev *dev; | |
603 | struct resource *res; | |
79361b2b | 604 | int ret, irq; |
3a9cf8ef | 605 | struct snd_soc_dai_driver *dw_i2s_dai; |
1d957d86 | 606 | const char *clk_id; |
3a9cf8ef | 607 | |
3a9cf8ef RK |
608 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); |
609 | if (!dev) { | |
610 | dev_warn(&pdev->dev, "kzalloc fail\n"); | |
611 | return -ENOMEM; | |
612 | } | |
613 | ||
b163be4c | 614 | dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); |
be33465e | 615 | if (!dw_i2s_dai) |
3a9cf8ef | 616 | return -ENOMEM; |
3a9cf8ef | 617 | |
b163be4c AJ |
618 | dw_i2s_dai->ops = &dw_i2s_dai_ops; |
619 | dw_i2s_dai->suspend = dw_i2s_suspend; | |
620 | dw_i2s_dai->resume = dw_i2s_resume; | |
621 | ||
622 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b163be4c | 623 | dev->i2s_base = devm_ioremap_resource(&pdev->dev, res); |
be33465e | 624 | if (IS_ERR(dev->i2s_base)) |
b163be4c | 625 | return PTR_ERR(dev->i2s_base); |
b163be4c | 626 | |
afa8603c | 627 | dev->dev = &pdev->dev; |
1d957d86 | 628 | |
79361b2b JA |
629 | irq = platform_get_irq(pdev, 0); |
630 | if (irq >= 0) { | |
631 | ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, | |
632 | pdev->name, dev); | |
633 | if (ret < 0) { | |
634 | dev_err(&pdev->dev, "failed to request irq\n"); | |
635 | return ret; | |
636 | } | |
637 | } | |
638 | ||
d2f916aa JMT |
639 | dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; |
640 | dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; | |
0d274544 | 641 | if (pdata) { |
1d957d86 MSB |
642 | dev->capability = pdata->cap; |
643 | clk_id = NULL; | |
e164835a MSB |
644 | dev->quirks = pdata->quirks; |
645 | if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { | |
646 | dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; | |
647 | dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; | |
e164835a | 648 | } |
0d274544 | 649 | ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); |
1d957d86 MSB |
650 | } else { |
651 | clk_id = "i2sclk"; | |
652 | ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); | |
653 | } | |
654 | if (ret < 0) | |
655 | return ret; | |
0d274544 | 656 | |
1d957d86 MSB |
657 | if (dev->capability & DW_I2S_MASTER) { |
658 | if (pdata) { | |
659 | dev->i2s_clk_cfg = pdata->i2s_clk_cfg; | |
660 | if (!dev->i2s_clk_cfg) { | |
661 | dev_err(&pdev->dev, "no clock configure method\n"); | |
662 | return -ENODEV; | |
663 | } | |
0d274544 | 664 | } |
1d957d86 | 665 | dev->clk = devm_clk_get(&pdev->dev, clk_id); |
3a9cf8ef | 666 | |
1d957d86 MSB |
667 | if (IS_ERR(dev->clk)) |
668 | return PTR_ERR(dev->clk); | |
669 | ||
670 | ret = clk_prepare_enable(dev->clk); | |
0d274544 AJ |
671 | if (ret < 0) |
672 | return ret; | |
0d274544 | 673 | } |
3a9cf8ef | 674 | |
3a9cf8ef | 675 | dev_set_drvdata(&pdev->dev, dev); |
758c2deb | 676 | ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, |
92eaa328 | 677 | dw_i2s_dai, 1); |
3a9cf8ef RK |
678 | if (ret != 0) { |
679 | dev_err(&pdev->dev, "not able to register dai\n"); | |
e925a6b1 | 680 | goto err_clk_disable; |
3a9cf8ef RK |
681 | } |
682 | ||
0d274544 | 683 | if (!pdata) { |
6fce983f | 684 | if (irq >= 0) { |
79361b2b | 685 | ret = dw_pcm_register(pdev); |
6fce983f JA |
686 | dev->use_pio = true; |
687 | } else { | |
688 | ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, | |
689 | 0); | |
690 | dev->use_pio = false; | |
691 | } | |
692 | ||
693 | if (ret) { | |
694 | dev_err(&pdev->dev, "could not register pcm: %d\n", | |
79361b2b | 695 | ret); |
6fce983f | 696 | goto err_clk_disable; |
0d274544 AJ |
697 | } |
698 | } | |
79361b2b | 699 | |
f4830312 | 700 | pm_runtime_enable(&pdev->dev); |
3a9cf8ef RK |
701 | return 0; |
702 | ||
3a9cf8ef | 703 | err_clk_disable: |
1d957d86 MSB |
704 | if (dev->capability & DW_I2S_MASTER) |
705 | clk_disable_unprepare(dev->clk); | |
3a9cf8ef RK |
706 | return ret; |
707 | } | |
708 | ||
709 | static int dw_i2s_remove(struct platform_device *pdev) | |
710 | { | |
711 | struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); | |
712 | ||
1d957d86 MSB |
713 | if (dev->capability & DW_I2S_MASTER) |
714 | clk_disable_unprepare(dev->clk); | |
3a9cf8ef | 715 | |
f4830312 | 716 | pm_runtime_disable(&pdev->dev); |
3a9cf8ef RK |
717 | return 0; |
718 | } | |
719 | ||
0d274544 AJ |
720 | #ifdef CONFIG_OF |
721 | static const struct of_device_id dw_i2s_of_match[] = { | |
722 | { .compatible = "snps,designware-i2s", }, | |
723 | {}, | |
724 | }; | |
725 | ||
726 | MODULE_DEVICE_TABLE(of, dw_i2s_of_match); | |
727 | #endif | |
728 | ||
f4830312 MSB |
729 | static const struct dev_pm_ops dwc_pm_ops = { |
730 | SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL) | |
731 | }; | |
732 | ||
3a9cf8ef RK |
733 | static struct platform_driver dw_i2s_driver = { |
734 | .probe = dw_i2s_probe, | |
735 | .remove = dw_i2s_remove, | |
736 | .driver = { | |
737 | .name = "designware-i2s", | |
0d274544 | 738 | .of_match_table = of_match_ptr(dw_i2s_of_match), |
f4830312 | 739 | .pm = &dwc_pm_ops, |
3a9cf8ef RK |
740 | }, |
741 | }; | |
742 | ||
743 | module_platform_driver(dw_i2s_driver); | |
744 | ||
b794dbcd | 745 | MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>"); |
3a9cf8ef RK |
746 | MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface"); |
747 | MODULE_LICENSE("GPL"); | |
748 | MODULE_ALIAS("platform:designware_i2s"); |