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ASoC: dwc: Added a quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to dwc driver
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / dwc / dwc-i2s.c
CommitLineData
3a9cf8ef
RK		 1/*
2 * ALSA SoC Synopsys I2S Audio Layer
3 *
22a4adf2 4 * sound/soc/dwc/designware_i2s.c
3a9cf8ef
RK		 5 *
6 * Copyright (C) 2010 ST Microelectronics
9a302c32 7 * Rajeev Kumar <rajeevkumar.linux@gmail.com>
3a9cf8ef
RK		 8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/device.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/slab.h>
f4830312 21#include <linux/pm_runtime.h>
3a9cf8ef
RK		 22#include <sound/designware_i2s.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
0d274544 26#include <sound/dmaengine_pcm.h>
79361b2b 27#include "local.h"
3a9cf8ef 28
6b4a21b6 29static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
3a9cf8ef
RK		 30{
31 writel(val, io_base + reg);
32}
33
6b4a21b6 34static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
3a9cf8ef
RK		 35{
36 return readl(io_base + reg);
37}
38
39static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
40{
41 u32 i = 0;
42
43 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
44 for (i = 0; i < 4; i++)
45 i2s_write_reg(dev->i2s_base, TER(i), 0);
46 } else {
47 for (i = 0; i < 4; i++)
48 i2s_write_reg(dev->i2s_base, RER(i), 0);
49 }
50}
51
52static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
53{
54 u32 i = 0;
55
56 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
57 for (i = 0; i < 4; i++)
4873867e 58 i2s_read_reg(dev->i2s_base, TOR(i));
3a9cf8ef
RK		 59 } else {
60 for (i = 0; i < 4; i++)
4873867e 61 i2s_read_reg(dev->i2s_base, ROR(i));
3a9cf8ef
RK		 62 }
63}
64
b1d32feb
JA		 65static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
66 int chan_nr)
3a9cf8ef 67{
924eb475 68 u32 i, irq;
3a9cf8ef 69
b1d32feb
JA		 70 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
71 for (i = 0; i < (chan_nr / 2); i++) {
72 irq = i2s_read_reg(dev->i2s_base, IMR(i));
73 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
74 }
75 } else {
76 for (i = 0; i < (chan_nr / 2); i++) {
77 irq = i2s_read_reg(dev->i2s_base, IMR(i));
78 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
79 }
80 }
81}
82
83static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
84 int chan_nr)
85{
86 u32 i, irq;
87
88 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
89 for (i = 0; i < (chan_nr / 2); i++) {
924eb475 90 irq = i2s_read_reg(dev->i2s_base, IMR(i));
91 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
92 }
924eb475 93 } else {
b1d32feb 94 for (i = 0; i < (chan_nr / 2); i++) {
924eb475 95 irq = i2s_read_reg(dev->i2s_base, IMR(i));
96 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
97 }
924eb475 98 }
b1d32feb
JA		 99}
100
79361b2b
JA		 101static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
102{
103 struct dw_i2s_dev *dev = dev_id;
104 bool irq_valid = false;
105 u32 isr[4];
106 int i;
107
108 for (i = 0; i < 4; i++)
109 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
110
111 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
112 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
113
114 for (i = 0; i < 4; i++) {
115 /*
116 * Check if TX fifo is empty. If empty fill FIFO with samples
117 * NOTE: Only two channels supported
118 */
119 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
120 dw_pcm_push_tx(dev);
121 irq_valid = true;
122 }
123
e2f748e0
JA		 124 /*
125 * Data available. Retrieve samples from FIFO
126 * NOTE: Only two channels supported
127 */
128 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
129 dw_pcm_pop_rx(dev);
79361b2b 130 irq_valid = true;
e2f748e0 131 }
79361b2b
JA		 132
133 /* Error Handling: TX */
134 if (isr[i] & ISR_TXFO) {
135 dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
136 irq_valid = true;
137 }
138
139 /* Error Handling: TX */
140 if (isr[i] & ISR_RXFO) {
141 dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
142 irq_valid = true;
143 }
144 }
145
146 if (irq_valid)
147 return IRQ_HANDLED;
148 else
149 return IRQ_NONE;
150}
151
b1d32feb
JA		 152static void i2s_start(struct dw_i2s_dev *dev,
153 struct snd_pcm_substream *substream)
154{
155 struct i2s_clk_config_data *config = &dev->config;
156
157 i2s_write_reg(dev->i2s_base, IER, 1);
158 i2s_enable_irqs(dev, substream->stream, config->chan_nr);
159
160 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
161 i2s_write_reg(dev->i2s_base, ITER, 1);
162 else
163 i2s_write_reg(dev->i2s_base, IRER, 1);
3a9cf8ef
RK		 164
165 i2s_write_reg(dev->i2s_base, CER, 1);
166}
167
168static void i2s_stop(struct dw_i2s_dev *dev,
169 struct snd_pcm_substream *substream)
170{
3a9cf8ef
RK		 171
172 i2s_clear_irqs(dev, substream->stream);
b1d32feb 173 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3a9cf8ef 174 i2s_write_reg(dev->i2s_base, ITER, 0);
b1d32feb 175 else
3a9cf8ef
RK		 176 i2s_write_reg(dev->i2s_base, IRER, 0);
177
b1d32feb 178 i2s_disable_irqs(dev, substream->stream, 8);
3a9cf8ef
RK		 179
180 if (!dev->active) {
181 i2s_write_reg(dev->i2s_base, CER, 0);
182 i2s_write_reg(dev->i2s_base, IER, 0);
183 }
184}
185
186static int dw_i2s_startup(struct snd_pcm_substream *substream,
187 struct snd_soc_dai *cpu_dai)
188{
189 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
0d274544 190 union dw_i2s_snd_dma_data *dma_data = NULL;
3a9cf8ef
RK		 191
192 if (!(dev->capability & DWC_I2S_RECORD) &&
193 (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
194 return -EINVAL;
195
196 if (!(dev->capability & DWC_I2S_PLAY) &&
197 (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
198 return -EINVAL;
199
200 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
201 dma_data = &dev->play_dma_data;
202 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
203 dma_data = &dev->capture_dma_data;
204
205 snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
206
207 return 0;
208}
209
0032e9db
MSB		 210static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
211{
b1d32feb 212 u32 ch_reg;
0032e9db
MSB		 213 struct i2s_clk_config_data *config = &dev->config;
214
215
216 i2s_disable_channels(dev, stream);
217
218 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
219 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
220 i2s_write_reg(dev->i2s_base, TCR(ch_reg),
221 dev->xfer_resolution);
3fafd14d
JA		 222 i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
223 dev->fifo_th - 1);
0032e9db
MSB		 224 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
225 } else {
226 i2s_write_reg(dev->i2s_base, RCR(ch_reg),
227 dev->xfer_resolution);
3fafd14d
JA		 228 i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
229 dev->fifo_th - 1);
0032e9db
MSB		 230 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
231 }
232
233 }
234}
235
3a9cf8ef
RK		 236static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
237 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
238{
239 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
240 struct i2s_clk_config_data *config = &dev->config;
3a9cf8ef
RK		 241 int ret;
242
243 switch (params_format(params)) {
244 case SNDRV_PCM_FORMAT_S16_LE:
245 config->data_width = 16;
0032e9db
MSB		 246 dev->ccr = 0x00;
247 dev->xfer_resolution = 0x02;
3a9cf8ef
RK		 248 break;
249
250 case SNDRV_PCM_FORMAT_S24_LE:
251 config->data_width = 24;
0032e9db
MSB		 252 dev->ccr = 0x08;
253 dev->xfer_resolution = 0x04;
3a9cf8ef
RK		 254 break;
255
256 case SNDRV_PCM_FORMAT_S32_LE:
257 config->data_width = 32;
0032e9db
MSB		 258 dev->ccr = 0x10;
259 dev->xfer_resolution = 0x05;
3a9cf8ef
RK		 260 break;
261
262 default:
57072ae1 263 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
3a9cf8ef
RK		 264 return -EINVAL;
265 }
266
267 config->chan_nr = params_channels(params);
268
269 switch (config->chan_nr) {
270 case EIGHT_CHANNEL_SUPPORT:
3a9cf8ef 271 case SIX_CHANNEL_SUPPORT:
3a9cf8ef 272 case FOUR_CHANNEL_SUPPORT:
3a9cf8ef 273 case TWO_CHANNEL_SUPPORT:
3a9cf8ef
RK		 274 break;
275 default:
276 dev_err(dev->dev, "channel not supported\n");
0099d24c 277 return -EINVAL;
3a9cf8ef
RK		 278 }
279
0032e9db 280 dw_i2s_config(dev, substream->stream);
3a9cf8ef 281
0032e9db 282 i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
3a9cf8ef
RK		 283
284 config->sample_rate = params_rate(params);
285
1d957d86
MSB		 286 if (dev->capability & DW_I2S_MASTER) {
287 if (dev->i2s_clk_cfg) {
288 ret = dev->i2s_clk_cfg(config);
289 if (ret < 0) {
290 dev_err(dev->dev, "runtime audio clk config fail\n");
291 return ret;
292 }
293 } else {
294 u32 bitclk = config->sample_rate *
295 config->data_width * 2;
296
297 ret = clk_set_rate(dev->clk, bitclk);
298 if (ret) {
299 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
300 ret);
301 return ret;
302 }
0d274544 303 }
3a9cf8ef 304 }
3a9cf8ef
RK		 305 return 0;
306}
307
308static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
309 struct snd_soc_dai *dai)
310{
311 snd_soc_dai_set_dma_data(dai, substream, NULL);
312}
313
3475c3d0
AJ		 314static int dw_i2s_prepare(struct snd_pcm_substream *substream,
315 struct snd_soc_dai *dai)
316{
317 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
318
319 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
320 i2s_write_reg(dev->i2s_base, TXFFR, 1);
321 else
322 i2s_write_reg(dev->i2s_base, RXFFR, 1);
323
324 return 0;
325}
326
3a9cf8ef
RK		 327static int dw_i2s_trigger(struct snd_pcm_substream *substream,
328 int cmd, struct snd_soc_dai *dai)
329{
330 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
331 int ret = 0;
332
333 switch (cmd) {
334 case SNDRV_PCM_TRIGGER_START:
335 case SNDRV_PCM_TRIGGER_RESUME:
336 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
337 dev->active++;
338 i2s_start(dev, substream);
339 break;
340
341 case SNDRV_PCM_TRIGGER_STOP:
342 case SNDRV_PCM_TRIGGER_SUSPEND:
343 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
344 dev->active--;
345 i2s_stop(dev, substream);
346 break;
347 default:
348 ret = -EINVAL;
349 break;
350 }
351 return ret;
352}
353
ab57b8e9
MSB		 354static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
355{
356 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
357 int ret = 0;
358
359 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
360 case SND_SOC_DAIFMT_CBM_CFM:
361 if (dev->capability & DW_I2S_SLAVE)
362 ret = 0;
363 else
364 ret = -EINVAL;
365 break;
366 case SND_SOC_DAIFMT_CBS_CFS:
367 if (dev->capability & DW_I2S_MASTER)
368 ret = 0;
369 else
370 ret = -EINVAL;
371 break;
372 case SND_SOC_DAIFMT_CBM_CFS:
373 case SND_SOC_DAIFMT_CBS_CFM:
374 ret = -EINVAL;
375 break;
376 default:
377 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
378 ret = -EINVAL;
379 break;
380 }
381 return ret;
382}
383
3a9cf8ef
RK		 384static struct snd_soc_dai_ops dw_i2s_dai_ops = {
385 .startup = dw_i2s_startup,
386 .shutdown = dw_i2s_shutdown,
387 .hw_params = dw_i2s_hw_params,
3475c3d0 388 .prepare = dw_i2s_prepare,
3a9cf8ef 389 .trigger = dw_i2s_trigger,
ab57b8e9 390 .set_fmt = dw_i2s_set_fmt,
3a9cf8ef
RK		 391};
392
92eaa328
KM		 393static const struct snd_soc_component_driver dw_i2s_component = {
394 .name = "dw-i2s",
395};
396
3a9cf8ef 397#ifdef CONFIG_PM
f4830312
MSB		 398static int dw_i2s_runtime_suspend(struct device *dev)
399{
400 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
401
402 if (dw_dev->capability & DW_I2S_MASTER)
403 clk_disable(dw_dev->clk);
404 return 0;
405}
406
407static int dw_i2s_runtime_resume(struct device *dev)
408{
409 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
410
411 if (dw_dev->capability & DW_I2S_MASTER)
412 clk_enable(dw_dev->clk);
413 return 0;
414}
3a9cf8ef
RK		 415
416static int dw_i2s_suspend(struct snd_soc_dai *dai)
417{
418 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
419
1d957d86
MSB		 420 if (dev->capability & DW_I2S_MASTER)
421 clk_disable(dev->clk);
3a9cf8ef
RK		 422 return 0;
423}
424
425static int dw_i2s_resume(struct snd_soc_dai *dai)
426{
427 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
428
1d957d86
MSB		 429 if (dev->capability & DW_I2S_MASTER)
430 clk_enable(dev->clk);
0032e9db
MSB		 431
432 if (dai->playback_active)
433 dw_i2s_config(dev, SNDRV_PCM_STREAM_PLAYBACK);
434 if (dai->capture_active)
435 dw_i2s_config(dev, SNDRV_PCM_STREAM_CAPTURE);
3a9cf8ef
RK		 436 return 0;
437}
438
439#else
440#define dw_i2s_suspend NULL
441#define dw_i2s_resume NULL
442#endif
443
b226efe5
AJ		 444/*
445 * The following tables allow a direct lookup of various parameters
446 * defined in the I2S block's configuration in terms of sound system
447 * parameters. Each table is sized to the number of entries possible
448 * according to the number of configuration bits describing an I2S
449 * block parameter.
450 */
451
0d274544
AJ		 452/* Maximum bit resolution of a channel - not uniformly spaced */
453static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
454 12, 16, 20, 24, 32, 0, 0, 0
455};
456
b226efe5
AJ		 457/* Width of (DMA) bus */
458static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
459 DMA_SLAVE_BUSWIDTH_1_BYTE,
460 DMA_SLAVE_BUSWIDTH_2_BYTES,
461 DMA_SLAVE_BUSWIDTH_4_BYTES,
462 DMA_SLAVE_BUSWIDTH_UNDEFINED
463};
464
465/* PCM format to support channel resolution */
466static const u32 formats[COMP_MAX_WORDSIZE] = {
467 SNDRV_PCM_FMTBIT_S16_LE,
468 SNDRV_PCM_FMTBIT_S16_LE,
469 SNDRV_PCM_FMTBIT_S24_LE,
470 SNDRV_PCM_FMTBIT_S24_LE,
471 SNDRV_PCM_FMTBIT_S32_LE,
472 0,
473 0,
474 0
475};
476
0d274544 477static int dw_configure_dai(struct dw_i2s_dev *dev,
afa8603c 478 struct snd_soc_dai_driver *dw_i2s_dai,
0d274544 479 unsigned int rates)
afa8603c 480{
b226efe5
AJ		 481 /*
482 * Read component parameter registers to extract
483 * the I2S block's configuration.
484 */
e164835a
MSB		 485 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
486 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
3fafd14d 487 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
0d274544 488 u32 idx;
afa8603c 489
a242cac1
MSB		 490 if (dev->capability & DWC_I2S_RECORD &&
491 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
492 comp1 = comp1 & ~BIT(5);
493
b226efe5 494 if (COMP1_TX_ENABLED(comp1)) {
afa8603c 495 dev_dbg(dev->dev, " designware: play supported\n");
b226efe5
AJ		 496 idx = COMP1_TX_WORDSIZE_0(comp1);
497 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
498 return -EINVAL;
286345ee
VM		 499 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
500 idx = 1;
afa8603c 501 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
b226efe5
AJ		 502 dw_i2s_dai->playback.channels_max =
503 1 << (COMP1_TX_CHANNELS(comp1) + 1);
504 dw_i2s_dai->playback.formats = formats[idx];
0d274544 505 dw_i2s_dai->playback.rates = rates;
afa8603c
AJ		 506 }
507
b226efe5 508 if (COMP1_RX_ENABLED(comp1)) {
afa8603c 509 dev_dbg(dev->dev, "designware: record supported\n");
b226efe5
AJ		 510 idx = COMP2_RX_WORDSIZE_0(comp2);
511 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
512 return -EINVAL;
286345ee
VM		 513 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
514 idx = 1;
afa8603c 515 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
b226efe5
AJ		 516 dw_i2s_dai->capture.channels_max =
517 1 << (COMP1_RX_CHANNELS(comp1) + 1);
518 dw_i2s_dai->capture.formats = formats[idx];
0d274544
AJ		 519 dw_i2s_dai->capture.rates = rates;
520 }
521
1d957d86
MSB		 522 if (COMP1_MODE_EN(comp1)) {
523 dev_dbg(dev->dev, "designware: i2s master mode supported\n");
524 dev->capability |= DW_I2S_MASTER;
525 } else {
526 dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
527 dev->capability |= DW_I2S_SLAVE;
528 }
529
3fafd14d 530 dev->fifo_th = fifo_depth / 2;
0d274544
AJ		 531 return 0;
532}
533
534static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
535 struct snd_soc_dai_driver *dw_i2s_dai,
536 struct resource *res,
537 const struct i2s_platform_data *pdata)
538{
e164835a 539 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
0d274544
AJ		 540 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
541 int ret;
542
543 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
544 return -EINVAL;
545
546 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
547 if (ret < 0)
548 return ret;
549
286345ee
VM		 550 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
551 idx = 1;
0d274544
AJ		 552 /* Set DMA slaves info */
553 dev->play_dma_data.pd.data = pdata->play_dma_data;
554 dev->capture_dma_data.pd.data = pdata->capture_dma_data;
555 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
556 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
557 dev->play_dma_data.pd.max_burst = 16;
558 dev->capture_dma_data.pd.max_burst = 16;
559 dev->play_dma_data.pd.addr_width = bus_widths[idx];
560 dev->capture_dma_data.pd.addr_width = bus_widths[idx];
561 dev->play_dma_data.pd.filter = pdata->filter;
562 dev->capture_dma_data.pd.filter = pdata->filter;
563
564 return 0;
565}
566
567static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
568 struct snd_soc_dai_driver *dw_i2s_dai,
569 struct resource *res)
570{
571 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
572 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
573 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
574 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
575 u32 idx2;
576 int ret;
577
578 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
579 return -EINVAL;
580
581 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
582 if (ret < 0)
583 return ret;
584
585 if (COMP1_TX_ENABLED(comp1)) {
586 idx2 = COMP1_TX_WORDSIZE_0(comp1);
587
588 dev->capability |= DWC_I2S_PLAY;
589 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
590 dev->play_dma_data.dt.addr_width = bus_widths[idx];
0d274544
AJ		 591 dev->play_dma_data.dt.fifo_size = fifo_depth *
592 (fifo_width[idx2]) >> 8;
593 dev->play_dma_data.dt.maxburst = 16;
594 }
595 if (COMP1_RX_ENABLED(comp1)) {
596 idx2 = COMP2_RX_WORDSIZE_0(comp2);
597
598 dev->capability |= DWC_I2S_RECORD;
599 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
600 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
0d274544
AJ		 601 dev->capture_dma_data.dt.fifo_size = fifo_depth *
602 (fifo_width[idx2] >> 8);
603 dev->capture_dma_data.dt.maxburst = 16;
afa8603c 604 }
b226efe5
AJ		 605
606 return 0;
0d274544 607
afa8603c
AJ		 608}
609
3a9cf8ef
RK		 610static int dw_i2s_probe(struct platform_device *pdev)
611{
612 const struct i2s_platform_data *pdata = pdev->dev.platform_data;
613 struct dw_i2s_dev *dev;
614 struct resource *res;
79361b2b 615 int ret, irq;
3a9cf8ef 616 struct snd_soc_dai_driver *dw_i2s_dai;
1d957d86 617 const char *clk_id;
3a9cf8ef 618
3a9cf8ef
RK		 619 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
620 if (!dev) {
621 dev_warn(&pdev->dev, "kzalloc fail\n");
622 return -ENOMEM;
623 }
624
b163be4c 625 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
be33465e 626 if (!dw_i2s_dai)
3a9cf8ef 627 return -ENOMEM;
3a9cf8ef 628
b163be4c
AJ		 629 dw_i2s_dai->ops = &dw_i2s_dai_ops;
630 dw_i2s_dai->suspend = dw_i2s_suspend;
631 dw_i2s_dai->resume = dw_i2s_resume;
632
633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b163be4c 634 dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
be33465e 635 if (IS_ERR(dev->i2s_base))
b163be4c 636 return PTR_ERR(dev->i2s_base);
b163be4c 637
afa8603c 638 dev->dev = &pdev->dev;
1d957d86 639
79361b2b
JA		 640 irq = platform_get_irq(pdev, 0);
641 if (irq >= 0) {
642 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
643 pdev->name, dev);
644 if (ret < 0) {
645 dev_err(&pdev->dev, "failed to request irq\n");
646 return ret;
647 }
648 }
649
d2f916aa
JMT		 650 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
651 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
0d274544 652 if (pdata) {
1d957d86
MSB		 653 dev->capability = pdata->cap;
654 clk_id = NULL;
e164835a
MSB		 655 dev->quirks = pdata->quirks;
656 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
657 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
658 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
e164835a 659 }
0d274544 660 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
1d957d86
MSB		 661 } else {
662 clk_id = "i2sclk";
663 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
664 }
665 if (ret < 0)
666 return ret;
0d274544 667
1d957d86
MSB		 668 if (dev->capability & DW_I2S_MASTER) {
669 if (pdata) {
670 dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
671 if (!dev->i2s_clk_cfg) {
672 dev_err(&pdev->dev, "no clock configure method\n");
673 return -ENODEV;
674 }
0d274544 675 }
1d957d86 676 dev->clk = devm_clk_get(&pdev->dev, clk_id);
3a9cf8ef 677
1d957d86
MSB		 678 if (IS_ERR(dev->clk))
679 return PTR_ERR(dev->clk);
680
681 ret = clk_prepare_enable(dev->clk);
0d274544
AJ		 682 if (ret < 0)
683 return ret;
0d274544 684 }
3a9cf8ef 685
3a9cf8ef 686 dev_set_drvdata(&pdev->dev, dev);
758c2deb 687 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
92eaa328 688 dw_i2s_dai, 1);
3a9cf8ef
RK		 689 if (ret != 0) {
690 dev_err(&pdev->dev, "not able to register dai\n");
e925a6b1 691 goto err_clk_disable;
3a9cf8ef
RK		 692 }
693
0d274544 694 if (!pdata) {
6fce983f 695 if (irq >= 0) {
79361b2b 696 ret = dw_pcm_register(pdev);
6fce983f
JA		 697 dev->use_pio = true;
698 } else {
699 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
700 0);
701 dev->use_pio = false;
702 }
703
704 if (ret) {
705 dev_err(&pdev->dev, "could not register pcm: %d\n",
79361b2b 706 ret);
6fce983f 707 goto err_clk_disable;
0d274544
AJ		 708 }
709 }
79361b2b 710
f4830312 711 pm_runtime_enable(&pdev->dev);
3a9cf8ef
RK		 712 return 0;
713
3a9cf8ef 714err_clk_disable:
1d957d86
MSB		 715 if (dev->capability & DW_I2S_MASTER)
716 clk_disable_unprepare(dev->clk);
3a9cf8ef
RK		 717 return ret;
718}
719
720static int dw_i2s_remove(struct platform_device *pdev)
721{
722 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
723
1d957d86
MSB		 724 if (dev->capability & DW_I2S_MASTER)
725 clk_disable_unprepare(dev->clk);
3a9cf8ef 726
f4830312 727 pm_runtime_disable(&pdev->dev);
3a9cf8ef
RK		 728 return 0;
729}
730
0d274544
AJ		 731#ifdef CONFIG_OF
732static const struct of_device_id dw_i2s_of_match[] = {
733 { .compatible = "snps,designware-i2s", },
734 {},
735};
736
737MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
738#endif
739
f4830312
MSB		 740static const struct dev_pm_ops dwc_pm_ops = {
741 SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
742};
743
3a9cf8ef
RK		 744static struct platform_driver dw_i2s_driver = {
745 .probe = dw_i2s_probe,
746 .remove = dw_i2s_remove,
747 .driver = {
748 .name = "designware-i2s",
0d274544 749 .of_match_table = of_match_ptr(dw_i2s_of_match),
f4830312 750 .pm = &dwc_pm_ops,
3a9cf8ef
RK		 751 },
752};
753
754module_platform_driver(dw_i2s_driver);
755
b794dbcd 756MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
3a9cf8ef
RK		 757MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
758MODULE_LICENSE("GPL");
759MODULE_ALIAS("platform:designware_i2s");
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