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47a70e6f CS |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright 2018 NXP | |
3 | ||
17f2142b | 4 | #include <linux/bitfield.h> |
47a70e6f CS |
5 | #include <linux/clk.h> |
6 | #include <linux/device.h> | |
7 | #include <linux/interrupt.h> | |
8 | #include <linux/kobject.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/of_address.h> | |
13 | #include <linux/of_irq.h> | |
14 | #include <linux/of_platform.h> | |
15 | #include <linux/pm_runtime.h> | |
16 | #include <linux/regmap.h> | |
17 | #include <linux/sysfs.h> | |
18 | #include <linux/types.h> | |
2495ba26 | 19 | #include <linux/dma/imx-dma.h> |
47a70e6f CS |
20 | #include <sound/dmaengine_pcm.h> |
21 | #include <sound/pcm.h> | |
22 | #include <sound/soc.h> | |
23 | #include <sound/tlv.h> | |
24 | #include <sound/core.h> | |
25 | ||
26 | #include "fsl_micfil.h" | |
27 | #include "imx-pcm.h" | |
28 | ||
29 | #define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000 | |
30 | #define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE) | |
31 | ||
fb855b8d SH |
32 | #define MICFIL_OSR_DEFAULT 16 |
33 | ||
47a70e6f CS |
34 | struct fsl_micfil { |
35 | struct platform_device *pdev; | |
36 | struct regmap *regmap; | |
37 | const struct fsl_micfil_soc_data *soc; | |
b5cf28f7 | 38 | struct clk *busclk; |
47a70e6f CS |
39 | struct clk *mclk; |
40 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
2495ba26 | 41 | struct sdma_peripheral_config sdmacfg; |
47a70e6f CS |
42 | unsigned int dataline; |
43 | char name[32]; | |
44 | int irq[MICFIL_IRQ_LINES]; | |
47a70e6f | 45 | int quality; /*QUALITY 2-0 bits */ |
47a70e6f CS |
46 | }; |
47 | ||
48 | struct fsl_micfil_soc_data { | |
49 | unsigned int fifos; | |
50 | unsigned int fifo_depth; | |
51 | unsigned int dataline; | |
52 | bool imx; | |
53 | }; | |
54 | ||
55 | static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { | |
56 | .imx = true, | |
57 | .fifos = 8, | |
58 | .fifo_depth = 8, | |
59 | .dataline = 0xf, | |
60 | }; | |
61 | ||
62 | static const struct of_device_id fsl_micfil_dt_ids[] = { | |
63 | { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, | |
64 | {} | |
65 | }; | |
66 | MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); | |
67 | ||
68 | /* Table 5. Quality Modes | |
69 | * Medium 0 0 0 | |
70 | * High 0 0 1 | |
71 | * Very Low 2 1 0 0 | |
72 | * Very Low 1 1 0 1 | |
73 | * Very Low 0 1 1 0 | |
74 | * Low 1 1 1 | |
75 | */ | |
76 | static const char * const micfil_quality_select_texts[] = { | |
77 | "Medium", "High", | |
78 | "N/A", "N/A", | |
79 | "VLow2", "VLow1", | |
80 | "VLow0", "Low", | |
81 | }; | |
82 | ||
83 | static const struct soc_enum fsl_micfil_quality_enum = | |
84 | SOC_ENUM_SINGLE(REG_MICFIL_CTRL2, | |
85 | MICFIL_CTRL2_QSEL_SHIFT, | |
86 | ARRAY_SIZE(micfil_quality_select_texts), | |
87 | micfil_quality_select_texts); | |
88 | ||
89 | static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); | |
90 | ||
91 | static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { | |
92 | SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, | |
93 | MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv), | |
94 | SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, | |
95 | MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv), | |
96 | SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, | |
97 | MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv), | |
98 | SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, | |
99 | MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv), | |
100 | SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, | |
101 | MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv), | |
102 | SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, | |
103 | MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv), | |
104 | SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, | |
105 | MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv), | |
106 | SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, | |
107 | MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv), | |
108 | SOC_ENUM_EXT("MICFIL Quality Select", | |
109 | fsl_micfil_quality_enum, | |
110 | snd_soc_get_enum_double, snd_soc_put_enum_double), | |
111 | }; | |
112 | ||
47a70e6f CS |
113 | static inline int get_clk_div(struct fsl_micfil *micfil, |
114 | unsigned int rate) | |
115 | { | |
47a70e6f | 116 | long mclk_rate; |
47a70e6f CS |
117 | int clk_div; |
118 | ||
47a70e6f CS |
119 | mclk_rate = clk_get_rate(micfil->mclk); |
120 | ||
be6aeee2 | 121 | clk_div = mclk_rate / (rate * MICFIL_OSR_DEFAULT * 8); |
47a70e6f CS |
122 | |
123 | return clk_div; | |
124 | } | |
125 | ||
126 | /* The SRES is a self-negated bit which provides the CPU with the | |
127 | * capability to initialize the PDM Interface module through the | |
128 | * slave-bus interface. This bit always reads as zero, and this | |
129 | * bit is only effective when MDIS is cleared | |
130 | */ | |
131 | static int fsl_micfil_reset(struct device *dev) | |
132 | { | |
133 | struct fsl_micfil *micfil = dev_get_drvdata(dev); | |
134 | int ret; | |
135 | ||
d46c2127 SH |
136 | ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, |
137 | MICFIL_CTRL1_MDIS); | |
2c602c7e | 138 | if (ret) |
47a70e6f | 139 | return ret; |
47a70e6f | 140 | |
d46c2127 SH |
141 | ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, |
142 | MICFIL_CTRL1_SRES); | |
2c602c7e | 143 | if (ret) |
47a70e6f | 144 | return ret; |
47a70e6f CS |
145 | |
146 | return 0; | |
147 | } | |
148 | ||
149 | static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil, | |
150 | unsigned int freq) | |
151 | { | |
152 | struct device *dev = &micfil->pdev->dev; | |
153 | int ret; | |
154 | ||
155 | clk_disable_unprepare(micfil->mclk); | |
156 | ||
157 | ret = clk_set_rate(micfil->mclk, freq * 1024); | |
158 | if (ret) | |
159 | dev_warn(dev, "failed to set rate (%u): %d\n", | |
160 | freq * 1024, ret); | |
161 | ||
162 | clk_prepare_enable(micfil->mclk); | |
163 | ||
164 | return ret; | |
165 | } | |
166 | ||
167 | static int fsl_micfil_startup(struct snd_pcm_substream *substream, | |
168 | struct snd_soc_dai *dai) | |
169 | { | |
170 | struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); | |
171 | ||
172 | if (!micfil) { | |
11106cb3 | 173 | dev_err(dai->dev, "micfil dai priv_data not set\n"); |
47a70e6f CS |
174 | return -EINVAL; |
175 | } | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, | |
181 | struct snd_soc_dai *dai) | |
182 | { | |
183 | struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); | |
184 | struct device *dev = &micfil->pdev->dev; | |
185 | int ret; | |
186 | ||
187 | switch (cmd) { | |
188 | case SNDRV_PCM_TRIGGER_START: | |
189 | case SNDRV_PCM_TRIGGER_RESUME: | |
190 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
191 | ret = fsl_micfil_reset(dev); | |
192 | if (ret) { | |
193 | dev_err(dev, "failed to soft reset\n"); | |
194 | return ret; | |
195 | } | |
196 | ||
197 | /* DMA Interrupt Selection - DISEL bits | |
198 | * 00 - DMA and IRQ disabled | |
199 | * 01 - DMA req enabled | |
200 | * 10 - IRQ enabled | |
201 | * 11 - reserved | |
202 | */ | |
203 | ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, | |
17f2142b SH |
204 | MICFIL_CTRL1_DISEL, |
205 | FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA)); | |
2c602c7e | 206 | if (ret) |
47a70e6f | 207 | return ret; |
47a70e6f CS |
208 | |
209 | /* Enable the module */ | |
d46c2127 SH |
210 | ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, |
211 | MICFIL_CTRL1_PDMIEN); | |
2c602c7e | 212 | if (ret) |
47a70e6f | 213 | return ret; |
47a70e6f CS |
214 | |
215 | break; | |
216 | case SNDRV_PCM_TRIGGER_STOP: | |
217 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
218 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
219 | /* Disable the module */ | |
d46c2127 SH |
220 | ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, |
221 | MICFIL_CTRL1_PDMIEN); | |
2c602c7e | 222 | if (ret) |
47a70e6f | 223 | return ret; |
47a70e6f CS |
224 | |
225 | ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, | |
17f2142b SH |
226 | MICFIL_CTRL1_DISEL, |
227 | FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE)); | |
2c602c7e | 228 | if (ret) |
47a70e6f | 229 | return ret; |
47a70e6f CS |
230 | break; |
231 | default: | |
232 | return -EINVAL; | |
233 | } | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static int fsl_set_clock_params(struct device *dev, unsigned int rate) | |
238 | { | |
239 | struct fsl_micfil *micfil = dev_get_drvdata(dev); | |
240 | int clk_div; | |
15b5c496 | 241 | int ret; |
47a70e6f CS |
242 | |
243 | ret = fsl_micfil_set_mclk_rate(micfil, rate); | |
244 | if (ret < 0) | |
245 | dev_err(dev, "failed to set mclk[%lu] to rate %u\n", | |
246 | clk_get_rate(micfil->mclk), rate); | |
247 | ||
248 | /* set CICOSR */ | |
2c602c7e | 249 | ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, |
17f2142b | 250 | MICFIL_CTRL2_CICOSR, |
fb855b8d | 251 | FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - MICFIL_OSR_DEFAULT)); |
47a70e6f | 252 | if (ret) |
2c602c7e | 253 | return ret; |
47a70e6f CS |
254 | |
255 | /* set CLK_DIV */ | |
256 | clk_div = get_clk_div(micfil, rate); | |
257 | if (clk_div < 0) | |
258 | ret = -EINVAL; | |
259 | ||
2c602c7e | 260 | ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, |
17f2142b SH |
261 | MICFIL_CTRL2_CLKDIV, |
262 | FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div)); | |
47a70e6f CS |
263 | |
264 | return ret; | |
265 | } | |
266 | ||
267 | static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, | |
268 | struct snd_pcm_hw_params *params, | |
269 | struct snd_soc_dai *dai) | |
270 | { | |
271 | struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); | |
272 | unsigned int channels = params_channels(params); | |
273 | unsigned int rate = params_rate(params); | |
274 | struct device *dev = &micfil->pdev->dev; | |
275 | int ret; | |
276 | ||
277 | /* 1. Disable the module */ | |
d46c2127 SH |
278 | ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, |
279 | MICFIL_CTRL1_PDMIEN); | |
2c602c7e | 280 | if (ret) |
47a70e6f | 281 | return ret; |
47a70e6f CS |
282 | |
283 | /* enable channels */ | |
284 | ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, | |
285 | 0xFF, ((1 << channels) - 1)); | |
2c602c7e | 286 | if (ret) |
47a70e6f | 287 | return ret; |
47a70e6f CS |
288 | |
289 | ret = fsl_set_clock_params(dev, rate); | |
290 | if (ret < 0) { | |
291 | dev_err(dev, "Failed to set clock parameters [%d]\n", ret); | |
292 | return ret; | |
293 | } | |
294 | ||
2495ba26 SH |
295 | micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg; |
296 | micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg); | |
297 | micfil->sdmacfg.n_fifos_src = channels; | |
298 | micfil->sdmacfg.sw_done = true; | |
47a70e6f CS |
299 | micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
38d89a56 | 304 | static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { |
47a70e6f CS |
305 | .startup = fsl_micfil_startup, |
306 | .trigger = fsl_micfil_trigger, | |
307 | .hw_params = fsl_micfil_hw_params, | |
47a70e6f CS |
308 | }; |
309 | ||
310 | static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) | |
311 | { | |
312 | struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); | |
47a70e6f | 313 | int ret; |
47a70e6f CS |
314 | |
315 | /* set qsel to medium */ | |
316 | ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, | |
17f2142b SH |
317 | MICFIL_CTRL2_QSEL, |
318 | FIELD_PREP(MICFIL_CTRL2_QSEL, MICFIL_QSEL_MEDIUM_QUALITY)); | |
2c602c7e | 319 | if (ret) |
47a70e6f | 320 | return ret; |
47a70e6f CS |
321 | |
322 | /* set default gain to max_gain */ | |
323 | regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777); | |
47a70e6f CS |
324 | |
325 | snd_soc_dai_init_dma_data(cpu_dai, NULL, | |
326 | &micfil->dma_params_rx); | |
327 | ||
328 | /* FIFO Watermark Control - FIFOWMK*/ | |
47a70e6f | 329 | ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, |
17f2142b SH |
330 | MICFIL_FIFO_CTRL_FIFOWMK, |
331 | FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1)); | |
2c602c7e | 332 | if (ret) |
47a70e6f | 333 | return ret; |
47a70e6f | 334 | |
47a70e6f CS |
335 | return 0; |
336 | } | |
337 | ||
338 | static struct snd_soc_dai_driver fsl_micfil_dai = { | |
339 | .probe = fsl_micfil_dai_probe, | |
340 | .capture = { | |
341 | .stream_name = "CPU-Capture", | |
342 | .channels_min = 1, | |
343 | .channels_max = 8, | |
344 | .rates = FSL_MICFIL_RATES, | |
345 | .formats = FSL_MICFIL_FORMATS, | |
346 | }, | |
347 | .ops = &fsl_micfil_dai_ops, | |
348 | }; | |
349 | ||
350 | static const struct snd_soc_component_driver fsl_micfil_component = { | |
351 | .name = "fsl-micfil-dai", | |
352 | .controls = fsl_micfil_snd_controls, | |
353 | .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), | |
354 | ||
355 | }; | |
356 | ||
357 | /* REGMAP */ | |
358 | static const struct reg_default fsl_micfil_reg_defaults[] = { | |
359 | {REG_MICFIL_CTRL1, 0x00000000}, | |
360 | {REG_MICFIL_CTRL2, 0x00000000}, | |
361 | {REG_MICFIL_STAT, 0x00000000}, | |
362 | {REG_MICFIL_FIFO_CTRL, 0x00000007}, | |
363 | {REG_MICFIL_FIFO_STAT, 0x00000000}, | |
364 | {REG_MICFIL_DATACH0, 0x00000000}, | |
365 | {REG_MICFIL_DATACH1, 0x00000000}, | |
366 | {REG_MICFIL_DATACH2, 0x00000000}, | |
367 | {REG_MICFIL_DATACH3, 0x00000000}, | |
368 | {REG_MICFIL_DATACH4, 0x00000000}, | |
369 | {REG_MICFIL_DATACH5, 0x00000000}, | |
370 | {REG_MICFIL_DATACH6, 0x00000000}, | |
371 | {REG_MICFIL_DATACH7, 0x00000000}, | |
372 | {REG_MICFIL_DC_CTRL, 0x00000000}, | |
373 | {REG_MICFIL_OUT_CTRL, 0x00000000}, | |
374 | {REG_MICFIL_OUT_STAT, 0x00000000}, | |
375 | {REG_MICFIL_VAD0_CTRL1, 0x00000000}, | |
376 | {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, | |
377 | {REG_MICFIL_VAD0_STAT, 0x00000000}, | |
378 | {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, | |
379 | {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, | |
380 | {REG_MICFIL_VAD0_NDATA, 0x00000000}, | |
381 | {REG_MICFIL_VAD0_ZCD, 0x00000004}, | |
382 | }; | |
383 | ||
384 | static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) | |
385 | { | |
386 | switch (reg) { | |
387 | case REG_MICFIL_CTRL1: | |
388 | case REG_MICFIL_CTRL2: | |
389 | case REG_MICFIL_STAT: | |
390 | case REG_MICFIL_FIFO_CTRL: | |
391 | case REG_MICFIL_FIFO_STAT: | |
392 | case REG_MICFIL_DATACH0: | |
393 | case REG_MICFIL_DATACH1: | |
394 | case REG_MICFIL_DATACH2: | |
395 | case REG_MICFIL_DATACH3: | |
396 | case REG_MICFIL_DATACH4: | |
397 | case REG_MICFIL_DATACH5: | |
398 | case REG_MICFIL_DATACH6: | |
399 | case REG_MICFIL_DATACH7: | |
400 | case REG_MICFIL_DC_CTRL: | |
401 | case REG_MICFIL_OUT_CTRL: | |
402 | case REG_MICFIL_OUT_STAT: | |
403 | case REG_MICFIL_VAD0_CTRL1: | |
404 | case REG_MICFIL_VAD0_CTRL2: | |
405 | case REG_MICFIL_VAD0_STAT: | |
406 | case REG_MICFIL_VAD0_SCONFIG: | |
407 | case REG_MICFIL_VAD0_NCONFIG: | |
408 | case REG_MICFIL_VAD0_NDATA: | |
409 | case REG_MICFIL_VAD0_ZCD: | |
410 | return true; | |
411 | default: | |
412 | return false; | |
413 | } | |
414 | } | |
415 | ||
416 | static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) | |
417 | { | |
418 | switch (reg) { | |
419 | case REG_MICFIL_CTRL1: | |
420 | case REG_MICFIL_CTRL2: | |
421 | case REG_MICFIL_STAT: /* Write 1 to Clear */ | |
422 | case REG_MICFIL_FIFO_CTRL: | |
423 | case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ | |
424 | case REG_MICFIL_DC_CTRL: | |
425 | case REG_MICFIL_OUT_CTRL: | |
426 | case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ | |
427 | case REG_MICFIL_VAD0_CTRL1: | |
428 | case REG_MICFIL_VAD0_CTRL2: | |
429 | case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ | |
430 | case REG_MICFIL_VAD0_SCONFIG: | |
431 | case REG_MICFIL_VAD0_NCONFIG: | |
432 | case REG_MICFIL_VAD0_ZCD: | |
433 | return true; | |
434 | default: | |
435 | return false; | |
436 | } | |
437 | } | |
438 | ||
439 | static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) | |
440 | { | |
441 | switch (reg) { | |
442 | case REG_MICFIL_STAT: | |
443 | case REG_MICFIL_DATACH0: | |
444 | case REG_MICFIL_DATACH1: | |
445 | case REG_MICFIL_DATACH2: | |
446 | case REG_MICFIL_DATACH3: | |
447 | case REG_MICFIL_DATACH4: | |
448 | case REG_MICFIL_DATACH5: | |
449 | case REG_MICFIL_DATACH6: | |
450 | case REG_MICFIL_DATACH7: | |
451 | case REG_MICFIL_VAD0_STAT: | |
452 | case REG_MICFIL_VAD0_NDATA: | |
453 | return true; | |
454 | default: | |
455 | return false; | |
456 | } | |
457 | } | |
458 | ||
459 | static const struct regmap_config fsl_micfil_regmap_config = { | |
460 | .reg_bits = 32, | |
461 | .reg_stride = 4, | |
462 | .val_bits = 32, | |
463 | ||
464 | .max_register = REG_MICFIL_VAD0_ZCD, | |
465 | .reg_defaults = fsl_micfil_reg_defaults, | |
466 | .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), | |
467 | .readable_reg = fsl_micfil_readable_reg, | |
468 | .volatile_reg = fsl_micfil_volatile_reg, | |
469 | .writeable_reg = fsl_micfil_writeable_reg, | |
470 | .cache_type = REGCACHE_RBTREE, | |
471 | }; | |
472 | ||
473 | /* END OF REGMAP */ | |
474 | ||
475 | static irqreturn_t micfil_isr(int irq, void *devid) | |
476 | { | |
477 | struct fsl_micfil *micfil = (struct fsl_micfil *)devid; | |
478 | struct platform_device *pdev = micfil->pdev; | |
479 | u32 stat_reg; | |
480 | u32 fifo_stat_reg; | |
481 | u32 ctrl1_reg; | |
482 | bool dma_enabled; | |
483 | int i; | |
484 | ||
485 | regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); | |
486 | regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); | |
487 | regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); | |
488 | ||
17f2142b | 489 | dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA; |
47a70e6f CS |
490 | |
491 | /* Channel 0-7 Output Data Flags */ | |
492 | for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { | |
17f2142b | 493 | if (stat_reg & MICFIL_STAT_CHXF(i)) |
47a70e6f CS |
494 | dev_dbg(&pdev->dev, |
495 | "Data available in Data Channel %d\n", i); | |
496 | /* if DMA is not enabled, field must be written with 1 | |
497 | * to clear | |
498 | */ | |
499 | if (!dma_enabled) | |
500 | regmap_write_bits(micfil->regmap, | |
501 | REG_MICFIL_STAT, | |
17f2142b | 502 | MICFIL_STAT_CHXF(i), |
47a70e6f CS |
503 | 1); |
504 | } | |
505 | ||
506 | for (i = 0; i < MICFIL_FIFO_NUM; i++) { | |
17f2142b | 507 | if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i)) |
47a70e6f CS |
508 | dev_dbg(&pdev->dev, |
509 | "FIFO Overflow Exception flag for channel %d\n", | |
510 | i); | |
511 | ||
17f2142b | 512 | if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i)) |
47a70e6f CS |
513 | dev_dbg(&pdev->dev, |
514 | "FIFO Underflow Exception flag for channel %d\n", | |
515 | i); | |
516 | } | |
517 | ||
518 | return IRQ_HANDLED; | |
519 | } | |
520 | ||
521 | static irqreturn_t micfil_err_isr(int irq, void *devid) | |
522 | { | |
523 | struct fsl_micfil *micfil = (struct fsl_micfil *)devid; | |
524 | struct platform_device *pdev = micfil->pdev; | |
525 | u32 stat_reg; | |
526 | ||
527 | regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); | |
528 | ||
bd2cffd1 | 529 | if (stat_reg & MICFIL_STAT_BSY_FIL) |
47a70e6f CS |
530 | dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); |
531 | ||
bd2cffd1 | 532 | if (stat_reg & MICFIL_STAT_FIR_RDY) |
47a70e6f CS |
533 | dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); |
534 | ||
bd2cffd1 | 535 | if (stat_reg & MICFIL_STAT_LOWFREQF) { |
47a70e6f CS |
536 | dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); |
537 | regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, | |
bd2cffd1 | 538 | MICFIL_STAT_LOWFREQF, 1); |
47a70e6f CS |
539 | } |
540 | ||
541 | return IRQ_HANDLED; | |
542 | } | |
543 | ||
544 | static int fsl_micfil_probe(struct platform_device *pdev) | |
545 | { | |
546 | struct device_node *np = pdev->dev.of_node; | |
47a70e6f CS |
547 | struct fsl_micfil *micfil; |
548 | struct resource *res; | |
549 | void __iomem *regs; | |
550 | int ret, i; | |
551 | unsigned long irqflag = 0; | |
552 | ||
553 | micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); | |
554 | if (!micfil) | |
555 | return -ENOMEM; | |
556 | ||
557 | micfil->pdev = pdev; | |
558 | strncpy(micfil->name, np->name, sizeof(micfil->name) - 1); | |
559 | ||
d7388718 | 560 | micfil->soc = of_device_get_match_data(&pdev->dev); |
47a70e6f CS |
561 | |
562 | /* ipg_clk is used to control the registers | |
563 | * ipg_clk_app is used to operate the filter | |
564 | */ | |
565 | micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); | |
566 | if (IS_ERR(micfil->mclk)) { | |
567 | dev_err(&pdev->dev, "failed to get core clock: %ld\n", | |
568 | PTR_ERR(micfil->mclk)); | |
569 | return PTR_ERR(micfil->mclk); | |
570 | } | |
571 | ||
b5cf28f7 SW |
572 | micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); |
573 | if (IS_ERR(micfil->busclk)) { | |
574 | dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", | |
575 | PTR_ERR(micfil->busclk)); | |
576 | return PTR_ERR(micfil->busclk); | |
577 | } | |
578 | ||
47a70e6f | 579 | /* init regmap */ |
d9bf1e79 | 580 | regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
47a70e6f CS |
581 | if (IS_ERR(regs)) |
582 | return PTR_ERR(regs); | |
583 | ||
b5cf28f7 SW |
584 | micfil->regmap = devm_regmap_init_mmio(&pdev->dev, |
585 | regs, | |
586 | &fsl_micfil_regmap_config); | |
47a70e6f CS |
587 | if (IS_ERR(micfil->regmap)) { |
588 | dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", | |
589 | PTR_ERR(micfil->regmap)); | |
590 | return PTR_ERR(micfil->regmap); | |
591 | } | |
592 | ||
593 | /* dataline mask for RX */ | |
594 | ret = of_property_read_u32_index(np, | |
595 | "fsl,dataline", | |
596 | 0, | |
597 | &micfil->dataline); | |
598 | if (ret) | |
599 | micfil->dataline = 1; | |
600 | ||
601 | if (micfil->dataline & ~micfil->soc->dataline) { | |
602 | dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", | |
603 | micfil->soc->dataline); | |
604 | return -EINVAL; | |
605 | } | |
606 | ||
607 | /* get IRQs */ | |
608 | for (i = 0; i < MICFIL_IRQ_LINES; i++) { | |
609 | micfil->irq[i] = platform_get_irq(pdev, i); | |
610 | dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]); | |
83b35f45 | 611 | if (micfil->irq[i] < 0) |
47a70e6f | 612 | return micfil->irq[i]; |
47a70e6f CS |
613 | } |
614 | ||
615 | if (of_property_read_bool(np, "fsl,shared-interrupt")) | |
616 | irqflag = IRQF_SHARED; | |
617 | ||
a62ed960 | 618 | /* Digital Microphone interface interrupt */ |
47a70e6f CS |
619 | ret = devm_request_irq(&pdev->dev, micfil->irq[0], |
620 | micfil_isr, irqflag, | |
621 | micfil->name, micfil); | |
622 | if (ret) { | |
623 | dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", | |
624 | micfil->irq[0]); | |
625 | return ret; | |
626 | } | |
627 | ||
a62ed960 | 628 | /* Digital Microphone interface error interrupt */ |
47a70e6f CS |
629 | ret = devm_request_irq(&pdev->dev, micfil->irq[1], |
630 | micfil_err_isr, irqflag, | |
631 | micfil->name, micfil); | |
632 | if (ret) { | |
633 | dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", | |
634 | micfil->irq[1]); | |
635 | return ret; | |
636 | } | |
637 | ||
638 | micfil->dma_params_rx.chan_name = "rx"; | |
639 | micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; | |
640 | micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; | |
641 | ||
47a70e6f CS |
642 | platform_set_drvdata(pdev, micfil); |
643 | ||
644 | pm_runtime_enable(&pdev->dev); | |
b5cf28f7 | 645 | regcache_cache_only(micfil->regmap, true); |
47a70e6f | 646 | |
0adf2920 SW |
647 | /* |
648 | * Register platform component before registering cpu dai for there | |
649 | * is not defer probe for platform component in snd_soc_add_pcm_runtime(). | |
650 | */ | |
651 | ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); | |
652 | if (ret) { | |
653 | dev_err(&pdev->dev, "failed to pcm register\n"); | |
654 | return ret; | |
655 | } | |
656 | ||
47a70e6f CS |
657 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, |
658 | &fsl_micfil_dai, 1); | |
659 | if (ret) { | |
660 | dev_err(&pdev->dev, "failed to register component %s\n", | |
661 | fsl_micfil_component.name); | |
47a70e6f CS |
662 | } |
663 | ||
47a70e6f CS |
664 | return ret; |
665 | } | |
666 | ||
47a70e6f CS |
667 | static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev) |
668 | { | |
669 | struct fsl_micfil *micfil = dev_get_drvdata(dev); | |
670 | ||
671 | regcache_cache_only(micfil->regmap, true); | |
672 | ||
673 | clk_disable_unprepare(micfil->mclk); | |
b5cf28f7 | 674 | clk_disable_unprepare(micfil->busclk); |
47a70e6f CS |
675 | |
676 | return 0; | |
677 | } | |
678 | ||
679 | static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev) | |
680 | { | |
681 | struct fsl_micfil *micfil = dev_get_drvdata(dev); | |
682 | int ret; | |
683 | ||
b5cf28f7 | 684 | ret = clk_prepare_enable(micfil->busclk); |
47a70e6f CS |
685 | if (ret < 0) |
686 | return ret; | |
687 | ||
b5cf28f7 SW |
688 | ret = clk_prepare_enable(micfil->mclk); |
689 | if (ret < 0) { | |
690 | clk_disable_unprepare(micfil->busclk); | |
691 | return ret; | |
692 | } | |
693 | ||
47a70e6f CS |
694 | regcache_cache_only(micfil->regmap, false); |
695 | regcache_mark_dirty(micfil->regmap); | |
696 | regcache_sync(micfil->regmap); | |
697 | ||
698 | return 0; | |
699 | } | |
47a70e6f | 700 | |
47a70e6f CS |
701 | static int __maybe_unused fsl_micfil_suspend(struct device *dev) |
702 | { | |
703 | pm_runtime_force_suspend(dev); | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | static int __maybe_unused fsl_micfil_resume(struct device *dev) | |
709 | { | |
710 | pm_runtime_force_resume(dev); | |
711 | ||
712 | return 0; | |
713 | } | |
47a70e6f CS |
714 | |
715 | static const struct dev_pm_ops fsl_micfil_pm_ops = { | |
716 | SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, | |
717 | fsl_micfil_runtime_resume, | |
718 | NULL) | |
719 | SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend, | |
720 | fsl_micfil_resume) | |
721 | }; | |
722 | ||
723 | static struct platform_driver fsl_micfil_driver = { | |
724 | .probe = fsl_micfil_probe, | |
725 | .driver = { | |
726 | .name = "fsl-micfil-dai", | |
727 | .pm = &fsl_micfil_pm_ops, | |
728 | .of_match_table = fsl_micfil_dt_ids, | |
729 | }, | |
730 | }; | |
731 | module_platform_driver(fsl_micfil_driver); | |
732 | ||
733 | MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>"); | |
734 | MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); | |
735 | MODULE_LICENSE("GPL v2"); |