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dbbeaad4 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Freescale ALSA SoC Digital Audio Interface (SAI) driver. | |
4 | // | |
5 | // Copyright 2012-2015 Freescale Semiconductor, Inc. | |
43550821 XL |
6 | |
7 | #include <linux/clk.h> | |
8 | #include <linux/delay.h> | |
9 | #include <linux/dmaengine.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of_address.h> | |
89c9679f | 12 | #include <linux/of_device.h> |
907e0cde | 13 | #include <linux/pm_qos.h> |
812ad463 | 14 | #include <linux/pm_runtime.h> |
78957fc3 | 15 | #include <linux/regmap.h> |
43550821 | 16 | #include <linux/slab.h> |
512feb4e | 17 | #include <linux/time.h> |
43550821 XL |
18 | #include <sound/core.h> |
19 | #include <sound/dmaengine_pcm.h> | |
20 | #include <sound/pcm_params.h> | |
4d245850 FE |
21 | #include <linux/mfd/syscon.h> |
22 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
43550821 XL |
23 | |
24 | #include "fsl_sai.h" | |
c7540644 | 25 | #include "imx-pcm.h" |
43550821 | 26 | |
e2681a1b NC |
27 | #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ |
28 | FSL_SAI_CSR_FEIE) | |
29 | ||
444c37ae | 30 | static const unsigned int fsl_sai_rates[] = { |
c5f4823b ZW |
31 | 8000, 11025, 12000, 16000, 22050, |
32 | 24000, 32000, 44100, 48000, 64000, | |
33 | 88200, 96000, 176400, 192000 | |
34 | }; | |
35 | ||
444c37ae | 36 | static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { |
c5f4823b ZW |
37 | .count = ARRAY_SIZE(fsl_sai_rates), |
38 | .list = fsl_sai_rates, | |
39 | }; | |
40 | ||
94741eba SW |
41 | /** |
42 | * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream | |
43 | * | |
44 | * SAI supports synchronous mode using bit/frame clocks of either Transmitter's | |
45 | * or Receiver's for both streams. This function is used to check if clocks of | |
46 | * the stream's are synced by the opposite stream. | |
47 | * | |
48 | * @sai: SAI context | |
49 | * @dir: stream direction | |
50 | */ | |
51 | static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) | |
52 | { | |
53 | int adir = (dir == TX) ? RX : TX; | |
54 | ||
55 | /* current dir in async mode while opposite dir in sync mode */ | |
56 | return !sai->synchronous[dir] && sai->synchronous[adir]; | |
57 | } | |
58 | ||
e2681a1b NC |
59 | static irqreturn_t fsl_sai_isr(int irq, void *devid) |
60 | { | |
61 | struct fsl_sai *sai = (struct fsl_sai *)devid; | |
4f7a0728 | 62 | unsigned int ofs = sai->soc_data->reg_offset; |
e2681a1b | 63 | struct device *dev = &sai->pdev->dev; |
413312aa NC |
64 | u32 flags, xcsr, mask; |
65 | bool irq_none = true; | |
66 | ||
67 | /* | |
68 | * Both IRQ status bits and IRQ mask bits are in the xCSR but | |
69 | * different shifts. And we here create a mask only for those | |
70 | * IRQs that we activated. | |
71 | */ | |
e2681a1b NC |
72 | mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; |
73 | ||
74 | /* Tx IRQ */ | |
4f7a0728 | 75 | regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); |
413312aa NC |
76 | flags = xcsr & mask; |
77 | ||
78 | if (flags) | |
79 | irq_none = false; | |
80 | else | |
81 | goto irq_rx; | |
e2681a1b | 82 | |
413312aa | 83 | if (flags & FSL_SAI_CSR_WSF) |
e2681a1b NC |
84 | dev_dbg(dev, "isr: Start of Tx word detected\n"); |
85 | ||
413312aa | 86 | if (flags & FSL_SAI_CSR_SEF) |
e412fcb0 | 87 | dev_dbg(dev, "isr: Tx Frame sync error detected\n"); |
e2681a1b | 88 | |
413312aa | 89 | if (flags & FSL_SAI_CSR_FEF) { |
e412fcb0 | 90 | dev_dbg(dev, "isr: Transmit underrun detected\n"); |
e2681a1b NC |
91 | /* FIFO reset for safety */ |
92 | xcsr |= FSL_SAI_CSR_FR; | |
93 | } | |
94 | ||
413312aa | 95 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
96 | dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); |
97 | ||
413312aa | 98 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
99 | dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); |
100 | ||
413312aa NC |
101 | flags &= FSL_SAI_CSR_xF_W_MASK; |
102 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
103 | ||
104 | if (flags) | |
4f7a0728 | 105 | regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); |
e2681a1b | 106 | |
413312aa | 107 | irq_rx: |
e2681a1b | 108 | /* Rx IRQ */ |
4f7a0728 | 109 | regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); |
413312aa | 110 | flags = xcsr & mask; |
e2681a1b | 111 | |
413312aa NC |
112 | if (flags) |
113 | irq_none = false; | |
114 | else | |
115 | goto out; | |
116 | ||
117 | if (flags & FSL_SAI_CSR_WSF) | |
e2681a1b NC |
118 | dev_dbg(dev, "isr: Start of Rx word detected\n"); |
119 | ||
413312aa | 120 | if (flags & FSL_SAI_CSR_SEF) |
e412fcb0 | 121 | dev_dbg(dev, "isr: Rx Frame sync error detected\n"); |
e2681a1b | 122 | |
413312aa | 123 | if (flags & FSL_SAI_CSR_FEF) { |
e412fcb0 | 124 | dev_dbg(dev, "isr: Receive overflow detected\n"); |
e2681a1b NC |
125 | /* FIFO reset for safety */ |
126 | xcsr |= FSL_SAI_CSR_FR; | |
127 | } | |
128 | ||
413312aa | 129 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
130 | dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); |
131 | ||
413312aa | 132 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
133 | dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); |
134 | ||
413312aa NC |
135 | flags &= FSL_SAI_CSR_xF_W_MASK; |
136 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
e2681a1b | 137 | |
413312aa | 138 | if (flags) |
4f7a0728 | 139 | regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); |
413312aa NC |
140 | |
141 | out: | |
142 | if (irq_none) | |
143 | return IRQ_NONE; | |
144 | else | |
145 | return IRQ_HANDLED; | |
e2681a1b NC |
146 | } |
147 | ||
c1df2964 ZW |
148 | static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, |
149 | u32 rx_mask, int slots, int slot_width) | |
150 | { | |
151 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
152 | ||
153 | sai->slots = slots; | |
154 | sai->slot_width = slot_width; | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
63d1a348 VS |
159 | static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, |
160 | unsigned int ratio) | |
161 | { | |
162 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); | |
163 | ||
164 | sai->bclk_ratio = ratio; | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
43550821 XL |
169 | static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, |
170 | int clk_id, unsigned int freq, int fsl_dir) | |
171 | { | |
43550821 | 172 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
4f7a0728 | 173 | unsigned int ofs = sai->soc_data->reg_offset; |
2a266f8b NC |
174 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
175 | u32 val_cr2 = 0; | |
633ff8f8 | 176 | |
43550821 XL |
177 | switch (clk_id) { |
178 | case FSL_SAI_CLK_BUS: | |
43550821 XL |
179 | val_cr2 |= FSL_SAI_CR2_MSEL_BUS; |
180 | break; | |
181 | case FSL_SAI_CLK_MAST1: | |
43550821 XL |
182 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; |
183 | break; | |
184 | case FSL_SAI_CLK_MAST2: | |
43550821 XL |
185 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; |
186 | break; | |
187 | case FSL_SAI_CLK_MAST3: | |
43550821 XL |
188 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; |
189 | break; | |
190 | default: | |
191 | return -EINVAL; | |
192 | } | |
633ff8f8 | 193 | |
4f7a0728 | 194 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), |
2a266f8b | 195 | FSL_SAI_CR2_MSEL_MASK, val_cr2); |
43550821 XL |
196 | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
201 | int clk_id, unsigned int freq, int dir) | |
202 | { | |
4e3a99f5 | 203 | int ret; |
43550821 XL |
204 | |
205 | if (dir == SND_SOC_CLOCK_IN) | |
206 | return 0; | |
207 | ||
43550821 XL |
208 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, |
209 | FSL_FMT_TRANSMITTER); | |
210 | if (ret) { | |
190af12d | 211 | dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); |
78957fc3 | 212 | return ret; |
43550821 XL |
213 | } |
214 | ||
215 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, | |
216 | FSL_FMT_RECEIVER); | |
78957fc3 | 217 | if (ret) |
190af12d | 218 | dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); |
43550821 | 219 | |
1fb2d9d7 | 220 | return ret; |
43550821 XL |
221 | } |
222 | ||
223 | static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, | |
224 | unsigned int fmt, int fsl_dir) | |
225 | { | |
43550821 | 226 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
4f7a0728 | 227 | unsigned int ofs = sai->soc_data->reg_offset; |
2a266f8b NC |
228 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
229 | u32 val_cr2 = 0, val_cr4 = 0; | |
43550821 | 230 | |
eadb0019 | 231 | if (!sai->is_lsb_first) |
72aa62be | 232 | val_cr4 |= FSL_SAI_CR4_MF; |
43550821 | 233 | |
13cde090 | 234 | /* DAI mode */ |
43550821 XL |
235 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
236 | case SND_SOC_DAIFMT_I2S: | |
a3f7dcc9 XL |
237 | /* |
238 | * Frame low, 1clk before data, one word length for frame sync, | |
239 | * frame sync starts one serial clock cycle earlier, | |
240 | * that is, together with the last bit of the previous | |
241 | * data word. | |
242 | */ | |
ef33bc32 | 243 | val_cr2 |= FSL_SAI_CR2_BCP; |
13cde090 XL |
244 | val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; |
245 | break; | |
246 | case SND_SOC_DAIFMT_LEFT_J: | |
a3f7dcc9 XL |
247 | /* |
248 | * Frame high, one word length for frame sync, | |
249 | * frame sync asserts with the first bit of the frame. | |
250 | */ | |
ef33bc32 | 251 | val_cr2 |= FSL_SAI_CR2_BCP; |
43550821 | 252 | break; |
a3f7dcc9 XL |
253 | case SND_SOC_DAIFMT_DSP_A: |
254 | /* | |
255 | * Frame high, 1clk before data, one bit for frame sync, | |
256 | * frame sync starts one serial clock cycle earlier, | |
257 | * that is, together with the last bit of the previous | |
258 | * data word. | |
259 | */ | |
ef33bc32 | 260 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
261 | val_cr4 |= FSL_SAI_CR4_FSE; |
262 | sai->is_dsp_mode = true; | |
263 | break; | |
264 | case SND_SOC_DAIFMT_DSP_B: | |
265 | /* | |
266 | * Frame high, one bit for frame sync, | |
267 | * frame sync asserts with the first bit of the frame. | |
268 | */ | |
ef33bc32 | 269 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
270 | sai->is_dsp_mode = true; |
271 | break; | |
13cde090 XL |
272 | case SND_SOC_DAIFMT_RIGHT_J: |
273 | /* To be done */ | |
43550821 XL |
274 | default: |
275 | return -EINVAL; | |
276 | } | |
277 | ||
13cde090 | 278 | /* DAI clock inversion */ |
43550821 XL |
279 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
280 | case SND_SOC_DAIFMT_IB_IF: | |
13cde090 XL |
281 | /* Invert both clocks */ |
282 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
283 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
284 | break; |
285 | case SND_SOC_DAIFMT_IB_NF: | |
13cde090 XL |
286 | /* Invert bit clock */ |
287 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
43550821 XL |
288 | break; |
289 | case SND_SOC_DAIFMT_NB_IF: | |
13cde090 XL |
290 | /* Invert frame clock */ |
291 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
292 | break; |
293 | case SND_SOC_DAIFMT_NB_NF: | |
13cde090 | 294 | /* Nothing to do for both normal cases */ |
43550821 XL |
295 | break; |
296 | default: | |
297 | return -EINVAL; | |
298 | } | |
299 | ||
361284a4 MB |
300 | /* DAI clock provider masks */ |
301 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { | |
302 | case SND_SOC_DAIFMT_CBC_CFC: | |
43550821 XL |
303 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; |
304 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; | |
361284a4 | 305 | sai->is_consumer_mode = false; |
43550821 | 306 | break; |
361284a4 MB |
307 | case SND_SOC_DAIFMT_CBP_CFP: |
308 | sai->is_consumer_mode = true; | |
43550821 | 309 | break; |
361284a4 | 310 | case SND_SOC_DAIFMT_CBC_CFP: |
13cde090 | 311 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; |
361284a4 | 312 | sai->is_consumer_mode = false; |
13cde090 | 313 | break; |
361284a4 | 314 | case SND_SOC_DAIFMT_CBP_CFC: |
13cde090 | 315 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; |
361284a4 | 316 | sai->is_consumer_mode = true; |
13cde090 | 317 | break; |
43550821 XL |
318 | default: |
319 | return -EINVAL; | |
320 | } | |
321 | ||
4f7a0728 | 322 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), |
2a266f8b | 323 | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); |
4f7a0728 | 324 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), |
2a266f8b NC |
325 | FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | |
326 | FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); | |
43550821 XL |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
331 | static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
332 | { | |
4e3a99f5 | 333 | int ret; |
43550821 | 334 | |
43550821 XL |
335 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); |
336 | if (ret) { | |
190af12d | 337 | dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); |
78957fc3 | 338 | return ret; |
43550821 XL |
339 | } |
340 | ||
341 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); | |
78957fc3 | 342 | if (ret) |
190af12d | 343 | dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); |
43550821 | 344 | |
1fb2d9d7 | 345 | return ret; |
43550821 XL |
346 | } |
347 | ||
c3ecef21 ZW |
348 | static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) |
349 | { | |
350 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); | |
4f7a0728 | 351 | unsigned int ofs = sai->soc_data->reg_offset; |
c3ecef21 ZW |
352 | unsigned long clk_rate; |
353 | u32 savediv = 0, ratio, savesub = freq; | |
9355a7b1 SW |
354 | int adir = tx ? RX : TX; |
355 | int dir = tx ? TX : RX; | |
c3ecef21 ZW |
356 | u32 id; |
357 | int ret = 0; | |
358 | ||
361284a4 MB |
359 | /* Don't apply to consumer mode */ |
360 | if (sai->is_consumer_mode) | |
c3ecef21 ZW |
361 | return 0; |
362 | ||
53233e40 SW |
363 | /* |
364 | * There is no point in polling MCLK0 if it is identical to MCLK1. | |
365 | * And given that MQS use case has to use MCLK1 though two clocks | |
366 | * are the same, we simply skip MCLK0 and start to find from MCLK1. | |
367 | */ | |
368 | id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; | |
369 | ||
370 | for (; id < FSL_SAI_MCLK_MAX; id++) { | |
c3ecef21 ZW |
371 | clk_rate = clk_get_rate(sai->mclk_clk[id]); |
372 | if (!clk_rate) | |
373 | continue; | |
374 | ||
375 | ratio = clk_rate / freq; | |
376 | ||
377 | ret = clk_rate - ratio * freq; | |
378 | ||
379 | /* | |
380 | * Drop the source that can not be | |
381 | * divided into the required rate. | |
382 | */ | |
383 | if (ret != 0 && clk_rate / ret < 1000) | |
384 | continue; | |
385 | ||
386 | dev_dbg(dai->dev, | |
387 | "ratio %d for freq %dHz based on clock %ldHz\n", | |
388 | ratio, freq, clk_rate); | |
389 | ||
390 | if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) | |
391 | ratio /= 2; | |
392 | else | |
393 | continue; | |
394 | ||
395 | if (ret < savesub) { | |
396 | savediv = ratio; | |
397 | sai->mclk_id[tx] = id; | |
398 | savesub = ret; | |
399 | } | |
400 | ||
401 | if (ret == 0) | |
402 | break; | |
403 | } | |
404 | ||
405 | if (savediv == 0) { | |
406 | dev_err(dai->dev, "failed to derive required %cx rate: %d\n", | |
407 | tx ? 'T' : 'R', freq); | |
408 | return -EINVAL; | |
409 | } | |
410 | ||
9cc58712 ZW |
411 | /* |
412 | * 1) For Asynchronous mode, we must set RCR2 register for capture, and | |
413 | * set TCR2 register for playback. | |
414 | * 2) For Tx sync with Rx clock, we must set RCR2 register for playback | |
415 | * and capture. | |
416 | * 3) For Rx sync with Tx clock, we must set TCR2 register for playback | |
417 | * and capture. | |
418 | * 4) For Tx and Rx are both Synchronous with another SAI, we just | |
419 | * ignore it. | |
420 | */ | |
9355a7b1 SW |
421 | if (fsl_sai_dir_is_synced(sai, adir)) { |
422 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), | |
c3ecef21 ZW |
423 | FSL_SAI_CR2_MSEL_MASK, |
424 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
9355a7b1 | 425 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), |
c3ecef21 | 426 | FSL_SAI_CR2_DIV_MASK, savediv - 1); |
9355a7b1 SW |
427 | } else if (!sai->synchronous[dir]) { |
428 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), | |
c3ecef21 ZW |
429 | FSL_SAI_CR2_MSEL_MASK, |
430 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
9355a7b1 | 431 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), |
c3ecef21 ZW |
432 | FSL_SAI_CR2_DIV_MASK, savediv - 1); |
433 | } | |
434 | ||
435 | dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", | |
436 | sai->mclk_id[tx], savediv, savesub); | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
43550821 XL |
441 | static int fsl_sai_hw_params(struct snd_pcm_substream *substream, |
442 | struct snd_pcm_hw_params *params, | |
443 | struct snd_soc_dai *cpu_dai) | |
444 | { | |
4e3a99f5 | 445 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
4f7a0728 | 446 | unsigned int ofs = sai->soc_data->reg_offset; |
2a266f8b | 447 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 448 | unsigned int channels = params_channels(params); |
4ca73043 | 449 | u32 word_width = params_width(params); |
2a266f8b | 450 | u32 val_cr4 = 0, val_cr5 = 0; |
c1df2964 ZW |
451 | u32 slots = (channels == 1) ? 2 : channels; |
452 | u32 slot_width = word_width; | |
9355a7b1 | 453 | int adir = tx ? RX : TX; |
770f58d7 | 454 | u32 pins; |
c3ecef21 ZW |
455 | int ret; |
456 | ||
c1df2964 ZW |
457 | if (sai->slots) |
458 | slots = sai->slots; | |
459 | ||
460 | if (sai->slot_width) | |
461 | slot_width = sai->slot_width; | |
462 | ||
770f58d7 SW |
463 | pins = DIV_ROUND_UP(channels, slots); |
464 | ||
361284a4 | 465 | if (!sai->is_consumer_mode) { |
63d1a348 VS |
466 | if (sai->bclk_ratio) |
467 | ret = fsl_sai_set_bclk(cpu_dai, tx, | |
468 | sai->bclk_ratio * | |
469 | params_rate(params)); | |
470 | else | |
471 | ret = fsl_sai_set_bclk(cpu_dai, tx, | |
472 | slots * slot_width * | |
473 | params_rate(params)); | |
c3ecef21 ZW |
474 | if (ret) |
475 | return ret; | |
476 | ||
477 | /* Do not enable the clock if it is already enabled */ | |
478 | if (!(sai->mclk_streams & BIT(substream->stream))) { | |
479 | ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); | |
480 | if (ret) | |
481 | return ret; | |
482 | ||
483 | sai->mclk_streams |= BIT(substream->stream); | |
484 | } | |
c3ecef21 | 485 | } |
43550821 | 486 | |
a3f7dcc9 | 487 | if (!sai->is_dsp_mode) |
c1df2964 | 488 | val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); |
a3f7dcc9 | 489 | |
c1df2964 ZW |
490 | val_cr5 |= FSL_SAI_CR5_WNW(slot_width); |
491 | val_cr5 |= FSL_SAI_CR5_W0W(slot_width); | |
43550821 | 492 | |
eadb0019 | 493 | if (sai->is_lsb_first) |
43550821 | 494 | val_cr5 |= FSL_SAI_CR5_FBT(0); |
72aa62be XL |
495 | else |
496 | val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); | |
43550821 | 497 | |
c1df2964 | 498 | val_cr4 |= FSL_SAI_CR4_FRSZ(slots); |
43550821 | 499 | |
f4c4b1bb SW |
500 | /* Set to output mode to avoid tri-stated data pins */ |
501 | if (tx) | |
502 | val_cr4 |= FSL_SAI_CR4_CHMOD; | |
503 | ||
51659ca0 | 504 | /* |
361284a4 | 505 | * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will |
51659ca0 | 506 | * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), |
7b3bee09 | 507 | * RCR5(TCR5) for playback(capture), or there will be sync error. |
51659ca0 ZW |
508 | */ |
509 | ||
361284a4 | 510 | if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { |
9355a7b1 | 511 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), |
f4c4b1bb SW |
512 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | |
513 | FSL_SAI_CR4_CHMOD_MASK, | |
9355a7b1 SW |
514 | val_cr4); |
515 | regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), | |
516 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
517 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
51659ca0 | 518 | } |
43550821 | 519 | |
eba0f007 SH |
520 | if (sai->soc_data->pins > 1) |
521 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), | |
522 | FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); | |
523 | ||
770f58d7 SW |
524 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), |
525 | FSL_SAI_CR3_TRCE_MASK, | |
526 | FSL_SAI_CR3_TRCE((1 << pins) - 1)); | |
4f7a0728 | 527 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), |
f4c4b1bb SW |
528 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | |
529 | FSL_SAI_CR4_CHMOD_MASK, | |
2a266f8b | 530 | val_cr4); |
4f7a0728 | 531 | regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), |
2a266f8b NC |
532 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | |
533 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
770f58d7 SW |
534 | regmap_write(sai->regmap, FSL_SAI_xMR(tx), |
535 | ~0UL - ((1 << min(channels, slots)) - 1)); | |
43550821 XL |
536 | |
537 | return 0; | |
538 | } | |
539 | ||
c3ecef21 ZW |
540 | static int fsl_sai_hw_free(struct snd_pcm_substream *substream, |
541 | struct snd_soc_dai *cpu_dai) | |
542 | { | |
543 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
544 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
770f58d7 SW |
545 | unsigned int ofs = sai->soc_data->reg_offset; |
546 | ||
547 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), | |
548 | FSL_SAI_CR3_TRCE_MASK, 0); | |
c3ecef21 | 549 | |
361284a4 | 550 | if (!sai->is_consumer_mode && |
c3ecef21 ZW |
551 | sai->mclk_streams & BIT(substream->stream)) { |
552 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); | |
553 | sai->mclk_streams &= ~BIT(substream->stream); | |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
94741eba SW |
559 | static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) |
560 | { | |
561 | unsigned int ofs = sai->soc_data->reg_offset; | |
562 | bool tx = dir == TX; | |
563 | u32 xcsr, count = 100; | |
564 | ||
565 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), | |
566 | FSL_SAI_CSR_TERE, 0); | |
567 | ||
568 | /* TERE will remain set till the end of current frame */ | |
569 | do { | |
570 | udelay(10); | |
571 | regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); | |
572 | } while (--count && xcsr & FSL_SAI_CSR_TERE); | |
573 | ||
574 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), | |
575 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
576 | ||
577 | /* | |
578 | * For sai master mode, after several open/close sai, | |
579 | * there will be no frame clock, and can't recover | |
580 | * anymore. Add software reset to fix this issue. | |
581 | * This is a hardware bug, and will be fix in the | |
582 | * next sai version. | |
583 | */ | |
361284a4 | 584 | if (!sai->is_consumer_mode) { |
94741eba SW |
585 | /* Software Reset */ |
586 | regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); | |
587 | /* Clear SR bit to finish the reset */ | |
588 | regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); | |
589 | } | |
590 | } | |
c3ecef21 | 591 | |
43550821 XL |
592 | static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, |
593 | struct snd_soc_dai *cpu_dai) | |
594 | { | |
595 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
4f7a0728 DB |
596 | unsigned int ofs = sai->soc_data->reg_offset; |
597 | ||
e6b39846 | 598 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
94741eba SW |
599 | int adir = tx ? RX : TX; |
600 | int dir = tx ? TX : RX; | |
601 | u32 xcsr; | |
496a39d9 | 602 | |
a3f7dcc9 | 603 | /* |
08fdf65e NC |
604 | * Asynchronous mode: Clear SYNC for both Tx and Rx. |
605 | * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. | |
606 | * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. | |
a3f7dcc9 | 607 | */ |
4f7a0728 DB |
608 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, |
609 | sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); | |
610 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, | |
08fdf65e | 611 | sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); |
43550821 | 612 | |
a3f7dcc9 XL |
613 | /* |
614 | * It is recommended that the transmitter is the last enabled | |
615 | * and the first disabled. | |
616 | */ | |
43550821 XL |
617 | switch (cmd) { |
618 | case SNDRV_PCM_TRIGGER_START: | |
619 | case SNDRV_PCM_TRIGGER_RESUME: | |
620 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
4f7a0728 | 621 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), |
a3fdc674 NC |
622 | FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); |
623 | ||
94741eba | 624 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), |
f4075a8f | 625 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); |
94741eba SW |
626 | /* |
627 | * Enable the opposite direction for synchronous mode | |
628 | * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx | |
629 | * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx | |
630 | * | |
631 | * RM recommends to enable RE after TE for case 1 and to enable | |
632 | * TE after RE for case 2, but we here may not always guarantee | |
633 | * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables | |
634 | * TE after RE, which is against what RM recommends but should | |
635 | * be safe to do, judging by years of testing results. | |
636 | */ | |
637 | if (fsl_sai_dir_is_synced(sai, adir)) | |
638 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), | |
639 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
e5d0fa9c | 640 | |
4f7a0728 | 641 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), |
8abba5d6 | 642 | FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); |
43550821 | 643 | break; |
43550821 XL |
644 | case SNDRV_PCM_TRIGGER_STOP: |
645 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
646 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
4f7a0728 | 647 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), |
e6b39846 | 648 | FSL_SAI_CSR_FRDE, 0); |
4f7a0728 | 649 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), |
8abba5d6 | 650 | FSL_SAI_CSR_xIE_MASK, 0); |
e6b39846 | 651 | |
f84526cf | 652 | /* Check if the opposite FRDE is also disabled */ |
4f7a0728 | 653 | regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); |
94741eba SW |
654 | |
655 | /* | |
656 | * If opposite stream provides clocks for synchronous mode and | |
657 | * it is inactive, disable it before disabling the current one | |
658 | */ | |
659 | if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) | |
660 | fsl_sai_config_disable(sai, adir); | |
661 | ||
662 | /* | |
663 | * Disable current stream if either of: | |
664 | * 1. current stream doesn't provide clocks for synchronous mode | |
665 | * 2. current stream provides clocks for synchronous mode but no | |
666 | * more stream is active. | |
667 | */ | |
668 | if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) | |
669 | fsl_sai_config_disable(sai, dir); | |
670 | ||
43550821 XL |
671 | break; |
672 | default: | |
673 | return -EINVAL; | |
674 | } | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
679 | static int fsl_sai_startup(struct snd_pcm_substream *substream, | |
680 | struct snd_soc_dai *cpu_dai) | |
681 | { | |
43550821 | 682 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 683 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
ca3e35c7 NC |
684 | int ret; |
685 | ||
e75f4940 MS |
686 | /* |
687 | * EDMA controller needs period size to be a multiple of | |
688 | * tx/rx maxburst | |
689 | */ | |
690 | if (sai->soc_data->use_edma) | |
691 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
692 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
693 | tx ? sai->dma_params_tx.maxburst : | |
694 | sai->dma_params_rx.maxburst); | |
695 | ||
c5f4823b ZW |
696 | ret = snd_pcm_hw_constraint_list(substream->runtime, 0, |
697 | SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); | |
698 | ||
699 | return ret; | |
43550821 XL |
700 | } |
701 | ||
43550821 | 702 | static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { |
63d1a348 | 703 | .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, |
43550821 XL |
704 | .set_sysclk = fsl_sai_set_dai_sysclk, |
705 | .set_fmt = fsl_sai_set_dai_fmt, | |
c1df2964 | 706 | .set_tdm_slot = fsl_sai_set_dai_tdm_slot, |
43550821 | 707 | .hw_params = fsl_sai_hw_params, |
c3ecef21 | 708 | .hw_free = fsl_sai_hw_free, |
43550821 XL |
709 | .trigger = fsl_sai_trigger, |
710 | .startup = fsl_sai_startup, | |
43550821 XL |
711 | }; |
712 | ||
713 | static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) | |
714 | { | |
715 | struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); | |
4f7a0728 | 716 | unsigned int ofs = sai->soc_data->reg_offset; |
e6dc12d7 | 717 | |
376d1a92 | 718 | /* Software Reset for both Tx and Rx */ |
4f7a0728 DB |
719 | regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); |
720 | regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); | |
376d1a92 | 721 | /* Clear SR bit to finish the reset */ |
4f7a0728 DB |
722 | regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); |
723 | regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); | |
376d1a92 | 724 | |
4f7a0728 | 725 | regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), |
5aef1ff2 | 726 | FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), |
bd517707 | 727 | sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); |
4f7a0728 | 728 | regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), |
5aef1ff2 SW |
729 | FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), |
730 | FSL_SAI_MAXBURST_RX - 1); | |
43550821 | 731 | |
dd9f4060 XL |
732 | snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, |
733 | &sai->dma_params_rx); | |
43550821 | 734 | |
43550821 XL |
735 | return 0; |
736 | } | |
737 | ||
22a16145 | 738 | static struct snd_soc_dai_driver fsl_sai_dai_template = { |
43550821 | 739 | .probe = fsl_sai_dai_probe, |
43550821 | 740 | .playback = { |
20d5b76f | 741 | .stream_name = "CPU-Playback", |
43550821 | 742 | .channels_min = 1, |
4957b556 | 743 | .channels_max = 32, |
c5f4823b ZW |
744 | .rate_min = 8000, |
745 | .rate_max = 192000, | |
746 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
747 | .formats = FSL_SAI_FORMATS, |
748 | }, | |
749 | .capture = { | |
20d5b76f | 750 | .stream_name = "CPU-Capture", |
43550821 | 751 | .channels_min = 1, |
4957b556 | 752 | .channels_max = 32, |
c5f4823b ZW |
753 | .rate_min = 8000, |
754 | .rate_max = 192000, | |
755 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
756 | .formats = FSL_SAI_FORMATS, |
757 | }, | |
758 | .ops = &fsl_sai_pcm_dai_ops, | |
759 | }; | |
760 | ||
761 | static const struct snd_soc_component_driver fsl_component = { | |
762 | .name = "fsl-sai", | |
763 | }; | |
764 | ||
4f7a0728 DB |
765 | static struct reg_default fsl_sai_reg_defaults_ofs0[] = { |
766 | {FSL_SAI_TCR1(0), 0}, | |
767 | {FSL_SAI_TCR2(0), 0}, | |
768 | {FSL_SAI_TCR3(0), 0}, | |
769 | {FSL_SAI_TCR4(0), 0}, | |
770 | {FSL_SAI_TCR5(0), 0}, | |
5f0ac20e DB |
771 | {FSL_SAI_TDR0, 0}, |
772 | {FSL_SAI_TDR1, 0}, | |
773 | {FSL_SAI_TDR2, 0}, | |
774 | {FSL_SAI_TDR3, 0}, | |
775 | {FSL_SAI_TDR4, 0}, | |
776 | {FSL_SAI_TDR5, 0}, | |
777 | {FSL_SAI_TDR6, 0}, | |
778 | {FSL_SAI_TDR7, 0}, | |
4f7a0728 DB |
779 | {FSL_SAI_TMR, 0}, |
780 | {FSL_SAI_RCR1(0), 0}, | |
781 | {FSL_SAI_RCR2(0), 0}, | |
782 | {FSL_SAI_RCR3(0), 0}, | |
783 | {FSL_SAI_RCR4(0), 0}, | |
784 | {FSL_SAI_RCR5(0), 0}, | |
785 | {FSL_SAI_RMR, 0}, | |
786 | }; | |
787 | ||
788 | static struct reg_default fsl_sai_reg_defaults_ofs8[] = { | |
789 | {FSL_SAI_TCR1(8), 0}, | |
790 | {FSL_SAI_TCR2(8), 0}, | |
791 | {FSL_SAI_TCR3(8), 0}, | |
792 | {FSL_SAI_TCR4(8), 0}, | |
793 | {FSL_SAI_TCR5(8), 0}, | |
794 | {FSL_SAI_TDR0, 0}, | |
795 | {FSL_SAI_TDR1, 0}, | |
796 | {FSL_SAI_TDR2, 0}, | |
797 | {FSL_SAI_TDR3, 0}, | |
798 | {FSL_SAI_TDR4, 0}, | |
799 | {FSL_SAI_TDR5, 0}, | |
800 | {FSL_SAI_TDR6, 0}, | |
801 | {FSL_SAI_TDR7, 0}, | |
802 | {FSL_SAI_TMR, 0}, | |
803 | {FSL_SAI_RCR1(8), 0}, | |
804 | {FSL_SAI_RCR2(8), 0}, | |
805 | {FSL_SAI_RCR3(8), 0}, | |
806 | {FSL_SAI_RCR4(8), 0}, | |
807 | {FSL_SAI_RCR5(8), 0}, | |
808 | {FSL_SAI_RMR, 0}, | |
0b2cbce6 SW |
809 | {FSL_SAI_MCTL, 0}, |
810 | {FSL_SAI_MDIV, 0}, | |
3f6f5b0c ZW |
811 | }; |
812 | ||
78957fc3 XL |
813 | static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) |
814 | { | |
4f7a0728 DB |
815 | struct fsl_sai *sai = dev_get_drvdata(dev); |
816 | unsigned int ofs = sai->soc_data->reg_offset; | |
817 | ||
818 | if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) | |
819 | return true; | |
820 | ||
821 | if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) | |
822 | return true; | |
823 | ||
78957fc3 | 824 | switch (reg) { |
5f0ac20e DB |
825 | case FSL_SAI_TFR0: |
826 | case FSL_SAI_TFR1: | |
827 | case FSL_SAI_TFR2: | |
828 | case FSL_SAI_TFR3: | |
829 | case FSL_SAI_TFR4: | |
830 | case FSL_SAI_TFR5: | |
831 | case FSL_SAI_TFR6: | |
832 | case FSL_SAI_TFR7: | |
78957fc3 | 833 | case FSL_SAI_TMR: |
5f0ac20e DB |
834 | case FSL_SAI_RDR0: |
835 | case FSL_SAI_RDR1: | |
836 | case FSL_SAI_RDR2: | |
837 | case FSL_SAI_RDR3: | |
838 | case FSL_SAI_RDR4: | |
839 | case FSL_SAI_RDR5: | |
840 | case FSL_SAI_RDR6: | |
841 | case FSL_SAI_RDR7: | |
842 | case FSL_SAI_RFR0: | |
843 | case FSL_SAI_RFR1: | |
844 | case FSL_SAI_RFR2: | |
845 | case FSL_SAI_RFR3: | |
846 | case FSL_SAI_RFR4: | |
847 | case FSL_SAI_RFR5: | |
848 | case FSL_SAI_RFR6: | |
849 | case FSL_SAI_RFR7: | |
78957fc3 | 850 | case FSL_SAI_RMR: |
0b2cbce6 SW |
851 | case FSL_SAI_MCTL: |
852 | case FSL_SAI_MDIV: | |
853 | case FSL_SAI_VERID: | |
854 | case FSL_SAI_PARAM: | |
855 | case FSL_SAI_TTCTN: | |
856 | case FSL_SAI_RTCTN: | |
857 | case FSL_SAI_TTCTL: | |
858 | case FSL_SAI_TBCTN: | |
859 | case FSL_SAI_TTCAP: | |
860 | case FSL_SAI_RTCTL: | |
861 | case FSL_SAI_RBCTN: | |
862 | case FSL_SAI_RTCAP: | |
78957fc3 XL |
863 | return true; |
864 | default: | |
865 | return false; | |
866 | } | |
867 | } | |
868 | ||
869 | static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) | |
870 | { | |
4f7a0728 DB |
871 | struct fsl_sai *sai = dev_get_drvdata(dev); |
872 | unsigned int ofs = sai->soc_data->reg_offset; | |
873 | ||
874 | if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) | |
875 | return true; | |
876 | ||
0b2cbce6 SW |
877 | /* Set VERID and PARAM be volatile for reading value in probe */ |
878 | if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) | |
879 | return true; | |
880 | ||
78957fc3 | 881 | switch (reg) { |
5f0ac20e DB |
882 | case FSL_SAI_TFR0: |
883 | case FSL_SAI_TFR1: | |
884 | case FSL_SAI_TFR2: | |
885 | case FSL_SAI_TFR3: | |
886 | case FSL_SAI_TFR4: | |
887 | case FSL_SAI_TFR5: | |
888 | case FSL_SAI_TFR6: | |
889 | case FSL_SAI_TFR7: | |
890 | case FSL_SAI_RFR0: | |
891 | case FSL_SAI_RFR1: | |
892 | case FSL_SAI_RFR2: | |
893 | case FSL_SAI_RFR3: | |
894 | case FSL_SAI_RFR4: | |
895 | case FSL_SAI_RFR5: | |
896 | case FSL_SAI_RFR6: | |
897 | case FSL_SAI_RFR7: | |
898 | case FSL_SAI_RDR0: | |
899 | case FSL_SAI_RDR1: | |
900 | case FSL_SAI_RDR2: | |
901 | case FSL_SAI_RDR3: | |
902 | case FSL_SAI_RDR4: | |
903 | case FSL_SAI_RDR5: | |
904 | case FSL_SAI_RDR6: | |
905 | case FSL_SAI_RDR7: | |
78957fc3 XL |
906 | return true; |
907 | default: | |
908 | return false; | |
909 | } | |
78957fc3 XL |
910 | } |
911 | ||
912 | static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) | |
913 | { | |
4f7a0728 DB |
914 | struct fsl_sai *sai = dev_get_drvdata(dev); |
915 | unsigned int ofs = sai->soc_data->reg_offset; | |
916 | ||
917 | if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) | |
918 | return true; | |
919 | ||
920 | if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) | |
921 | return true; | |
922 | ||
78957fc3 | 923 | switch (reg) { |
5f0ac20e DB |
924 | case FSL_SAI_TDR0: |
925 | case FSL_SAI_TDR1: | |
926 | case FSL_SAI_TDR2: | |
927 | case FSL_SAI_TDR3: | |
928 | case FSL_SAI_TDR4: | |
929 | case FSL_SAI_TDR5: | |
930 | case FSL_SAI_TDR6: | |
931 | case FSL_SAI_TDR7: | |
78957fc3 | 932 | case FSL_SAI_TMR: |
78957fc3 | 933 | case FSL_SAI_RMR: |
0b2cbce6 SW |
934 | case FSL_SAI_MCTL: |
935 | case FSL_SAI_MDIV: | |
936 | case FSL_SAI_TTCTL: | |
937 | case FSL_SAI_RTCTL: | |
78957fc3 XL |
938 | return true; |
939 | default: | |
940 | return false; | |
941 | } | |
942 | } | |
943 | ||
4f7a0728 | 944 | static struct regmap_config fsl_sai_regmap_config = { |
78957fc3 XL |
945 | .reg_bits = 32, |
946 | .reg_stride = 4, | |
947 | .val_bits = 32, | |
6d19d8a3 | 948 | .fast_io = true, |
78957fc3 XL |
949 | |
950 | .max_register = FSL_SAI_RMR, | |
4f7a0728 DB |
951 | .reg_defaults = fsl_sai_reg_defaults_ofs0, |
952 | .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), | |
78957fc3 XL |
953 | .readable_reg = fsl_sai_readable_reg, |
954 | .volatile_reg = fsl_sai_volatile_reg, | |
955 | .writeable_reg = fsl_sai_writeable_reg, | |
1fde5e83 | 956 | .cache_type = REGCACHE_FLAT, |
78957fc3 XL |
957 | }; |
958 | ||
1dc658b1 SW |
959 | static int fsl_sai_check_version(struct device *dev) |
960 | { | |
961 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
962 | unsigned char ofs = sai->soc_data->reg_offset; | |
963 | unsigned int val; | |
964 | int ret; | |
965 | ||
966 | if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) | |
967 | return 0; | |
968 | ||
969 | ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); | |
970 | if (ret < 0) | |
971 | return ret; | |
972 | ||
973 | dev_dbg(dev, "VERID: 0x%016X\n", val); | |
974 | ||
975 | sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >> | |
976 | FSL_SAI_VERID_MAJOR_SHIFT; | |
977 | sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >> | |
978 | FSL_SAI_VERID_MINOR_SHIFT; | |
979 | sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; | |
980 | ||
981 | ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); | |
982 | if (ret < 0) | |
983 | return ret; | |
984 | ||
985 | dev_dbg(dev, "PARAM: 0x%016X\n", val); | |
986 | ||
987 | /* Max slots per frame, power of 2 */ | |
988 | sai->param.slot_num = 1 << | |
989 | ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); | |
990 | ||
991 | /* Words per fifo, power of 2 */ | |
992 | sai->param.fifo_depth = 1 << | |
993 | ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); | |
994 | ||
995 | /* Number of datalines implemented */ | |
996 | sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
2277e7e3 SW |
1001 | static int fsl_sai_runtime_suspend(struct device *dev); |
1002 | static int fsl_sai_runtime_resume(struct device *dev); | |
1003 | ||
43550821 XL |
1004 | static int fsl_sai_probe(struct platform_device *pdev) |
1005 | { | |
4e3a99f5 | 1006 | struct device_node *np = pdev->dev.of_node; |
43550821 | 1007 | struct fsl_sai *sai; |
4d245850 | 1008 | struct regmap *gpr; |
43550821 | 1009 | struct resource *res; |
78957fc3 | 1010 | void __iomem *base; |
ca3e35c7 NC |
1011 | char tmp[8]; |
1012 | int irq, ret, i; | |
4d245850 | 1013 | int index; |
43550821 XL |
1014 | |
1015 | sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); | |
1016 | if (!sai) | |
1017 | return -ENOMEM; | |
1018 | ||
e2681a1b | 1019 | sai->pdev = pdev; |
89c9679f | 1020 | sai->soc_data = of_device_get_match_data(&pdev->dev); |
c7540644 | 1021 | |
eadb0019 | 1022 | sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); |
78957fc3 | 1023 | |
664107f6 | 1024 | base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
78957fc3 XL |
1025 | if (IS_ERR(base)) |
1026 | return PTR_ERR(base); | |
1027 | ||
4f7a0728 DB |
1028 | if (sai->soc_data->reg_offset == 8) { |
1029 | fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; | |
0b2cbce6 | 1030 | fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; |
4f7a0728 DB |
1031 | fsl_sai_regmap_config.num_reg_defaults = |
1032 | ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); | |
1033 | } | |
1034 | ||
2277e7e3 | 1035 | sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, &fsl_sai_regmap_config); |
78957fc3 XL |
1036 | if (IS_ERR(sai->regmap)) { |
1037 | dev_err(&pdev->dev, "regmap init failed\n"); | |
1038 | return PTR_ERR(sai->regmap); | |
43550821 XL |
1039 | } |
1040 | ||
ca3e35c7 | 1041 | sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); |
2277e7e3 SW |
1042 | /* Compatible with old DTB cases */ |
1043 | if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) | |
1044 | sai->bus_clk = devm_clk_get(&pdev->dev, "sai"); | |
ca3e35c7 NC |
1045 | if (IS_ERR(sai->bus_clk)) { |
1046 | dev_err(&pdev->dev, "failed to get bus clock: %ld\n", | |
1047 | PTR_ERR(sai->bus_clk)); | |
2277e7e3 SW |
1048 | /* -EPROBE_DEFER */ |
1049 | return PTR_ERR(sai->bus_clk); | |
ca3e35c7 NC |
1050 | } |
1051 | ||
c3ecef21 ZW |
1052 | for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { |
1053 | sprintf(tmp, "mclk%d", i); | |
ca3e35c7 NC |
1054 | sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); |
1055 | if (IS_ERR(sai->mclk_clk[i])) { | |
1056 | dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", | |
1057 | i + 1, PTR_ERR(sai->mclk_clk[i])); | |
1058 | sai->mclk_clk[i] = NULL; | |
1059 | } | |
1060 | } | |
1061 | ||
53233e40 SW |
1062 | if (sai->soc_data->mclk0_is_mclk1) |
1063 | sai->mclk_clk[0] = sai->mclk_clk[1]; | |
1064 | else | |
1065 | sai->mclk_clk[0] = sai->bus_clk; | |
1066 | ||
e2681a1b | 1067 | irq = platform_get_irq(pdev, 0); |
cf9441ad | 1068 | if (irq < 0) |
e2681a1b | 1069 | return irq; |
e2681a1b | 1070 | |
2eb2d314 MW |
1071 | ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED, |
1072 | np->name, sai); | |
e2681a1b NC |
1073 | if (ret) { |
1074 | dev_err(&pdev->dev, "failed to claim irq %u\n", irq); | |
1075 | return ret; | |
1076 | } | |
1077 | ||
22a16145 SW |
1078 | memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, |
1079 | sizeof(fsl_sai_dai_template)); | |
1080 | ||
08fdf65e NC |
1081 | /* Sync Tx with Rx as default by following old DT binding */ |
1082 | sai->synchronous[RX] = true; | |
1083 | sai->synchronous[TX] = false; | |
cb2f6927 | 1084 | sai->cpu_dai_drv.symmetric_rate = 1; |
22a16145 | 1085 | sai->cpu_dai_drv.symmetric_channels = 1; |
cb2f6927 | 1086 | sai->cpu_dai_drv.symmetric_sample_bits = 1; |
08fdf65e | 1087 | |
ce7344a4 NC |
1088 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && |
1089 | of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
1090 | /* error out if both synchronous and asynchronous are present */ | |
1091 | dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); | |
1092 | return -EINVAL; | |
1093 | } | |
1094 | ||
08fdf65e NC |
1095 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { |
1096 | /* Sync Rx with Tx */ | |
1097 | sai->synchronous[RX] = false; | |
1098 | sai->synchronous[TX] = true; | |
1099 | } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
1100 | /* Discard all settings for asynchronous mode */ | |
1101 | sai->synchronous[RX] = false; | |
1102 | sai->synchronous[TX] = false; | |
cb2f6927 | 1103 | sai->cpu_dai_drv.symmetric_rate = 0; |
22a16145 | 1104 | sai->cpu_dai_drv.symmetric_channels = 0; |
cb2f6927 | 1105 | sai->cpu_dai_drv.symmetric_sample_bits = 0; |
08fdf65e NC |
1106 | } |
1107 | ||
4d245850 | 1108 | if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && |
6ea9c7dd | 1109 | of_device_is_compatible(np, "fsl,imx6ul-sai")) { |
4d245850 FE |
1110 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); |
1111 | if (IS_ERR(gpr)) { | |
1112 | dev_err(&pdev->dev, "cannot find iomuxc registers\n"); | |
1113 | return PTR_ERR(gpr); | |
1114 | } | |
1115 | ||
1116 | index = of_alias_get_id(np, "sai"); | |
1117 | if (index < 0) | |
1118 | return index; | |
1119 | ||
1120 | regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), | |
1121 | MCLK_DIR(index)); | |
1122 | } | |
1123 | ||
5f0ac20e DB |
1124 | sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; |
1125 | sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; | |
43550821 XL |
1126 | sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; |
1127 | sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; | |
1128 | ||
43550821 | 1129 | platform_set_drvdata(pdev, sai); |
2277e7e3 SW |
1130 | pm_runtime_enable(&pdev->dev); |
1131 | if (!pm_runtime_enabled(&pdev->dev)) { | |
1132 | ret = fsl_sai_runtime_resume(&pdev->dev); | |
1133 | if (ret) | |
1134 | goto err_pm_disable; | |
1135 | } | |
1136 | ||
1137 | ret = pm_runtime_get_sync(&pdev->dev); | |
1138 | if (ret < 0) { | |
1139 | pm_runtime_put_noidle(&pdev->dev); | |
1140 | goto err_pm_get_sync; | |
1141 | } | |
43550821 | 1142 | |
1dc658b1 SW |
1143 | /* Get sai version */ |
1144 | ret = fsl_sai_check_version(&pdev->dev); | |
1145 | if (ret < 0) | |
1146 | dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret); | |
1147 | ||
a57d4e87 SW |
1148 | /* Select MCLK direction */ |
1149 | if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && | |
1150 | sai->verid.major >= 3 && sai->verid.minor >= 1) { | |
1151 | regmap_update_bits(sai->regmap, FSL_SAI_MCTL, | |
1152 | FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); | |
1153 | } | |
1154 | ||
2277e7e3 SW |
1155 | ret = pm_runtime_put_sync(&pdev->dev); |
1156 | if (ret < 0) | |
1157 | goto err_pm_get_sync; | |
812ad463 | 1158 | |
9c3ad33b SW |
1159 | /* |
1160 | * Register platform component before registering cpu dai for there | |
1161 | * is not defer probe for platform component in snd_soc_add_pcm_runtime(). | |
1162 | */ | |
d1520889 OS |
1163 | if (sai->soc_data->use_imx_pcm) { |
1164 | ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); | |
1165 | if (ret) | |
2277e7e3 | 1166 | goto err_pm_get_sync; |
d1520889 OS |
1167 | } else { |
1168 | ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); | |
1169 | if (ret) | |
2277e7e3 | 1170 | goto err_pm_get_sync; |
d1520889 OS |
1171 | } |
1172 | ||
9c3ad33b SW |
1173 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, |
1174 | &sai->cpu_dai_drv, 1); | |
1175 | if (ret) | |
1176 | goto err_pm_get_sync; | |
1177 | ||
d1520889 OS |
1178 | return ret; |
1179 | ||
2277e7e3 SW |
1180 | err_pm_get_sync: |
1181 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
1182 | fsl_sai_runtime_suspend(&pdev->dev); | |
d1520889 OS |
1183 | err_pm_disable: |
1184 | pm_runtime_disable(&pdev->dev); | |
1185 | ||
1186 | return ret; | |
43550821 XL |
1187 | } |
1188 | ||
812ad463 DB |
1189 | static int fsl_sai_remove(struct platform_device *pdev) |
1190 | { | |
1191 | pm_runtime_disable(&pdev->dev); | |
2277e7e3 SW |
1192 | if (!pm_runtime_status_suspended(&pdev->dev)) |
1193 | fsl_sai_runtime_suspend(&pdev->dev); | |
b46ea8f4 NC |
1194 | |
1195 | return 0; | |
812ad463 DB |
1196 | } |
1197 | ||
89c9679f LS |
1198 | static const struct fsl_sai_soc_data fsl_sai_vf610_data = { |
1199 | .use_imx_pcm = false, | |
e75f4940 | 1200 | .use_edma = false, |
bd517707 | 1201 | .fifo_depth = 32, |
eba0f007 | 1202 | .pins = 1, |
4f7a0728 | 1203 | .reg_offset = 0, |
53233e40 | 1204 | .mclk0_is_mclk1 = false, |
907e0cde | 1205 | .flags = 0, |
89c9679f LS |
1206 | }; |
1207 | ||
1208 | static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { | |
1209 | .use_imx_pcm = true, | |
e75f4940 | 1210 | .use_edma = false, |
bd517707 | 1211 | .fifo_depth = 32, |
eba0f007 | 1212 | .pins = 1, |
4f7a0728 | 1213 | .reg_offset = 0, |
53233e40 | 1214 | .mclk0_is_mclk1 = true, |
907e0cde | 1215 | .flags = 0, |
89c9679f LS |
1216 | }; |
1217 | ||
a860fac4 DB |
1218 | static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { |
1219 | .use_imx_pcm = true, | |
e75f4940 | 1220 | .use_edma = false, |
a860fac4 | 1221 | .fifo_depth = 16, |
eba0f007 | 1222 | .pins = 2, |
a860fac4 | 1223 | .reg_offset = 8, |
53233e40 | 1224 | .mclk0_is_mclk1 = false, |
907e0cde | 1225 | .flags = PMQOS_CPU_LATENCY, |
a860fac4 DB |
1226 | }; |
1227 | ||
1228 | static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { | |
1229 | .use_imx_pcm = true, | |
e75f4940 | 1230 | .use_edma = false, |
a860fac4 | 1231 | .fifo_depth = 128, |
eba0f007 | 1232 | .pins = 8, |
a860fac4 | 1233 | .reg_offset = 8, |
53233e40 | 1234 | .mclk0_is_mclk1 = false, |
907e0cde | 1235 | .flags = 0, |
a860fac4 DB |
1236 | }; |
1237 | ||
6eeb60be DB |
1238 | static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { |
1239 | .use_imx_pcm = true, | |
e75f4940 | 1240 | .use_edma = true, |
6eeb60be | 1241 | .fifo_depth = 64, |
eba0f007 | 1242 | .pins = 1, |
6eeb60be | 1243 | .reg_offset = 0, |
53233e40 | 1244 | .mclk0_is_mclk1 = false, |
907e0cde | 1245 | .flags = 0, |
6eeb60be DB |
1246 | }; |
1247 | ||
43550821 | 1248 | static const struct of_device_id fsl_sai_ids[] = { |
89c9679f LS |
1249 | { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, |
1250 | { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, | |
1251 | { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, | |
a860fac4 DB |
1252 | { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, |
1253 | { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, | |
6eeb60be | 1254 | { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, |
43550821 XL |
1255 | { /* sentinel */ } |
1256 | }; | |
c759241f | 1257 | MODULE_DEVICE_TABLE(of, fsl_sai_ids); |
43550821 | 1258 | |
812ad463 | 1259 | static int fsl_sai_runtime_suspend(struct device *dev) |
1fde5e83 ZW |
1260 | { |
1261 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
1262 | ||
c0ffbd64 SW |
1263 | if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) |
1264 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); | |
1265 | ||
1266 | if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) | |
1267 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); | |
1268 | ||
1269 | clk_disable_unprepare(sai->bus_clk); | |
1270 | ||
907e0cde SW |
1271 | if (sai->soc_data->flags & PMQOS_CPU_LATENCY) |
1272 | cpu_latency_qos_remove_request(&sai->pm_qos_req); | |
1273 | ||
1fde5e83 | 1274 | regcache_cache_only(sai->regmap, true); |
1fde5e83 ZW |
1275 | |
1276 | return 0; | |
1277 | } | |
1278 | ||
812ad463 | 1279 | static int fsl_sai_runtime_resume(struct device *dev) |
1fde5e83 ZW |
1280 | { |
1281 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
4f7a0728 | 1282 | unsigned int ofs = sai->soc_data->reg_offset; |
c0ffbd64 SW |
1283 | int ret; |
1284 | ||
1285 | ret = clk_prepare_enable(sai->bus_clk); | |
1286 | if (ret) { | |
1287 | dev_err(dev, "failed to enable bus clock: %d\n", ret); | |
1288 | return ret; | |
1289 | } | |
1290 | ||
1291 | if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { | |
1292 | ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); | |
1293 | if (ret) | |
1294 | goto disable_bus_clk; | |
1295 | } | |
1296 | ||
1297 | if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { | |
1298 | ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); | |
1299 | if (ret) | |
1300 | goto disable_tx_clk; | |
1301 | } | |
1fde5e83 | 1302 | |
907e0cde SW |
1303 | if (sai->soc_data->flags & PMQOS_CPU_LATENCY) |
1304 | cpu_latency_qos_add_request(&sai->pm_qos_req, 0); | |
1305 | ||
1fde5e83 | 1306 | regcache_cache_only(sai->regmap, false); |
d8d702e1 | 1307 | regcache_mark_dirty(sai->regmap); |
4f7a0728 DB |
1308 | regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); |
1309 | regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); | |
512feb4e | 1310 | usleep_range(1000, 2000); |
4f7a0728 DB |
1311 | regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); |
1312 | regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); | |
c0ffbd64 SW |
1313 | |
1314 | ret = regcache_sync(sai->regmap); | |
1315 | if (ret) | |
1316 | goto disable_rx_clk; | |
1317 | ||
1318 | return 0; | |
1319 | ||
1320 | disable_rx_clk: | |
1321 | if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) | |
1322 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); | |
1323 | disable_tx_clk: | |
1324 | if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) | |
1325 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); | |
1326 | disable_bus_clk: | |
1327 | clk_disable_unprepare(sai->bus_clk); | |
1328 | ||
1329 | return ret; | |
1fde5e83 | 1330 | } |
1fde5e83 ZW |
1331 | |
1332 | static const struct dev_pm_ops fsl_sai_pm_ops = { | |
812ad463 DB |
1333 | SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, |
1334 | fsl_sai_runtime_resume, NULL) | |
1335 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
1336 | pm_runtime_force_resume) | |
1fde5e83 ZW |
1337 | }; |
1338 | ||
43550821 XL |
1339 | static struct platform_driver fsl_sai_driver = { |
1340 | .probe = fsl_sai_probe, | |
812ad463 | 1341 | .remove = fsl_sai_remove, |
43550821 XL |
1342 | .driver = { |
1343 | .name = "fsl-sai", | |
1fde5e83 | 1344 | .pm = &fsl_sai_pm_ops, |
43550821 XL |
1345 | .of_match_table = fsl_sai_ids, |
1346 | }, | |
1347 | }; | |
1348 | module_platform_driver(fsl_sai_driver); | |
1349 | ||
1350 | MODULE_DESCRIPTION("Freescale Soc SAI Interface"); | |
1351 | MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); | |
1352 | MODULE_ALIAS("platform:fsl-sai"); | |
1353 | MODULE_LICENSE("GPL"); |