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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
17467f23 TT |
11 | */ |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/delay.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
f0fba2ad | 19 | #include <linux/of_platform.h> |
17467f23 | 20 | |
17467f23 TT |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/soc.h> | |
26 | ||
17467f23 TT |
27 | #include "fsl_ssi.h" |
28 | ||
29 | /** | |
30 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
31 | * | |
32 | * This driver currently only supports the SSI running in I2S slave mode, | |
33 | * which means the codec determines the sample rate. Therefore, we tell | |
34 | * ALSA that we support all rates and let the codec driver decide what rates | |
35 | * are really supported. | |
36 | */ | |
37 | #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ | |
38 | SNDRV_PCM_RATE_CONTINUOUS) | |
39 | ||
40 | /** | |
41 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
42 | * | |
43 | * This driver currently only supports the SSI running in I2S slave mode. | |
44 | * | |
45 | * The SSI has a limitation in that the samples must be in the same byte | |
46 | * order as the host CPU. This is because when multiple bytes are written | |
47 | * to the STX register, the bytes and bits must be written in the same | |
48 | * order. The STX is a shift register, so all the bits need to be aligned | |
49 | * (bit-endianness must match byte-endianness). Processors typically write | |
50 | * the bits within a byte in the same order that the bytes of a word are | |
51 | * written in. So if the host CPU is big-endian, then only big-endian | |
52 | * samples will be written to STX properly. | |
53 | */ | |
54 | #ifdef __BIG_ENDIAN | |
55 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
56 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
57 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
58 | #else | |
59 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
60 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
61 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
62 | #endif | |
63 | ||
d5a908b2 TT |
64 | /* SIER bitflag of interrupts to enable */ |
65 | #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ | |
66 | CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ | |
67 | CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ | |
68 | CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ | |
69 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) | |
70 | ||
17467f23 TT |
71 | /** |
72 | * fsl_ssi_private: per-SSI private data | |
73 | * | |
17467f23 TT |
74 | * @ssi: pointer to the SSI's registers |
75 | * @ssi_phys: physical address of the SSI registers | |
76 | * @irq: IRQ of this SSI | |
be41e941 TT |
77 | * @first_stream: pointer to the stream that was opened first |
78 | * @second_stream: pointer to second stream | |
17467f23 TT |
79 | * @playback: the number of playback streams opened |
80 | * @capture: the number of capture streams opened | |
a454dad1 | 81 | * @asynchronous: 0=synchronous mode, 1=asynchronous mode |
17467f23 TT |
82 | * @cpu_dai: the CPU DAI for this device |
83 | * @dev_attr: the sysfs device attribute structure | |
84 | * @stats: SSI statistics | |
f0fba2ad | 85 | * @name: name for this device |
17467f23 TT |
86 | */ |
87 | struct fsl_ssi_private { | |
17467f23 TT |
88 | struct ccsr_ssi __iomem *ssi; |
89 | dma_addr_t ssi_phys; | |
90 | unsigned int irq; | |
be41e941 TT |
91 | struct snd_pcm_substream *first_stream; |
92 | struct snd_pcm_substream *second_stream; | |
17467f23 TT |
93 | unsigned int playback; |
94 | unsigned int capture; | |
a454dad1 | 95 | int asynchronous; |
f0fba2ad | 96 | struct snd_soc_dai_driver cpu_dai_drv; |
17467f23 | 97 | struct device_attribute dev_attr; |
f0fba2ad | 98 | struct platform_device *pdev; |
17467f23 TT |
99 | |
100 | struct { | |
101 | unsigned int rfrc; | |
102 | unsigned int tfrc; | |
103 | unsigned int cmdau; | |
104 | unsigned int cmddu; | |
105 | unsigned int rxt; | |
106 | unsigned int rdr1; | |
107 | unsigned int rdr0; | |
108 | unsigned int tde1; | |
109 | unsigned int tde0; | |
110 | unsigned int roe1; | |
111 | unsigned int roe0; | |
112 | unsigned int tue1; | |
113 | unsigned int tue0; | |
114 | unsigned int tfs; | |
115 | unsigned int rfs; | |
116 | unsigned int tls; | |
117 | unsigned int rls; | |
118 | unsigned int rff1; | |
119 | unsigned int rff0; | |
120 | unsigned int tfe1; | |
121 | unsigned int tfe0; | |
122 | } stats; | |
f0fba2ad LG |
123 | |
124 | char name[1]; | |
17467f23 TT |
125 | }; |
126 | ||
127 | /** | |
128 | * fsl_ssi_isr: SSI interrupt handler | |
129 | * | |
130 | * Although it's possible to use the interrupt handler to send and receive | |
131 | * data to/from the SSI, we use the DMA instead. Programming is more | |
132 | * complicated, but the performance is much better. | |
133 | * | |
134 | * This interrupt handler is used only to gather statistics. | |
135 | * | |
136 | * @irq: IRQ of the SSI device | |
137 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
138 | */ | |
139 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
140 | { | |
141 | struct fsl_ssi_private *ssi_private = dev_id; | |
142 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
143 | irqreturn_t ret = IRQ_NONE; | |
144 | __be32 sisr; | |
145 | __be32 sisr2 = 0; | |
146 | ||
147 | /* We got an interrupt, so read the status register to see what we | |
148 | were interrupted for. We mask it with the Interrupt Enable register | |
149 | so that we only check for events that we're interested in. | |
150 | */ | |
d5a908b2 | 151 | sisr = in_be32(&ssi->sisr) & SIER_FLAGS; |
17467f23 TT |
152 | |
153 | if (sisr & CCSR_SSI_SISR_RFRC) { | |
154 | ssi_private->stats.rfrc++; | |
155 | sisr2 |= CCSR_SSI_SISR_RFRC; | |
156 | ret = IRQ_HANDLED; | |
157 | } | |
158 | ||
159 | if (sisr & CCSR_SSI_SISR_TFRC) { | |
160 | ssi_private->stats.tfrc++; | |
161 | sisr2 |= CCSR_SSI_SISR_TFRC; | |
162 | ret = IRQ_HANDLED; | |
163 | } | |
164 | ||
165 | if (sisr & CCSR_SSI_SISR_CMDAU) { | |
166 | ssi_private->stats.cmdau++; | |
167 | ret = IRQ_HANDLED; | |
168 | } | |
169 | ||
170 | if (sisr & CCSR_SSI_SISR_CMDDU) { | |
171 | ssi_private->stats.cmddu++; | |
172 | ret = IRQ_HANDLED; | |
173 | } | |
174 | ||
175 | if (sisr & CCSR_SSI_SISR_RXT) { | |
176 | ssi_private->stats.rxt++; | |
177 | ret = IRQ_HANDLED; | |
178 | } | |
179 | ||
180 | if (sisr & CCSR_SSI_SISR_RDR1) { | |
181 | ssi_private->stats.rdr1++; | |
182 | ret = IRQ_HANDLED; | |
183 | } | |
184 | ||
185 | if (sisr & CCSR_SSI_SISR_RDR0) { | |
186 | ssi_private->stats.rdr0++; | |
187 | ret = IRQ_HANDLED; | |
188 | } | |
189 | ||
190 | if (sisr & CCSR_SSI_SISR_TDE1) { | |
191 | ssi_private->stats.tde1++; | |
192 | ret = IRQ_HANDLED; | |
193 | } | |
194 | ||
195 | if (sisr & CCSR_SSI_SISR_TDE0) { | |
196 | ssi_private->stats.tde0++; | |
197 | ret = IRQ_HANDLED; | |
198 | } | |
199 | ||
200 | if (sisr & CCSR_SSI_SISR_ROE1) { | |
201 | ssi_private->stats.roe1++; | |
202 | sisr2 |= CCSR_SSI_SISR_ROE1; | |
203 | ret = IRQ_HANDLED; | |
204 | } | |
205 | ||
206 | if (sisr & CCSR_SSI_SISR_ROE0) { | |
207 | ssi_private->stats.roe0++; | |
208 | sisr2 |= CCSR_SSI_SISR_ROE0; | |
209 | ret = IRQ_HANDLED; | |
210 | } | |
211 | ||
212 | if (sisr & CCSR_SSI_SISR_TUE1) { | |
213 | ssi_private->stats.tue1++; | |
214 | sisr2 |= CCSR_SSI_SISR_TUE1; | |
215 | ret = IRQ_HANDLED; | |
216 | } | |
217 | ||
218 | if (sisr & CCSR_SSI_SISR_TUE0) { | |
219 | ssi_private->stats.tue0++; | |
220 | sisr2 |= CCSR_SSI_SISR_TUE0; | |
221 | ret = IRQ_HANDLED; | |
222 | } | |
223 | ||
224 | if (sisr & CCSR_SSI_SISR_TFS) { | |
225 | ssi_private->stats.tfs++; | |
226 | ret = IRQ_HANDLED; | |
227 | } | |
228 | ||
229 | if (sisr & CCSR_SSI_SISR_RFS) { | |
230 | ssi_private->stats.rfs++; | |
231 | ret = IRQ_HANDLED; | |
232 | } | |
233 | ||
234 | if (sisr & CCSR_SSI_SISR_TLS) { | |
235 | ssi_private->stats.tls++; | |
236 | ret = IRQ_HANDLED; | |
237 | } | |
238 | ||
239 | if (sisr & CCSR_SSI_SISR_RLS) { | |
240 | ssi_private->stats.rls++; | |
241 | ret = IRQ_HANDLED; | |
242 | } | |
243 | ||
244 | if (sisr & CCSR_SSI_SISR_RFF1) { | |
245 | ssi_private->stats.rff1++; | |
246 | ret = IRQ_HANDLED; | |
247 | } | |
248 | ||
249 | if (sisr & CCSR_SSI_SISR_RFF0) { | |
250 | ssi_private->stats.rff0++; | |
251 | ret = IRQ_HANDLED; | |
252 | } | |
253 | ||
254 | if (sisr & CCSR_SSI_SISR_TFE1) { | |
255 | ssi_private->stats.tfe1++; | |
256 | ret = IRQ_HANDLED; | |
257 | } | |
258 | ||
259 | if (sisr & CCSR_SSI_SISR_TFE0) { | |
260 | ssi_private->stats.tfe0++; | |
261 | ret = IRQ_HANDLED; | |
262 | } | |
263 | ||
264 | /* Clear the bits that we set */ | |
265 | if (sisr2) | |
266 | out_be32(&ssi->sisr, sisr2); | |
267 | ||
268 | return ret; | |
269 | } | |
270 | ||
271 | /** | |
272 | * fsl_ssi_startup: create a new substream | |
273 | * | |
274 | * This is the first function called when a stream is opened. | |
275 | * | |
276 | * If this is the first stream open, then grab the IRQ and program most of | |
277 | * the SSI registers. | |
278 | */ | |
dee89c4d MB |
279 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
280 | struct snd_soc_dai *dai) | |
17467f23 TT |
281 | { |
282 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 283 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
284 | |
285 | /* | |
286 | * If this is the first stream opened, then request the IRQ | |
287 | * and initialize the SSI registers. | |
288 | */ | |
289 | if (!ssi_private->playback && !ssi_private->capture) { | |
290 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
291 | int ret; | |
292 | ||
f0fba2ad | 293 | /* The 'name' should not have any slashes in it. */ |
17467f23 TT |
294 | ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, |
295 | ssi_private->name, ssi_private); | |
296 | if (ret < 0) { | |
297 | dev_err(substream->pcm->card->dev, | |
298 | "could not claim irq %u\n", ssi_private->irq); | |
299 | return ret; | |
300 | } | |
301 | ||
302 | /* | |
303 | * Section 16.5 of the MPC8610 reference manual says that the | |
304 | * SSI needs to be disabled before updating the registers we set | |
305 | * here. | |
306 | */ | |
307 | clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); | |
308 | ||
309 | /* | |
310 | * Program the SSI into I2S Slave Non-Network Synchronous mode. | |
311 | * Also enable the transmit and receive FIFO. | |
312 | * | |
313 | * FIXME: Little-endian samples require a different shift dir | |
314 | */ | |
a454dad1 TT |
315 | clrsetbits_be32(&ssi->scr, |
316 | CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, | |
317 | CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE | |
318 | | (ssi_private->asynchronous ? 0 : CCSR_SSI_SCR_SYN)); | |
17467f23 TT |
319 | |
320 | out_be32(&ssi->stcr, | |
321 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | | |
322 | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | | |
323 | CCSR_SSI_STCR_TSCKP); | |
324 | ||
325 | out_be32(&ssi->srcr, | |
326 | CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | | |
327 | CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | | |
328 | CCSR_SSI_SRCR_RSCKP); | |
329 | ||
330 | /* | |
331 | * The DC and PM bits are only used if the SSI is the clock | |
332 | * master. | |
333 | */ | |
334 | ||
335 | /* 4. Enable the interrupts and DMA requests */ | |
d5a908b2 | 336 | out_be32(&ssi->sier, SIER_FLAGS); |
17467f23 TT |
337 | |
338 | /* | |
339 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We | |
340 | * don't use FIFO 1. Since the SSI only supports stereo, the | |
341 | * watermark should never be an odd number. | |
342 | */ | |
343 | out_be32(&ssi->sfcsr, | |
344 | CCSR_SSI_SFCSR_TFWM0(6) | CCSR_SSI_SFCSR_RFWM0(2)); | |
345 | ||
346 | /* | |
347 | * We keep the SSI disabled because if we enable it, then the | |
348 | * DMA controller will start. It's not supposed to start until | |
349 | * the SCR.TE (or SCR.RE) bit is set, but it does anyway. The | |
350 | * DMA controller will transfer one "BWC" of data (i.e. the | |
351 | * amount of data that the MR.BWC bits are set to). The reason | |
352 | * this is bad is because at this point, the PCM driver has not | |
353 | * finished initializing the DMA controller. | |
354 | */ | |
355 | } | |
356 | ||
be41e941 TT |
357 | if (!ssi_private->first_stream) |
358 | ssi_private->first_stream = substream; | |
359 | else { | |
360 | /* This is the second stream open, so we need to impose sample | |
361 | * rate and maybe sample size constraints. Note that this can | |
362 | * cause a race condition if the second stream is opened before | |
363 | * the first stream is fully initialized. | |
364 | * | |
365 | * We provide some protection by checking to make sure the first | |
366 | * stream is initialized, but it's not perfect. ALSA sometimes | |
367 | * re-initializes the driver with a different sample rate or | |
368 | * size. If the second stream is opened before the first stream | |
369 | * has received its final parameters, then the second stream may | |
370 | * be constrained to the wrong sample rate or size. | |
371 | * | |
372 | * FIXME: This code does not handle opening and closing streams | |
373 | * repeatedly. If you open two streams and then close the first | |
374 | * one, you may not be able to open another stream until you | |
375 | * close the second one as well. | |
376 | */ | |
377 | struct snd_pcm_runtime *first_runtime = | |
378 | ssi_private->first_stream->runtime; | |
379 | ||
08d15f03 | 380 | if (!first_runtime->sample_bits) { |
be41e941 | 381 | dev_err(substream->pcm->card->dev, |
08d15f03 | 382 | "set sample size in %s stream first\n", |
be41e941 TT |
383 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK |
384 | ? "capture" : "playback"); | |
385 | return -EAGAIN; | |
386 | } | |
387 | ||
a454dad1 TT |
388 | /* If we're in synchronous mode, then we need to constrain |
389 | * the sample size as well. We don't support independent sample | |
390 | * rates in asynchronous mode. | |
391 | */ | |
392 | if (!ssi_private->asynchronous) | |
393 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
394 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
395 | first_runtime->sample_bits, | |
396 | first_runtime->sample_bits); | |
be41e941 TT |
397 | |
398 | ssi_private->second_stream = substream; | |
399 | } | |
400 | ||
17467f23 TT |
401 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
402 | ssi_private->playback++; | |
403 | ||
404 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
405 | ssi_private->capture++; | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | /** | |
85ef2375 | 411 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
412 | * |
413 | * Most of the SSI registers have been programmed in the startup function, | |
414 | * but the word length must be programmed here. Unfortunately, programming | |
415 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
416 | * cause a problem with supporting simultaneous playback and capture. If | |
417 | * the SSI is already playing a stream, then that stream may be temporarily | |
418 | * stopped when you start capture. | |
419 | * | |
420 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
421 | * clock master. | |
422 | */ | |
85ef2375 TT |
423 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
424 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 425 | { |
f0fba2ad | 426 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
17467f23 | 427 | |
be41e941 | 428 | if (substream == ssi_private->first_stream) { |
85ef2375 TT |
429 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
430 | unsigned int sample_size = | |
431 | snd_pcm_format_width(params_format(hw_params)); | |
a454dad1 | 432 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); |
17467f23 | 433 | |
be41e941 | 434 | /* The SSI should always be disabled at this points (SSIEN=0) */ |
17467f23 | 435 | |
be41e941 | 436 | /* In synchronous mode, the SSI uses STCCR for capture */ |
a454dad1 TT |
437 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || |
438 | !ssi_private->asynchronous) | |
439 | clrsetbits_be32(&ssi->stccr, | |
440 | CCSR_SSI_SxCCR_WL_MASK, wl); | |
441 | else | |
442 | clrsetbits_be32(&ssi->srccr, | |
443 | CCSR_SSI_SxCCR_WL_MASK, wl); | |
be41e941 | 444 | } |
17467f23 TT |
445 | |
446 | return 0; | |
447 | } | |
448 | ||
449 | /** | |
450 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
451 | * | |
452 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
453 | * transfer of data. | |
454 | * | |
455 | * The DMA channel is in external master start and pause mode, which | |
456 | * means the SSI completely controls the flow of data. | |
457 | */ | |
dee89c4d MB |
458 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
459 | struct snd_soc_dai *dai) | |
17467f23 TT |
460 | { |
461 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 462 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
463 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
464 | ||
465 | switch (cmd) { | |
466 | case SNDRV_PCM_TRIGGER_START: | |
3a638ff2 | 467 | clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); |
17467f23 | 468 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 469 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
be41e941 TT |
470 | setbits32(&ssi->scr, |
471 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); | |
a4d11fe5 | 472 | else |
be41e941 TT |
473 | setbits32(&ssi->scr, |
474 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); | |
17467f23 TT |
475 | break; |
476 | ||
477 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
478 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
479 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
480 | clrbits32(&ssi->scr, CCSR_SSI_SCR_TE); | |
481 | else | |
482 | clrbits32(&ssi->scr, CCSR_SSI_SCR_RE); | |
483 | break; | |
484 | ||
485 | default: | |
486 | return -EINVAL; | |
487 | } | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | /** | |
493 | * fsl_ssi_shutdown: shutdown the SSI | |
494 | * | |
495 | * Shutdown the SSI if there are no other substreams open. | |
496 | */ | |
dee89c4d MB |
497 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
498 | struct snd_soc_dai *dai) | |
17467f23 TT |
499 | { |
500 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 501 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
502 | |
503 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
504 | ssi_private->playback--; | |
505 | ||
506 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
507 | ssi_private->capture--; | |
508 | ||
be41e941 TT |
509 | if (ssi_private->first_stream == substream) |
510 | ssi_private->first_stream = ssi_private->second_stream; | |
511 | ||
512 | ssi_private->second_stream = NULL; | |
513 | ||
17467f23 TT |
514 | /* |
515 | * If this is the last active substream, disable the SSI and release | |
516 | * the IRQ. | |
517 | */ | |
518 | if (!ssi_private->playback && !ssi_private->capture) { | |
519 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
520 | ||
521 | clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); | |
522 | ||
523 | free_irq(ssi_private->irq, ssi_private); | |
524 | } | |
525 | } | |
526 | ||
6335d055 EM |
527 | static struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
528 | .startup = fsl_ssi_startup, | |
529 | .hw_params = fsl_ssi_hw_params, | |
530 | .shutdown = fsl_ssi_shutdown, | |
531 | .trigger = fsl_ssi_trigger, | |
6335d055 EM |
532 | }; |
533 | ||
f0fba2ad LG |
534 | /* Template for the CPU dai driver structure */ |
535 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
17467f23 TT |
536 | .playback = { |
537 | /* The SSI does not support monaural audio. */ | |
538 | .channels_min = 2, | |
539 | .channels_max = 2, | |
540 | .rates = FSLSSI_I2S_RATES, | |
541 | .formats = FSLSSI_I2S_FORMATS, | |
542 | }, | |
543 | .capture = { | |
544 | .channels_min = 2, | |
545 | .channels_max = 2, | |
546 | .rates = FSLSSI_I2S_RATES, | |
547 | .formats = FSLSSI_I2S_FORMATS, | |
548 | }, | |
6335d055 | 549 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
550 | }; |
551 | ||
d5a908b2 TT |
552 | /* Show the statistics of a flag only if its interrupt is enabled. The |
553 | * compiler will optimze this code to a no-op if the interrupt is not | |
554 | * enabled. | |
555 | */ | |
556 | #define SIER_SHOW(flag, name) \ | |
557 | do { \ | |
558 | if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \ | |
559 | length += sprintf(buf + length, #name "=%u\n", \ | |
560 | ssi_private->stats.name); \ | |
561 | } while (0) | |
562 | ||
563 | ||
17467f23 TT |
564 | /** |
565 | * fsl_sysfs_ssi_show: display SSI statistics | |
566 | * | |
d5a908b2 TT |
567 | * Display the statistics for the current SSI device. To avoid confusion, |
568 | * we only show those counts that are enabled. | |
17467f23 TT |
569 | */ |
570 | static ssize_t fsl_sysfs_ssi_show(struct device *dev, | |
571 | struct device_attribute *attr, char *buf) | |
572 | { | |
573 | struct fsl_ssi_private *ssi_private = | |
d5a908b2 TT |
574 | container_of(attr, struct fsl_ssi_private, dev_attr); |
575 | ssize_t length = 0; | |
576 | ||
577 | SIER_SHOW(RFRC_EN, rfrc); | |
578 | SIER_SHOW(TFRC_EN, tfrc); | |
579 | SIER_SHOW(CMDAU_EN, cmdau); | |
580 | SIER_SHOW(CMDDU_EN, cmddu); | |
581 | SIER_SHOW(RXT_EN, rxt); | |
582 | SIER_SHOW(RDR1_EN, rdr1); | |
583 | SIER_SHOW(RDR0_EN, rdr0); | |
584 | SIER_SHOW(TDE1_EN, tde1); | |
585 | SIER_SHOW(TDE0_EN, tde0); | |
586 | SIER_SHOW(ROE1_EN, roe1); | |
587 | SIER_SHOW(ROE0_EN, roe0); | |
588 | SIER_SHOW(TUE1_EN, tue1); | |
589 | SIER_SHOW(TUE0_EN, tue0); | |
590 | SIER_SHOW(TFS_EN, tfs); | |
591 | SIER_SHOW(RFS_EN, rfs); | |
592 | SIER_SHOW(TLS_EN, tls); | |
593 | SIER_SHOW(RLS_EN, rls); | |
594 | SIER_SHOW(RFF1_EN, rff1); | |
595 | SIER_SHOW(RFF0_EN, rff0); | |
596 | SIER_SHOW(TFE1_EN, tfe1); | |
597 | SIER_SHOW(TFE0_EN, tfe0); | |
17467f23 TT |
598 | |
599 | return length; | |
600 | } | |
601 | ||
602 | /** | |
f0fba2ad | 603 | * Make every character in a string lower-case |
17467f23 | 604 | */ |
f0fba2ad LG |
605 | static void make_lowercase(char *s) |
606 | { | |
607 | char *p = s; | |
608 | char c; | |
609 | ||
610 | while ((c = *p)) { | |
611 | if ((c >= 'A') && (c <= 'Z')) | |
612 | *p = c + ('a' - 'A'); | |
613 | p++; | |
614 | } | |
615 | } | |
616 | ||
617 | static int __devinit fsl_ssi_probe(struct of_device *of_dev, | |
618 | const struct of_device_id *match) | |
17467f23 | 619 | { |
17467f23 TT |
620 | struct fsl_ssi_private *ssi_private; |
621 | int ret = 0; | |
622 | struct device_attribute *dev_attr; | |
f0fba2ad LG |
623 | struct device_node *np = of_dev->dev.of_node; |
624 | const char *p, *sprop; | |
625 | struct resource res; | |
626 | char name[64]; | |
17467f23 | 627 | |
f0fba2ad LG |
628 | /* We are only interested in SSIs with a codec phandle in them, so let's |
629 | * make sure this SSI has one. | |
630 | */ | |
631 | if (!of_get_property(np, "codec-handle", NULL)) | |
632 | return -ENODEV; | |
633 | ||
634 | /* We only support the SSI in "I2S Slave" mode */ | |
635 | sprop = of_get_property(np, "fsl,mode", NULL); | |
636 | if (!sprop || strcmp(sprop, "i2s-slave")) { | |
637 | dev_notice(&of_dev->dev, "mode %s is unsupported\n", sprop); | |
638 | return -ENODEV; | |
639 | } | |
640 | ||
641 | /* The DAI name is the last part of the full name of the node. */ | |
642 | p = strrchr(np->full_name, '/') + 1; | |
643 | ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p), | |
644 | GFP_KERNEL); | |
17467f23 | 645 | if (!ssi_private) { |
f0fba2ad LG |
646 | dev_err(&of_dev->dev, "could not allocate DAI object\n"); |
647 | return -ENOMEM; | |
17467f23 | 648 | } |
17467f23 | 649 | |
f0fba2ad | 650 | strcpy(ssi_private->name, p); |
17467f23 | 651 | |
f0fba2ad LG |
652 | /* Initialize this copy of the CPU DAI driver structure */ |
653 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
654 | sizeof(fsl_ssi_dai_template)); | |
655 | ssi_private->cpu_dai_drv.name = ssi_private->name; | |
656 | ||
657 | /* Get the addresses and IRQ */ | |
658 | ret = of_address_to_resource(np, 0, &res); | |
659 | if (ret) { | |
660 | dev_err(&of_dev->dev, "could not determine device resources\n"); | |
661 | kfree(ssi_private); | |
662 | return ret; | |
663 | } | |
664 | ssi_private->ssi = ioremap(res.start, 1 + res.end - res.start); | |
665 | ssi_private->ssi_phys = res.start; | |
666 | ssi_private->irq = irq_of_parse_and_map(np, 0); | |
17467f23 | 667 | |
f0fba2ad LG |
668 | /* Are the RX and the TX clocks locked? */ |
669 | if (of_find_property(np, "fsl,ssi-asynchronous", NULL)) | |
670 | ssi_private->asynchronous = 1; | |
671 | else | |
672 | ssi_private->cpu_dai_drv.symmetric_rates = 1; | |
17467f23 TT |
673 | |
674 | /* Initialize the the device_attribute structure */ | |
f0fba2ad LG |
675 | dev_attr = &ssi_private->dev_attr; |
676 | dev_attr->attr.name = "statistics"; | |
17467f23 TT |
677 | dev_attr->attr.mode = S_IRUGO; |
678 | dev_attr->show = fsl_sysfs_ssi_show; | |
679 | ||
f0fba2ad | 680 | ret = device_create_file(&of_dev->dev, dev_attr); |
17467f23 | 681 | if (ret) { |
f0fba2ad | 682 | dev_err(&of_dev->dev, "could not create sysfs %s file\n", |
17467f23 | 683 | ssi_private->dev_attr.attr.name); |
f0fba2ad LG |
684 | kfree(ssi_private); |
685 | return ret; | |
17467f23 TT |
686 | } |
687 | ||
f0fba2ad LG |
688 | /* Register with ASoC */ |
689 | dev_set_drvdata(&of_dev->dev, ssi_private); | |
3f4b783c | 690 | |
f0fba2ad | 691 | ret = snd_soc_register_dai(&of_dev->dev, &ssi_private->cpu_dai_drv); |
3f4b783c | 692 | if (ret != 0) { |
f0fba2ad LG |
693 | dev_err(&of_dev->dev, "failed to register DAI: %d\n", ret); |
694 | kfree(ssi_private); | |
695 | return ret; | |
696 | } | |
697 | ||
698 | /* Trigger the machine driver's probe function. The platform driver | |
699 | * name of the machine driver is taken from the /model property of the | |
700 | * device tree. We also pass the address of the CPU DAI driver | |
701 | * structure. | |
702 | */ | |
703 | sprop = of_get_property(of_find_node_by_path("/"), "model", NULL); | |
704 | /* Sometimes the model name has a "fsl," prefix, so we strip that. */ | |
705 | p = strrchr(sprop, ','); | |
706 | if (p) | |
707 | sprop = p + 1; | |
708 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
709 | make_lowercase(name); | |
710 | ||
711 | ssi_private->pdev = | |
712 | platform_device_register_data(&of_dev->dev, name, 0, NULL, 0); | |
713 | if (IS_ERR(ssi_private->pdev)) { | |
714 | ret = PTR_ERR(ssi_private->pdev); | |
715 | dev_err(&of_dev->dev, "failed to register platform: %d\n", ret); | |
716 | kfree(ssi_private); | |
717 | return ret; | |
3f4b783c | 718 | } |
17467f23 | 719 | |
f0fba2ad | 720 | return 0; |
17467f23 | 721 | } |
17467f23 TT |
722 | |
723 | /** | |
8cf7b2b3 | 724 | * fsl_ssi_destroy_dai: destroy the snd_soc_dai object |
17467f23 | 725 | * |
f0fba2ad | 726 | * This function undoes the operations of fsl_ssi_probe() |
17467f23 | 727 | */ |
f0fba2ad | 728 | static int fsl_ssi_remove(struct of_device *of_dev) |
17467f23 | 729 | { |
f0fba2ad | 730 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&of_dev->dev); |
17467f23 | 731 | |
f0fba2ad LG |
732 | platform_device_unregister(ssi_private->pdev); |
733 | snd_soc_unregister_dai(&of_dev->dev); | |
734 | device_remove_file(&of_dev->dev, &ssi_private->dev_attr); | |
3f4b783c | 735 | |
17467f23 | 736 | kfree(ssi_private); |
f0fba2ad LG |
737 | dev_set_drvdata(&of_dev->dev, NULL); |
738 | ||
739 | return 0; | |
17467f23 | 740 | } |
f0fba2ad LG |
741 | |
742 | static const struct of_device_id fsl_ssi_ids[] = { | |
743 | { .compatible = "fsl,mpc8610-ssi", }, | |
744 | {} | |
745 | }; | |
746 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
747 | ||
748 | static struct of_platform_driver fsl_ssi_driver = { | |
749 | .driver = { | |
750 | .name = "fsl-ssi-dai", | |
751 | .owner = THIS_MODULE, | |
752 | .of_match_table = fsl_ssi_ids, | |
753 | }, | |
754 | .probe = fsl_ssi_probe, | |
755 | .remove = fsl_ssi_remove, | |
756 | }; | |
17467f23 | 757 | |
a454dad1 TT |
758 | static int __init fsl_ssi_init(void) |
759 | { | |
760 | printk(KERN_INFO "Freescale Synchronous Serial Interface (SSI) ASoC Driver\n"); | |
761 | ||
f0fba2ad LG |
762 | return of_register_platform_driver(&fsl_ssi_driver); |
763 | } | |
764 | ||
765 | static void __exit fsl_ssi_exit(void) | |
766 | { | |
767 | of_unregister_platform_driver(&fsl_ssi_driver); | |
a454dad1 | 768 | } |
f0fba2ad | 769 | |
a454dad1 | 770 | module_init(fsl_ssi_init); |
f0fba2ad | 771 | module_exit(fsl_ssi_exit); |
a454dad1 | 772 | |
17467f23 TT |
773 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
774 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 775 | MODULE_LICENSE("GPL v2"); |