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1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | */ | |
6 | ||
7 | #ifndef _IMX_SSI_H | |
8 | #define _IMX_SSI_H | |
9 | ||
10 | #include <mach/hardware.h> | |
11 | ||
12 | /* SSI regs definition - MOVE to /arch/arm/plat-mxc/include/mach/ when stable */ | |
13 | #define SSI1_IO_BASE_ADDR IO_ADDRESS(SSI1_BASE_ADDR) | |
14 | #define SSI2_IO_BASE_ADDR IO_ADDRESS(SSI2_BASE_ADDR) | |
15 | ||
16 | #define STX0 0x00 | |
17 | #define STX1 0x04 | |
18 | #define SRX0 0x08 | |
19 | #define SRX1 0x0c | |
20 | #define SCR 0x10 | |
21 | #define SISR 0x14 | |
22 | #define SIER 0x18 | |
23 | #define STCR 0x1c | |
24 | #define SRCR 0x20 | |
25 | #define STCCR 0x24 | |
26 | #define SRCCR 0x28 | |
27 | #define SFCSR 0x2c | |
28 | #define STR 0x30 | |
29 | #define SOR 0x34 | |
30 | #define SACNT 0x38 | |
31 | #define SACADD 0x3c | |
32 | #define SACDAT 0x40 | |
33 | #define SATAG 0x44 | |
34 | #define STMSK 0x48 | |
35 | #define SRMSK 0x4c | |
36 | ||
37 | #define SSI1_STX0 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STX0))) | |
38 | #define SSI1_STX1 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STX1))) | |
39 | #define SSI1_SRX0 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRX0))) | |
40 | #define SSI1_SRX1 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRX1))) | |
41 | #define SSI1_SCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SCR))) | |
42 | #define SSI1_SISR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SISR))) | |
43 | #define SSI1_SIER (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SIER))) | |
44 | #define SSI1_STCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STCR))) | |
45 | #define SSI1_SRCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRCR))) | |
46 | #define SSI1_STCCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STCCR))) | |
47 | #define SSI1_SRCCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRCCR))) | |
48 | #define SSI1_SFCSR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SFCSR))) | |
49 | #define SSI1_STR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STR))) | |
50 | #define SSI1_SOR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SOR))) | |
51 | #define SSI1_SACNT (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACNT))) | |
52 | #define SSI1_SACADD (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACADD))) | |
53 | #define SSI1_SACDAT (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACDAT))) | |
54 | #define SSI1_SATAG (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SATAG))) | |
55 | #define SSI1_STMSK (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STMSK))) | |
56 | #define SSI1_SRMSK (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRMSK))) | |
57 | ||
58 | ||
59 | #define SSI2_STX0 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STX0))) | |
60 | #define SSI2_STX1 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STX1))) | |
61 | #define SSI2_SRX0 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRX0))) | |
62 | #define SSI2_SRX1 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRX1))) | |
63 | #define SSI2_SCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SCR))) | |
64 | #define SSI2_SISR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SISR))) | |
65 | #define SSI2_SIER (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SIER))) | |
66 | #define SSI2_STCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STCR))) | |
67 | #define SSI2_SRCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRCR))) | |
68 | #define SSI2_STCCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STCCR))) | |
69 | #define SSI2_SRCCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRCCR))) | |
70 | #define SSI2_SFCSR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SFCSR))) | |
71 | #define SSI2_STR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STR))) | |
72 | #define SSI2_SOR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SOR))) | |
73 | #define SSI2_SACNT (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACNT))) | |
74 | #define SSI2_SACADD (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACADD))) | |
75 | #define SSI2_SACDAT (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACDAT))) | |
76 | #define SSI2_SATAG (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SATAG))) | |
77 | #define SSI2_STMSK (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STMSK))) | |
78 | #define SSI2_SRMSK (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRMSK))) | |
79 | ||
80 | #define SSI_SCR_CLK_IST (1 << 9) | |
81 | #define SSI_SCR_TCH_EN (1 << 8) | |
82 | #define SSI_SCR_SYS_CLK_EN (1 << 7) | |
83 | #define SSI_SCR_I2S_MODE_NORM (0 << 5) | |
84 | #define SSI_SCR_I2S_MODE_MSTR (1 << 5) | |
85 | #define SSI_SCR_I2S_MODE_SLAVE (2 << 5) | |
86 | #define SSI_SCR_SYN (1 << 4) | |
87 | #define SSI_SCR_NET (1 << 3) | |
88 | #define SSI_SCR_RE (1 << 2) | |
89 | #define SSI_SCR_TE (1 << 1) | |
90 | #define SSI_SCR_SSIEN (1 << 0) | |
91 | ||
92 | #define SSI_SISR_CMDAU (1 << 18) | |
93 | #define SSI_SISR_CMDDU (1 << 17) | |
94 | #define SSI_SISR_RXT (1 << 16) | |
95 | #define SSI_SISR_RDR1 (1 << 15) | |
96 | #define SSI_SISR_RDR0 (1 << 14) | |
97 | #define SSI_SISR_TDE1 (1 << 13) | |
98 | #define SSI_SISR_TDE0 (1 << 12) | |
99 | #define SSI_SISR_ROE1 (1 << 11) | |
100 | #define SSI_SISR_ROE0 (1 << 10) | |
101 | #define SSI_SISR_TUE1 (1 << 9) | |
102 | #define SSI_SISR_TUE0 (1 << 8) | |
103 | #define SSI_SISR_TFS (1 << 7) | |
104 | #define SSI_SISR_RFS (1 << 6) | |
105 | #define SSI_SISR_TLS (1 << 5) | |
106 | #define SSI_SISR_RLS (1 << 4) | |
107 | #define SSI_SISR_RFF1 (1 << 3) | |
108 | #define SSI_SISR_RFF0 (1 << 2) | |
109 | #define SSI_SISR_TFE1 (1 << 1) | |
110 | #define SSI_SISR_TFE0 (1 << 0) | |
111 | ||
112 | #define SSI_SIER_RDMAE (1 << 22) | |
113 | #define SSI_SIER_RIE (1 << 21) | |
114 | #define SSI_SIER_TDMAE (1 << 20) | |
115 | #define SSI_SIER_TIE (1 << 19) | |
116 | #define SSI_SIER_CMDAU_EN (1 << 18) | |
117 | #define SSI_SIER_CMDDU_EN (1 << 17) | |
118 | #define SSI_SIER_RXT_EN (1 << 16) | |
119 | #define SSI_SIER_RDR1_EN (1 << 15) | |
120 | #define SSI_SIER_RDR0_EN (1 << 14) | |
121 | #define SSI_SIER_TDE1_EN (1 << 13) | |
122 | #define SSI_SIER_TDE0_EN (1 << 12) | |
123 | #define SSI_SIER_ROE1_EN (1 << 11) | |
124 | #define SSI_SIER_ROE0_EN (1 << 10) | |
125 | #define SSI_SIER_TUE1_EN (1 << 9) | |
126 | #define SSI_SIER_TUE0_EN (1 << 8) | |
127 | #define SSI_SIER_TFS_EN (1 << 7) | |
128 | #define SSI_SIER_RFS_EN (1 << 6) | |
129 | #define SSI_SIER_TLS_EN (1 << 5) | |
130 | #define SSI_SIER_RLS_EN (1 << 4) | |
131 | #define SSI_SIER_RFF1_EN (1 << 3) | |
132 | #define SSI_SIER_RFF0_EN (1 << 2) | |
133 | #define SSI_SIER_TFE1_EN (1 << 1) | |
134 | #define SSI_SIER_TFE0_EN (1 << 0) | |
135 | ||
136 | #define SSI_STCR_TXBIT0 (1 << 9) | |
137 | #define SSI_STCR_TFEN1 (1 << 8) | |
138 | #define SSI_STCR_TFEN0 (1 << 7) | |
139 | #define SSI_STCR_TFDIR (1 << 6) | |
140 | #define SSI_STCR_TXDIR (1 << 5) | |
141 | #define SSI_STCR_TSHFD (1 << 4) | |
142 | #define SSI_STCR_TSCKP (1 << 3) | |
143 | #define SSI_STCR_TFSI (1 << 2) | |
144 | #define SSI_STCR_TFSL (1 << 1) | |
145 | #define SSI_STCR_TEFS (1 << 0) | |
146 | ||
147 | #define SSI_SRCR_RXBIT0 (1 << 9) | |
148 | #define SSI_SRCR_RFEN1 (1 << 8) | |
149 | #define SSI_SRCR_RFEN0 (1 << 7) | |
150 | #define SSI_SRCR_RFDIR (1 << 6) | |
151 | #define SSI_SRCR_RXDIR (1 << 5) | |
152 | #define SSI_SRCR_RSHFD (1 << 4) | |
153 | #define SSI_SRCR_RSCKP (1 << 3) | |
154 | #define SSI_SRCR_RFSI (1 << 2) | |
155 | #define SSI_SRCR_RFSL (1 << 1) | |
156 | #define SSI_SRCR_REFS (1 << 0) | |
157 | ||
158 | #define SSI_STCCR_DIV2 (1 << 18) | |
159 | #define SSI_STCCR_PSR (1 << 15) | |
160 | #define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) | |
161 | #define SSI_STCCR_DC(x) (((x) & 0x1f) << 8) | |
162 | #define SSI_STCCR_PM(x) (((x) & 0xff) << 0) | |
163 | #define SSI_STCCR_WL_MASK (0xf << 13) | |
164 | #define SSI_STCCR_DC_MASK (0x1f << 8) | |
165 | #define SSI_STCCR_PM_MASK (0xff << 0) | |
166 | ||
167 | #define SSI_SRCCR_DIV2 (1 << 18) | |
168 | #define SSI_SRCCR_PSR (1 << 15) | |
169 | #define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) | |
170 | #define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8) | |
171 | #define SSI_SRCCR_PM(x) (((x) & 0xff) << 0) | |
172 | #define SSI_SRCCR_WL_MASK (0xf << 13) | |
173 | #define SSI_SRCCR_DC_MASK (0x1f << 8) | |
174 | #define SSI_SRCCR_PM_MASK (0xff << 0) | |
175 | ||
176 | ||
177 | #define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28) | |
178 | #define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24) | |
179 | #define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20) | |
180 | #define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16) | |
181 | #define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12) | |
182 | #define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8) | |
183 | #define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4) | |
184 | #define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0) | |
185 | ||
186 | #define SSI_STR_TEST (1 << 15) | |
187 | #define SSI_STR_RCK2TCK (1 << 14) | |
188 | #define SSI_STR_RFS2TFS (1 << 13) | |
189 | #define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8) | |
190 | #define SSI_STR_TXD2RXD (1 << 7) | |
191 | #define SSI_STR_TCK2RCK (1 << 6) | |
192 | #define SSI_STR_TFS2RFS (1 << 5) | |
193 | #define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0) | |
194 | ||
195 | #define SSI_SOR_CLKOFF (1 << 6) | |
196 | #define SSI_SOR_RX_CLR (1 << 5) | |
197 | #define SSI_SOR_TX_CLR (1 << 4) | |
198 | #define SSI_SOR_INIT (1 << 3) | |
199 | #define SSI_SOR_WAIT(x) (((x) & 0x3) << 1) | |
200 | #define SSI_SOR_SYNRST (1 << 0) | |
201 | ||
202 | #define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5) | |
203 | #define SSI_SACNT_WR (x << 4) | |
204 | #define SSI_SACNT_RD (x << 3) | |
205 | #define SSI_SACNT_TIF (x << 2) | |
206 | #define SSI_SACNT_FV (x << 1) | |
207 | #define SSI_SACNT_AC97EN (x << 0) | |
208 | ||
209 | /* Watermarks for FIFO's */ | |
210 | #define TXFIFO_WATERMARK 0x4 | |
211 | #define RXFIFO_WATERMARK 0x4 | |
212 | ||
213 | /* i.MX DAI SSP ID's */ | |
214 | #define IMX_DAI_SSI0 0 /* SSI1 FIFO 0 */ | |
215 | #define IMX_DAI_SSI1 1 /* SSI1 FIFO 1 */ | |
216 | #define IMX_DAI_SSI2 2 /* SSI2 FIFO 0 */ | |
217 | #define IMX_DAI_SSI3 3 /* SSI2 FIFO 1 */ | |
218 | ||
219 | /* SSI clock sources */ | |
220 | #define IMX_SSP_SYS_CLK 0 | |
221 | ||
222 | /* SSI audio dividers */ | |
223 | #define IMX_SSI_TX_DIV_2 0 | |
224 | #define IMX_SSI_TX_DIV_PSR 1 | |
225 | #define IMX_SSI_TX_DIV_PM 2 | |
226 | #define IMX_SSI_RX_DIV_2 3 | |
227 | #define IMX_SSI_RX_DIV_PSR 4 | |
228 | #define IMX_SSI_RX_DIV_PM 5 | |
229 | ||
230 | ||
231 | /* SSI Div 2 */ | |
232 | #define IMX_SSI_DIV_2_OFF (~SSI_STCCR_DIV2) | |
233 | #define IMX_SSI_DIV_2_ON SSI_STCCR_DIV2 | |
234 | ||
235 | extern struct snd_soc_dai imx_ssi_pcm_dai[4]; | |
236 | extern int get_ssi_clk(int ssi, struct device *dev); | |
237 | extern void put_ssi_clk(int ssi); | |
238 | #endif |