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[mirror_ubuntu-jammy-kernel.git] / sound / soc / intel / boards / cht_bsw_rt5645.c
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1/*
2 * cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms
3 * Cherrytrail and Braswell, with RT5645 codec.
4 *
5 * Copyright (C) 2015 Intel Corp
6 * Author: Fang, Yang A <yang.a.fang@intel.com>
7 * N,Harshapriya <harshapriya.n@intel.com>
8 * This file is modified from cht_bsw_rt5672.c
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 */
22
23#include <linux/module.h>
24#include <linux/platform_device.h>
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25#include <linux/acpi.h>
26#include <linux/clk.h>
22af2911 27#include <linux/dmi.h>
e18acdc0 28#include <linux/slab.h>
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29#include <asm/cpu_device_id.h>
30#include <asm/platform_sst_audio.h>
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31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/jack.h>
7feb2f78 35#include <sound/soc-acpi.h>
e56c72d5 36#include "../../codecs/rt5645.h"
b97169da 37#include "../atom/sst-atom-controls.h"
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38
39#define CHT_PLAT_CLK_3_HZ 19200000
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40#define CHT_CODEC_DAI1 "rt5645-aif1"
41#define CHT_CODEC_DAI2 "rt5645-aif2"
e18acdc0 42
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43struct cht_acpi_card {
44 char *codec_id;
45 int codec_type;
46 struct snd_soc_card *soc_card;
47};
48
e18acdc0 49struct cht_mc_private {
673c4f89 50 struct snd_soc_jack jack;
c4ba51ba 51 struct cht_acpi_card *acpi_card;
2be2d579 52 char codec_name[SND_ACPI_I2C_ID_LEN];
a50477e5 53 struct clk *mclk;
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54};
55
6cdf01a5 56#define CHT_RT5645_MAP(quirk) ((quirk) & GENMASK(7, 0))
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57#define CHT_RT5645_SSP2_AIF2 BIT(16) /* default is using AIF1 */
58#define CHT_RT5645_SSP0_AIF1 BIT(17)
59#define CHT_RT5645_SSP0_AIF2 BIT(18)
60
61static unsigned long cht_rt5645_quirk = 0;
62
63static void log_quirks(struct device *dev)
64{
65 if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2)
66 dev_info(dev, "quirk SSP2_AIF2 enabled");
67 if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1)
68 dev_info(dev, "quirk SSP0_AIF1 enabled");
69 if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)
70 dev_info(dev, "quirk SSP0_AIF2 enabled");
71}
72
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73static int platform_clock_control(struct snd_soc_dapm_widget *w,
74 struct snd_kcontrol *k, int event)
75{
76 struct snd_soc_dapm_context *dapm = w->dapm;
77 struct snd_soc_card *card = dapm->card;
78 struct snd_soc_dai *codec_dai;
a50477e5 79 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
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80 int ret;
81
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82 codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI1);
83 if (!codec_dai)
84 codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI2);
85
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86 if (!codec_dai) {
87 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n");
88 return -EIO;
89 }
90
a50477e5 91 if (SND_SOC_DAPM_EVENT_ON(event)) {
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92 ret = clk_prepare_enable(ctx->mclk);
93 if (ret < 0) {
94 dev_err(card->dev,
95 "could not configure MCLK state");
96 return ret;
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97 }
98 } else {
99 /* Set codec sysclk source to its internal clock because codec PLL will
100 * be off when idle and MCLK will also be off when codec is
101 * runtime suspended. Codec needs clock for jack detection and button
102 * press. MCLK is turned off with clock framework or ACPI.
103 */
104 ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_RCCLK,
105 48000 * 512, SND_SOC_CLOCK_IN);
106 if (ret < 0) {
107 dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
108 return ret;
109 }
e18acdc0 110
6cdf01a5 111 clk_disable_unprepare(ctx->mclk);
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112 }
113
114 return 0;
115}
116
117static const struct snd_soc_dapm_widget cht_dapm_widgets[] = {
118 SND_SOC_DAPM_HP("Headphone", NULL),
119 SND_SOC_DAPM_MIC("Headset Mic", NULL),
120 SND_SOC_DAPM_MIC("Int Mic", NULL),
121 SND_SOC_DAPM_SPK("Ext Spk", NULL),
122 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
a50477e5 123 platform_clock_control, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
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124};
125
c4ba51ba 126static const struct snd_soc_dapm_route cht_rt5645_audio_map[] = {
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127 {"IN1P", NULL, "Headset Mic"},
128 {"IN1N", NULL, "Headset Mic"},
129 {"DMIC L1", NULL, "Int Mic"},
130 {"DMIC R1", NULL, "Int Mic"},
131 {"Headphone", NULL, "HPOL"},
132 {"Headphone", NULL, "HPOR"},
133 {"Ext Spk", NULL, "SPOL"},
134 {"Ext Spk", NULL, "SPOR"},
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135 {"Headphone", NULL, "Platform Clock"},
136 {"Headset Mic", NULL, "Platform Clock"},
137 {"Int Mic", NULL, "Platform Clock"},
138 {"Ext Spk", NULL, "Platform Clock"},
139};
140
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141static const struct snd_soc_dapm_route cht_rt5650_audio_map[] = {
142 {"IN1P", NULL, "Headset Mic"},
143 {"IN1N", NULL, "Headset Mic"},
144 {"DMIC L2", NULL, "Int Mic"},
145 {"DMIC R2", NULL, "Int Mic"},
146 {"Headphone", NULL, "HPOL"},
147 {"Headphone", NULL, "HPOR"},
148 {"Ext Spk", NULL, "SPOL"},
149 {"Ext Spk", NULL, "SPOR"},
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150 {"Headphone", NULL, "Platform Clock"},
151 {"Headset Mic", NULL, "Platform Clock"},
152 {"Int Mic", NULL, "Platform Clock"},
153 {"Ext Spk", NULL, "Platform Clock"},
154};
155
156static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif1_map[] = {
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157 {"AIF1 Playback", NULL, "ssp2 Tx"},
158 {"ssp2 Tx", NULL, "codec_out0"},
159 {"ssp2 Tx", NULL, "codec_out1"},
160 {"codec_in0", NULL, "ssp2 Rx" },
161 {"codec_in1", NULL, "ssp2 Rx" },
162 {"ssp2 Rx", NULL, "AIF1 Capture"},
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163};
164
165static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif2_map[] = {
166 {"AIF2 Playback", NULL, "ssp2 Tx"},
167 {"ssp2 Tx", NULL, "codec_out0"},
168 {"ssp2 Tx", NULL, "codec_out1"},
169 {"codec_in0", NULL, "ssp2 Rx" },
170 {"codec_in1", NULL, "ssp2 Rx" },
171 {"ssp2 Rx", NULL, "AIF2 Capture"},
172};
173
174static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif1_map[] = {
175 {"AIF1 Playback", NULL, "ssp0 Tx"},
176 {"ssp0 Tx", NULL, "modem_out"},
177 {"modem_in", NULL, "ssp0 Rx" },
178 {"ssp0 Rx", NULL, "AIF1 Capture"},
179};
180
181static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif2_map[] = {
182 {"AIF2 Playback", NULL, "ssp0 Tx"},
183 {"ssp0 Tx", NULL, "modem_out"},
184 {"modem_in", NULL, "ssp0 Rx" },
185 {"ssp0 Rx", NULL, "AIF2 Capture"},
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186};
187
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188static const struct snd_kcontrol_new cht_mc_controls[] = {
189 SOC_DAPM_PIN_SWITCH("Headphone"),
190 SOC_DAPM_PIN_SWITCH("Headset Mic"),
191 SOC_DAPM_PIN_SWITCH("Int Mic"),
192 SOC_DAPM_PIN_SWITCH("Ext Spk"),
193};
194
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195static struct snd_soc_jack_pin cht_bsw_jack_pins[] = {
196 {
197 .pin = "Headphone",
198 .mask = SND_JACK_HEADPHONE,
199 },
200 {
201 .pin = "Headset Mic",
202 .mask = SND_JACK_MICROPHONE,
203 },
204};
205
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206static int cht_aif1_hw_params(struct snd_pcm_substream *substream,
207 struct snd_pcm_hw_params *params)
208{
209 struct snd_soc_pcm_runtime *rtd = substream->private_data;
210 struct snd_soc_dai *codec_dai = rtd->codec_dai;
211 int ret;
212
213 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */
214 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,
215 CHT_PLAT_CLK_3_HZ, params_rate(params) * 512);
216 if (ret < 0) {
217 dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
218 return ret;
219 }
220
221 ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,
222 params_rate(params) * 512, SND_SOC_CLOCK_IN);
223 if (ret < 0) {
224 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
225 return ret;
226 }
227
228 return 0;
229}
230
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231/* uncomment when we have a real quirk
232static int cht_rt5645_quirk_cb(const struct dmi_system_id *id)
233{
234 cht_rt5645_quirk = (unsigned long)id->driver_data;
235 return 1;
236}
237*/
238
239static const struct dmi_system_id cht_rt5645_quirk_table[] = {
240 {
241 },
242};
243
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244static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
245{
22af2911 246 struct snd_soc_card *card = runtime->card;
e18acdc0 247 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card);
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248 struct snd_soc_codec *codec = runtime->codec;
249 int jack_type;
250 int ret;
e18acdc0 251
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252 if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||
253 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
254 /* Select clk_i2s2_asrc as ASRC clock source */
255 rt5645_sel_asrc_clk_src(codec,
256 RT5645_DA_STEREO_FILTER |
257 RT5645_DA_MONO_L_FILTER |
258 RT5645_DA_MONO_R_FILTER |
259 RT5645_AD_STEREO_FILTER,
260 RT5645_CLK_SEL_I2S2_ASRC);
261 } else {
262 /* Select clk_i2s1_asrc as ASRC clock source */
263 rt5645_sel_asrc_clk_src(codec,
264 RT5645_DA_STEREO_FILTER |
265 RT5645_DA_MONO_L_FILTER |
266 RT5645_DA_MONO_R_FILTER |
267 RT5645_AD_STEREO_FILTER,
268 RT5645_CLK_SEL_I2S1_ASRC);
269 }
e18acdc0 270
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271 if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) {
272 ret = snd_soc_dapm_add_routes(&card->dapm,
273 cht_rt5645_ssp2_aif2_map,
274 ARRAY_SIZE(cht_rt5645_ssp2_aif2_map));
275 } else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) {
276 ret = snd_soc_dapm_add_routes(&card->dapm,
277 cht_rt5645_ssp0_aif1_map,
278 ARRAY_SIZE(cht_rt5645_ssp0_aif1_map));
279 } else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2) {
280 ret = snd_soc_dapm_add_routes(&card->dapm,
281 cht_rt5645_ssp0_aif2_map,
282 ARRAY_SIZE(cht_rt5645_ssp0_aif2_map));
283 } else {
284 ret = snd_soc_dapm_add_routes(&card->dapm,
285 cht_rt5645_ssp2_aif1_map,
286 ARRAY_SIZE(cht_rt5645_ssp2_aif1_map));
287 }
288 if (ret)
289 return ret;
290
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291 if (ctx->acpi_card->codec_type == CODEC_TYPE_RT5650)
292 jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
293 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
294 SND_JACK_BTN_2 | SND_JACK_BTN_3;
295 else
296 jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE;
e18acdc0 297
2303b32f 298 ret = snd_soc_card_jack_new(runtime->card, "Headset",
673c4f89 299 jack_type, &ctx->jack,
2303b32f 300 cht_bsw_jack_pins, ARRAY_SIZE(cht_bsw_jack_pins));
e18acdc0 301 if (ret) {
673c4f89 302 dev_err(runtime->dev, "Headset jack creation failed %d\n", ret);
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303 return ret;
304 }
305
673c4f89 306 rt5645_set_jack_detect(codec, &ctx->jack, &ctx->jack, &ctx->jack);
e18acdc0 307
a50477e5 308
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309 /*
310 * The firmware might enable the clock at
311 * boot (this information may or may not
312 * be reflected in the enable clock register).
313 * To change the rate we must disable the clock
314 * first to cover these cases. Due to common
315 * clock framework restrictions that do not allow
316 * to disable a clock that has not been enabled,
317 * we need to enable the clock first.
318 */
319 ret = clk_prepare_enable(ctx->mclk);
320 if (!ret)
321 clk_disable_unprepare(ctx->mclk);
322
323 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
324
325 if (ret)
326 dev_err(runtime->dev, "unable to set MCLK rate\n");
a50477e5 327
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328 return ret;
329}
330
331static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd,
332 struct snd_pcm_hw_params *params)
333{
22af2911 334 int ret;
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335 struct snd_interval *rate = hw_param_interval(params,
336 SNDRV_PCM_HW_PARAM_RATE);
337 struct snd_interval *channels = hw_param_interval(params,
338 SNDRV_PCM_HW_PARAM_CHANNELS);
339
340 /* The DSP will covert the FE rate to 48k, stereo, 24bits */
341 rate->min = rate->max = 48000;
342 channels->min = channels->max = 2;
343
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344 if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) ||
345 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
346
347 /* set SSP0 to 16-bit */
348 params_set_format(params, SNDRV_PCM_FORMAT_S16_LE);
349
350 /*
351 * Default mode for SSP configuration is TDM 4 slot, override config
352 * with explicit setting to I2S 2ch 16-bit. The word length is set with
353 * dai_set_tdm_slot() since there is no other API exposed
354 */
355 ret = snd_soc_dai_set_fmt(rtd->cpu_dai,
356 SND_SOC_DAIFMT_I2S |
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357 SND_SOC_DAIFMT_NB_NF |
358 SND_SOC_DAIFMT_CBS_CFS
359 );
360 if (ret < 0) {
361 dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
362 return ret;
363 }
364
365 ret = snd_soc_dai_set_fmt(rtd->codec_dai,
366 SND_SOC_DAIFMT_I2S |
367 SND_SOC_DAIFMT_NB_NF |
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368 SND_SOC_DAIFMT_CBS_CFS
369 );
370 if (ret < 0) {
371 dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
372 return ret;
373 }
374
375 ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, 0x3, 0x3, 2, 16);
376 if (ret < 0) {
377 dev_err(rtd->dev, "can't set I2S config, err %d\n", ret);
378 return ret;
379 }
380
381 } else {
382
383 /* set SSP2 to 24-bit */
384 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
385
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386 /*
387 * Default mode for SSP configuration is TDM 4 slot
388 */
389 ret = snd_soc_dai_set_fmt(rtd->codec_dai,
390 SND_SOC_DAIFMT_DSP_B |
391 SND_SOC_DAIFMT_IB_NF |
392 SND_SOC_DAIFMT_CBS_CFS);
393 if (ret < 0) {
394 dev_err(rtd->dev, "can't set format to TDM %d\n", ret);
395 return ret;
396 }
397
398 /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */
399 ret = snd_soc_dai_set_tdm_slot(rtd->codec_dai, 0xF, 0xF, 4, 24);
400 if (ret < 0) {
401 dev_err(rtd->dev, "can't set codec TDM slot %d\n", ret);
402 return ret;
403 }
22af2911 404 }
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405 return 0;
406}
407
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408static int cht_aif1_startup(struct snd_pcm_substream *substream)
409{
3d6a76c4
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410 return snd_pcm_hw_constraint_single(substream->runtime,
411 SNDRV_PCM_HW_PARAM_RATE, 48000);
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412}
413
9b6fdef6 414static const struct snd_soc_ops cht_aif1_ops = {
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415 .startup = cht_aif1_startup,
416};
417
9b6fdef6 418static const struct snd_soc_ops cht_be_ssp2_ops = {
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419 .hw_params = cht_aif1_hw_params,
420};
421
422static struct snd_soc_dai_link cht_dailink[] = {
423 [MERR_DPCM_AUDIO] = {
424 .name = "Audio Port",
425 .stream_name = "Audio",
426 .cpu_dai_name = "media-cpu-dai",
427 .codec_dai_name = "snd-soc-dummy-dai",
428 .codec_name = "snd-soc-dummy",
429 .platform_name = "sst-mfld-platform",
c4ba51ba 430 .nonatomic = true,
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431 .dynamic = 1,
432 .dpcm_playback = 1,
433 .dpcm_capture = 1,
434 .ops = &cht_aif1_ops,
435 },
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436 [MERR_DPCM_DEEP_BUFFER] = {
437 .name = "Deep-Buffer Audio Port",
438 .stream_name = "Deep-Buffer Audio",
439 .cpu_dai_name = "deepbuffer-cpu-dai",
440 .codec_dai_name = "snd-soc-dummy-dai",
441 .codec_name = "snd-soc-dummy",
442 .platform_name = "sst-mfld-platform",
443 .nonatomic = true,
444 .dynamic = 1,
445 .dpcm_playback = 1,
446 .ops = &cht_aif1_ops,
447 },
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448 /* CODEC<->CODEC link */
449 /* back ends */
450 {
451 .name = "SSP2-Codec",
149f7757 452 .id = 0,
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453 .cpu_dai_name = "ssp2-port",
454 .platform_name = "sst-mfld-platform",
455 .no_pcm = 1,
456 .codec_dai_name = "rt5645-aif1",
457 .codec_name = "i2c-10EC5645:00",
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458 .init = cht_codec_init,
459 .be_hw_params_fixup = cht_codec_fixup,
c4ba51ba 460 .nonatomic = true,
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461 .dpcm_playback = 1,
462 .dpcm_capture = 1,
463 .ops = &cht_be_ssp2_ops,
464 },
465};
466
467/* SoC card */
c4ba51ba 468static struct snd_soc_card snd_soc_card_chtrt5645 = {
e18acdc0 469 .name = "chtrt5645",
54d8697f 470 .owner = THIS_MODULE,
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471 .dai_link = cht_dailink,
472 .num_links = ARRAY_SIZE(cht_dailink),
473 .dapm_widgets = cht_dapm_widgets,
474 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
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475 .dapm_routes = cht_rt5645_audio_map,
476 .num_dapm_routes = ARRAY_SIZE(cht_rt5645_audio_map),
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477 .controls = cht_mc_controls,
478 .num_controls = ARRAY_SIZE(cht_mc_controls),
479};
480
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481static struct snd_soc_card snd_soc_card_chtrt5650 = {
482 .name = "chtrt5650",
54d8697f 483 .owner = THIS_MODULE,
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484 .dai_link = cht_dailink,
485 .num_links = ARRAY_SIZE(cht_dailink),
486 .dapm_widgets = cht_dapm_widgets,
487 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
488 .dapm_routes = cht_rt5650_audio_map,
489 .num_dapm_routes = ARRAY_SIZE(cht_rt5650_audio_map),
490 .controls = cht_mc_controls,
491 .num_controls = ARRAY_SIZE(cht_mc_controls),
492};
493
494static struct cht_acpi_card snd_soc_cards[] = {
07d5c17b 495 {"10EC5640", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
c4ba51ba 496 {"10EC5645", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
11ad8089 497 {"10EC5648", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
bf92c6ef 498 {"10EC3270", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
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FY
499 {"10EC5650", CODEC_TYPE_RT5650, &snd_soc_card_chtrt5650},
500};
501
2be2d579 502static char cht_rt5645_codec_name[SND_ACPI_I2C_ID_LEN];
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503static char cht_rt5645_codec_aif_name[12]; /* = "rt5645-aif[1|2]" */
504static char cht_rt5645_cpu_dai_name[10]; /* = "ssp[0|2]-port" */
07d5c17b 505
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506static bool is_valleyview(void)
507{
508 static const struct x86_cpu_id cpu_ids[] = {
509 { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
510 {}
511 };
512
513 if (!x86_match_cpu(cpu_ids))
514 return false;
515 return true;
516}
517
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518struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */
519 u64 aif_value; /* 1: AIF1, 2: AIF2 */
520 u64 mclock_value; /* usually 25MHz (0x17d7940), ignored */
521};
522
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FY
523static int snd_cht_mc_probe(struct platform_device *pdev)
524{
c4ba51ba 525 struct snd_soc_card *card = snd_soc_cards[0].soc_card;
7feb2f78 526 struct snd_soc_acpi_mach *mach;
6cdf01a5 527 struct cht_mc_private *drv;
07d5c17b 528 const char *i2c_name = NULL;
42648c22 529 bool found = false;
22af2911 530 bool is_bytcr = false;
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531 int dai_index = 0;
532 int ret_val = 0;
533 int i;
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534
535 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_ATOMIC);
536 if (!drv)
537 return -ENOMEM;
538
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539 mach = (&pdev->dev)->platform_data;
540
c4ba51ba 541 for (i = 0; i < ARRAY_SIZE(snd_soc_cards); i++) {
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542 if (acpi_dev_found(snd_soc_cards[i].codec_id) &&
543 (!strncmp(snd_soc_cards[i].codec_id, mach->id, 8))) {
c4ba51ba
FY
544 dev_dbg(&pdev->dev,
545 "found codec %s\n", snd_soc_cards[i].codec_id);
546 card = snd_soc_cards[i].soc_card;
547 drv->acpi_card = &snd_soc_cards[i];
42648c22 548 found = true;
c4ba51ba
FY
549 break;
550 }
551 }
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552
553 if (!found) {
554 dev_err(&pdev->dev, "No matching HID found in supported list\n");
555 return -ENODEV;
556 }
557
c4ba51ba 558 card->dev = &pdev->dev;
a823a179 559 sprintf(drv->codec_name, "i2c-%s:00", drv->acpi_card->codec_id);
c8560b7c 560
c4ba51ba 561 /* set correct codec name */
c8560b7c 562 for (i = 0; i < ARRAY_SIZE(cht_dailink); i++)
07d5c17b 563 if (!strcmp(card->dai_link[i].codec_name, "i2c-10EC5645:00")) {
a823a179 564 card->dai_link[i].codec_name = drv->codec_name;
07d5c17b
VK
565 dai_index = i;
566 }
567
568 /* fixup codec name based on HID */
7feb2f78 569 i2c_name = snd_soc_acpi_find_name_from_hid(mach->id);
6cdf01a5 570 if (i2c_name) {
22af2911 571 snprintf(cht_rt5645_codec_name, sizeof(cht_rt5645_codec_name),
07d5c17b 572 "%s%s", "i2c-", i2c_name);
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573 cht_dailink[dai_index].codec_name = cht_rt5645_codec_name;
574 }
575
576 /*
577 * swap SSP0 if bytcr is detected
578 * (will be overridden if DMI quirk is detected)
579 */
580 if (is_valleyview()) {
581 struct sst_platform_info *p_info = mach->pdata;
582 const struct sst_res_info *res_info = p_info->res_info;
583
584 if (res_info->acpi_ipc_irq_index == 0)
585 is_bytcr = true;
586 }
587
588 if (is_bytcr) {
589 /*
590 * Baytrail CR platforms may have CHAN package in BIOS, try
591 * to find relevant routing quirk based as done on Windows
592 * platforms. We have to read the information directly from the
593 * BIOS, at this stage the card is not created and the links
594 * with the codec driver/pdata are non-existent
595 */
596
597 struct acpi_chan_package chan_package;
598
599 /* format specified: 2 64-bit integers */
600 struct acpi_buffer format = {sizeof("NN"), "NN"};
601 struct acpi_buffer state = {0, NULL};
7feb2f78 602 struct snd_soc_acpi_package_context pkg_ctx;
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603 bool pkg_found = false;
604
605 state.length = sizeof(chan_package);
606 state.pointer = &chan_package;
607
608 pkg_ctx.name = "CHAN";
609 pkg_ctx.length = 2;
610 pkg_ctx.format = &format;
611 pkg_ctx.state = &state;
612 pkg_ctx.data_valid = false;
613
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614 pkg_found = snd_soc_acpi_find_package_from_hid(mach->id,
615 &pkg_ctx);
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616 if (pkg_found) {
617 if (chan_package.aif_value == 1) {
618 dev_info(&pdev->dev, "BIOS Routing: AIF1 connected\n");
619 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF1;
620 } else if (chan_package.aif_value == 2) {
621 dev_info(&pdev->dev, "BIOS Routing: AIF2 connected\n");
622 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2;
623 } else {
624 dev_info(&pdev->dev, "BIOS Routing isn't valid, ignored\n");
625 pkg_found = false;
626 }
627 }
628
629 if (!pkg_found) {
630 /* no BIOS indications, assume SSP0-AIF2 connection */
631 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2;
632 }
633 }
634
635 /* check quirks before creating card */
636 dmi_check_system(cht_rt5645_quirk_table);
637 log_quirks(&pdev->dev);
638
639 if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||
640 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
641
642 /* fixup codec aif name */
643 snprintf(cht_rt5645_codec_aif_name,
644 sizeof(cht_rt5645_codec_aif_name),
645 "%s", "rt5645-aif2");
646
647 cht_dailink[dai_index].codec_dai_name =
648 cht_rt5645_codec_aif_name;
649 }
650
651 if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) ||
652 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
653
654 /* fixup cpu dai name name */
655 snprintf(cht_rt5645_cpu_dai_name,
656 sizeof(cht_rt5645_cpu_dai_name),
657 "%s", "ssp0-port");
658
659 cht_dailink[dai_index].cpu_dai_name =
660 cht_rt5645_cpu_dai_name;
07d5c17b 661 }
c8560b7c 662
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PLB
663 drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
664 if (IS_ERR(drv->mclk)) {
665 dev_err(&pdev->dev,
666 "Failed to get MCLK from pmc_plt_clk_3: %ld\n",
667 PTR_ERR(drv->mclk));
668 return PTR_ERR(drv->mclk);
a50477e5
PLB
669 }
670
c4ba51ba
FY
671 snd_soc_card_set_drvdata(card, drv);
672 ret_val = devm_snd_soc_register_card(&pdev->dev, card);
e18acdc0
FY
673 if (ret_val) {
674 dev_err(&pdev->dev,
675 "snd_soc_register_card failed %d\n", ret_val);
676 return ret_val;
677 }
c4ba51ba 678 platform_set_drvdata(pdev, card);
e18acdc0
FY
679 return ret_val;
680}
681
682static struct platform_driver snd_cht_mc_driver = {
683 .driver = {
e18acdc0 684 .name = "cht-bsw-rt5645",
e18acdc0
FY
685 },
686 .probe = snd_cht_mc_probe,
687};
688
689module_platform_driver(snd_cht_mc_driver)
690
691MODULE_DESCRIPTION("ASoC Intel(R) Braswell Machine driver");
692MODULE_AUTHOR("Fang, Yang A,N,Harshapriya");
693MODULE_LICENSE("GPL v2");
694MODULE_ALIAS("platform:cht-bsw-rt5645");