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ASoC: Intel: cht-bsw-rt5645: select ASRC source based on routing quirk
[mirror_ubuntu-bionic-kernel.git] / sound / soc / intel / boards / cht_bsw_rt5645.c
CommitLineData
e18acdc0
FY		 1/*
2 * cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms
3 * Cherrytrail and Braswell, with RT5645 codec.
4 *
5 * Copyright (C) 2015 Intel Corp
6 * Author: Fang, Yang A <yang.a.fang@intel.com>
7 * N,Harshapriya <harshapriya.n@intel.com>
8 * This file is modified from cht_bsw_rt5672.c
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 */
22
23#include <linux/module.h>
c4ba51ba 24#include <linux/acpi.h>
e18acdc0 25#include <linux/platform_device.h>
22af2911 26#include <linux/dmi.h>
e18acdc0 27#include <linux/slab.h>
a50477e5
PLB		 28#include <asm/cpu_device_id.h>
29#include <asm/platform_sst_audio.h>
30#include <linux/clk.h>
e18acdc0
FY		 31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/jack.h>
e56c72d5 35#include "../../codecs/rt5645.h"
b97169da 36#include "../atom/sst-atom-controls.h"
07d5c17b 37#include "../common/sst-acpi.h"
e18acdc0
FY		 38
39#define CHT_PLAT_CLK_3_HZ 19200000
22af2911
PLB		 40#define CHT_CODEC_DAI1 "rt5645-aif1"
41#define CHT_CODEC_DAI2 "rt5645-aif2"
e18acdc0 42
c4ba51ba
FY		 43struct cht_acpi_card {
44 char *codec_id;
45 int codec_type;
46 struct snd_soc_card *soc_card;
47};
48
e18acdc0 49struct cht_mc_private {
673c4f89 50 struct snd_soc_jack jack;
c4ba51ba 51 struct cht_acpi_card *acpi_card;
a823a179 52 char codec_name[16];
a50477e5 53 struct clk *mclk;
e18acdc0
FY		 54};
55
22af2911
PLB		 56#define CHT_RT5645_MAP(quirk) ((quirk) & 0xff)
57#define CHT_RT5645_SSP2_AIF2 BIT(16) /* default is using AIF1 */
58#define CHT_RT5645_SSP0_AIF1 BIT(17)
59#define CHT_RT5645_SSP0_AIF2 BIT(18)
60
61static unsigned long cht_rt5645_quirk = 0;
62
63static void log_quirks(struct device *dev)
64{
65 if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2)
66 dev_info(dev, "quirk SSP2_AIF2 enabled");
67 if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1)
68 dev_info(dev, "quirk SSP0_AIF1 enabled");
69 if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)
70 dev_info(dev, "quirk SSP0_AIF2 enabled");
71}
72
e18acdc0
FY		 73static inline struct snd_soc_dai *cht_get_codec_dai(struct snd_soc_card *card)
74{
1a497983 75 struct snd_soc_pcm_runtime *rtd;
e18acdc0 76
1a497983 77 list_for_each_entry(rtd, &card->rtd_list, list) {
22af2911
PLB		 78 if (!strncmp(rtd->codec_dai->name, CHT_CODEC_DAI1,
79 strlen(CHT_CODEC_DAI1)))
80 return rtd->codec_dai;
81 if (!strncmp(rtd->codec_dai->name, CHT_CODEC_DAI2,
82 strlen(CHT_CODEC_DAI2)))
e18acdc0
FY		 83 return rtd->codec_dai;
84 }
85 return NULL;
86}
87
88static int platform_clock_control(struct snd_soc_dapm_widget *w,
89 struct snd_kcontrol *k, int event)
90{
91 struct snd_soc_dapm_context *dapm = w->dapm;
92 struct snd_soc_card *card = dapm->card;
93 struct snd_soc_dai *codec_dai;
a50477e5 94 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
e18acdc0
FY		 95 int ret;
96
97 codec_dai = cht_get_codec_dai(card);
98 if (!codec_dai) {
99 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n");
100 return -EIO;
101 }
102
a50477e5
PLB		 103 if (SND_SOC_DAPM_EVENT_ON(event)) {
104 if (ctx->mclk) {
105 ret = clk_prepare_enable(ctx->mclk);
106 if (ret < 0) {
107 dev_err(card->dev,
108 "could not configure MCLK state");
109 return ret;
110 }
111 }
112 } else {
113 /* Set codec sysclk source to its internal clock because codec PLL will
114 * be off when idle and MCLK will also be off when codec is
115 * runtime suspended. Codec needs clock for jack detection and button
116 * press. MCLK is turned off with clock framework or ACPI.
117 */
118 ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_RCCLK,
119 48000 * 512, SND_SOC_CLOCK_IN);
120 if (ret < 0) {
121 dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
122 return ret;
123 }
e18acdc0 124
a50477e5
PLB		 125 if (ctx->mclk)
126 clk_disable_unprepare(ctx->mclk);
e18acdc0
FY		 127 }
128
129 return 0;
130}
131
132static const struct snd_soc_dapm_widget cht_dapm_widgets[] = {
133 SND_SOC_DAPM_HP("Headphone", NULL),
134 SND_SOC_DAPM_MIC("Headset Mic", NULL),
135 SND_SOC_DAPM_MIC("Int Mic", NULL),
136 SND_SOC_DAPM_SPK("Ext Spk", NULL),
137 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
a50477e5 138 platform_clock_control, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
e18acdc0
FY		 139};
140
c4ba51ba 141static const struct snd_soc_dapm_route cht_rt5645_audio_map[] = {
e18acdc0
FY		 142 {"IN1P", NULL, "Headset Mic"},
143 {"IN1N", NULL, "Headset Mic"},
144 {"DMIC L1", NULL, "Int Mic"},
145 {"DMIC R1", NULL, "Int Mic"},
146 {"Headphone", NULL, "HPOL"},
147 {"Headphone", NULL, "HPOR"},
148 {"Ext Spk", NULL, "SPOL"},
149 {"Ext Spk", NULL, "SPOR"},
e18acdc0
FY		 150 {"Headphone", NULL, "Platform Clock"},
151 {"Headset Mic", NULL, "Platform Clock"},
152 {"Int Mic", NULL, "Platform Clock"},
153 {"Ext Spk", NULL, "Platform Clock"},
154};
155
c4ba51ba
FY		 156static const struct snd_soc_dapm_route cht_rt5650_audio_map[] = {
157 {"IN1P", NULL, "Headset Mic"},
158 {"IN1N", NULL, "Headset Mic"},
159 {"DMIC L2", NULL, "Int Mic"},
160 {"DMIC R2", NULL, "Int Mic"},
161 {"Headphone", NULL, "HPOL"},
162 {"Headphone", NULL, "HPOR"},
163 {"Ext Spk", NULL, "SPOL"},
164 {"Ext Spk", NULL, "SPOR"},
22af2911
PLB		 165 {"Headphone", NULL, "Platform Clock"},
166 {"Headset Mic", NULL, "Platform Clock"},
167 {"Int Mic", NULL, "Platform Clock"},
168 {"Ext Spk", NULL, "Platform Clock"},
169};
170
171static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif1_map[] = {
c4ba51ba
FY		 172 {"AIF1 Playback", NULL, "ssp2 Tx"},
173 {"ssp2 Tx", NULL, "codec_out0"},
174 {"ssp2 Tx", NULL, "codec_out1"},
175 {"codec_in0", NULL, "ssp2 Rx" },
176 {"codec_in1", NULL, "ssp2 Rx" },
177 {"ssp2 Rx", NULL, "AIF1 Capture"},
22af2911
PLB		 178};
179
180static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif2_map[] = {
181 {"AIF2 Playback", NULL, "ssp2 Tx"},
182 {"ssp2 Tx", NULL, "codec_out0"},
183 {"ssp2 Tx", NULL, "codec_out1"},
184 {"codec_in0", NULL, "ssp2 Rx" },
185 {"codec_in1", NULL, "ssp2 Rx" },
186 {"ssp2 Rx", NULL, "AIF2 Capture"},
187};
188
189static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif1_map[] = {
190 {"AIF1 Playback", NULL, "ssp0 Tx"},
191 {"ssp0 Tx", NULL, "modem_out"},
192 {"modem_in", NULL, "ssp0 Rx" },
193 {"ssp0 Rx", NULL, "AIF1 Capture"},
194};
195
196static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif2_map[] = {
197 {"AIF2 Playback", NULL, "ssp0 Tx"},
198 {"ssp0 Tx", NULL, "modem_out"},
199 {"modem_in", NULL, "ssp0 Rx" },
200 {"ssp0 Rx", NULL, "AIF2 Capture"},
c4ba51ba
FY		 201};
202
e18acdc0
FY		 203static const struct snd_kcontrol_new cht_mc_controls[] = {
204 SOC_DAPM_PIN_SWITCH("Headphone"),
205 SOC_DAPM_PIN_SWITCH("Headset Mic"),
206 SOC_DAPM_PIN_SWITCH("Int Mic"),
207 SOC_DAPM_PIN_SWITCH("Ext Spk"),
208};
209
2303b32f
CC		 210static struct snd_soc_jack_pin cht_bsw_jack_pins[] = {
211 {
212 .pin = "Headphone",
213 .mask = SND_JACK_HEADPHONE,
214 },
215 {
216 .pin = "Headset Mic",
217 .mask = SND_JACK_MICROPHONE,
218 },
219};
220
e18acdc0
FY		 221static int cht_aif1_hw_params(struct snd_pcm_substream *substream,
222 struct snd_pcm_hw_params *params)
223{
224 struct snd_soc_pcm_runtime *rtd = substream->private_data;
225 struct snd_soc_dai *codec_dai = rtd->codec_dai;
226 int ret;
227
228 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */
229 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,
230 CHT_PLAT_CLK_3_HZ, params_rate(params) * 512);
231 if (ret < 0) {
232 dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
233 return ret;
234 }
235
236 ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,
237 params_rate(params) * 512, SND_SOC_CLOCK_IN);
238 if (ret < 0) {
239 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
240 return ret;
241 }
242
243 return 0;
244}
245
22af2911
PLB		 246/* uncomment when we have a real quirk
247static int cht_rt5645_quirk_cb(const struct dmi_system_id *id)
248{
249 cht_rt5645_quirk = (unsigned long)id->driver_data;
250 return 1;
251}
252*/
253
254static const struct dmi_system_id cht_rt5645_quirk_table[] = {
255 {
256 },
257};
258
e18acdc0
FY		 259static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
260{
261 int ret;
673c4f89 262 int jack_type;
e18acdc0 263 struct snd_soc_codec *codec = runtime->codec;
22af2911 264 struct snd_soc_card *card = runtime->card;
e18acdc0
FY		 265 struct snd_soc_dai *codec_dai = runtime->codec_dai;
266 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card);
267
d74390b5
PLB		 268 if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||
269 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
270 /* Select clk_i2s2_asrc as ASRC clock source */
271 rt5645_sel_asrc_clk_src(codec,
272 RT5645_DA_STEREO_FILTER |
273 RT5645_DA_MONO_L_FILTER |
274 RT5645_DA_MONO_R_FILTER |
275 RT5645_AD_STEREO_FILTER,
276 RT5645_CLK_SEL_I2S2_ASRC);
277 } else {
278 /* Select clk_i2s1_asrc as ASRC clock source */
279 rt5645_sel_asrc_clk_src(codec,
280 RT5645_DA_STEREO_FILTER |
281 RT5645_DA_MONO_L_FILTER |
282 RT5645_DA_MONO_R_FILTER |
283 RT5645_AD_STEREO_FILTER,
284 RT5645_CLK_SEL_I2S1_ASRC);
285 }
e18acdc0 286
22af2911
PLB		 287 if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) {
288 ret = snd_soc_dapm_add_routes(&card->dapm,
289 cht_rt5645_ssp2_aif2_map,
290 ARRAY_SIZE(cht_rt5645_ssp2_aif2_map));
291 } else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) {
292 ret = snd_soc_dapm_add_routes(&card->dapm,
293 cht_rt5645_ssp0_aif1_map,
294 ARRAY_SIZE(cht_rt5645_ssp0_aif1_map));
295 } else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2) {
296 ret = snd_soc_dapm_add_routes(&card->dapm,
297 cht_rt5645_ssp0_aif2_map,
298 ARRAY_SIZE(cht_rt5645_ssp0_aif2_map));
299 } else {
300 ret = snd_soc_dapm_add_routes(&card->dapm,
301 cht_rt5645_ssp2_aif1_map,
302 ARRAY_SIZE(cht_rt5645_ssp2_aif1_map));
303 }
304 if (ret)
305 return ret;
306
e18acdc0
FY		 307 /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */
308 ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xF, 0xF, 4, 24);
309 if (ret < 0) {
310 dev_err(runtime->dev, "can't set codec TDM slot %d\n", ret);
311 return ret;
312 }
313
673c4f89
FY		 314 if (ctx->acpi_card->codec_type == CODEC_TYPE_RT5650)
315 jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
316 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
317 SND_JACK_BTN_2 | SND_JACK_BTN_3;
318 else
319 jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE;
e18acdc0 320
2303b32f 321 ret = snd_soc_card_jack_new(runtime->card, "Headset",
673c4f89 322 jack_type, &ctx->jack,
2303b32f 323 cht_bsw_jack_pins, ARRAY_SIZE(cht_bsw_jack_pins));
e18acdc0 324 if (ret) {
673c4f89 325 dev_err(runtime->dev, "Headset jack creation failed %d\n", ret);
e18acdc0
FY		 326 return ret;
327 }
328
673c4f89 329 rt5645_set_jack_detect(codec, &ctx->jack, &ctx->jack, &ctx->jack);
e18acdc0 330
a50477e5
PLB		 331 if (ctx->mclk) {
332 /*
333 * The firmware might enable the clock at
334 * boot (this information may or may not
335 * be reflected in the enable clock register).
336 * To change the rate we must disable the clock
337 * first to cover these cases. Due to common
338 * clock framework restrictions that do not allow
339 * to disable a clock that has not been enabled,
340 * we need to enable the clock first.
341 */
342 ret = clk_prepare_enable(ctx->mclk);
343 if (!ret)
344 clk_disable_unprepare(ctx->mclk);
345
346 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
347
348 if (ret)
349 dev_err(runtime->dev, "unable to set MCLK rate\n");
350 }
e18acdc0
FY		 351 return ret;
352}
353
354static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd,
355 struct snd_pcm_hw_params *params)
356{
22af2911 357 int ret;
e18acdc0
FY		 358 struct snd_interval *rate = hw_param_interval(params,
359 SNDRV_PCM_HW_PARAM_RATE);
360 struct snd_interval *channels = hw_param_interval(params,
361 SNDRV_PCM_HW_PARAM_CHANNELS);
362
363 /* The DSP will covert the FE rate to 48k, stereo, 24bits */
364 rate->min = rate->max = 48000;
365 channels->min = channels->max = 2;
366
22af2911
PLB		 367 if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) ||
368 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
369
370 /* set SSP0 to 16-bit */
371 params_set_format(params, SNDRV_PCM_FORMAT_S16_LE);
372
373 /*
374 * Default mode for SSP configuration is TDM 4 slot, override config
375 * with explicit setting to I2S 2ch 16-bit. The word length is set with
376 * dai_set_tdm_slot() since there is no other API exposed
377 */
378 ret = snd_soc_dai_set_fmt(rtd->cpu_dai,
379 SND_SOC_DAIFMT_I2S |
380 SND_SOC_DAIFMT_NB_IF |
381 SND_SOC_DAIFMT_CBS_CFS
382 );
383 if (ret < 0) {
384 dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
385 return ret;
386 }
387
388 ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, 0x3, 0x3, 2, 16);
389 if (ret < 0) {
390 dev_err(rtd->dev, "can't set I2S config, err %d\n", ret);
391 return ret;
392 }
393
394 } else {
395
396 /* set SSP2 to 24-bit */
397 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
398
399 }
e18acdc0
FY		 400 return 0;
401}
402
e18acdc0
FY		 403static int cht_aif1_startup(struct snd_pcm_substream *substream)
404{
3d6a76c4
LPC		 405 return snd_pcm_hw_constraint_single(substream->runtime,
406 SNDRV_PCM_HW_PARAM_RATE, 48000);
e18acdc0
FY		 407}
408
9b6fdef6 409static const struct snd_soc_ops cht_aif1_ops = {
e18acdc0
FY		 410 .startup = cht_aif1_startup,
411};
412
9b6fdef6 413static const struct snd_soc_ops cht_be_ssp2_ops = {
e18acdc0
FY		 414 .hw_params = cht_aif1_hw_params,
415};
416
417static struct snd_soc_dai_link cht_dailink[] = {
418 [MERR_DPCM_AUDIO] = {
419 .name = "Audio Port",
420 .stream_name = "Audio",
421 .cpu_dai_name = "media-cpu-dai",
422 .codec_dai_name = "snd-soc-dummy-dai",
423 .codec_name = "snd-soc-dummy",
424 .platform_name = "sst-mfld-platform",
c4ba51ba 425 .nonatomic = true,
e18acdc0
FY		 426 .dynamic = 1,
427 .dpcm_playback = 1,
428 .dpcm_capture = 1,
429 .ops = &cht_aif1_ops,
430 },
d35eb96a
PLB		 431 [MERR_DPCM_DEEP_BUFFER] = {
432 .name = "Deep-Buffer Audio Port",
433 .stream_name = "Deep-Buffer Audio",
434 .cpu_dai_name = "deepbuffer-cpu-dai",
435 .codec_dai_name = "snd-soc-dummy-dai",
436 .codec_name = "snd-soc-dummy",
437 .platform_name = "sst-mfld-platform",
438 .nonatomic = true,
439 .dynamic = 1,
440 .dpcm_playback = 1,
441 .ops = &cht_aif1_ops,
442 },
e18acdc0
FY		 443 [MERR_DPCM_COMPR] = {
444 .name = "Compressed Port",
445 .stream_name = "Compress",
446 .cpu_dai_name = "compress-cpu-dai",
447 .codec_dai_name = "snd-soc-dummy-dai",
448 .codec_name = "snd-soc-dummy",
449 .platform_name = "sst-mfld-platform",
450 },
451 /* CODEC<->CODEC link */
452 /* back ends */
453 {
454 .name = "SSP2-Codec",
2f0ad491 455 .id = 1,
e18acdc0
FY		 456 .cpu_dai_name = "ssp2-port",
457 .platform_name = "sst-mfld-platform",
458 .no_pcm = 1,
459 .codec_dai_name = "rt5645-aif1",
460 .codec_name = "i2c-10EC5645:00",
461 .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF
462 | SND_SOC_DAIFMT_CBS_CFS,
463 .init = cht_codec_init,
464 .be_hw_params_fixup = cht_codec_fixup,
c4ba51ba 465 .nonatomic = true,
e18acdc0
FY		 466 .dpcm_playback = 1,
467 .dpcm_capture = 1,
468 .ops = &cht_be_ssp2_ops,
469 },
470};
471
472/* SoC card */
c4ba51ba 473static struct snd_soc_card snd_soc_card_chtrt5645 = {
e18acdc0 474 .name = "chtrt5645",
54d8697f 475 .owner = THIS_MODULE,
e18acdc0
FY		 476 .dai_link = cht_dailink,
477 .num_links = ARRAY_SIZE(cht_dailink),
478 .dapm_widgets = cht_dapm_widgets,
479 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
c4ba51ba
FY		 480 .dapm_routes = cht_rt5645_audio_map,
481 .num_dapm_routes = ARRAY_SIZE(cht_rt5645_audio_map),
e18acdc0
FY		 482 .controls = cht_mc_controls,
483 .num_controls = ARRAY_SIZE(cht_mc_controls),
484};
485
c4ba51ba
FY		 486static struct snd_soc_card snd_soc_card_chtrt5650 = {
487 .name = "chtrt5650",
54d8697f 488 .owner = THIS_MODULE,
c4ba51ba
FY		 489 .dai_link = cht_dailink,
490 .num_links = ARRAY_SIZE(cht_dailink),
491 .dapm_widgets = cht_dapm_widgets,
492 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
493 .dapm_routes = cht_rt5650_audio_map,
494 .num_dapm_routes = ARRAY_SIZE(cht_rt5650_audio_map),
495 .controls = cht_mc_controls,
496 .num_controls = ARRAY_SIZE(cht_mc_controls),
497};
498
499static struct cht_acpi_card snd_soc_cards[] = {
07d5c17b 500 {"10EC5640", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
c4ba51ba 501 {"10EC5645", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
11ad8089 502 {"10EC5648", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
c4ba51ba
FY		 503 {"10EC5650", CODEC_TYPE_RT5650, &snd_soc_card_chtrt5650},
504};
505
22af2911
PLB		 506static char cht_rt5645_codec_name[16]; /* i2c-<HID>:00 with HID being 8 chars */
507static char cht_rt5645_codec_aif_name[12]; /* = "rt5645-aif[1|2]" */
508static char cht_rt5645_cpu_dai_name[10]; /* = "ssp[0|2]-port" */
07d5c17b 509
a50477e5
PLB		 510static bool is_valleyview(void)
511{
512 static const struct x86_cpu_id cpu_ids[] = {
513 { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
514 {}
515 };
516
517 if (!x86_match_cpu(cpu_ids))
518 return false;
519 return true;
520}
521
22af2911
PLB		 522struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */
523 u64 aif_value; /* 1: AIF1, 2: AIF2 */
524 u64 mclock_value; /* usually 25MHz (0x17d7940), ignored */
525};
526
e18acdc0
FY		 527static int snd_cht_mc_probe(struct platform_device *pdev)
528{
529 int ret_val = 0;
c4ba51ba 530 int i;
e18acdc0 531 struct cht_mc_private *drv;
c4ba51ba 532 struct snd_soc_card *card = snd_soc_cards[0].soc_card;
07d5c17b
VK		 533 struct sst_acpi_mach *mach;
534 const char *i2c_name = NULL;
5d554ea4 535 int dai_index = 0;
42648c22 536 bool found = false;
22af2911 537 bool is_bytcr = false;
e18acdc0
FY		 538
539 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_ATOMIC);
540 if (!drv)
541 return -ENOMEM;
542
42648c22
PLB		 543 mach = (&pdev->dev)->platform_data;
544
c4ba51ba 545 for (i = 0; i < ARRAY_SIZE(snd_soc_cards); i++) {
42648c22
PLB		 546 if (acpi_dev_found(snd_soc_cards[i].codec_id) &&
547 (!strncmp(snd_soc_cards[i].codec_id, mach->id, 8))) {
c4ba51ba
FY		 548 dev_dbg(&pdev->dev,
549 "found codec %s\n", snd_soc_cards[i].codec_id);
550 card = snd_soc_cards[i].soc_card;
551 drv->acpi_card = &snd_soc_cards[i];
42648c22 552 found = true;
c4ba51ba
FY		 553 break;
554 }
555 }
42648c22
PLB		 556
557 if (!found) {
558 dev_err(&pdev->dev, "No matching HID found in supported list\n");
559 return -ENODEV;
560 }
561
c4ba51ba 562 card->dev = &pdev->dev;
a823a179 563 sprintf(drv->codec_name, "i2c-%s:00", drv->acpi_card->codec_id);
c8560b7c 564
c4ba51ba 565 /* set correct codec name */
c8560b7c 566 for (i = 0; i < ARRAY_SIZE(cht_dailink); i++)
07d5c17b 567 if (!strcmp(card->dai_link[i].codec_name, "i2c-10EC5645:00")) {
a823a179 568 card->dai_link[i].codec_name = drv->codec_name;
07d5c17b
VK		 569 dai_index = i;
570 }
571
572 /* fixup codec name based on HID */
573 i2c_name = sst_acpi_find_name_from_hid(mach->id);
574 if (i2c_name != NULL) {
22af2911 575 snprintf(cht_rt5645_codec_name, sizeof(cht_rt5645_codec_name),
07d5c17b 576 "%s%s", "i2c-", i2c_name);
22af2911
PLB		 577 cht_dailink[dai_index].codec_name = cht_rt5645_codec_name;
578 }
579
580 /*
581 * swap SSP0 if bytcr is detected
582 * (will be overridden if DMI quirk is detected)
583 */
584 if (is_valleyview()) {
585 struct sst_platform_info *p_info = mach->pdata;
586 const struct sst_res_info *res_info = p_info->res_info;
587
588 if (res_info->acpi_ipc_irq_index == 0)
589 is_bytcr = true;
590 }
591
592 if (is_bytcr) {
593 /*
594 * Baytrail CR platforms may have CHAN package in BIOS, try
595 * to find relevant routing quirk based as done on Windows
596 * platforms. We have to read the information directly from the
597 * BIOS, at this stage the card is not created and the links
598 * with the codec driver/pdata are non-existent
599 */
600
601 struct acpi_chan_package chan_package;
602
603 /* format specified: 2 64-bit integers */
604 struct acpi_buffer format = {sizeof("NN"), "NN"};
605 struct acpi_buffer state = {0, NULL};
606 struct sst_acpi_package_context pkg_ctx;
607 bool pkg_found = false;
608
609 state.length = sizeof(chan_package);
610 state.pointer = &chan_package;
611
612 pkg_ctx.name = "CHAN";
613 pkg_ctx.length = 2;
614 pkg_ctx.format = &format;
615 pkg_ctx.state = &state;
616 pkg_ctx.data_valid = false;
617
618 pkg_found = sst_acpi_find_package_from_hid(mach->id, &pkg_ctx);
619 if (pkg_found) {
620 if (chan_package.aif_value == 1) {
621 dev_info(&pdev->dev, "BIOS Routing: AIF1 connected\n");
622 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF1;
623 } else if (chan_package.aif_value == 2) {
624 dev_info(&pdev->dev, "BIOS Routing: AIF2 connected\n");
625 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2;
626 } else {
627 dev_info(&pdev->dev, "BIOS Routing isn't valid, ignored\n");
628 pkg_found = false;
629 }
630 }
631
632 if (!pkg_found) {
633 /* no BIOS indications, assume SSP0-AIF2 connection */
634 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2;
635 }
636 }
637
638 /* check quirks before creating card */
639 dmi_check_system(cht_rt5645_quirk_table);
640 log_quirks(&pdev->dev);
641
642 if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||
643 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
644
645 /* fixup codec aif name */
646 snprintf(cht_rt5645_codec_aif_name,
647 sizeof(cht_rt5645_codec_aif_name),
648 "%s", "rt5645-aif2");
649
650 cht_dailink[dai_index].codec_dai_name =
651 cht_rt5645_codec_aif_name;
652 }
653
654 if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) ||
655 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
656
657 /* fixup cpu dai name name */
658 snprintf(cht_rt5645_cpu_dai_name,
659 sizeof(cht_rt5645_cpu_dai_name),
660 "%s", "ssp0-port");
661
662 cht_dailink[dai_index].cpu_dai_name =
663 cht_rt5645_cpu_dai_name;
07d5c17b 664 }
c8560b7c 665
a50477e5
PLB		 666 if (is_valleyview()) {
667 drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
668 if (IS_ERR(drv->mclk)) {
669 dev_err(&pdev->dev,
670 "Failed to get MCLK from pmc_plt_clk_3: %ld\n",
671 PTR_ERR(drv->mclk));
672 return PTR_ERR(drv->mclk);
673 }
674 }
675
c4ba51ba
FY		 676 snd_soc_card_set_drvdata(card, drv);
677 ret_val = devm_snd_soc_register_card(&pdev->dev, card);
e18acdc0
FY		 678 if (ret_val) {
679 dev_err(&pdev->dev,
680 "snd_soc_register_card failed %d\n", ret_val);
681 return ret_val;
682 }
c4ba51ba 683 platform_set_drvdata(pdev, card);
e18acdc0
FY		 684 return ret_val;
685}
686
687static struct platform_driver snd_cht_mc_driver = {
688 .driver = {
e18acdc0 689 .name = "cht-bsw-rt5645",
e18acdc0
FY		 690 },
691 .probe = snd_cht_mc_probe,
692};
693
694module_platform_driver(snd_cht_mc_driver)
695
696MODULE_DESCRIPTION("ASoC Intel(R) Braswell Machine driver");
697MODULE_AUTHOR("Fang, Yang A,N,Harshapriya");
698MODULE_LICENSE("GPL v2");
699MODULE_ALIAS("platform:cht-bsw-rt5645");
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