[mirror_ubuntu-eoan-kernel.git] / sound / soc / intel / common / sst-dsp.h

/*
 * Intel Smart Sound Technology (SST) Core
 *
 * Copyright (C) 2013, Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __SOUND_SOC_SST_DSP_H
#define __SOUND_SOC_SST_DSP_H

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>

/* SST Device IDs  */
#define SST_DEV_ID_LYNX_POINT		0x33C8
#define SST_DEV_ID_WILDCAT_POINT	0x3438
#define SST_DEV_ID_BYT			0x0F28

/* Supported SST DMA Devices */
#define SST_DMA_TYPE_DW		1

/* autosuspend delay 5s*/
#define SST_RUNTIME_SUSPEND_DELAY	(5 * 1000)

/* SST Shim register map
 * The register naming can differ between products. Some products also
 * contain extra functionality.
 */
#define SST_CSR			0x00
#define SST_PISR		0x08
#define SST_PIMR		0x10
#define SST_ISRX		0x18
#define SST_ISRD		0x20
#define SST_IMRX		0x28
#define SST_IMRD		0x30
#define SST_IPCX		0x38 /* IPC IA -> SST */
#define SST_IPCD		0x40 /* IPC SST -> IA */
#define SST_ISRSC		0x48
#define SST_ISRLPESC		0x50
#define SST_IMRSC		0x58
#define SST_IMRLPESC		0x60
#define SST_IPCSC		0x68
#define SST_IPCLPESC		0x70
#define SST_CLKCTL		0x78
#define SST_CSR2		0x80
#define SST_LTRC		0xE0
#define SST_HMDC		0xE8

#define SST_SHIM_BEGIN		SST_CSR
#define SST_SHIM_END		SST_HDMC

#define SST_DBGO		0xF0

#define SST_SHIM_SIZE		0x100
#define SST_PWMCTRL             0x1000

/* SST Shim Register bits
 * The register bit naming can differ between products. Some products also
 * contain extra functionality.
 */

/* CSR / CS */
#define SST_CSR_RST		(0x1 << 1)
#define SST_CSR_SBCS0		(0x1 << 2)
#define SST_CSR_SBCS1		(0x1 << 3)
#define SST_CSR_DCS(x)		(x << 4)
#define SST_CSR_DCS_MASK	(0x7 << 4)
#define SST_CSR_STALL		(0x1 << 10)
#define SST_CSR_S0IOCS		(0x1 << 21)
#define SST_CSR_S1IOCS		(0x1 << 23)
#define SST_CSR_LPCS		(0x1 << 31)
#define SST_CSR_24MHZ_LPCS	(SST_CSR_SBCS0 | SST_CSR_SBCS1 | SST_CSR_LPCS)
#define SST_CSR_24MHZ_NO_LPCS	(SST_CSR_SBCS0 | SST_CSR_SBCS1)
#define SST_BYT_CSR_RST		(0x1 << 0)
#define SST_BYT_CSR_VECTOR_SEL	(0x1 << 1)
#define SST_BYT_CSR_STALL	(0x1 << 2)
#define SST_BYT_CSR_PWAITMODE	(0x1 << 3)

/*  ISRX / ISC */
#define SST_ISRX_BUSY		(0x1 << 1)
#define SST_ISRX_DONE		(0x1 << 0)
#define SST_BYT_ISRX_REQUEST	(0x1 << 1)

/*  ISRD / ISD */
#define SST_ISRD_BUSY		(0x1 << 1)
#define SST_ISRD_DONE		(0x1 << 0)

/* IMRX / IMC */
#define SST_IMRX_BUSY		(0x1 << 1)
#define SST_IMRX_DONE		(0x1 << 0)
#define SST_BYT_IMRX_REQUEST	(0x1 << 1)

/* IMRD / IMD */
#define SST_IMRD_DONE		(0x1 << 0)
#define SST_IMRD_BUSY		(0x1 << 1)
#define SST_IMRD_SSP0		(0x1 << 16)
#define SST_IMRD_DMAC0		(0x1 << 21)
#define SST_IMRD_DMAC1		(0x1 << 22)
#define SST_IMRD_DMAC		(SST_IMRD_DMAC0 | SST_IMRD_DMAC1)

/*  IPCX / IPCC */
#define	SST_IPCX_DONE		(0x1 << 30)
#define	SST_IPCX_BUSY		(0x1 << 31)
#define SST_BYT_IPCX_DONE	((u64)0x1 << 62)
#define SST_BYT_IPCX_BUSY	((u64)0x1 << 63)

/*  IPCD */
#define	SST_IPCD_DONE		(0x1 << 30)
#define	SST_IPCD_BUSY		(0x1 << 31)
#define SST_BYT_IPCD_DONE	((u64)0x1 << 62)
#define SST_BYT_IPCD_BUSY	((u64)0x1 << 63)

/* CLKCTL */
#define SST_CLKCTL_SMOS(x)	(x << 24)
#define SST_CLKCTL_MASK		(3 << 24)
#define SST_CLKCTL_DCPLCG	(1 << 18)
#define SST_CLKCTL_SCOE1	(1 << 17)
#define SST_CLKCTL_SCOE0	(1 << 16)

/* CSR2 / CS2 */
#define SST_CSR2_SDFD_SSP0	(1 << 1)
#define SST_CSR2_SDFD_SSP1	(1 << 2)

/* LTRC */
#define SST_LTRC_VAL(x)		(x << 0)

/* HMDC */
#define SST_HMDC_HDDA0(x)	(x << 0)
#define SST_HMDC_HDDA1(x)	(x << 7)
#define SST_HMDC_HDDA_E0_CH0	1
#define SST_HMDC_HDDA_E0_CH1	2
#define SST_HMDC_HDDA_E0_CH2	4
#define SST_HMDC_HDDA_E0_CH3	8
#define SST_HMDC_HDDA_E1_CH0	SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH0)
#define SST_HMDC_HDDA_E1_CH1	SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH1)
#define SST_HMDC_HDDA_E1_CH2	SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH2)
#define SST_HMDC_HDDA_E1_CH3	SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH3)
#define SST_HMDC_HDDA_E0_ALLCH	(SST_HMDC_HDDA_E0_CH0 | SST_HMDC_HDDA_E0_CH1 | \
				 SST_HMDC_HDDA_E0_CH2 | SST_HMDC_HDDA_E0_CH3)
#define SST_HMDC_HDDA_E1_ALLCH	(SST_HMDC_HDDA_E1_CH0 | SST_HMDC_HDDA_E1_CH1 | \
				 SST_HMDC_HDDA_E1_CH2 | SST_HMDC_HDDA_E1_CH3)


/* SST Vendor Defined Registers and bits */
#define SST_VDRTCTL0		0xa0
#define SST_VDRTCTL1		0xa4
#define SST_VDRTCTL2		0xa8
#define SST_VDRTCTL3		0xaC

/* VDRTCTL0 */
#define SST_VDRTCL0_D3PGD		(1 << 0)
#define SST_VDRTCL0_D3SRAMPGD		(1 << 1)
#define SST_VDRTCL0_DSRAMPGE_SHIFT	12
#define SST_VDRTCL0_DSRAMPGE_MASK	(0xfffff << SST_VDRTCL0_DSRAMPGE_SHIFT)
#define SST_VDRTCL0_ISRAMPGE_SHIFT	2
#define SST_VDRTCL0_ISRAMPGE_MASK	(0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT)

/* VDRTCTL2 */
#define SST_VDRTCL2_DCLCGE		(1 << 1)
#define SST_VDRTCL2_DTCGE		(1 << 10)
#define SST_VDRTCL2_APLLSE_MASK		(1 << 31)

/* PMCS */
#define SST_PMCS		0x84
#define SST_PMCS_PS_MASK	0x3

struct sst_dsp;

/*
 * SST Device.
 *
 * This structure is populated by the SST core driver.
 */
struct sst_dsp_device {
	/* Mandatory fields */
	struct sst_ops *ops;
	irqreturn_t (*thread)(int irq, void *context);
	void *thread_context;
};

/*
 * SST Platform Data.
 */
struct sst_pdata {
	/* ACPI data */
	u32 lpe_base;
	u32 lpe_size;
	u32 pcicfg_base;
	u32 pcicfg_size;
	u32 fw_base;
	u32 fw_size;
	int irq;

	/* Firmware */
	const struct firmware *fw;

	/* DMA */
	int resindex_dma_base; /* other fields invalid if equals to -1 */
	u32 dma_base;
	u32 dma_size;
	int dma_engine;
	struct device *dma_dev;

	/* DSP */
	u32 id;
	void *dsp;
};

#if IS_ENABLED(CONFIG_DW_DMAC_CORE)
/* Initialization */
struct sst_dsp *sst_dsp_new(struct device *dev,
	struct sst_dsp_device *sst_dev, struct sst_pdata *pdata);
void sst_dsp_free(struct sst_dsp *sst);
#endif

/* SHIM Read / Write */
void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
				u32 mask, u32 value);
void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value);
u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset);
int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
				u64 mask, u64 value);
void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
				u32 mask, u32 value);

/* SHIM Read / Write Unlocked for callers already holding sst lock */
void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
				u32 mask, u32 value);
void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value);
u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset);
int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
					u64 mask, u64 value);
void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
				u32 mask, u32 value);

/* Internal generic low-level SST IO functions - can be overidden */
void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
u32 sst_shim32_read(void __iomem *addr, u32 offset);
void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
u64 sst_shim32_read64(void __iomem *addr, u32 offset);
void sst_memcpy_toio_32(struct sst_dsp *sst,
			void __iomem *dest, void *src, size_t bytes);
void sst_memcpy_fromio_32(struct sst_dsp *sst,
			  void *dest, void __iomem *src, size_t bytes);

/* DSP reset & boot */
void sst_dsp_reset(struct sst_dsp *sst);
int sst_dsp_boot(struct sst_dsp *sst);
int sst_dsp_wake(struct sst_dsp *sst);
void sst_dsp_sleep(struct sst_dsp *sst);
void sst_dsp_stall(struct sst_dsp *sst);

/* DMA */
int sst_dsp_dma_get_channel(struct sst_dsp *dsp, int chan_id);
void sst_dsp_dma_put_channel(struct sst_dsp *dsp);
int sst_dsp_dma_copyfrom(struct sst_dsp *sst, dma_addr_t dest_addr,
	dma_addr_t src_addr, size_t size);
int sst_dsp_dma_copyto(struct sst_dsp *sst, dma_addr_t dest_addr,
	dma_addr_t src_addr, size_t size);

/* Msg IO */
void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg);
u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp);

/* Mailbox management */
int sst_dsp_mailbox_init(struct sst_dsp *dsp, u32 inbox_offset,
	size_t inbox_size, u32 outbox_offset, size_t outbox_size);
void sst_dsp_inbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
void sst_dsp_inbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
void sst_dsp_outbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
void sst_dsp_outbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
void sst_dsp_mailbox_dump(struct sst_dsp *dsp, size_t bytes);
int sst_dsp_register_poll(struct sst_dsp  *dsp, u32 offset, u32 mask,
		 u32 expected_value, u32 timeout, char *operation);

/* Debug */
void sst_dsp_dump(struct sst_dsp *sst);

#endif
Commit	Line	Data
a4b12990 MB	1	/*
	2	* Intel Smart Sound Technology (SST) Core
	3	*
	4	* Copyright (C) 2013, Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License version
	8	* 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
	17	#ifndef __SOUND_SOC_SST_DSP_H
	18	#define __SOUND_SOC_SST_DSP_H
	19
	20	#include <linux/kernel.h>
	21	#include <linux/types.h>
	22	#include <linux/interrupt.h>
	23
	24	/* SST Device IDs */
	25	#define SST_DEV_ID_LYNX_POINT 0x33C8
	26	#define SST_DEV_ID_WILDCAT_POINT 0x3438
	27	#define SST_DEV_ID_BYT 0x0F28
	28
	29	/* Supported SST DMA Devices */
	30	#define SST_DMA_TYPE_DW 1
a4b12990	31
2e4f7591 LG	32	/* autosuspend delay 5s*/
	33	#define SST_RUNTIME_SUSPEND_DELAY (5 * 1000)
	34
a4b12990 MB	35	/* SST Shim register map
	36	* The register naming can differ between products. Some products also
	37	* contain extra functionality.
	38	*/
	39	#define SST_CSR 0x00
	40	#define SST_PISR 0x08
	41	#define SST_PIMR 0x10
	42	#define SST_ISRX 0x18
	43	#define SST_ISRD 0x20
	44	#define SST_IMRX 0x28
	45	#define SST_IMRD 0x30
	46	#define SST_IPCX 0x38 /* IPC IA -> SST */
	47	#define SST_IPCD 0x40 /* IPC SST -> IA */
	48	#define SST_ISRSC 0x48
	49	#define SST_ISRLPESC 0x50
	50	#define SST_IMRSC 0x58
	51	#define SST_IMRLPESC 0x60
	52	#define SST_IPCSC 0x68
	53	#define SST_IPCLPESC 0x70
	54	#define SST_CLKCTL 0x78
	55	#define SST_CSR2 0x80
	56	#define SST_LTRC 0xE0
ee4a6ce6	57	#define SST_HMDC 0xE8
1ad0e330 VK	58
	59	#define SST_SHIM_BEGIN SST_CSR
	60	#define SST_SHIM_END SST_HDMC
	61
a4b12990 MB	62	#define SST_DBGO 0xF0
	63
	64	#define SST_SHIM_SIZE 0x100
	65	#define SST_PWMCTRL 0x1000
	66
	67	/* SST Shim Register bits
	68	* The register bit naming can differ between products. Some products also
	69	* contain extra functionality.
	70	*/
	71
	72	/* CSR / CS */
	73	#define SST_CSR_RST (0x1 << 1)
	74	#define SST_CSR_SBCS0 (0x1 << 2)
	75	#define SST_CSR_SBCS1 (0x1 << 3)
	76	#define SST_CSR_DCS(x) (x << 4)
	77	#define SST_CSR_DCS_MASK (0x7 << 4)
	78	#define SST_CSR_STALL (0x1 << 10)
	79	#define SST_CSR_S0IOCS (0x1 << 21)
	80	#define SST_CSR_S1IOCS (0x1 << 23)
	81	#define SST_CSR_LPCS (0x1 << 31)
d7d7d1ed LG	82	#define SST_CSR_24MHZ_LPCS (SST_CSR_SBCS0 \| SST_CSR_SBCS1 \| SST_CSR_LPCS)
d7d7d1ed LG	83	#define SST_CSR_24MHZ_NO_LPCS (SST_CSR_SBCS0 \| SST_CSR_SBCS1)
a4b12990 MB	84	#define SST_BYT_CSR_RST (0x1 << 0)
	85	#define SST_BYT_CSR_VECTOR_SEL (0x1 << 1)
	86	#define SST_BYT_CSR_STALL (0x1 << 2)
	87	#define SST_BYT_CSR_PWAITMODE (0x1 << 3)
	88
	89	/* ISRX / ISC */
	90	#define SST_ISRX_BUSY (0x1 << 1)
	91	#define SST_ISRX_DONE (0x1 << 0)
	92	#define SST_BYT_ISRX_REQUEST (0x1 << 1)
	93
	94	/* ISRD / ISD */
	95	#define SST_ISRD_BUSY (0x1 << 1)
	96	#define SST_ISRD_DONE (0x1 << 0)
	97
	98	/* IMRX / IMC */
	99	#define SST_IMRX_BUSY (0x1 << 1)
	100	#define SST_IMRX_DONE (0x1 << 0)
	101	#define SST_BYT_IMRX_REQUEST (0x1 << 1)
	102
d7d7d1ed LG	103	/* IMRD / IMD */
	104	#define SST_IMRD_DONE (0x1 << 0)
	105	#define SST_IMRD_BUSY (0x1 << 1)
	106	#define SST_IMRD_SSP0 (0x1 << 16)
	107	#define SST_IMRD_DMAC0 (0x1 << 21)
	108	#define SST_IMRD_DMAC1 (0x1 << 22)
	109	#define SST_IMRD_DMAC (SST_IMRD_DMAC0 \| SST_IMRD_DMAC1)
	110
a4b12990 MB	111	/* IPCX / IPCC */
	112	#define SST_IPCX_DONE (0x1 << 30)
	113	#define SST_IPCX_BUSY (0x1 << 31)
	114	#define SST_BYT_IPCX_DONE ((u64)0x1 << 62)
	115	#define SST_BYT_IPCX_BUSY ((u64)0x1 << 63)
	116
	117	/* IPCD */
	118	#define SST_IPCD_DONE (0x1 << 30)
	119	#define SST_IPCD_BUSY (0x1 << 31)
	120	#define SST_BYT_IPCD_DONE ((u64)0x1 << 62)
	121	#define SST_BYT_IPCD_BUSY ((u64)0x1 << 63)
	122
	123	/* CLKCTL */
	124	#define SST_CLKCTL_SMOS(x) (x << 24)
	125	#define SST_CLKCTL_MASK (3 << 24)
	126	#define SST_CLKCTL_DCPLCG (1 << 18)
	127	#define SST_CLKCTL_SCOE1 (1 << 17)
	128	#define SST_CLKCTL_SCOE0 (1 << 16)
	129
	130	/* CSR2 / CS2 */
	131	#define SST_CSR2_SDFD_SSP0 (1 << 1)
	132	#define SST_CSR2_SDFD_SSP1 (1 << 2)
	133
	134	/* LTRC */
	135	#define SST_LTRC_VAL(x) (x << 0)
	136
ee4a6ce6 LG	137	/* HMDC */
	138	#define SST_HMDC_HDDA0(x) (x << 0)
	139	#define SST_HMDC_HDDA1(x) (x << 7)
d7d7d1ed LG	140	#define SST_HMDC_HDDA_E0_CH0 1
	141	#define SST_HMDC_HDDA_E0_CH1 2
	142	#define SST_HMDC_HDDA_E0_CH2 4
	143	#define SST_HMDC_HDDA_E0_CH3 8
	144	#define SST_HMDC_HDDA_E1_CH0 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH0)
	145	#define SST_HMDC_HDDA_E1_CH1 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH1)
	146	#define SST_HMDC_HDDA_E1_CH2 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH2)
	147	#define SST_HMDC_HDDA_E1_CH3 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH3)
	148	#define SST_HMDC_HDDA_E0_ALLCH (SST_HMDC_HDDA_E0_CH0 \| SST_HMDC_HDDA_E0_CH1 \| \
	149	SST_HMDC_HDDA_E0_CH2 \| SST_HMDC_HDDA_E0_CH3)
	150	#define SST_HMDC_HDDA_E1_ALLCH (SST_HMDC_HDDA_E1_CH0 \| SST_HMDC_HDDA_E1_CH1 \| \
	151	SST_HMDC_HDDA_E1_CH2 \| SST_HMDC_HDDA_E1_CH3)
a4b12990 MB	152
	153
	154	/* SST Vendor Defined Registers and bits */
	155	#define SST_VDRTCTL0 0xa0
	156	#define SST_VDRTCTL1 0xa4
	157	#define SST_VDRTCTL2 0xa8
	158	#define SST_VDRTCTL3 0xaC
	159
	160	/* VDRTCTL0 */
0d2135ec JY	161	#define SST_VDRTCL0_D3PGD (1 << 0)
	162	#define SST_VDRTCL0_D3SRAMPGD (1 << 1)
	163	#define SST_VDRTCL0_DSRAMPGE_SHIFT 12
	164	#define SST_VDRTCL0_DSRAMPGE_MASK (0xfffff << SST_VDRTCL0_DSRAMPGE_SHIFT)
	165	#define SST_VDRTCL0_ISRAMPGE_SHIFT 2
a4b12990 MB	166	#define SST_VDRTCL0_ISRAMPGE_MASK (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT)
a4b12990 MB	167
0d2135ec JY	168	/* VDRTCTL2 */
	169	#define SST_VDRTCL2_DCLCGE (1 << 1)
	170	#define SST_VDRTCL2_DTCGE (1 << 10)
	171	#define SST_VDRTCL2_APLLSE_MASK (1 << 31)
	172
d7d7d1ed LG	173	/* PMCS */
	174	#define SST_PMCS 0x84
	175	#define SST_PMCS_PS_MASK 0x3
	176
a4b12990 MB	177	struct sst_dsp;
	178
	179	/*
	180	* SST Device.
	181	*
	182	* This structure is populated by the SST core driver.
	183	*/
	184	struct sst_dsp_device {
	185	/* Mandatory fields */
	186	struct sst_ops *ops;
	187	irqreturn_t (thread)(int irq, void context);
	188	void *thread_context;
	189	};
	190
	191	/*
	192	* SST Platform Data.
	193	*/
	194	struct sst_pdata {
	195	/* ACPI data */
	196	u32 lpe_base;
	197	u32 lpe_size;
	198	u32 pcicfg_base;
	199	u32 pcicfg_size;
	200	u32 fw_base;
	201	u32 fw_size;
	202	int irq;
	203
	204	/* Firmware */
	205	const struct firmware *fw;
	206
	207	/* DMA */
6212755e	208	int resindex_dma_base; /* other fields invalid if equals to -1 */
a4b12990 MB	209	u32 dma_base;
	210	u32 dma_size;
	211	int dma_engine;
10df3509	212	struct device *dma_dev;
a4b12990 MB	213
	214	/* DSP */
	215	u32 id;
	216	void *dsp;
	217	};
	218
a395bdd6	219	#if IS_ENABLED(CONFIG_DW_DMAC_CORE)
a4b12990 MB	220	/* Initialization */
	221	struct sst_dsp sst_dsp_new(struct device dev,
	222	struct sst_dsp_device sst_dev, struct sst_pdata pdata);
	223	void sst_dsp_free(struct sst_dsp *sst);
ef3e199a	224	#endif
a4b12990 MB	225
	226	/* SHIM Read / Write */
	227	void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
	228	u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
	229	int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
	230	u32 mask, u32 value);
	231	void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value);
	232	u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset);
	233	int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
	234	u64 mask, u64 value);
d15b1ae1 SP	235	void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
d15b1ae1 SP	236	u32 mask, u32 value);
a4b12990 MB	237
	238	/* SHIM Read / Write Unlocked for callers already holding sst lock */
	239	void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
	240	u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
	241	int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
	242	u32 mask, u32 value);
	243	void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value);
	244	u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset);
	245	int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
	246	u64 mask, u64 value);
d15b1ae1 SP	247	void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
d15b1ae1 SP	248	u32 mask, u32 value);
a4b12990 MB	249
	250	/* Internal generic low-level SST IO functions - can be overidden */
	251	void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
	252	u32 sst_shim32_read(void __iomem *addr, u32 offset);
	253	void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
	254	u64 sst_shim32_read64(void __iomem *addr, u32 offset);
	255	void sst_memcpy_toio_32(struct sst_dsp *sst,
	256	void __iomem dest, void src, size_t bytes);
	257	void sst_memcpy_fromio_32(struct sst_dsp *sst,
	258	void dest, void __iomem src, size_t bytes);
	259
	260	/* DSP reset & boot */
	261	void sst_dsp_reset(struct sst_dsp *sst);
	262	int sst_dsp_boot(struct sst_dsp *sst);
d96c53a1 LG	263	int sst_dsp_wake(struct sst_dsp *sst);
	264	void sst_dsp_sleep(struct sst_dsp *sst);
	265	void sst_dsp_stall(struct sst_dsp *sst);
	266
e9600bc1 LG	267	/* DMA */
	268	int sst_dsp_dma_get_channel(struct sst_dsp *dsp, int chan_id);
	269	void sst_dsp_dma_put_channel(struct sst_dsp *dsp);
	270	int sst_dsp_dma_copyfrom(struct sst_dsp *sst, dma_addr_t dest_addr,
	271	dma_addr_t src_addr, size_t size);
	272	int sst_dsp_dma_copyto(struct sst_dsp *sst, dma_addr_t dest_addr,
	273	dma_addr_t src_addr, size_t size);
a4b12990 MB	274
	275	/* Msg IO */
	276	void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg);
	277	u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp);
	278
	279	/* Mailbox management */
	280	int sst_dsp_mailbox_init(struct sst_dsp *dsp, u32 inbox_offset,
	281	size_t inbox_size, u32 outbox_offset, size_t outbox_size);
	282	void sst_dsp_inbox_write(struct sst_dsp dsp, void message, size_t bytes);
	283	void sst_dsp_inbox_read(struct sst_dsp dsp, void message, size_t bytes);
	284	void sst_dsp_outbox_write(struct sst_dsp dsp, void message, size_t bytes);
	285	void sst_dsp_outbox_read(struct sst_dsp dsp, void message, size_t bytes);
	286	void sst_dsp_mailbox_dump(struct sst_dsp *dsp, size_t bytes);
7a2c52b6 SP	287	int sst_dsp_register_poll(struct sst_dsp *dsp, u32 offset, u32 mask,
7a2c52b6 SP	288	u32 expected_value, u32 timeout, char *operation);
a4b12990 MB	289
	290	/* Debug */
	291	void sst_dsp_dump(struct sst_dsp *sst);
	292
	293	#endif