[mirror_ubuntu-jammy-kernel.git] / sound / soc / intel / skylake / bxt-sst.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  bxt-sst.c - DSP library functions for BXT platform
 *
 *  Copyright (C) 2015-16 Intel Corp
 *  Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
 *	   Jeeja KP <jeeja.kp@intel.com>
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/device.h>

#include "../common/sst-dsp.h"
#include "../common/sst-dsp-priv.h"
#include "skl.h"

#define BXT_BASEFW_TIMEOUT	3000
#define BXT_ROM_INIT_TIMEOUT	70
#define BXT_IPC_PURGE_FW	0x01004000

#define BXT_ROM_INIT		0x5
#define BXT_ADSP_SRAM0_BASE	0x80000

/* Firmware status window */
#define BXT_ADSP_FW_STATUS	BXT_ADSP_SRAM0_BASE
#define BXT_ADSP_ERROR_CODE     (BXT_ADSP_FW_STATUS + 0x4)

#define BXT_ADSP_SRAM1_BASE	0xA0000

#define BXT_INSTANCE_ID 0
#define BXT_BASE_FW_MODULE_ID 0

#define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000

/* Delay before scheduling D0i3 entry */
#define BXT_D0I3_DELAY 5000

static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
{
	 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
}

static int
bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
{
	struct snd_dma_buffer dmab;
	struct skl_dev *skl = ctx->thread_context;
	struct firmware stripped_fw;
	int ret = 0, i, dma_id, stream_tag;

	/* library indices start from 1 to N. 0 represents base FW */
	for (i = 1; i < lib_count; i++) {
		ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
					BXT_ADSP_FW_BIN_HDR_OFFSET, i);
		if (ret < 0)
			goto load_library_failed;

		stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
					stripped_fw.size, &dmab);
		if (stream_tag <= 0) {
			dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
					stream_tag);
			ret = stream_tag;
			goto load_library_failed;
		}

		dma_id = stream_tag - 1;
		memcpy(dmab.area, stripped_fw.data, stripped_fw.size);

		ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
		ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
		if (ret < 0)
			dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
					linfo[i].name, ret);

		ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
		ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
	}

	return ret;

load_library_failed:
	skl_release_library(linfo, lib_count);
	return ret;
}

/*
 * First boot sequence has some extra steps. Core 0 waits for power
 * status on core 1, so power up core 1 also momentarily, keep it in
 * reset/stall and then turn it off
 */
static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
			const void *fwdata, u32 fwsize)
{
	int stream_tag, ret;

	stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
	if (stream_tag <= 0) {
		dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
				stream_tag);
		return stream_tag;
	}

	ctx->dsp_ops.stream_tag = stream_tag;
	memcpy(ctx->dmab.area, fwdata, fwsize);

	/* Step 1: Power up core 0 and core1 */
	ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
				SKL_DSP_CORE_MASK(1));
	if (ret < 0) {
		dev_err(ctx->dev, "dsp core0/1 power up failed\n");
		goto base_fw_load_failed;
	}

	/* Step 2: Purge FW request */
	sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
				(BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));

	/* Step 3: Unset core0 reset state & unstall/run core0 */
	ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
	if (ret < 0) {
		dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
		ret = -EIO;
		goto base_fw_load_failed;
	}

	/* Step 4: Wait for DONE Bit */
	ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
					SKL_ADSP_REG_HIPCIE_DONE,
					SKL_ADSP_REG_HIPCIE_DONE,
					BXT_INIT_TIMEOUT, "HIPCIE Done");
	if (ret < 0) {
		dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
		goto base_fw_load_failed;
	}

	/* Step 5: power down core1 */
	ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
	if (ret < 0) {
		dev_err(ctx->dev, "dsp core1 power down failed\n");
		goto base_fw_load_failed;
	}

	/* Step 6: Enable Interrupt */
	skl_ipc_int_enable(ctx);
	skl_ipc_op_int_enable(ctx);

	/* Step 7: Wait for ROM init */
	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
			SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
	if (ret < 0) {
		dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
		goto base_fw_load_failed;
	}

	return ret;

base_fw_load_failed:
	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
	skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
	skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
	return ret;
}

static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
{
	int ret;

	ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
			BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");

	ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);

	return ret;
}

static int bxt_load_base_firmware(struct sst_dsp *ctx)
{
	struct firmware stripped_fw;
	struct skl_dev *skl = ctx->thread_context;
	int ret, i;

	if (ctx->fw == NULL) {
		ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
		if (ret < 0) {
			dev_err(ctx->dev, "Request firmware failed %d\n", ret);
			return ret;
		}
	}

	/* prase uuids on first boot */
	if (skl->is_first_boot) {
		ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
		if (ret < 0)
			goto sst_load_base_firmware_failed;
	}

	stripped_fw.data = ctx->fw->data;
	stripped_fw.size = ctx->fw->size;
	skl_dsp_strip_extended_manifest(&stripped_fw);


	for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
		ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
		if (ret == 0)
			break;
	}

	if (ret < 0) {
		dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
			sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
			sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));

		dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
		goto sst_load_base_firmware_failed;
	}

	ret = sst_transfer_fw_host_dma(ctx);
	if (ret < 0) {
		dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
		dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
			sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
			sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));

		skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
	} else {
		dev_dbg(ctx->dev, "Firmware download successful\n");
		ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
					msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
		if (ret == 0) {
			dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
			skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
			ret = -EIO;
		} else {
			ret = 0;
			skl->fw_loaded = true;
		}
	}

	return ret;

sst_load_base_firmware_failed:
	release_firmware(ctx->fw);
	ctx->fw = NULL;
	return ret;
}

/*
 * Decide the D0i3 state that can be targeted based on the usecase
 * ref counts and DSP state
 *
 * Decision Matrix:  (X= dont care; state = target state)
 *
 * DSP state != SKL_DSP_RUNNING ; state = no d0i3
 *
 * DSP state == SKL_DSP_RUNNING , the following matrix applies
 * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
 * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
 * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
 * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
 */
static int bxt_d0i3_target_state(struct sst_dsp *ctx)
{
	struct skl_dev *skl = ctx->thread_context;
	struct skl_d0i3_data *d0i3 = &skl->d0i3;

	if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
		return SKL_DSP_D0I3_NONE;

	if (d0i3->non_d0i3)
		return SKL_DSP_D0I3_NONE;
	else if (d0i3->streaming)
		return SKL_DSP_D0I3_STREAMING;
	else if (d0i3->non_streaming)
		return SKL_DSP_D0I3_NON_STREAMING;
	else
		return SKL_DSP_D0I3_NONE;
}

static void bxt_set_dsp_D0i3(struct work_struct *work)
{
	int ret;
	struct skl_ipc_d0ix_msg msg;
	struct skl_dev *skl = container_of(work,
			struct skl_dev, d0i3.work.work);
	struct sst_dsp *ctx = skl->dsp;
	struct skl_d0i3_data *d0i3 = &skl->d0i3;
	int target_state;

	dev_dbg(ctx->dev, "In %s:\n", __func__);

	/* D0i3 entry allowed only if core 0 alone is running */
	if (skl_dsp_get_enabled_cores(ctx) !=  SKL_DSP_CORE0_MASK) {
		dev_warn(ctx->dev,
				"D0i3 allowed when only core0 running:Exit\n");
		return;
	}

	target_state = bxt_d0i3_target_state(ctx);
	if (target_state == SKL_DSP_D0I3_NONE)
		return;

	msg.instance_id = 0;
	msg.module_id = 0;
	msg.wake = 1;
	msg.streaming = 0;
	if (target_state == SKL_DSP_D0I3_STREAMING)
		msg.streaming = 1;

	ret =  skl_ipc_set_d0ix(&skl->ipc, &msg);

	if (ret < 0) {
		dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
		return;
	}

	/* Set Vendor specific register D0I3C.I3 to enable D0i3*/
	if (skl->update_d0i3c)
		skl->update_d0i3c(skl->dev, true);

	d0i3->state = target_state;
	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
}

static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
{
	struct skl_dev *skl = ctx->thread_context;
	struct skl_d0i3_data *d0i3 = &skl->d0i3;

	/* Schedule D0i3 only if the usecase ref counts are appropriate */
	if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {

		dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);

		schedule_delayed_work(&d0i3->work,
				msecs_to_jiffies(BXT_D0I3_DELAY));
	}

	return 0;
}

static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
{
	int ret;
	struct skl_ipc_d0ix_msg msg;
	struct skl_dev *skl = ctx->thread_context;

	dev_dbg(ctx->dev, "In %s:\n", __func__);

	/* First Cancel any pending attempt to put DSP to D0i3 */
	cancel_delayed_work_sync(&skl->d0i3.work);

	/* If DSP is currently in D0i3, bring it to D0i0 */
	if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
		return 0;

	dev_dbg(ctx->dev, "Set DSP to D0i0\n");

	msg.instance_id = 0;
	msg.module_id = 0;
	msg.streaming = 0;
	msg.wake = 0;

	if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
		msg.streaming = 1;

	/* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
	if (skl->update_d0i3c)
		skl->update_d0i3c(skl->dev, false);

	ret =  skl_ipc_set_d0ix(&skl->ipc, &msg);
	if (ret < 0) {
		dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
		return ret;
	}

	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
	skl->d0i3.state = SKL_DSP_D0I3_NONE;

	return 0;
}

static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
{
	struct skl_dev *skl = ctx->thread_context;
	int ret;
	struct skl_ipc_dxstate_info dx;
	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);

	if (skl->fw_loaded == false) {
		skl->boot_complete = false;
		ret = bxt_load_base_firmware(ctx);
		if (ret < 0) {
			dev_err(ctx->dev, "reload fw failed: %d\n", ret);
			return ret;
		}

		if (skl->lib_count > 1) {
			ret = bxt_load_library(ctx, skl->lib_info,
						skl->lib_count);
			if (ret < 0) {
				dev_err(ctx->dev, "reload libs failed: %d\n", ret);
				return ret;
			}
		}
		skl->cores.state[core_id] = SKL_DSP_RUNNING;
		return ret;
	}

	/* If core 0 is being turned on, turn on core 1 as well */
	if (core_id == SKL_DSP_CORE0_ID)
		ret = skl_dsp_core_power_up(ctx, core_mask |
				SKL_DSP_CORE_MASK(1));
	else
		ret = skl_dsp_core_power_up(ctx, core_mask);

	if (ret < 0)
		goto err;

	if (core_id == SKL_DSP_CORE0_ID) {

		/*
		 * Enable interrupt after SPA is set and before
		 * DSP is unstalled
		 */
		skl_ipc_int_enable(ctx);
		skl_ipc_op_int_enable(ctx);
		skl->boot_complete = false;
	}

	ret = skl_dsp_start_core(ctx, core_mask);
	if (ret < 0)
		goto err;

	if (core_id == SKL_DSP_CORE0_ID) {
		ret = wait_event_timeout(skl->boot_wait,
				skl->boot_complete,
				msecs_to_jiffies(SKL_IPC_BOOT_MSECS));

	/* If core 1 was turned on for booting core 0, turn it off */
		skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
		if (ret == 0) {
			dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
			dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
				sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
				sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
			dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
			ret = -EIO;
			goto err;
		}
	}

	/* Tell FW if additional core in now On */

	if (core_id != SKL_DSP_CORE0_ID) {
		dx.core_mask = core_mask;
		dx.dx_mask = core_mask;

		ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
					BXT_BASE_FW_MODULE_ID, &dx);
		if (ret < 0) {
			dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
								core_id, ret);
			goto err;
		}
	}

	skl->cores.state[core_id] = SKL_DSP_RUNNING;
	return 0;
err:
	if (core_id == SKL_DSP_CORE0_ID)
		core_mask |= SKL_DSP_CORE_MASK(1);
	skl_dsp_disable_core(ctx, core_mask);

	return ret;
}

static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
{
	int ret;
	struct skl_ipc_dxstate_info dx;
	struct skl_dev *skl = ctx->thread_context;
	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);

	dx.core_mask = core_mask;
	dx.dx_mask = SKL_IPC_D3_MASK;

	dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
			dx.core_mask, dx.dx_mask);

	ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
				BXT_BASE_FW_MODULE_ID, &dx);
	if (ret < 0) {
		dev_err(ctx->dev,
		"Failed to set DSP to D3:core id = %d;Continue reset\n",
		core_id);
		/*
		 * In case of D3 failure, re-download the firmware, so set
		 * fw_loaded to false.
		 */
		skl->fw_loaded = false;
	}

	if (core_id == SKL_DSP_CORE0_ID) {
		/* disable Interrupt */
		skl_ipc_op_int_disable(ctx);
		skl_ipc_int_disable(ctx);
	}
	ret = skl_dsp_disable_core(ctx, core_mask);
	if (ret < 0) {
		dev_err(ctx->dev, "Failed to disable core %d\n", ret);
		return ret;
	}
	skl->cores.state[core_id] = SKL_DSP_RESET;
	return 0;
}

static const struct skl_dsp_fw_ops bxt_fw_ops = {
	.set_state_D0 = bxt_set_dsp_D0,
	.set_state_D3 = bxt_set_dsp_D3,
	.set_state_D0i3 = bxt_schedule_dsp_D0i3,
	.set_state_D0i0 = bxt_set_dsp_D0i0,
	.load_fw = bxt_load_base_firmware,
	.get_fw_errcode = bxt_get_errorcode,
	.load_library = bxt_load_library,
};

static struct sst_ops skl_ops = {
	.irq_handler = skl_dsp_sst_interrupt,
	.write = sst_shim32_write,
	.read = sst_shim32_read,
	.free = skl_dsp_free,
};

static struct sst_dsp_device skl_dev = {
	.thread = skl_dsp_irq_thread_handler,
	.ops = &skl_ops,
};

int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
			const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
			struct skl_dev **dsp)
{
	struct skl_dev *skl;
	struct sst_dsp *sst;
	int ret;

	ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
	if (ret < 0) {
		dev_err(dev, "%s: no device\n", __func__);
		return ret;
	}

	skl = *dsp;
	sst = skl->dsp;
	sst->fw_ops = bxt_fw_ops;
	sst->addr.lpe = mmio_base;
	sst->addr.shim = mmio_base;
	sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
	sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
	sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
	sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;

	sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
			SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);

	ret = skl_ipc_init(dev, skl);
	if (ret) {
		skl_dsp_free(sst);
		return ret;
	}

	/* set the D0i3 check */
	skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;

	skl->boot_complete = false;
	init_waitqueue_head(&skl->boot_wait);
	INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
	skl->d0i3.state = SKL_DSP_D0I3_NONE;

	return skl_dsp_acquire_irq(sst);
}
EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);

int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl)
{
	int ret;
	struct sst_dsp *sst = skl->dsp;

	ret = sst->fw_ops.load_fw(sst);
	if (ret < 0) {
		dev_err(dev, "Load base fw failed: %x\n", ret);
		return ret;
	}

	skl_dsp_init_core_state(sst);

	if (skl->lib_count > 1) {
		ret = sst->fw_ops.load_library(sst, skl->lib_info,
						skl->lib_count);
		if (ret < 0) {
			dev_err(dev, "Load Library failed : %x\n", ret);
			return ret;
		}
	}
	skl->is_first_boot = false;

	return 0;
}
EXPORT_SYMBOL_GPL(bxt_sst_init_fw);

void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl)
{

	skl_release_library(skl->lib_info, skl->lib_count);
	if (skl->dsp->fw)
		release_firmware(skl->dsp->fw);
	skl_freeup_uuid_list(skl);
	skl_ipc_free(&skl->ipc);
	skl->dsp->ops->free(skl->dsp);
}
EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel Broxton IPC driver");
Commit	Line	Data
8e8e69d6	1	// SPDX-License-Identifier: GPL-2.0-only
92eb4f62 JK	2	/*
	3	* bxt-sst.c - DSP library functions for BXT platform
	4	*
	5	* Copyright (C) 2015-16 Intel Corp
	6	* Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
	7	* Jeeja KP <jeeja.kp@intel.com>
92eb4f62 JK	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/delay.h>
	12	#include <linux/firmware.h>
	13	#include <linux/device.h>
	14
	15	#include "../common/sst-dsp.h"
	16	#include "../common/sst-dsp-priv.h"
bcc2a2dc	17	#include "skl.h"
92eb4f62 JK	18
92eb4f62 JK	19	#define BXT_BASEFW_TIMEOUT 3000
7d3f91dc	20	#define BXT_ROM_INIT_TIMEOUT 70
92eb4f62 JK	21	#define BXT_IPC_PURGE_FW 0x01004000
	22
	23	#define BXT_ROM_INIT 0x5
	24	#define BXT_ADSP_SRAM0_BASE 0x80000
	25
	26	/* Firmware status window */
	27	#define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
	28	#define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
	29
	30	#define BXT_ADSP_SRAM1_BASE 0xA0000
	31
e68aca08 J	32	#define BXT_INSTANCE_ID 0
	33	#define BXT_BASE_FW_MODULE_ID 0
	34
1ef015e6 RB	35	#define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
1ef015e6 RB	36
5bb4cd46 J	37	/* Delay before scheduling D0i3 entry */
	38	#define BXT_D0I3_DELAY 5000
	39
92eb4f62 JK	40	static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
	41	{
	42	return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
	43	}
	44
1ef015e6	45	static int
eee0e16f	46	bxt_load_library(struct sst_dsp ctx, struct skl_lib_info linfo, int lib_count)
1ef015e6 RB	47	{
1ef015e6 RB	48	struct snd_dma_buffer dmab;
bcc2a2dc	49	struct skl_dev *skl = ctx->thread_context;
1ef015e6 RB	50	struct firmware stripped_fw;
	51	int ret = 0, i, dma_id, stream_tag;
	52
	53	/* library indices start from 1 to N. 0 represents base FW */
eee0e16f	54	for (i = 1; i < lib_count; i++) {
ebe89076	55	ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
1ef015e6	56	BXT_ADSP_FW_BIN_HDR_OFFSET, i);
ebe89076 SP	57	if (ret < 0)
ebe89076 SP	58	goto load_library_failed;
1ef015e6 RB	59
	60	stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
	61	stripped_fw.size, &dmab);
	62	if (stream_tag <= 0) {
	63	dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
	64	stream_tag);
	65	ret = stream_tag;
	66	goto load_library_failed;
	67	}
	68
	69	dma_id = stream_tag - 1;
	70	memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
	71
	72	ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
100e7f39	73	ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
1ef015e6 RB	74	if (ret < 0)
1ef015e6 RB	75	dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
eee0e16f	76	linfo[i].name, ret);
1ef015e6 RB	77
	78	ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
	79	ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
1ef015e6 RB	80	}
	81
	82	return ret;
	83
	84	load_library_failed:
ebe89076	85	skl_release_library(linfo, lib_count);
1ef015e6 RB	86	return ret;
	87	}
	88
e68aca08 J	89	/*
	90	* First boot sequence has some extra steps. Core 0 waits for power
	91	* status on core 1, so power up core 1 also momentarily, keep it in
	92	* reset/stall and then turn it off
	93	*/
92eb4f62 JK	94	static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
	95	const void *fwdata, u32 fwsize)
	96	{
eee0e16f	97	int stream_tag, ret;
92eb4f62 JK	98
92eb4f62 JK	99	stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
e68aca08	100	if (stream_tag <= 0) {
92eb4f62 JK	101	dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
	102	stream_tag);
	103	return stream_tag;
	104	}
	105
	106	ctx->dsp_ops.stream_tag = stream_tag;
	107	memcpy(ctx->dmab.area, fwdata, fwsize);
	108
e68aca08 J	109	/* Step 1: Power up core 0 and core1 */
	110	ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK \|
	111	SKL_DSP_CORE_MASK(1));
2023576d	112	if (ret < 0) {
e68aca08	113	dev_err(ctx->dev, "dsp core0/1 power up failed\n");
2023576d SV	114	goto base_fw_load_failed;
	115	}
	116
e68aca08	117	/* Step 2: Purge FW request */
92eb4f62	118	sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY \|
2023576d	119	(BXT_IPC_PURGE_FW \| ((stream_tag - 1) << 9)));
92eb4f62	120
e68aca08	121	/* Step 3: Unset core0 reset state & unstall/run core0 */
052f103c	122	ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
92eb4f62	123	if (ret < 0) {
2023576d	124	dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
92eb4f62 JK	125	ret = -EIO;
	126	goto base_fw_load_failed;
	127	}
	128
e68aca08	129	/* Step 4: Wait for DONE Bit */
1448099d	130	ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
92eb4f62	131	SKL_ADSP_REG_HIPCIE_DONE,
1448099d JK	132	SKL_ADSP_REG_HIPCIE_DONE,
	133	BXT_INIT_TIMEOUT, "HIPCIE Done");
	134	if (ret < 0) {
5f75b19e	135	dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
1448099d	136	goto base_fw_load_failed;
92eb4f62 JK	137	}
92eb4f62 JK	138
e68aca08 J	139	/* Step 5: power down core1 */
	140	ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
	141	if (ret < 0) {
	142	dev_err(ctx->dev, "dsp core1 power down failed\n");
	143	goto base_fw_load_failed;
	144	}
	145
	146	/* Step 6: Enable Interrupt */
92eb4f62 JK	147	skl_ipc_int_enable(ctx);
	148	skl_ipc_op_int_enable(ctx);
	149
e68aca08	150	/* Step 7: Wait for ROM init */
1448099d	151	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
7d3f91dc	152	SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
1448099d JK	153	if (ret < 0) {
1448099d JK	154	dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
92eb4f62 JK	155	goto base_fw_load_failed;
	156	}
	157
	158	return ret;
	159
	160	base_fw_load_failed:
	161	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
052f103c	162	skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
c7872267	163	skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
92eb4f62 JK	164	return ret;
	165	}
	166
	167	static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
	168	{
	169	int ret;
	170
	171	ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
	172	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
	173	BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
	174
	175	ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
	176	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
	177
	178	return ret;
	179	}
	180
	181	static int bxt_load_base_firmware(struct sst_dsp *ctx)
	182	{
bf242d19	183	struct firmware stripped_fw;
bcc2a2dc	184	struct skl_dev *skl = ctx->thread_context;
7d3f91dc	185	int ret, i;
92eb4f62	186
31d648f0 JK	187	if (ctx->fw == NULL) {
	188	ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
	189	if (ret < 0) {
	190	dev_err(ctx->dev, "Request firmware failed %d\n", ret);
	191	return ret;
	192	}
92eb4f62 JK	193	}
92eb4f62 JK	194
0bdd6d8b VK	195	/* prase uuids on first boot */
	196	if (skl->is_first_boot) {
	197	ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
	198	if (ret < 0)
	199	goto sst_load_base_firmware_failed;
	200	}
bf242d19 VK	201
	202	stripped_fw.data = ctx->fw->data;
	203	stripped_fw.size = ctx->fw->size;
	204	skl_dsp_strip_extended_manifest(&stripped_fw);
	205
7d3f91dc JK	206
7d3f91dc JK	207	for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
bf242d19	208	ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
7d3f91dc JK	209	if (ret == 0)
	210	break;
	211	}
	212
	213	if (ret < 0) {
	214	dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
2023576d SV	215	sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
	216	sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
	217
7d3f91dc JK	218	dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
7d3f91dc JK	219	goto sst_load_base_firmware_failed;
92eb4f62 JK	220	}
	221
	222	ret = sst_transfer_fw_host_dma(ctx);
	223	if (ret < 0) {
	224	dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
	225	dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
	226	sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
	227	sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
	228
052f103c	229	skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
92eb4f62 JK	230	} else {
	231	dev_dbg(ctx->dev, "Firmware download successful\n");
	232	ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
	233	msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
	234	if (ret == 0) {
	235	dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
052f103c	236	skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
92eb4f62 JK	237	ret = -EIO;
92eb4f62 JK	238	} else {
92eb4f62	239	ret = 0;
1665c177	240	skl->fw_loaded = true;
92eb4f62 JK	241	}
	242	}
	243
31d648f0 JK	244	return ret;
31d648f0 JK	245
92eb4f62	246	sst_load_base_firmware_failed:
fdfa82ee	247	release_firmware(ctx->fw);
31d648f0	248	ctx->fw = NULL;
92eb4f62 JK	249	return ret;
	250	}
	251
5bb4cd46 J	252	/*
	253	* Decide the D0i3 state that can be targeted based on the usecase
	254	* ref counts and DSP state
	255	*
	256	* Decision Matrix: (X= dont care; state = target state)
	257	*
	258	* DSP state != SKL_DSP_RUNNING ; state = no d0i3
	259	*
	260	* DSP state == SKL_DSP_RUNNING , the following matrix applies
	261	* non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
	262	* non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
	263	* non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
	264	* non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
	265	*/
	266	static int bxt_d0i3_target_state(struct sst_dsp *ctx)
	267	{
bcc2a2dc	268	struct skl_dev *skl = ctx->thread_context;
5bb4cd46 J	269	struct skl_d0i3_data *d0i3 = &skl->d0i3;
	270
	271	if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
	272	return SKL_DSP_D0I3_NONE;
	273
	274	if (d0i3->non_d0i3)
	275	return SKL_DSP_D0I3_NONE;
	276	else if (d0i3->streaming)
	277	return SKL_DSP_D0I3_STREAMING;
	278	else if (d0i3->non_streaming)
	279	return SKL_DSP_D0I3_NON_STREAMING;
	280	else
	281	return SKL_DSP_D0I3_NONE;
	282	}
	283
	284	static void bxt_set_dsp_D0i3(struct work_struct *work)
	285	{
	286	int ret;
	287	struct skl_ipc_d0ix_msg msg;
bcc2a2dc CR	288	struct skl_dev *skl = container_of(work,
bcc2a2dc CR	289	struct skl_dev, d0i3.work.work);
5bb4cd46 J	290	struct sst_dsp *ctx = skl->dsp;
	291	struct skl_d0i3_data *d0i3 = &skl->d0i3;
	292	int target_state;
	293
	294	dev_dbg(ctx->dev, "In %s:\n", __func__);
	295
	296	/* D0i3 entry allowed only if core 0 alone is running */
	297	if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) {
	298	dev_warn(ctx->dev,
	299	"D0i3 allowed when only core0 running:Exit\n");
	300	return;
	301	}
	302
	303	target_state = bxt_d0i3_target_state(ctx);
	304	if (target_state == SKL_DSP_D0I3_NONE)
	305	return;
	306
	307	msg.instance_id = 0;
	308	msg.module_id = 0;
	309	msg.wake = 1;
	310	msg.streaming = 0;
	311	if (target_state == SKL_DSP_D0I3_STREAMING)
	312	msg.streaming = 1;
	313
	314	ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
	315
	316	if (ret < 0) {
	317	dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
	318	return;
	319	}
	320
	321	/* Set Vendor specific register D0I3C.I3 to enable D0i3*/
	322	if (skl->update_d0i3c)
	323	skl->update_d0i3c(skl->dev, true);
	324
	325	d0i3->state = target_state;
	326	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
	327	}
	328
	329	static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
	330	{
bcc2a2dc	331	struct skl_dev *skl = ctx->thread_context;
5bb4cd46 J	332	struct skl_d0i3_data *d0i3 = &skl->d0i3;
	333
	334	/* Schedule D0i3 only if the usecase ref counts are appropriate */
	335	if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {
	336
	337	dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);
	338
	339	schedule_delayed_work(&d0i3->work,
	340	msecs_to_jiffies(BXT_D0I3_DELAY));
	341	}
	342
	343	return 0;
	344	}
	345
	346	static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
	347	{
	348	int ret;
	349	struct skl_ipc_d0ix_msg msg;
bcc2a2dc	350	struct skl_dev *skl = ctx->thread_context;
5bb4cd46 J	351
	352	dev_dbg(ctx->dev, "In %s:\n", __func__);
	353
	354	/* First Cancel any pending attempt to put DSP to D0i3 */
	355	cancel_delayed_work_sync(&skl->d0i3.work);
	356
	357	/* If DSP is currently in D0i3, bring it to D0i0 */
	358	if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
	359	return 0;
	360
	361	dev_dbg(ctx->dev, "Set DSP to D0i0\n");
	362
	363	msg.instance_id = 0;
	364	msg.module_id = 0;
	365	msg.streaming = 0;
	366	msg.wake = 0;
	367
	368	if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
	369	msg.streaming = 1;
	370
	371	/* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
	372	if (skl->update_d0i3c)
	373	skl->update_d0i3c(skl->dev, false);
	374
	375	ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
	376	if (ret < 0) {
	377	dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
	378	return ret;
	379	}
	380
	381	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
	382	skl->d0i3.state = SKL_DSP_D0I3_NONE;
	383
	384	return 0;
	385	}
	386
052f103c	387	static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
92eb4f62	388	{
bcc2a2dc	389	struct skl_dev *skl = ctx->thread_context;
92eb4f62	390	int ret;
e68aca08 J	391	struct skl_ipc_dxstate_info dx;
e68aca08 J	392	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
92eb4f62	393
1665c177	394	if (skl->fw_loaded == false) {
c7872267	395	skl->boot_complete = false;
1665c177	396	ret = bxt_load_base_firmware(ctx);
1ef015e6	397	if (ret < 0) {
1665c177	398	dev_err(ctx->dev, "reload fw failed: %d\n", ret);
1ef015e6 RB	399	return ret;
	400	}
	401
eee0e16f JK	402	if (skl->lib_count > 1) {
	403	ret = bxt_load_library(ctx, skl->lib_info,
	404	skl->lib_count);
1ef015e6 RB	405	if (ret < 0) {
	406	dev_err(ctx->dev, "reload libs failed: %d\n", ret);
	407	return ret;
	408	}
	409	}
1fb344a3	410	skl->cores.state[core_id] = SKL_DSP_RUNNING;
92eb4f62 JK	411	return ret;
	412	}
	413
e68aca08 J	414	/* If core 0 is being turned on, turn on core 1 as well */
	415	if (core_id == SKL_DSP_CORE0_ID)
	416	ret = skl_dsp_core_power_up(ctx, core_mask \|
	417	SKL_DSP_CORE_MASK(1));
	418	else
	419	ret = skl_dsp_core_power_up(ctx, core_mask);
	420
	421	if (ret < 0)
	422	goto err;
	423
	424	if (core_id == SKL_DSP_CORE0_ID) {
	425
	426	/*
	427	* Enable interrupt after SPA is set and before
	428	* DSP is unstalled
	429	*/
	430	skl_ipc_int_enable(ctx);
	431	skl_ipc_op_int_enable(ctx);
	432	skl->boot_complete = false;
92eb4f62	433	}
92eb4f62	434
e68aca08 J	435	ret = skl_dsp_start_core(ctx, core_mask);
	436	if (ret < 0)
	437	goto err;
92eb4f62	438
e68aca08 J	439	if (core_id == SKL_DSP_CORE0_ID) {
	440	ret = wait_event_timeout(skl->boot_wait,
	441	skl->boot_complete,
	442	msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
	443
	444	/* If core 1 was turned on for booting core 0, turn it off */
	445	skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
	446	if (ret == 0) {
	447	dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
	448	dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
	449	sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
	450	sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
	451	dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
	452	ret = -EIO;
	453	goto err;
	454	}
92eb4f62 JK	455	}
92eb4f62 JK	456
e68aca08 J	457	/* Tell FW if additional core in now On */
	458
	459	if (core_id != SKL_DSP_CORE0_ID) {
	460	dx.core_mask = core_mask;
	461	dx.dx_mask = core_mask;
	462
	463	ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
	464	BXT_BASE_FW_MODULE_ID, &dx);
	465	if (ret < 0) {
	466	dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
	467	core_id, ret);
	468	goto err;
	469	}
92eb4f62 JK	470	}
92eb4f62 JK	471
e68aca08	472	skl->cores.state[core_id] = SKL_DSP_RUNNING;
92eb4f62	473	return 0;
e68aca08 J	474	err:
	475	if (core_id == SKL_DSP_CORE0_ID)
	476	core_mask \|= SKL_DSP_CORE_MASK(1);
	477	skl_dsp_disable_core(ctx, core_mask);
	478
	479	return ret;
92eb4f62 JK	480	}
92eb4f62 JK	481
052f103c	482	static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
92eb4f62	483	{
e68aca08	484	int ret;
92eb4f62	485	struct skl_ipc_dxstate_info dx;
bcc2a2dc	486	struct skl_dev *skl = ctx->thread_context;
e68aca08	487	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
92eb4f62	488
e68aca08	489	dx.core_mask = core_mask;
92eb4f62 JK	490	dx.dx_mask = SKL_IPC_D3_MASK;
92eb4f62 JK	491
e68aca08 J	492	dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
e68aca08 J	493	dx.core_mask, dx.dx_mask);
92eb4f62	494
e68aca08 J	495	ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
e68aca08 J	496	BXT_BASE_FW_MODULE_ID, &dx);
03de8c2e	497	if (ret < 0) {
e68aca08 J	498	dev_err(ctx->dev,
	499	"Failed to set DSP to D3:core id = %d;Continue reset\n",
	500	core_id);
03de8c2e JK	501	/*
	502	* In case of D3 failure, re-download the firmware, so set
	503	* fw_loaded to false.
	504	*/
	505	skl->fw_loaded = false;
	506	}
92eb4f62	507
5518af9f JK	508	if (core_id == SKL_DSP_CORE0_ID) {
	509	/* disable Interrupt */
	510	skl_ipc_op_int_disable(ctx);
	511	skl_ipc_int_disable(ctx);
	512	}
e68aca08	513	ret = skl_dsp_disable_core(ctx, core_mask);
92eb4f62	514	if (ret < 0) {
ecd286a9	515	dev_err(ctx->dev, "Failed to disable core %d\n", ret);
e68aca08	516	return ret;
92eb4f62	517	}
e68aca08	518	skl->cores.state[core_id] = SKL_DSP_RESET;
92eb4f62 JK	519	return 0;
	520	}
	521
2788808a	522	static const struct skl_dsp_fw_ops bxt_fw_ops = {
92eb4f62 JK	523	.set_state_D0 = bxt_set_dsp_D0,
92eb4f62 JK	524	.set_state_D3 = bxt_set_dsp_D3,
5bb4cd46 J	525	.set_state_D0i3 = bxt_schedule_dsp_D0i3,
5bb4cd46 J	526	.set_state_D0i0 = bxt_set_dsp_D0i0,
92eb4f62 JK	527	.load_fw = bxt_load_base_firmware,
92eb4f62 JK	528	.get_fw_errcode = bxt_get_errorcode,
1ef015e6	529	.load_library = bxt_load_library,
92eb4f62 JK	530	};
	531
	532	static struct sst_ops skl_ops = {
	533	.irq_handler = skl_dsp_sst_interrupt,
	534	.write = sst_shim32_write,
	535	.read = sst_shim32_read,
92eb4f62 JK	536	.free = skl_dsp_free,
	537	};
	538
	539	static struct sst_dsp_device skl_dev = {
	540	.thread = skl_dsp_irq_thread_handler,
	541	.ops = &skl_ops,
	542	};
	543
	544	int bxt_sst_dsp_init(struct device dev, void __iomem mmio_base, int irq,
	545	const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
bcc2a2dc	546	struct skl_dev **dsp)
92eb4f62	547	{
bcc2a2dc	548	struct skl_dev *skl;
92eb4f62 JK	549	struct sst_dsp *sst;
	550	int ret;
	551
9fe9c711 K	552	ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
9fe9c711 K	553	if (ret < 0) {
351d74e4	554	dev_err(dev, "%s: no device\n", __func__);
9fe9c711	555	return ret;
92eb4f62 JK	556	}
92eb4f62 JK	557
9fe9c711	558	skl = *dsp;
92eb4f62	559	sst = skl->dsp;
92eb4f62 JK	560	sst->fw_ops = bxt_fw_ops;
	561	sst->addr.lpe = mmio_base;
	562	sst->addr.shim = mmio_base;
09e914d6 GS	563	sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
	564	sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
	565	sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
	566	sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
92eb4f62 JK	567
	568	sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
	569	SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
	570
2eed1b02	571	ret = skl_ipc_init(dev, skl);
3b3011ad SP	572	if (ret) {
3b3011ad SP	573	skl_dsp_free(sst);
2eed1b02	574	return ret;
3b3011ad	575	}
2eed1b02	576
a83e3b4c VK	577	/* set the D0i3 check */
	578	skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;
	579
92eb4f62 JK	580	skl->boot_complete = false;
92eb4f62 JK	581	init_waitqueue_head(&skl->boot_wait);
a83e3b4c VK	582	INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
a83e3b4c VK	583	skl->d0i3.state = SKL_DSP_D0I3_NONE;
78cdbbda	584
8e9d8e19	585	return skl_dsp_acquire_irq(sst);
78cdbbda VK	586	}
	587	EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
	588
bcc2a2dc	589	int bxt_sst_init_fw(struct device dev, struct skl_dev skl)
78cdbbda VK	590	{
78cdbbda VK	591	int ret;
bcc2a2dc	592	struct sst_dsp *sst = skl->dsp;
92eb4f62 JK	593
	594	ret = sst->fw_ops.load_fw(sst);
	595	if (ret < 0) {
ecd286a9	596	dev_err(dev, "Load base fw failed: %x\n", ret);
92eb4f62 JK	597	return ret;
	598	}
	599
052f103c J	600	skl_dsp_init_core_state(sst);
052f103c J	601
bcc2a2dc CR	602	if (skl->lib_count > 1) {
	603	ret = sst->fw_ops.load_library(sst, skl->lib_info,
	604	skl->lib_count);
1ef015e6	605	if (ret < 0) {
ecd286a9	606	dev_err(dev, "Load Library failed : %x\n", ret);
1ef015e6 RB	607	return ret;
	608	}
	609	}
bcc2a2dc	610	skl->is_first_boot = false;
92eb4f62 JK	611
	612	return 0;
	613	}
78cdbbda	614	EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
92eb4f62	615
bcc2a2dc	616	void bxt_sst_dsp_cleanup(struct device dev, struct skl_dev skl)
92eb4f62	617	{
31d648f0	618
bcc2a2dc CR	619	skl_release_library(skl->lib_info, skl->lib_count);
	620	if (skl->dsp->fw)
	621	release_firmware(skl->dsp->fw);
	622	skl_freeup_uuid_list(skl);
	623	skl_ipc_free(&skl->ipc);
	624	skl->dsp->ops->free(skl->dsp);
92eb4f62 JK	625	}
	626	EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
	627
	628	MODULE_LICENSE("GPL v2");
	629	MODULE_DESCRIPTION("Intel Broxton IPC driver");