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ASoC: Intel: Skylake: Disable clock gating during firmware and library download
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d255b095
JK
1/*
2 * skl-message.c - HDA DSP interface for FW registration, Pipe and Module
3 * configurations
4 *
5 * Copyright (C) 2015 Intel Corp
6 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
7 * Jeeja KP <jeeja.kp@intel.com>
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 */
19
20#include <linux/slab.h>
21#include <linux/pci.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include "skl-sst-dsp.h"
b003a345 25#include "cnl-sst-dsp.h"
d255b095
JK
26#include "skl-sst-ipc.h"
27#include "skl.h"
28#include "../common/sst-dsp.h"
29#include "../common/sst-dsp-priv.h"
23db472b
JK
30#include "skl-topology.h"
31#include "skl-tplg-interface.h"
d255b095
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32
33static int skl_alloc_dma_buf(struct device *dev,
34 struct snd_dma_buffer *dmab, size_t size)
35{
36 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
37 struct hdac_bus *bus = ebus_to_hbus(ebus);
38
39 if (!bus)
40 return -ENODEV;
41
42 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, size, dmab);
43}
44
45static int skl_free_dma_buf(struct device *dev, struct snd_dma_buffer *dmab)
46{
47 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
48 struct hdac_bus *bus = ebus_to_hbus(ebus);
49
50 if (!bus)
51 return -ENODEV;
52
53 bus->io_ops->dma_free_pages(bus, dmab);
54
55 return 0;
56}
57
4e10996b
JK
58#define NOTIFICATION_PARAM_ID 3
59#define NOTIFICATION_MASK 0xf
60
61/* disable notfication for underruns/overruns from firmware module */
cb729d80 62void skl_dsp_enable_notification(struct skl_sst *ctx, bool enable)
4e10996b
JK
63{
64 struct notification_mask mask;
65 struct skl_ipc_large_config_msg msg = {0};
66
67 mask.notify = NOTIFICATION_MASK;
68 mask.enable = enable;
69
70 msg.large_param_id = NOTIFICATION_PARAM_ID;
71 msg.param_data_size = sizeof(mask);
72
73 skl_ipc_set_large_config(&ctx->ipc, &msg, (u32 *)&mask);
74}
75
92eb4f62
JK
76static int skl_dsp_setup_spib(struct device *dev, unsigned int size,
77 int stream_tag, int enable)
78{
79 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
80 struct hdac_bus *bus = ebus_to_hbus(ebus);
81 struct hdac_stream *stream = snd_hdac_get_stream(bus,
82 SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
83 struct hdac_ext_stream *estream;
84
85 if (!stream)
86 return -EINVAL;
87
88 estream = stream_to_hdac_ext_stream(stream);
89 /* enable/disable SPIB for this hdac stream */
90 snd_hdac_ext_stream_spbcap_enable(ebus, enable, stream->index);
91
92 /* set the spib value */
93 snd_hdac_ext_stream_set_spib(ebus, estream, size);
94
95 return 0;
96}
97
98static int skl_dsp_prepare(struct device *dev, unsigned int format,
99 unsigned int size, struct snd_dma_buffer *dmab)
100{
101 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
102 struct hdac_bus *bus = ebus_to_hbus(ebus);
103 struct hdac_ext_stream *estream;
104 struct hdac_stream *stream;
105 struct snd_pcm_substream substream;
106 int ret;
107
108 if (!bus)
109 return -ENODEV;
110
111 memset(&substream, 0, sizeof(substream));
112 substream.stream = SNDRV_PCM_STREAM_PLAYBACK;
113
114 estream = snd_hdac_ext_stream_assign(ebus, &substream,
115 HDAC_EXT_STREAM_TYPE_HOST);
116 if (!estream)
117 return -ENODEV;
118
119 stream = hdac_stream(estream);
120
121 /* assign decouple host dma channel */
122 ret = snd_hdac_dsp_prepare(stream, format, size, dmab);
123 if (ret < 0)
124 return ret;
125
126 skl_dsp_setup_spib(dev, size, stream->stream_tag, true);
127
128 return stream->stream_tag;
129}
130
131static int skl_dsp_trigger(struct device *dev, bool start, int stream_tag)
132{
133 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
134 struct hdac_stream *stream;
135 struct hdac_bus *bus = ebus_to_hbus(ebus);
136
137 if (!bus)
138 return -ENODEV;
139
140 stream = snd_hdac_get_stream(bus,
141 SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
142 if (!stream)
143 return -EINVAL;
144
145 snd_hdac_dsp_trigger(stream, start);
146
147 return 0;
148}
149
150static int skl_dsp_cleanup(struct device *dev,
151 struct snd_dma_buffer *dmab, int stream_tag)
152{
153 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
154 struct hdac_stream *stream;
155 struct hdac_ext_stream *estream;
156 struct hdac_bus *bus = ebus_to_hbus(ebus);
157
158 if (!bus)
159 return -ENODEV;
160
161 stream = snd_hdac_get_stream(bus,
162 SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
163 if (!stream)
164 return -EINVAL;
165
166 estream = stream_to_hdac_ext_stream(stream);
167 skl_dsp_setup_spib(dev, 0, stream_tag, false);
168 snd_hdac_ext_stream_release(estream, HDAC_EXT_STREAM_TYPE_HOST);
169
170 snd_hdac_dsp_cleanup(stream, dmab);
171
172 return 0;
173}
174
bc23ca35
JK
175static struct skl_dsp_loader_ops skl_get_loader_ops(void)
176{
177 struct skl_dsp_loader_ops loader_ops;
178
179 memset(&loader_ops, 0, sizeof(struct skl_dsp_loader_ops));
180
181 loader_ops.alloc_dma_buf = skl_alloc_dma_buf;
182 loader_ops.free_dma_buf = skl_free_dma_buf;
183
184 return loader_ops;
185};
186
92eb4f62
JK
187static struct skl_dsp_loader_ops bxt_get_loader_ops(void)
188{
189 struct skl_dsp_loader_ops loader_ops;
190
191 memset(&loader_ops, 0, sizeof(loader_ops));
192
193 loader_ops.alloc_dma_buf = skl_alloc_dma_buf;
194 loader_ops.free_dma_buf = skl_free_dma_buf;
195 loader_ops.prepare = skl_dsp_prepare;
196 loader_ops.trigger = skl_dsp_trigger;
197 loader_ops.cleanup = skl_dsp_cleanup;
198
199 return loader_ops;
200};
201
bc23ca35
JK
202static const struct skl_dsp_ops dsp_ops[] = {
203 {
204 .id = 0x9d70,
363d4538 205 .num_cores = 2,
bc23ca35
JK
206 .loader_ops = skl_get_loader_ops,
207 .init = skl_sst_dsp_init,
78cdbbda 208 .init_fw = skl_sst_init_fw,
bc23ca35
JK
209 .cleanup = skl_sst_dsp_cleanup
210 },
451dfb5f
VK
211 {
212 .id = 0x9d71,
363d4538 213 .num_cores = 2,
451dfb5f 214 .loader_ops = skl_get_loader_ops,
89b0d8a5 215 .init = kbl_sst_dsp_init,
78cdbbda 216 .init_fw = skl_sst_init_fw,
451dfb5f
VK
217 .cleanup = skl_sst_dsp_cleanup
218 },
92eb4f62
JK
219 {
220 .id = 0x5a98,
363d4538 221 .num_cores = 2,
92eb4f62
JK
222 .loader_ops = bxt_get_loader_ops,
223 .init = bxt_sst_dsp_init,
78cdbbda 224 .init_fw = bxt_sst_init_fw,
92eb4f62
JK
225 .cleanup = bxt_sst_dsp_cleanup
226 },
25504863
VK
227 {
228 .id = 0x3198,
363d4538 229 .num_cores = 2,
25504863
VK
230 .loader_ops = bxt_get_loader_ops,
231 .init = bxt_sst_dsp_init,
232 .init_fw = bxt_sst_init_fw,
233 .cleanup = bxt_sst_dsp_cleanup
234 },
b003a345
GS
235 {
236 .id = 0x9dc8,
237 .num_cores = 4,
238 .loader_ops = bxt_get_loader_ops,
239 .init = cnl_sst_dsp_init,
240 .init_fw = cnl_sst_init_fw,
241 .cleanup = cnl_sst_dsp_cleanup
242 },
bc23ca35
JK
243};
244
73a67581 245const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id)
bc23ca35
JK
246{
247 int i;
248
249 for (i = 0; i < ARRAY_SIZE(dsp_ops); i++) {
250 if (dsp_ops[i].id == pci_id)
73a67581 251 return &dsp_ops[i];
bc23ca35
JK
252 }
253
73a67581 254 return NULL;
bc23ca35
JK
255}
256
d255b095
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257int skl_init_dsp(struct skl *skl)
258{
259 void __iomem *mmio_base;
260 struct hdac_ext_bus *ebus = &skl->ebus;
261 struct hdac_bus *bus = ebus_to_hbus(ebus);
d255b095 262 struct skl_dsp_loader_ops loader_ops;
bc23ca35 263 int irq = bus->irq;
73a67581 264 const struct skl_dsp_ops *ops;
f0a550a8 265 struct skl_dsp_cores *cores;
73a67581 266 int ret;
d255b095
JK
267
268 /* enable ppcap interrupt */
269 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true);
270 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true);
271
272 /* read the BAR of the ADSP MMIO */
273 mmio_base = pci_ioremap_bar(skl->pci, 4);
274 if (mmio_base == NULL) {
275 dev_err(bus->dev, "ioremap error\n");
276 return -ENXIO;
277 }
278
73a67581 279 ops = skl_get_dsp_ops(skl->pci->device);
f77d443c 280 if (!ops) {
f77d443c 281 ret = -EIO;
9149916f 282 goto unmap_mmio;
f77d443c 283 }
bc23ca35 284
73a67581
VK
285 loader_ops = ops->loader_ops();
286 ret = ops->init(bus->dev, mmio_base, irq,
287 skl->fw_name, loader_ops,
288 &skl->skl_sst);
bc23ca35 289
2ac454ff 290 if (ret < 0)
f77d443c 291 goto unmap_mmio;
2ac454ff 292
7bd86a30 293 skl->skl_sst->dsp_ops = ops;
f0a550a8
GS
294 cores = &skl->skl_sst->cores;
295 cores->count = ops->num_cores;
296
297 cores->state = kcalloc(cores->count, sizeof(*cores->state), GFP_KERNEL);
f77d443c
SP
298 if (!cores->state) {
299 ret = -ENOMEM;
300 goto unmap_mmio;
301 }
f0a550a8
GS
302
303 cores->usage_count = kcalloc(cores->count, sizeof(*cores->usage_count),
304 GFP_KERNEL);
305 if (!cores->usage_count) {
f77d443c
SP
306 ret = -ENOMEM;
307 goto free_core_state;
f0a550a8 308 }
363d4538 309
d255b095
JK
310 dev_dbg(bus->dev, "dsp registration status=%d\n", ret);
311
f77d443c
SP
312 return 0;
313
314free_core_state:
315 kfree(cores->state);
316
317unmap_mmio:
318 iounmap(mmio_base);
319
d255b095
JK
320 return ret;
321}
322
bc23ca35 323int skl_free_dsp(struct skl *skl)
d255b095
JK
324{
325 struct hdac_ext_bus *ebus = &skl->ebus;
326 struct hdac_bus *bus = ebus_to_hbus(ebus);
bc23ca35 327 struct skl_sst *ctx = skl->skl_sst;
d255b095
JK
328
329 /* disable ppcap interrupt */
330 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false);
331
7bd86a30 332 ctx->dsp_ops->cleanup(bus->dev, ctx);
bc23ca35 333
f0a550a8
GS
334 kfree(ctx->cores.state);
335 kfree(ctx->cores.usage_count);
336
d255b095
JK
337 if (ctx->dsp->addr.lpe)
338 iounmap(ctx->dsp->addr.lpe);
bc23ca35
JK
339
340 return 0;
d255b095
JK
341}
342
8b4a133c
J
343/*
344 * In the case of "suspend_active" i.e, the Audio IP being active
345 * during system suspend, immediately excecute any pending D0i3 work
346 * before suspending. This is needed for the IP to work in low power
347 * mode during system suspend. In the case of normal suspend, cancel
348 * any pending D0i3 work.
349 */
350int skl_suspend_late_dsp(struct skl *skl)
351{
352 struct skl_sst *ctx = skl->skl_sst;
353 struct delayed_work *dwork;
354
355 if (!ctx)
356 return 0;
357
358 dwork = &ctx->d0i3.work;
359
360 if (dwork->work.func) {
361 if (skl->supend_active)
362 flush_delayed_work(dwork);
363 else
364 cancel_delayed_work_sync(dwork);
365 }
366
367 return 0;
368}
369
d255b095
JK
370int skl_suspend_dsp(struct skl *skl)
371{
372 struct skl_sst *ctx = skl->skl_sst;
373 int ret;
374
375 /* if ppcap is not supported return 0 */
ec8ae570 376 if (!skl->ebus.bus.ppcap)
d255b095
JK
377 return 0;
378
379 ret = skl_dsp_sleep(ctx->dsp);
380 if (ret < 0)
381 return ret;
382
383 /* disable ppcap interrupt */
384 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false);
385 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, false);
386
387 return 0;
388}
389
390int skl_resume_dsp(struct skl *skl)
391{
392 struct skl_sst *ctx = skl->skl_sst;
4e10996b 393 int ret;
d255b095
JK
394
395 /* if ppcap is not supported return 0 */
ec8ae570 396 if (!skl->ebus.bus.ppcap)
d255b095
JK
397 return 0;
398
399 /* enable ppcap interrupt */
400 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true);
401 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true);
402
78cdbbda
VK
403 /* check if DSP 1st boot is done */
404 if (skl->skl_sst->is_first_boot == true)
405 return 0;
406
71b8e42d
PS
407 /* disable dynamic clock gating during fw and lib download */
408 ctx->enable_miscbdcge(ctx->dev, false);
409
4e10996b 410 ret = skl_dsp_wake(ctx->dsp);
71b8e42d 411 ctx->enable_miscbdcge(ctx->dev, true);
4e10996b
JK
412 if (ret < 0)
413 return ret;
414
415 skl_dsp_enable_notification(skl->skl_sst, false);
416 return ret;
d255b095 417}
23db472b
JK
418
419enum skl_bitdepth skl_get_bit_depth(int params)
420{
421 switch (params) {
422 case 8:
423 return SKL_DEPTH_8BIT;
424
425 case 16:
426 return SKL_DEPTH_16BIT;
427
428 case 24:
429 return SKL_DEPTH_24BIT;
430
431 case 32:
432 return SKL_DEPTH_32BIT;
433
434 default:
435 return SKL_DEPTH_INVALID;
436
437 }
438}
439
23db472b
JK
440/*
441 * Each module in DSP expects a base module configuration, which consists of
442 * PCM format information, which we calculate in driver and resource values
443 * which are read from widget information passed through topology binary
444 * This is send when we create a module with INIT_INSTANCE IPC msg
445 */
446static void skl_set_base_module_format(struct skl_sst *ctx,
447 struct skl_module_cfg *mconfig,
448 struct skl_base_cfg *base_cfg)
449{
f6fa56e2
RB
450 struct skl_module *module = mconfig->module;
451 struct skl_module_res *res = &module->resources[mconfig->res_idx];
452 struct skl_module_iface *fmt = &module->formats[mconfig->fmt_idx];
453 struct skl_module_fmt *format = &fmt->inputs[0].fmt;
23db472b 454
f6fa56e2 455 base_cfg->audio_fmt.number_of_channels = format->channels;
23db472b
JK
456
457 base_cfg->audio_fmt.s_freq = format->s_freq;
458 base_cfg->audio_fmt.bit_depth = format->bit_depth;
459 base_cfg->audio_fmt.valid_bit_depth = format->valid_bit_depth;
460 base_cfg->audio_fmt.ch_cfg = format->ch_cfg;
461
462 dev_dbg(ctx->dev, "bit_depth=%x valid_bd=%x ch_config=%x\n",
463 format->bit_depth, format->valid_bit_depth,
464 format->ch_cfg);
465
3e81f1a3 466 base_cfg->audio_fmt.channel_map = format->ch_map;
23db472b 467
3e81f1a3 468 base_cfg->audio_fmt.interleaving = format->interleaving_style;
23db472b 469
f6fa56e2
RB
470 base_cfg->cps = res->cps;
471 base_cfg->ibs = res->ibs;
472 base_cfg->obs = res->obs;
473 base_cfg->is_pages = res->is_pages;
23db472b
JK
474}
475
476/*
477 * Copies copier capabilities into copier module and updates copier module
478 * config size.
479 */
480static void skl_copy_copier_caps(struct skl_module_cfg *mconfig,
481 struct skl_cpr_cfg *cpr_mconfig)
482{
483 if (mconfig->formats_config.caps_size == 0)
484 return;
485
486 memcpy(cpr_mconfig->gtw_cfg.config_data,
487 mconfig->formats_config.caps,
488 mconfig->formats_config.caps_size);
489
490 cpr_mconfig->gtw_cfg.config_length =
491 (mconfig->formats_config.caps_size) / 4;
492}
493
bfa764ac 494#define SKL_NON_GATEWAY_CPR_NODE_ID 0xFFFFFFFF
23db472b
JK
495/*
496 * Calculate the gatewat settings required for copier module, type of
497 * gateway and index of gateway to use
498 */
4fdf810f
D
499static u32 skl_get_node_id(struct skl_sst *ctx,
500 struct skl_module_cfg *mconfig)
23db472b
JK
501{
502 union skl_connector_node_id node_id = {0};
d7b18813 503 union skl_ssp_dma_node ssp_node = {0};
23db472b
JK
504 struct skl_pipe_params *params = mconfig->pipe->p_params;
505
506 switch (mconfig->dev_type) {
507 case SKL_DEVICE_BT:
508 node_id.node.dma_type =
509 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
510 SKL_DMA_I2S_LINK_OUTPUT_CLASS :
511 SKL_DMA_I2S_LINK_INPUT_CLASS;
512 node_id.node.vindex = params->host_dma_id +
513 (mconfig->vbus_id << 3);
514 break;
515
516 case SKL_DEVICE_I2S:
517 node_id.node.dma_type =
518 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
519 SKL_DMA_I2S_LINK_OUTPUT_CLASS :
520 SKL_DMA_I2S_LINK_INPUT_CLASS;
d7b18813
JK
521 ssp_node.dma_node.time_slot_index = mconfig->time_slot;
522 ssp_node.dma_node.i2s_instance = mconfig->vbus_id;
523 node_id.node.vindex = ssp_node.val;
23db472b
JK
524 break;
525
526 case SKL_DEVICE_DMIC:
527 node_id.node.dma_type = SKL_DMA_DMIC_LINK_INPUT_CLASS;
528 node_id.node.vindex = mconfig->vbus_id +
529 (mconfig->time_slot);
530 break;
531
532 case SKL_DEVICE_HDALINK:
533 node_id.node.dma_type =
534 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
535 SKL_DMA_HDA_LINK_OUTPUT_CLASS :
536 SKL_DMA_HDA_LINK_INPUT_CLASS;
537 node_id.node.vindex = params->link_dma_id;
538 break;
539
bfa764ac 540 case SKL_DEVICE_HDAHOST:
23db472b
JK
541 node_id.node.dma_type =
542 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
543 SKL_DMA_HDA_HOST_OUTPUT_CLASS :
544 SKL_DMA_HDA_HOST_INPUT_CLASS;
545 node_id.node.vindex = params->host_dma_id;
546 break;
bfa764ac
JK
547
548 default:
4fdf810f
D
549 node_id.val = 0xFFFFFFFF;
550 break;
551 }
552
553 return node_id.val;
554}
555
556static void skl_setup_cpr_gateway_cfg(struct skl_sst *ctx,
557 struct skl_module_cfg *mconfig,
558 struct skl_cpr_cfg *cpr_mconfig)
559{
f6e6ab1d 560 u32 dma_io_buf;
f6fa56e2
RB
561 struct skl_module_res *res;
562 int res_idx = mconfig->res_idx;
563 struct skl *skl = get_skl_ctx(ctx->dev);
f6e6ab1d 564
4fdf810f
D
565 cpr_mconfig->gtw_cfg.node_id = skl_get_node_id(ctx, mconfig);
566
567 if (cpr_mconfig->gtw_cfg.node_id == SKL_NON_GATEWAY_CPR_NODE_ID) {
bfa764ac
JK
568 cpr_mconfig->cpr_feature_mask = 0;
569 return;
23db472b
JK
570 }
571
f6fa56e2
RB
572 if (skl->nr_modules) {
573 res = &mconfig->module->resources[mconfig->res_idx];
574 cpr_mconfig->gtw_cfg.dma_buffer_size = res->dma_buffer_size;
575 goto skip_buf_size_calc;
576 } else {
577 res = &mconfig->module->resources[res_idx];
578 }
579
f6e6ab1d
RB
580 switch (mconfig->hw_conn_type) {
581 case SKL_CONN_SOURCE:
582 if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
f6fa56e2 583 dma_io_buf = res->ibs;
f6e6ab1d 584 else
f6fa56e2 585 dma_io_buf = res->obs;
f6e6ab1d
RB
586 break;
587
588 case SKL_CONN_SINK:
589 if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
f6fa56e2 590 dma_io_buf = res->obs;
f6e6ab1d 591 else
f6fa56e2 592 dma_io_buf = res->ibs;
f6e6ab1d
RB
593 break;
594
595 default:
596 dev_warn(ctx->dev, "wrong connection type: %d\n",
597 mconfig->hw_conn_type);
598 return;
599 }
600
601 cpr_mconfig->gtw_cfg.dma_buffer_size =
602 mconfig->dma_buffer_size * dma_io_buf;
23db472b 603
5b43af6d
SP
604 /* fallback to 2ms default value */
605 if (!cpr_mconfig->gtw_cfg.dma_buffer_size) {
606 if (mconfig->hw_conn_type == SKL_CONN_SOURCE)
f6fa56e2 607 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * res->obs;
5b43af6d 608 else
f6fa56e2 609 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * res->ibs;
5b43af6d
SP
610 }
611
f6fa56e2 612skip_buf_size_calc:
23db472b
JK
613 cpr_mconfig->cpr_feature_mask = 0;
614 cpr_mconfig->gtw_cfg.config_length = 0;
615
616 skl_copy_copier_caps(mconfig, cpr_mconfig);
617}
618
c115fa5e 619#define DMA_CONTROL_ID 5
5514830d 620#define DMA_I2S_BLOB_SIZE 21
c115fa5e 621
5514830d
JN
622int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps,
623 u32 caps_size, u32 node_id)
c115fa5e
D
624{
625 struct skl_dma_control *dma_ctrl;
c115fa5e
D
626 struct skl_ipc_large_config_msg msg = {0};
627 int err = 0;
628
629
630 /*
c186fe74 631 * if blob size zero, then return
c115fa5e 632 */
5514830d 633 if (caps_size == 0)
c115fa5e
D
634 return 0;
635
636 msg.large_param_id = DMA_CONTROL_ID;
5514830d 637 msg.param_data_size = sizeof(struct skl_dma_control) + caps_size;
c115fa5e
D
638
639 dma_ctrl = kzalloc(msg.param_data_size, GFP_KERNEL);
640 if (dma_ctrl == NULL)
641 return -ENOMEM;
642
5514830d 643 dma_ctrl->node_id = node_id;
c115fa5e 644
5514830d
JN
645 /*
646 * NHLT blob may contain additional configs along with i2s blob.
647 * firmware expects only the i2s blob size as the config_length.
648 * So fix to i2s blob size.
649 * size in dwords.
650 */
651 dma_ctrl->config_length = DMA_I2S_BLOB_SIZE;
c115fa5e 652
5514830d 653 memcpy(dma_ctrl->config_data, caps, caps_size);
c115fa5e
D
654
655 err = skl_ipc_set_large_config(&ctx->ipc, &msg, (u32 *)dma_ctrl);
656
657 kfree(dma_ctrl);
c115fa5e
D
658 return err;
659}
660
23db472b
JK
661static void skl_setup_out_format(struct skl_sst *ctx,
662 struct skl_module_cfg *mconfig,
663 struct skl_audio_data_format *out_fmt)
664{
f6fa56e2
RB
665 struct skl_module *module = mconfig->module;
666 struct skl_module_iface *fmt = &module->formats[mconfig->fmt_idx];
667 struct skl_module_fmt *format = &fmt->outputs[0].fmt;
23db472b
JK
668
669 out_fmt->number_of_channels = (u8)format->channels;
670 out_fmt->s_freq = format->s_freq;
671 out_fmt->bit_depth = format->bit_depth;
672 out_fmt->valid_bit_depth = format->valid_bit_depth;
673 out_fmt->ch_cfg = format->ch_cfg;
674
3e81f1a3
JK
675 out_fmt->channel_map = format->ch_map;
676 out_fmt->interleaving = format->interleaving_style;
677 out_fmt->sample_type = format->sample_type;
23db472b
JK
678
679 dev_dbg(ctx->dev, "copier out format chan=%d fre=%d bitdepth=%d\n",
680 out_fmt->number_of_channels, format->s_freq, format->bit_depth);
681}
682
a0ffe48b
HS
683/*
684 * DSP needs SRC module for frequency conversion, SRC takes base module
685 * configuration and the target frequency as extra parameter passed as src
686 * config
687 */
688static void skl_set_src_format(struct skl_sst *ctx,
689 struct skl_module_cfg *mconfig,
690 struct skl_src_module_cfg *src_mconfig)
691{
f6fa56e2
RB
692 struct skl_module *module = mconfig->module;
693 struct skl_module_iface *iface = &module->formats[mconfig->fmt_idx];
694 struct skl_module_fmt *fmt = &iface->outputs[0].fmt;
a0ffe48b
HS
695
696 skl_set_base_module_format(ctx, mconfig,
697 (struct skl_base_cfg *)src_mconfig);
698
699 src_mconfig->src_cfg = fmt->s_freq;
700}
701
702/*
703 * DSP needs updown module to do channel conversion. updown module take base
704 * module configuration and channel configuration
705 * It also take coefficients and now we have defaults applied here
706 */
707static void skl_set_updown_mixer_format(struct skl_sst *ctx,
708 struct skl_module_cfg *mconfig,
709 struct skl_up_down_mixer_cfg *mixer_mconfig)
710{
f6fa56e2
RB
711 struct skl_module *module = mconfig->module;
712 struct skl_module_iface *iface = &module->formats[mconfig->fmt_idx];
713 struct skl_module_fmt *fmt = &iface->outputs[0].fmt;
a0ffe48b
HS
714
715 skl_set_base_module_format(ctx, mconfig,
716 (struct skl_base_cfg *)mixer_mconfig);
717 mixer_mconfig->out_ch_cfg = fmt->ch_cfg;
da3417fe 718 mixer_mconfig->ch_map = fmt->ch_map;
a0ffe48b
HS
719}
720
23db472b
JK
721/*
722 * 'copier' is DSP internal module which copies data from Host DMA (HDA host
723 * dma) or link (hda link, SSP, PDM)
724 * Here we calculate the copier module parameters, like PCM format, output
725 * format, gateway settings
726 * copier_module_config is sent as input buffer with INIT_INSTANCE IPC msg
727 */
728static void skl_set_copier_format(struct skl_sst *ctx,
729 struct skl_module_cfg *mconfig,
730 struct skl_cpr_cfg *cpr_mconfig)
731{
732 struct skl_audio_data_format *out_fmt = &cpr_mconfig->out_fmt;
733 struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)cpr_mconfig;
734
735 skl_set_base_module_format(ctx, mconfig, base_cfg);
736
737 skl_setup_out_format(ctx, mconfig, out_fmt);
738 skl_setup_cpr_gateway_cfg(ctx, mconfig, cpr_mconfig);
739}
740
399b210b
JK
741/*
742 * Algo module are DSP pre processing modules. Algo module take base module
743 * configuration and params
744 */
745
746static void skl_set_algo_format(struct skl_sst *ctx,
747 struct skl_module_cfg *mconfig,
748 struct skl_algo_cfg *algo_mcfg)
749{
750 struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)algo_mcfg;
751
752 skl_set_base_module_format(ctx, mconfig, base_cfg);
753
754 if (mconfig->formats_config.caps_size == 0)
755 return;
756
757 memcpy(algo_mcfg->params,
758 mconfig->formats_config.caps,
759 mconfig->formats_config.caps_size);
760
761}
762
fd18110f
D
763/*
764 * Mic select module allows selecting one or many input channels, thus
765 * acting as a demux.
766 *
767 * Mic select module take base module configuration and out-format
768 * configuration
769 */
770static void skl_set_base_outfmt_format(struct skl_sst *ctx,
771 struct skl_module_cfg *mconfig,
772 struct skl_base_outfmt_cfg *base_outfmt_mcfg)
773{
774 struct skl_audio_data_format *out_fmt = &base_outfmt_mcfg->out_fmt;
775 struct skl_base_cfg *base_cfg =
776 (struct skl_base_cfg *)base_outfmt_mcfg;
777
778 skl_set_base_module_format(ctx, mconfig, base_cfg);
779 skl_setup_out_format(ctx, mconfig, out_fmt);
780}
781
23db472b
JK
782static u16 skl_get_module_param_size(struct skl_sst *ctx,
783 struct skl_module_cfg *mconfig)
784{
785 u16 param_size;
786
787 switch (mconfig->m_type) {
788 case SKL_MODULE_TYPE_COPIER:
789 param_size = sizeof(struct skl_cpr_cfg);
790 param_size += mconfig->formats_config.caps_size;
791 return param_size;
792
a0ffe48b
HS
793 case SKL_MODULE_TYPE_SRCINT:
794 return sizeof(struct skl_src_module_cfg);
795
796 case SKL_MODULE_TYPE_UPDWMIX:
797 return sizeof(struct skl_up_down_mixer_cfg);
798
399b210b
JK
799 case SKL_MODULE_TYPE_ALGO:
800 param_size = sizeof(struct skl_base_cfg);
801 param_size += mconfig->formats_config.caps_size;
802 return param_size;
803
fd18110f 804 case SKL_MODULE_TYPE_BASE_OUTFMT:
db6879ef 805 case SKL_MODULE_TYPE_MIC_SELECT:
5e8f0ee4 806 case SKL_MODULE_TYPE_KPB:
fd18110f
D
807 return sizeof(struct skl_base_outfmt_cfg);
808
23db472b
JK
809 default:
810 /*
811 * return only base cfg when no specific module type is
812 * specified
813 */
814 return sizeof(struct skl_base_cfg);
815 }
816
817 return 0;
818}
819
820/*
a0ffe48b
HS
821 * DSP firmware supports various modules like copier, SRC, updown etc.
822 * These modules required various parameters to be calculated and sent for
823 * the module initialization to DSP. By default a generic module needs only
824 * base module format configuration
23db472b 825 */
a0ffe48b 826
23db472b
JK
827static int skl_set_module_format(struct skl_sst *ctx,
828 struct skl_module_cfg *module_config,
829 u16 *module_config_size,
830 void **param_data)
831{
832 u16 param_size;
833
834 param_size = skl_get_module_param_size(ctx, module_config);
835
836 *param_data = kzalloc(param_size, GFP_KERNEL);
837 if (NULL == *param_data)
838 return -ENOMEM;
839
840 *module_config_size = param_size;
841
842 switch (module_config->m_type) {
843 case SKL_MODULE_TYPE_COPIER:
844 skl_set_copier_format(ctx, module_config, *param_data);
845 break;
846
a0ffe48b
HS
847 case SKL_MODULE_TYPE_SRCINT:
848 skl_set_src_format(ctx, module_config, *param_data);
849 break;
850
851 case SKL_MODULE_TYPE_UPDWMIX:
852 skl_set_updown_mixer_format(ctx, module_config, *param_data);
853 break;
854
399b210b
JK
855 case SKL_MODULE_TYPE_ALGO:
856 skl_set_algo_format(ctx, module_config, *param_data);
857 break;
858
fd18110f 859 case SKL_MODULE_TYPE_BASE_OUTFMT:
db6879ef 860 case SKL_MODULE_TYPE_MIC_SELECT:
5e8f0ee4 861 case SKL_MODULE_TYPE_KPB:
fd18110f
D
862 skl_set_base_outfmt_format(ctx, module_config, *param_data);
863 break;
864
23db472b
JK
865 default:
866 skl_set_base_module_format(ctx, module_config, *param_data);
867 break;
868
869 }
870
871 dev_dbg(ctx->dev, "Module type=%d config size: %d bytes\n",
872 module_config->id.module_id, param_size);
91c18325 873 print_hex_dump_debug("Module params:", DUMP_PREFIX_OFFSET, 8, 4,
23db472b
JK
874 *param_data, param_size, false);
875 return 0;
876}
877
878static int skl_get_queue_index(struct skl_module_pin *mpin,
879 struct skl_module_inst_id id, int max)
880{
881 int i;
882
883 for (i = 0; i < max; i++) {
884 if (mpin[i].id.module_id == id.module_id &&
885 mpin[i].id.instance_id == id.instance_id)
886 return i;
887 }
888
889 return -EINVAL;
890}
891
892/*
893 * Allocates queue for each module.
894 * if dynamic, the pin_index is allocated 0 to max_pin.
895 * In static, the pin_index is fixed based on module_id and instance id
896 */
897static int skl_alloc_queue(struct skl_module_pin *mpin,
4f745708 898 struct skl_module_cfg *tgt_cfg, int max)
23db472b
JK
899{
900 int i;
4f745708 901 struct skl_module_inst_id id = tgt_cfg->id;
23db472b
JK
902 /*
903 * if pin in dynamic, find first free pin
904 * otherwise find match module and instance id pin as topology will
905 * ensure a unique pin is assigned to this so no need to
906 * allocate/free
907 */
908 for (i = 0; i < max; i++) {
909 if (mpin[i].is_dynamic) {
4f745708
JK
910 if (!mpin[i].in_use &&
911 mpin[i].pin_state == SKL_PIN_UNBIND) {
912
23db472b
JK
913 mpin[i].in_use = true;
914 mpin[i].id.module_id = id.module_id;
915 mpin[i].id.instance_id = id.instance_id;
ef2a352c 916 mpin[i].id.pvt_id = id.pvt_id;
4f745708 917 mpin[i].tgt_mcfg = tgt_cfg;
23db472b
JK
918 return i;
919 }
920 } else {
921 if (mpin[i].id.module_id == id.module_id &&
4f745708
JK
922 mpin[i].id.instance_id == id.instance_id &&
923 mpin[i].pin_state == SKL_PIN_UNBIND) {
924
925 mpin[i].tgt_mcfg = tgt_cfg;
23db472b 926 return i;
4f745708 927 }
23db472b
JK
928 }
929 }
930
931 return -EINVAL;
932}
933
934static void skl_free_queue(struct skl_module_pin *mpin, int q_index)
935{
936 if (mpin[q_index].is_dynamic) {
937 mpin[q_index].in_use = false;
938 mpin[q_index].id.module_id = 0;
939 mpin[q_index].id.instance_id = 0;
ef2a352c 940 mpin[q_index].id.pvt_id = 0;
23db472b 941 }
4f745708
JK
942 mpin[q_index].pin_state = SKL_PIN_UNBIND;
943 mpin[q_index].tgt_mcfg = NULL;
944}
945
946/* Module state will be set to unint, if all the out pin state is UNBIND */
947
948static void skl_clear_module_state(struct skl_module_pin *mpin, int max,
949 struct skl_module_cfg *mcfg)
950{
951 int i;
952 bool found = false;
953
954 for (i = 0; i < max; i++) {
955 if (mpin[i].pin_state == SKL_PIN_UNBIND)
956 continue;
957 found = true;
958 break;
959 }
960
961 if (!found)
473a4d51 962 mcfg->m_state = SKL_MODULE_INIT_DONE;
4f745708 963 return;
23db472b 964}
beb73b26
JK
965
966/*
967 * A module needs to be instanataited in DSP. A mdoule is present in a
968 * collection of module referred as a PIPE.
969 * We first calculate the module format, based on module type and then
970 * invoke the DSP by sending IPC INIT_INSTANCE using ipc helper
971 */
972int skl_init_module(struct skl_sst *ctx,
9939a9c3 973 struct skl_module_cfg *mconfig)
beb73b26
JK
974{
975 u16 module_config_size = 0;
976 void *param_data = NULL;
977 int ret;
978 struct skl_ipc_init_instance_msg msg;
979
980 dev_dbg(ctx->dev, "%s: module_id = %d instance=%d\n", __func__,
ef2a352c 981 mconfig->id.module_id, mconfig->id.pvt_id);
beb73b26
JK
982
983 if (mconfig->pipe->state != SKL_PIPE_CREATED) {
984 dev_err(ctx->dev, "Pipe not created state= %d pipe_id= %d\n",
985 mconfig->pipe->state, mconfig->pipe->ppl_id);
986 return -EIO;
987 }
988
989 ret = skl_set_module_format(ctx, mconfig,
990 &module_config_size, &param_data);
991 if (ret < 0) {
992 dev_err(ctx->dev, "Failed to set module format ret=%d\n", ret);
993 return ret;
994 }
995
996 msg.module_id = mconfig->id.module_id;
ef2a352c 997 msg.instance_id = mconfig->id.pvt_id;
beb73b26
JK
998 msg.ppl_instance_id = mconfig->pipe->ppl_id;
999 msg.param_data_size = module_config_size;
1000 msg.core_id = mconfig->core_id;
3d4006cd 1001 msg.domain = mconfig->domain;
beb73b26
JK
1002
1003 ret = skl_ipc_init_instance(&ctx->ipc, &msg, param_data);
1004 if (ret < 0) {
1005 dev_err(ctx->dev, "Failed to init instance ret=%d\n", ret);
1006 kfree(param_data);
1007 return ret;
1008 }
1009 mconfig->m_state = SKL_MODULE_INIT_DONE;
76222d6d 1010 kfree(param_data);
beb73b26
JK
1011 return ret;
1012}
1013
1014static void skl_dump_bind_info(struct skl_sst *ctx, struct skl_module_cfg
1015 *src_module, struct skl_module_cfg *dst_module)
1016{
1017 dev_dbg(ctx->dev, "%s: src module_id = %d src_instance=%d\n",
ef2a352c 1018 __func__, src_module->id.module_id, src_module->id.pvt_id);
d5c6d43b 1019 dev_dbg(ctx->dev, "%s: dst_module=%d dst_instance=%d\n", __func__,
ef2a352c 1020 dst_module->id.module_id, dst_module->id.pvt_id);
beb73b26
JK
1021
1022 dev_dbg(ctx->dev, "src_module state = %d dst module state = %d\n",
1023 src_module->m_state, dst_module->m_state);
1024}
1025
1026/*
1027 * On module freeup, we need to unbind the module with modules
1028 * it is already bind.
1029 * Find the pin allocated and unbind then using bind_unbind IPC
1030 */
1031int skl_unbind_modules(struct skl_sst *ctx,
1032 struct skl_module_cfg *src_mcfg,
1033 struct skl_module_cfg *dst_mcfg)
1034{
1035 int ret;
1036 struct skl_ipc_bind_unbind_msg msg;
1037 struct skl_module_inst_id src_id = src_mcfg->id;
1038 struct skl_module_inst_id dst_id = dst_mcfg->id;
f6fa56e2
RB
1039 int in_max = dst_mcfg->module->max_input_pins;
1040 int out_max = src_mcfg->module->max_output_pins;
4f745708 1041 int src_index, dst_index, src_pin_state, dst_pin_state;
beb73b26
JK
1042
1043 skl_dump_bind_info(ctx, src_mcfg, dst_mcfg);
1044
beb73b26
JK
1045 /* get src queue index */
1046 src_index = skl_get_queue_index(src_mcfg->m_out_pin, dst_id, out_max);
1047 if (src_index < 0)
9cf3049e 1048 return 0;
beb73b26 1049
4f745708 1050 msg.src_queue = src_index;
beb73b26
JK
1051
1052 /* get dst queue index */
1053 dst_index = skl_get_queue_index(dst_mcfg->m_in_pin, src_id, in_max);
1054 if (dst_index < 0)
9cf3049e 1055 return 0;
beb73b26 1056
4f745708
JK
1057 msg.dst_queue = dst_index;
1058
1059 src_pin_state = src_mcfg->m_out_pin[src_index].pin_state;
1060 dst_pin_state = dst_mcfg->m_in_pin[dst_index].pin_state;
1061
1062 if (src_pin_state != SKL_PIN_BIND_DONE ||
1063 dst_pin_state != SKL_PIN_BIND_DONE)
1064 return 0;
beb73b26
JK
1065
1066 msg.module_id = src_mcfg->id.module_id;
ef2a352c 1067 msg.instance_id = src_mcfg->id.pvt_id;
beb73b26 1068 msg.dst_module_id = dst_mcfg->id.module_id;
ef2a352c 1069 msg.dst_instance_id = dst_mcfg->id.pvt_id;
beb73b26
JK
1070 msg.bind = false;
1071
1072 ret = skl_ipc_bind_unbind(&ctx->ipc, &msg);
1073 if (!ret) {
beb73b26
JK
1074 /* free queue only if unbind is success */
1075 skl_free_queue(src_mcfg->m_out_pin, src_index);
1076 skl_free_queue(dst_mcfg->m_in_pin, dst_index);
4f745708
JK
1077
1078 /*
1079 * check only if src module bind state, bind is
1080 * always from src -> sink
1081 */
1082 skl_clear_module_state(src_mcfg->m_out_pin, out_max, src_mcfg);
beb73b26
JK
1083 }
1084
1085 return ret;
1086}
1087
38a77085
PT
1088static void fill_pin_params(struct skl_audio_data_format *pin_fmt,
1089 struct skl_module_fmt *format)
1090{
1091 pin_fmt->number_of_channels = format->channels;
1092 pin_fmt->s_freq = format->s_freq;
1093 pin_fmt->bit_depth = format->bit_depth;
1094 pin_fmt->valid_bit_depth = format->valid_bit_depth;
1095 pin_fmt->ch_cfg = format->ch_cfg;
1096 pin_fmt->sample_type = format->sample_type;
1097 pin_fmt->channel_map = format->ch_map;
1098 pin_fmt->interleaving = format->interleaving_style;
1099}
1100
1101#define CPR_SINK_FMT_PARAM_ID 2
1102
beb73b26
JK
1103/*
1104 * Once a module is instantiated it need to be 'bind' with other modules in
1105 * the pipeline. For binding we need to find the module pins which are bind
1106 * together
1107 * This function finds the pins and then sends bund_unbind IPC message to
1108 * DSP using IPC helper
1109 */
1110int skl_bind_modules(struct skl_sst *ctx,
1111 struct skl_module_cfg *src_mcfg,
1112 struct skl_module_cfg *dst_mcfg)
1113{
38a77085 1114 int ret = 0;
beb73b26 1115 struct skl_ipc_bind_unbind_msg msg;
f6fa56e2
RB
1116 int in_max = dst_mcfg->module->max_input_pins;
1117 int out_max = src_mcfg->module->max_output_pins;
beb73b26 1118 int src_index, dst_index;
38a77085
PT
1119 struct skl_module_fmt *format;
1120 struct skl_cpr_pin_fmt pin_fmt;
1121 struct skl_module *module;
1122 struct skl_module_iface *fmt;
beb73b26
JK
1123
1124 skl_dump_bind_info(ctx, src_mcfg, dst_mcfg);
1125
0c684c48 1126 if (src_mcfg->m_state < SKL_MODULE_INIT_DONE ||
beb73b26
JK
1127 dst_mcfg->m_state < SKL_MODULE_INIT_DONE)
1128 return 0;
1129
4f745708 1130 src_index = skl_alloc_queue(src_mcfg->m_out_pin, dst_mcfg, out_max);
beb73b26
JK
1131 if (src_index < 0)
1132 return -EINVAL;
1133
4f745708
JK
1134 msg.src_queue = src_index;
1135 dst_index = skl_alloc_queue(dst_mcfg->m_in_pin, src_mcfg, in_max);
beb73b26
JK
1136 if (dst_index < 0) {
1137 skl_free_queue(src_mcfg->m_out_pin, src_index);
1138 return -EINVAL;
1139 }
1140
38a77085
PT
1141 /*
1142 * Copier module requires the separate large_config_set_ipc to
1143 * configure the pins other than 0
1144 */
1145 if (src_mcfg->m_type == SKL_MODULE_TYPE_COPIER && src_index > 0) {
1146 pin_fmt.sink_id = src_index;
1147 module = src_mcfg->module;
1148 fmt = &module->formats[src_mcfg->fmt_idx];
1149
1150 /* Input fmt is same as that of src module input cfg */
1151 format = &fmt->inputs[0].fmt;
1152 fill_pin_params(&(pin_fmt.src_fmt), format);
1153
1154 format = &fmt->outputs[src_index].fmt;
1155 fill_pin_params(&(pin_fmt.dst_fmt), format);
1156 ret = skl_set_module_params(ctx, (void *)&pin_fmt,
1157 sizeof(struct skl_cpr_pin_fmt),
1158 CPR_SINK_FMT_PARAM_ID, src_mcfg);
1159
1160 if (ret < 0)
1161 goto out;
1162 }
1163
4f745708 1164 msg.dst_queue = dst_index;
beb73b26
JK
1165
1166 dev_dbg(ctx->dev, "src queue = %d dst queue =%d\n",
1167 msg.src_queue, msg.dst_queue);
1168
1169 msg.module_id = src_mcfg->id.module_id;
ef2a352c 1170 msg.instance_id = src_mcfg->id.pvt_id;
beb73b26 1171 msg.dst_module_id = dst_mcfg->id.module_id;
ef2a352c 1172 msg.dst_instance_id = dst_mcfg->id.pvt_id;
beb73b26
JK
1173 msg.bind = true;
1174
1175 ret = skl_ipc_bind_unbind(&ctx->ipc, &msg);
1176
1177 if (!ret) {
1178 src_mcfg->m_state = SKL_MODULE_BIND_DONE;
4f745708
JK
1179 src_mcfg->m_out_pin[src_index].pin_state = SKL_PIN_BIND_DONE;
1180 dst_mcfg->m_in_pin[dst_index].pin_state = SKL_PIN_BIND_DONE;
38a77085 1181 return ret;
beb73b26 1182 }
38a77085
PT
1183out:
1184 /* error case , if IPC fails, clear the queue index */
1185 skl_free_queue(src_mcfg->m_out_pin, src_index);
1186 skl_free_queue(dst_mcfg->m_in_pin, dst_index);
beb73b26
JK
1187
1188 return ret;
1189}
c9b1e834
JK
1190
1191static int skl_set_pipe_state(struct skl_sst *ctx, struct skl_pipe *pipe,
1192 enum skl_ipc_pipeline_state state)
1193{
1194 dev_dbg(ctx->dev, "%s: pipe_satate = %d\n", __func__, state);
1195
1196 return skl_ipc_set_pipeline_state(&ctx->ipc, pipe->ppl_id, state);
1197}
1198
1199/*
1200 * A pipeline is a collection of modules. Before a module in instantiated a
1201 * pipeline needs to be created for it.
1202 * This function creates pipeline, by sending create pipeline IPC messages
1203 * to FW
1204 */
1205int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe)
1206{
1207 int ret;
1208
1209 dev_dbg(ctx->dev, "%s: pipe_id = %d\n", __func__, pipe->ppl_id);
1210
1211 ret = skl_ipc_create_pipeline(&ctx->ipc, pipe->memory_pages,
8a0cb236
VK
1212 pipe->pipe_priority, pipe->ppl_id,
1213 pipe->lp_mode);
c9b1e834
JK
1214 if (ret < 0) {
1215 dev_err(ctx->dev, "Failed to create pipeline\n");
1216 return ret;
1217 }
1218
1219 pipe->state = SKL_PIPE_CREATED;
1220
1221 return 0;
1222}
1223
1224/*
1225 * A pipeline needs to be deleted on cleanup. If a pipeline is running, then
1226 * pause the pipeline first and then delete it
1227 * The pipe delete is done by sending delete pipeline IPC. DSP will stop the
1228 * DMA engines and releases resources
1229 */
1230int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
1231{
1232 int ret;
1233
1234 dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
1235
1ae7ca04 1236 /* If pipe is started, do stop the pipe in FW. */
6914968b 1237 if (pipe->state >= SKL_PIPE_STARTED) {
c9b1e834
JK
1238 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
1239 if (ret < 0) {
1240 dev_err(ctx->dev, "Failed to stop pipeline\n");
1241 return ret;
1242 }
1243
1244 pipe->state = SKL_PIPE_PAUSED;
1ae7ca04 1245 }
c9b1e834 1246
1ae7ca04
D
1247 /* If pipe was not created in FW, do not try to delete it */
1248 if (pipe->state < SKL_PIPE_CREATED)
1249 return 0;
d2c7db85 1250
1ae7ca04
D
1251 ret = skl_ipc_delete_pipeline(&ctx->ipc, pipe->ppl_id);
1252 if (ret < 0) {
1253 dev_err(ctx->dev, "Failed to delete pipeline\n");
1254 return ret;
c9b1e834
JK
1255 }
1256
1ae7ca04
D
1257 pipe->state = SKL_PIPE_INVALID;
1258
c9b1e834
JK
1259 return ret;
1260}
1261
1262/*
1263 * A pipeline is also a scheduling entity in DSP which can be run, stopped
1264 * For processing data the pipe need to be run by sending IPC set pipe state
1265 * to DSP
1266 */
1267int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
1268{
1269 int ret;
1270
1271 dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
1272
1273 /* If pipe was not created in FW, do not try to pause or delete */
1274 if (pipe->state < SKL_PIPE_CREATED)
1275 return 0;
1276
1277 /* Pipe has to be paused before it is started */
1278 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
1279 if (ret < 0) {
1280 dev_err(ctx->dev, "Failed to pause pipe\n");
1281 return ret;
1282 }
1283
1284 pipe->state = SKL_PIPE_PAUSED;
1285
1286 ret = skl_set_pipe_state(ctx, pipe, PPL_RUNNING);
1287 if (ret < 0) {
1288 dev_err(ctx->dev, "Failed to start pipe\n");
1289 return ret;
1290 }
1291
1292 pipe->state = SKL_PIPE_STARTED;
1293
1294 return 0;
1295}
1296
1297/*
1298 * Stop the pipeline by sending set pipe state IPC
1299 * DSP doesnt implement stop so we always send pause message
1300 */
1301int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
1302{
1303 int ret;
1304
1305 dev_dbg(ctx->dev, "In %s pipe=%d\n", __func__, pipe->ppl_id);
1306
1307 /* If pipe was not created in FW, do not try to pause or delete */
1308 if (pipe->state < SKL_PIPE_PAUSED)
1309 return 0;
1310
1311 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
1312 if (ret < 0) {
1313 dev_dbg(ctx->dev, "Failed to stop pipe\n");
1314 return ret;
1315 }
1316
353f72aa 1317 pipe->state = SKL_PIPE_PAUSED;
c9b1e834
JK
1318
1319 return 0;
1320}
9939a9c3 1321
2004432f
JK
1322/*
1323 * Reset the pipeline by sending set pipe state IPC this will reset the DMA
1324 * from the DSP side
1325 */
1326int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
1327{
1328 int ret;
1329
1330 /* If pipe was not created in FW, do not try to pause or delete */
1331 if (pipe->state < SKL_PIPE_PAUSED)
1332 return 0;
1333
1334 ret = skl_set_pipe_state(ctx, pipe, PPL_RESET);
1335 if (ret < 0) {
1336 dev_dbg(ctx->dev, "Failed to reset pipe ret=%d\n", ret);
1337 return ret;
1338 }
1339
1340 pipe->state = SKL_PIPE_RESET;
1341
1342 return 0;
1343}
1344
9939a9c3
JK
1345/* Algo parameter set helper function */
1346int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
1347 u32 param_id, struct skl_module_cfg *mcfg)
1348{
1349 struct skl_ipc_large_config_msg msg;
1350
1351 msg.module_id = mcfg->id.module_id;
ef2a352c 1352 msg.instance_id = mcfg->id.pvt_id;
9939a9c3
JK
1353 msg.param_data_size = size;
1354 msg.large_param_id = param_id;
1355
1356 return skl_ipc_set_large_config(&ctx->ipc, &msg, params);
1357}
7d9f2911
OA
1358
1359int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
1360 u32 param_id, struct skl_module_cfg *mcfg)
1361{
1362 struct skl_ipc_large_config_msg msg;
1363
1364 msg.module_id = mcfg->id.module_id;
ef2a352c 1365 msg.instance_id = mcfg->id.pvt_id;
7d9f2911
OA
1366 msg.param_data_size = size;
1367 msg.large_param_id = param_id;
1368
1369 return skl_ipc_get_large_config(&ctx->ipc, &msg, params);
1370}