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a40e693c JK |
1 | /* |
2 | * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality | |
3 | * | |
4 | * Copyright (C) 2014-2015 Intel Corp | |
5 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
6 | * | |
7 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/pci.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include "skl.h" | |
b663a8c5 | 27 | #include "skl-topology.h" |
721c3e36 D |
28 | #include "skl-sst-dsp.h" |
29 | #include "skl-sst-ipc.h" | |
a40e693c JK |
30 | |
31 | #define HDA_MONO 1 | |
32 | #define HDA_STEREO 2 | |
8f35bf3f | 33 | #define HDA_QUAD 4 |
a40e693c JK |
34 | |
35 | static struct snd_pcm_hardware azx_pcm_hw = { | |
36 | .info = (SNDRV_PCM_INFO_MMAP | | |
37 | SNDRV_PCM_INFO_INTERLEAVED | | |
38 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
39 | SNDRV_PCM_INFO_MMAP_VALID | | |
40 | SNDRV_PCM_INFO_PAUSE | | |
3637976b | 41 | SNDRV_PCM_INFO_RESUME | |
a40e693c JK |
42 | SNDRV_PCM_INFO_SYNC_START | |
43 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ | |
44 | SNDRV_PCM_INFO_HAS_LINK_ATIME | | |
45 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), | |
06b23d93 JK |
46 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
47 | SNDRV_PCM_FMTBIT_S32_LE | | |
48 | SNDRV_PCM_FMTBIT_S24_LE, | |
49 | .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | | |
50 | SNDRV_PCM_RATE_8000, | |
51 | .rate_min = 8000, | |
a40e693c | 52 | .rate_max = 48000, |
8f35bf3f | 53 | .channels_min = 1, |
7e12dc87 | 54 | .channels_max = 8, |
a40e693c JK |
55 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, |
56 | .period_bytes_min = 128, | |
57 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
58 | .periods_min = 2, | |
59 | .periods_max = AZX_MAX_FRAG, | |
60 | .fifo_size = 0, | |
61 | }; | |
62 | ||
63 | static inline | |
64 | struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream) | |
65 | { | |
66 | return substream->runtime->private_data; | |
67 | } | |
68 | ||
69 | static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream) | |
70 | { | |
71 | struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); | |
72 | struct hdac_stream *hstream = hdac_stream(stream); | |
73 | struct hdac_bus *bus = hstream->bus; | |
74 | ||
75 | return hbus_to_ebus(bus); | |
76 | } | |
77 | ||
78 | static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus, | |
79 | struct snd_pcm_substream *substream, | |
80 | size_t size) | |
81 | { | |
82 | struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); | |
83 | ||
84 | hdac_stream(stream)->bufsize = 0; | |
85 | hdac_stream(stream)->period_bytes = 0; | |
86 | hdac_stream(stream)->format_val = 0; | |
87 | ||
88 | return snd_pcm_lib_malloc_pages(substream, size); | |
89 | } | |
90 | ||
91 | static int skl_substream_free_pages(struct hdac_bus *bus, | |
92 | struct snd_pcm_substream *substream) | |
93 | { | |
94 | return snd_pcm_lib_free_pages(substream); | |
95 | } | |
96 | ||
97 | static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus, | |
98 | struct snd_pcm_runtime *runtime) | |
99 | { | |
100 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
101 | ||
102 | /* avoid wrap-around with wall-clock */ | |
103 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, | |
104 | 20, 178000000); | |
105 | } | |
106 | ||
05057001 JK |
107 | static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus) |
108 | { | |
ec8ae570 | 109 | if ((ebus_to_hbus(ebus))->ppcap) |
05057001 JK |
110 | return HDAC_EXT_STREAM_TYPE_HOST; |
111 | else | |
112 | return HDAC_EXT_STREAM_TYPE_COUPLED; | |
113 | } | |
114 | ||
4557c305 JK |
115 | /* |
116 | * check if the stream opened is marked as ignore_suspend by machine, if so | |
117 | * then enable suspend_active refcount | |
118 | * | |
119 | * The count supend_active does not need lock as it is used in open/close | |
120 | * and suspend context | |
121 | */ | |
122 | static void skl_set_suspend_active(struct snd_pcm_substream *substream, | |
123 | struct snd_soc_dai *dai, bool enable) | |
124 | { | |
125 | struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); | |
126 | struct snd_soc_dapm_widget *w; | |
127 | struct skl *skl = ebus_to_skl(ebus); | |
128 | ||
129 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
130 | w = dai->playback_widget; | |
131 | else | |
132 | w = dai->capture_widget; | |
133 | ||
134 | if (w->ignore_suspend && enable) | |
135 | skl->supend_active++; | |
136 | else if (w->ignore_suspend && !enable) | |
137 | skl->supend_active--; | |
138 | } | |
139 | ||
ad036bde JK |
140 | int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params) |
141 | { | |
142 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); | |
143 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
144 | unsigned int format_val; | |
145 | struct hdac_stream *hstream; | |
146 | struct hdac_ext_stream *stream; | |
147 | int err; | |
148 | ||
149 | hstream = snd_hdac_get_stream(bus, params->stream, | |
150 | params->host_dma_id + 1); | |
151 | if (!hstream) | |
152 | return -EINVAL; | |
153 | ||
154 | stream = stream_to_hdac_ext_stream(hstream); | |
155 | snd_hdac_ext_stream_decouple(ebus, stream, true); | |
156 | ||
157 | format_val = snd_hdac_calc_stream_format(params->s_freq, | |
7f975a38 | 158 | params->ch, params->format, params->host_bps, 0); |
ad036bde JK |
159 | |
160 | dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", | |
161 | format_val, params->s_freq, params->ch, params->format); | |
162 | ||
163 | snd_hdac_stream_reset(hdac_stream(stream)); | |
164 | err = snd_hdac_stream_set_params(hdac_stream(stream), format_val); | |
165 | if (err < 0) | |
166 | return err; | |
167 | ||
168 | err = snd_hdac_stream_setup(hdac_stream(stream)); | |
169 | if (err < 0) | |
170 | return err; | |
171 | ||
172 | hdac_stream(stream)->prepared = 1; | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params) | |
178 | { | |
179 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); | |
180 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
181 | unsigned int format_val; | |
182 | struct hdac_stream *hstream; | |
183 | struct hdac_ext_stream *stream; | |
184 | struct hdac_ext_link *link; | |
185 | ||
186 | hstream = snd_hdac_get_stream(bus, params->stream, | |
187 | params->link_dma_id + 1); | |
188 | if (!hstream) | |
189 | return -EINVAL; | |
190 | ||
191 | stream = stream_to_hdac_ext_stream(hstream); | |
192 | snd_hdac_ext_stream_decouple(ebus, stream, true); | |
7f975a38 JK |
193 | format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch, |
194 | params->format, params->link_bps, 0); | |
ad036bde JK |
195 | |
196 | dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", | |
197 | format_val, params->s_freq, params->ch, params->format); | |
198 | ||
199 | snd_hdac_ext_link_stream_reset(stream); | |
200 | ||
201 | snd_hdac_ext_link_stream_setup(stream, format_val); | |
202 | ||
203 | list_for_each_entry(link, &ebus->hlink_list, list) { | |
204 | if (link->index == params->link_index) | |
205 | snd_hdac_ext_link_set_stream_id(link, | |
206 | hstream->stream_tag); | |
207 | } | |
208 | ||
209 | stream->link_prepared = 1; | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
a40e693c JK |
214 | static int skl_pcm_open(struct snd_pcm_substream *substream, |
215 | struct snd_soc_dai *dai) | |
216 | { | |
217 | struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); | |
218 | struct hdac_ext_stream *stream; | |
219 | struct snd_pcm_runtime *runtime = substream->runtime; | |
220 | struct skl_dma_params *dma_params; | |
a83e3b4c VK |
221 | struct skl *skl = get_skl_ctx(dai->dev); |
222 | struct skl_module_cfg *mconfig; | |
a40e693c JK |
223 | |
224 | dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); | |
a40e693c JK |
225 | |
226 | stream = snd_hdac_ext_stream_assign(ebus, substream, | |
05057001 | 227 | skl_get_host_stream_type(ebus)); |
a40e693c JK |
228 | if (stream == NULL) |
229 | return -EBUSY; | |
230 | ||
231 | skl_set_pcm_constrains(ebus, runtime); | |
232 | ||
233 | /* | |
234 | * disable WALLCLOCK timestamps for capture streams | |
235 | * until we figure out how to handle digital inputs | |
236 | */ | |
237 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { | |
238 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ | |
239 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; | |
240 | } | |
241 | ||
242 | runtime->private_data = stream; | |
243 | ||
244 | dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL); | |
245 | if (!dma_params) | |
246 | return -ENOMEM; | |
247 | ||
248 | dma_params->stream_tag = hdac_stream(stream)->stream_tag; | |
249 | snd_soc_dai_set_dma_data(dai, substream, dma_params); | |
250 | ||
251 | dev_dbg(dai->dev, "stream tag set in dma params=%d\n", | |
252 | dma_params->stream_tag); | |
4557c305 | 253 | skl_set_suspend_active(substream, dai, true); |
a40e693c JK |
254 | snd_pcm_set_sync(substream); |
255 | ||
a83e3b4c | 256 | mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); |
91ce5497 K |
257 | if (!mconfig) |
258 | return -EINVAL; | |
259 | ||
a83e3b4c VK |
260 | skl_tplg_d0i3_get(skl, mconfig->d0i3_caps); |
261 | ||
a40e693c JK |
262 | return 0; |
263 | } | |
264 | ||
a40e693c JK |
265 | static int skl_pcm_prepare(struct snd_pcm_substream *substream, |
266 | struct snd_soc_dai *dai) | |
267 | { | |
2004432f | 268 | struct skl *skl = get_skl_ctx(dai->dev); |
2004432f | 269 | struct skl_module_cfg *mconfig; |
a40e693c JK |
270 | |
271 | dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); | |
a40e693c | 272 | |
2004432f JK |
273 | mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); |
274 | ||
2004432f JK |
275 | /* In case of XRUN recovery, reset the FW pipe to clean state */ |
276 | if (mconfig && (substream->runtime->status->state == | |
277 | SNDRV_PCM_STATE_XRUN)) | |
278 | skl_reset_pipe(skl->skl_sst, mconfig->pipe); | |
279 | ||
bb704a73 | 280 | return 0; |
a40e693c JK |
281 | } |
282 | ||
283 | static int skl_pcm_hw_params(struct snd_pcm_substream *substream, | |
284 | struct snd_pcm_hw_params *params, | |
285 | struct snd_soc_dai *dai) | |
286 | { | |
287 | struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); | |
05057001 | 288 | struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); |
a40e693c | 289 | struct snd_pcm_runtime *runtime = substream->runtime; |
b663a8c5 JK |
290 | struct skl_pipe_params p_params = {0}; |
291 | struct skl_module_cfg *m_cfg; | |
05057001 | 292 | int ret, dma_id; |
a40e693c JK |
293 | |
294 | dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); | |
295 | ret = skl_substream_alloc_pages(ebus, substream, | |
296 | params_buffer_bytes(params)); | |
297 | if (ret < 0) | |
298 | return ret; | |
299 | ||
300 | dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n", | |
301 | runtime->rate, runtime->channels, runtime->format); | |
302 | ||
05057001 JK |
303 | dma_id = hdac_stream(stream)->stream_tag - 1; |
304 | dev_dbg(dai->dev, "dma_id=%d\n", dma_id); | |
305 | ||
b663a8c5 JK |
306 | p_params.s_fmt = snd_pcm_format_width(params_format(params)); |
307 | p_params.ch = params_channels(params); | |
308 | p_params.s_freq = params_rate(params); | |
309 | p_params.host_dma_id = dma_id; | |
310 | p_params.stream = substream->stream; | |
12c3be0e | 311 | p_params.format = params_format(params); |
7f975a38 JK |
312 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
313 | p_params.host_bps = dai->driver->playback.sig_bits; | |
314 | else | |
315 | p_params.host_bps = dai->driver->capture.sig_bits; | |
316 | ||
b663a8c5 JK |
317 | |
318 | m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream); | |
319 | if (m_cfg) | |
320 | skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params); | |
321 | ||
a40e693c JK |
322 | return 0; |
323 | } | |
324 | ||
325 | static void skl_pcm_close(struct snd_pcm_substream *substream, | |
326 | struct snd_soc_dai *dai) | |
327 | { | |
328 | struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); | |
05057001 | 329 | struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); |
a40e693c | 330 | struct skl_dma_params *dma_params = NULL; |
721c3e36 | 331 | struct skl *skl = ebus_to_skl(ebus); |
a83e3b4c | 332 | struct skl_module_cfg *mconfig; |
a40e693c JK |
333 | |
334 | dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); | |
05057001 JK |
335 | |
336 | snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus)); | |
a40e693c JK |
337 | |
338 | dma_params = snd_soc_dai_get_dma_data(dai, substream); | |
339 | /* | |
340 | * now we should set this to NULL as we are freeing by the | |
341 | * dma_params | |
342 | */ | |
343 | snd_soc_dai_set_dma_data(dai, substream, NULL); | |
4557c305 | 344 | skl_set_suspend_active(substream, dai, false); |
a40e693c | 345 | |
721c3e36 D |
346 | /* |
347 | * check if close is for "Reference Pin" and set back the | |
348 | * CGCTL.MISCBDCGE if disabled by driver | |
349 | */ | |
350 | if (!strncmp(dai->name, "Reference Pin", 13) && | |
351 | skl->skl_sst->miscbdcg_disabled) { | |
352 | skl->skl_sst->enable_miscbdcge(dai->dev, true); | |
353 | skl->skl_sst->miscbdcg_disabled = false; | |
354 | } | |
355 | ||
a83e3b4c VK |
356 | mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); |
357 | skl_tplg_d0i3_put(skl, mconfig->d0i3_caps); | |
358 | ||
a40e693c JK |
359 | kfree(dma_params); |
360 | } | |
361 | ||
362 | static int skl_pcm_hw_free(struct snd_pcm_substream *substream, | |
363 | struct snd_soc_dai *dai) | |
364 | { | |
365 | struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); | |
366 | struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); | |
367 | ||
368 | dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); | |
369 | ||
370 | snd_hdac_stream_cleanup(hdac_stream(stream)); | |
371 | hdac_stream(stream)->prepared = 0; | |
372 | ||
373 | return skl_substream_free_pages(ebus_to_hbus(ebus), substream); | |
374 | } | |
375 | ||
b663a8c5 JK |
376 | static int skl_be_hw_params(struct snd_pcm_substream *substream, |
377 | struct snd_pcm_hw_params *params, | |
378 | struct snd_soc_dai *dai) | |
379 | { | |
380 | struct skl_pipe_params p_params = {0}; | |
381 | ||
382 | p_params.s_fmt = snd_pcm_format_width(params_format(params)); | |
383 | p_params.ch = params_channels(params); | |
384 | p_params.s_freq = params_rate(params); | |
385 | p_params.stream = substream->stream; | |
b663a8c5 | 386 | |
4bd073f9 | 387 | return skl_tplg_be_update_params(dai, &p_params); |
b663a8c5 JK |
388 | } |
389 | ||
d1730c3d JK |
390 | static int skl_decoupled_trigger(struct snd_pcm_substream *substream, |
391 | int cmd) | |
392 | { | |
393 | struct hdac_ext_bus *ebus = get_bus_ctx(substream); | |
394 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
395 | struct hdac_ext_stream *stream; | |
396 | int start; | |
397 | unsigned long cookie; | |
398 | struct hdac_stream *hstr; | |
399 | ||
400 | stream = get_hdac_ext_stream(substream); | |
401 | hstr = hdac_stream(stream); | |
402 | ||
403 | if (!hstr->prepared) | |
404 | return -EPIPE; | |
405 | ||
406 | switch (cmd) { | |
407 | case SNDRV_PCM_TRIGGER_START: | |
408 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
409 | case SNDRV_PCM_TRIGGER_RESUME: | |
410 | start = 1; | |
411 | break; | |
412 | ||
413 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
414 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
415 | case SNDRV_PCM_TRIGGER_STOP: | |
416 | start = 0; | |
417 | break; | |
418 | ||
419 | default: | |
420 | return -EINVAL; | |
421 | } | |
422 | ||
423 | spin_lock_irqsave(&bus->reg_lock, cookie); | |
424 | ||
425 | if (start) { | |
426 | snd_hdac_stream_start(hdac_stream(stream), true); | |
427 | snd_hdac_stream_timecounter_init(hstr, 0); | |
428 | } else { | |
429 | snd_hdac_stream_stop(hdac_stream(stream)); | |
430 | } | |
431 | ||
432 | spin_unlock_irqrestore(&bus->reg_lock, cookie); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
b663a8c5 JK |
437 | static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd, |
438 | struct snd_soc_dai *dai) | |
439 | { | |
440 | struct skl *skl = get_skl_ctx(dai->dev); | |
441 | struct skl_sst *ctx = skl->skl_sst; | |
442 | struct skl_module_cfg *mconfig; | |
7e3a17d3 JK |
443 | struct hdac_ext_bus *ebus = get_bus_ctx(substream); |
444 | struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); | |
9a655db0 | 445 | struct snd_soc_dapm_widget *w; |
d1730c3d | 446 | int ret; |
b663a8c5 JK |
447 | |
448 | mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); | |
449 | if (!mconfig) | |
450 | return -EIO; | |
451 | ||
9a655db0 JK |
452 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
453 | w = dai->playback_widget; | |
454 | else | |
455 | w = dai->capture_widget; | |
456 | ||
b663a8c5 | 457 | switch (cmd) { |
7e3a17d3 | 458 | case SNDRV_PCM_TRIGGER_RESUME: |
9a655db0 | 459 | if (!w->ignore_suspend) { |
9a655db0 JK |
460 | /* |
461 | * enable DMA Resume enable bit for the stream, set the | |
462 | * dpib & lpib position to resume before starting the | |
463 | * DMA | |
464 | */ | |
465 | snd_hdac_ext_stream_drsm_enable(ebus, true, | |
466 | hdac_stream(stream)->index); | |
467 | snd_hdac_ext_stream_set_dpibr(ebus, stream, | |
a700a1e6 | 468 | stream->lpib); |
9a655db0 JK |
469 | snd_hdac_ext_stream_set_lpib(stream, stream->lpib); |
470 | } | |
748a1d5a | 471 | |
d1730c3d | 472 | case SNDRV_PCM_TRIGGER_START: |
b663a8c5 | 473 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
d1730c3d JK |
474 | /* |
475 | * Start HOST DMA and Start FE Pipe.This is to make sure that | |
476 | * there are no underrun/overrun in the case when the FE | |
477 | * pipeline is started but there is a delay in starting the | |
478 | * DMA channel on the host. | |
479 | */ | |
480 | ret = skl_decoupled_trigger(substream, cmd); | |
481 | if (ret < 0) | |
482 | return ret; | |
b663a8c5 | 483 | return skl_run_pipe(ctx, mconfig->pipe); |
d1730c3d | 484 | break; |
b663a8c5 JK |
485 | |
486 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
487 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
d1730c3d JK |
488 | case SNDRV_PCM_TRIGGER_STOP: |
489 | /* | |
490 | * Stop FE Pipe first and stop DMA. This is to make sure that | |
491 | * there are no underrun/overrun in the case if there is a delay | |
492 | * between the two operations. | |
493 | */ | |
494 | ret = skl_stop_pipe(ctx, mconfig->pipe); | |
495 | if (ret < 0) | |
496 | return ret; | |
497 | ||
498 | ret = skl_decoupled_trigger(substream, cmd); | |
9a655db0 | 499 | if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) { |
748a1d5a JK |
500 | /* save the dpib and lpib positions */ |
501 | stream->dpib = readl(ebus->bus.remap_addr + | |
502 | AZX_REG_VS_SDXDPIB_XBASE + | |
503 | (AZX_REG_VS_SDXDPIB_XINTERVAL * | |
504 | hdac_stream(stream)->index)); | |
505 | ||
506 | stream->lpib = snd_hdac_stream_get_pos_lpib( | |
507 | hdac_stream(stream)); | |
7e3a17d3 | 508 | snd_hdac_ext_stream_decouple(ebus, stream, false); |
748a1d5a | 509 | } |
d1730c3d | 510 | break; |
b663a8c5 JK |
511 | |
512 | default: | |
d1730c3d | 513 | return -EINVAL; |
b663a8c5 | 514 | } |
d1730c3d JK |
515 | |
516 | return 0; | |
b663a8c5 JK |
517 | } |
518 | ||
05057001 JK |
519 | static int skl_link_hw_params(struct snd_pcm_substream *substream, |
520 | struct snd_pcm_hw_params *params, | |
521 | struct snd_soc_dai *dai) | |
522 | { | |
523 | struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); | |
524 | struct hdac_ext_stream *link_dev; | |
525 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); | |
05057001 | 526 | struct snd_soc_dai *codec_dai = rtd->codec_dai; |
b663a8c5 | 527 | struct skl_pipe_params p_params = {0}; |
12c3be0e | 528 | struct hdac_ext_link *link; |
1011509d | 529 | int stream_tag; |
05057001 | 530 | |
05057001 JK |
531 | link_dev = snd_hdac_ext_stream_assign(ebus, substream, |
532 | HDAC_EXT_STREAM_TYPE_LINK); | |
533 | if (!link_dev) | |
534 | return -EBUSY; | |
535 | ||
536 | snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev); | |
537 | ||
12c3be0e JK |
538 | link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name); |
539 | if (!link) | |
540 | return -EINVAL; | |
541 | ||
1011509d JK |
542 | stream_tag = hdac_stream(link_dev)->stream_tag; |
543 | ||
05057001 | 544 | /* set the stream tag in the codec dai dma params */ |
1011509d | 545 | snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0); |
b663a8c5 JK |
546 | |
547 | p_params.s_fmt = snd_pcm_format_width(params_format(params)); | |
548 | p_params.ch = params_channels(params); | |
549 | p_params.s_freq = params_rate(params); | |
550 | p_params.stream = substream->stream; | |
1011509d | 551 | p_params.link_dma_id = stream_tag - 1; |
12c3be0e JK |
552 | p_params.link_index = link->index; |
553 | p_params.format = params_format(params); | |
b663a8c5 | 554 | |
7f975a38 JK |
555 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
556 | p_params.link_bps = codec_dai->driver->playback.sig_bits; | |
557 | else | |
558 | p_params.link_bps = codec_dai->driver->capture.sig_bits; | |
559 | ||
4bd073f9 | 560 | return skl_tplg_be_update_params(dai, &p_params); |
05057001 JK |
561 | } |
562 | ||
563 | static int skl_link_pcm_prepare(struct snd_pcm_substream *substream, | |
564 | struct snd_soc_dai *dai) | |
565 | { | |
2004432f JK |
566 | struct skl *skl = get_skl_ctx(dai->dev); |
567 | struct skl_module_cfg *mconfig = NULL; | |
05057001 | 568 | |
2004432f JK |
569 | /* In case of XRUN recovery, reset the FW pipe to clean state */ |
570 | mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); | |
7cbfdf87 JK |
571 | if (mconfig && !mconfig->pipe->passthru && |
572 | (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN)) | |
2004432f JK |
573 | skl_reset_pipe(skl->skl_sst, mconfig->pipe); |
574 | ||
05057001 JK |
575 | return 0; |
576 | } | |
577 | ||
578 | static int skl_link_pcm_trigger(struct snd_pcm_substream *substream, | |
579 | int cmd, struct snd_soc_dai *dai) | |
580 | { | |
581 | struct hdac_ext_stream *link_dev = | |
582 | snd_soc_dai_get_dma_data(dai, substream); | |
920982c9 JK |
583 | struct hdac_ext_bus *ebus = get_bus_ctx(substream); |
584 | struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); | |
05057001 JK |
585 | |
586 | dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd); | |
587 | switch (cmd) { | |
920982c9 | 588 | case SNDRV_PCM_TRIGGER_RESUME: |
05057001 JK |
589 | case SNDRV_PCM_TRIGGER_START: |
590 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
05057001 JK |
591 | snd_hdac_ext_link_stream_start(link_dev); |
592 | break; | |
593 | ||
594 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
595 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
596 | case SNDRV_PCM_TRIGGER_STOP: | |
597 | snd_hdac_ext_link_stream_clear(link_dev); | |
920982c9 JK |
598 | if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) |
599 | snd_hdac_ext_stream_decouple(ebus, stream, false); | |
05057001 JK |
600 | break; |
601 | ||
602 | default: | |
603 | return -EINVAL; | |
604 | } | |
605 | return 0; | |
606 | } | |
607 | ||
608 | static int skl_link_hw_free(struct snd_pcm_substream *substream, | |
609 | struct snd_soc_dai *dai) | |
610 | { | |
611 | struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); | |
612 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); | |
613 | struct hdac_ext_stream *link_dev = | |
614 | snd_soc_dai_get_dma_data(dai, substream); | |
615 | struct hdac_ext_link *link; | |
616 | ||
617 | dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); | |
618 | ||
619 | link_dev->link_prepared = 0; | |
620 | ||
621 | link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name); | |
622 | if (!link) | |
623 | return -EINVAL; | |
624 | ||
625 | snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag); | |
626 | snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK); | |
627 | return 0; | |
628 | } | |
629 | ||
a40e693c JK |
630 | static struct snd_soc_dai_ops skl_pcm_dai_ops = { |
631 | .startup = skl_pcm_open, | |
632 | .shutdown = skl_pcm_close, | |
633 | .prepare = skl_pcm_prepare, | |
634 | .hw_params = skl_pcm_hw_params, | |
635 | .hw_free = skl_pcm_hw_free, | |
b663a8c5 | 636 | .trigger = skl_pcm_trigger, |
a40e693c JK |
637 | }; |
638 | ||
05057001 | 639 | static struct snd_soc_dai_ops skl_dmic_dai_ops = { |
b663a8c5 | 640 | .hw_params = skl_be_hw_params, |
b663a8c5 JK |
641 | }; |
642 | ||
643 | static struct snd_soc_dai_ops skl_be_ssp_dai_ops = { | |
b663a8c5 | 644 | .hw_params = skl_be_hw_params, |
05057001 JK |
645 | }; |
646 | ||
647 | static struct snd_soc_dai_ops skl_link_dai_ops = { | |
05057001 JK |
648 | .prepare = skl_link_pcm_prepare, |
649 | .hw_params = skl_link_hw_params, | |
650 | .hw_free = skl_link_hw_free, | |
651 | .trigger = skl_link_pcm_trigger, | |
05057001 JK |
652 | }; |
653 | ||
a40e693c JK |
654 | static struct snd_soc_dai_driver skl_platform_dai[] = { |
655 | { | |
656 | .name = "System Pin", | |
657 | .ops = &skl_pcm_dai_ops, | |
658 | .playback = { | |
659 | .stream_name = "System Playback", | |
660 | .channels_min = HDA_MONO, | |
661 | .channels_max = HDA_STEREO, | |
662 | .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000, | |
dde53bcc SK |
663 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
664 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
7f975a38 | 665 | .sig_bits = 32, |
a40e693c JK |
666 | }, |
667 | .capture = { | |
668 | .stream_name = "System Capture", | |
669 | .channels_min = HDA_MONO, | |
670 | .channels_max = HDA_STEREO, | |
671 | .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, | |
672 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, | |
7f975a38 | 673 | .sig_bits = 32, |
a40e693c JK |
674 | }, |
675 | }, | |
05057001 JK |
676 | { |
677 | .name = "Reference Pin", | |
678 | .ops = &skl_pcm_dai_ops, | |
679 | .capture = { | |
680 | .stream_name = "Reference Capture", | |
681 | .channels_min = HDA_MONO, | |
8f35bf3f | 682 | .channels_max = HDA_QUAD, |
05057001 JK |
683 | .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, |
684 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, | |
7f975a38 | 685 | .sig_bits = 32, |
05057001 JK |
686 | }, |
687 | }, | |
a40e693c JK |
688 | { |
689 | .name = "Deepbuffer Pin", | |
690 | .ops = &skl_pcm_dai_ops, | |
691 | .playback = { | |
692 | .stream_name = "Deepbuffer Playback", | |
693 | .channels_min = HDA_STEREO, | |
694 | .channels_max = HDA_STEREO, | |
695 | .rates = SNDRV_PCM_RATE_48000, | |
696 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, | |
7f975a38 | 697 | .sig_bits = 32, |
a40e693c JK |
698 | }, |
699 | }, | |
700 | { | |
701 | .name = "LowLatency Pin", | |
702 | .ops = &skl_pcm_dai_ops, | |
703 | .playback = { | |
704 | .stream_name = "Low Latency Playback", | |
705 | .channels_min = HDA_STEREO, | |
706 | .channels_max = HDA_STEREO, | |
707 | .rates = SNDRV_PCM_RATE_48000, | |
708 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, | |
7f975a38 | 709 | .sig_bits = 32, |
a40e693c JK |
710 | }, |
711 | }, | |
8f35bf3f JK |
712 | { |
713 | .name = "DMIC Pin", | |
714 | .ops = &skl_pcm_dai_ops, | |
715 | .capture = { | |
716 | .stream_name = "DMIC Capture", | |
717 | .channels_min = HDA_MONO, | |
718 | .channels_max = HDA_QUAD, | |
719 | .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, | |
720 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, | |
7f975a38 | 721 | .sig_bits = 32, |
8f35bf3f JK |
722 | }, |
723 | }, | |
8cca87c0 SP |
724 | { |
725 | .name = "HDMI1 Pin", | |
726 | .ops = &skl_pcm_dai_ops, | |
727 | .playback = { | |
728 | .stream_name = "HDMI1 Playback", | |
729 | .channels_min = HDA_STEREO, | |
7e12dc87 | 730 | .channels_max = 8, |
8cca87c0 SP |
731 | .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | |
732 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | | |
733 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | | |
734 | SNDRV_PCM_RATE_192000, | |
735 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | | |
736 | SNDRV_PCM_FMTBIT_S32_LE, | |
7f975a38 | 737 | .sig_bits = 32, |
8cca87c0 SP |
738 | }, |
739 | }, | |
740 | { | |
741 | .name = "HDMI2 Pin", | |
742 | .ops = &skl_pcm_dai_ops, | |
743 | .playback = { | |
744 | .stream_name = "HDMI2 Playback", | |
745 | .channels_min = HDA_STEREO, | |
7e12dc87 | 746 | .channels_max = 8, |
8cca87c0 SP |
747 | .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | |
748 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | | |
749 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | | |
750 | SNDRV_PCM_RATE_192000, | |
751 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | | |
752 | SNDRV_PCM_FMTBIT_S32_LE, | |
7f975a38 | 753 | .sig_bits = 32, |
8cca87c0 SP |
754 | }, |
755 | }, | |
756 | { | |
757 | .name = "HDMI3 Pin", | |
758 | .ops = &skl_pcm_dai_ops, | |
759 | .playback = { | |
760 | .stream_name = "HDMI3 Playback", | |
761 | .channels_min = HDA_STEREO, | |
7e12dc87 | 762 | .channels_max = 8, |
8cca87c0 SP |
763 | .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | |
764 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | | |
765 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | | |
766 | SNDRV_PCM_RATE_192000, | |
767 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | | |
768 | SNDRV_PCM_FMTBIT_S32_LE, | |
7f975a38 | 769 | .sig_bits = 32, |
8cca87c0 SP |
770 | }, |
771 | }, | |
8f35bf3f | 772 | |
05057001 | 773 | /* BE CPU Dais */ |
b663a8c5 JK |
774 | { |
775 | .name = "SSP0 Pin", | |
776 | .ops = &skl_be_ssp_dai_ops, | |
777 | .playback = { | |
778 | .stream_name = "ssp0 Tx", | |
779 | .channels_min = HDA_STEREO, | |
780 | .channels_max = HDA_STEREO, | |
781 | .rates = SNDRV_PCM_RATE_48000, | |
782 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
783 | }, | |
784 | .capture = { | |
785 | .stream_name = "ssp0 Rx", | |
786 | .channels_min = HDA_STEREO, | |
787 | .channels_max = HDA_STEREO, | |
788 | .rates = SNDRV_PCM_RATE_48000, | |
789 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
790 | }, | |
791 | }, | |
c80fd4da JK |
792 | { |
793 | .name = "SSP1 Pin", | |
794 | .ops = &skl_be_ssp_dai_ops, | |
795 | .playback = { | |
796 | .stream_name = "ssp1 Tx", | |
797 | .channels_min = HDA_STEREO, | |
798 | .channels_max = HDA_STEREO, | |
799 | .rates = SNDRV_PCM_RATE_48000, | |
800 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
801 | }, | |
802 | .capture = { | |
803 | .stream_name = "ssp1 Rx", | |
804 | .channels_min = HDA_STEREO, | |
805 | .channels_max = HDA_STEREO, | |
806 | .rates = SNDRV_PCM_RATE_48000, | |
807 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
808 | }, | |
809 | }, | |
fcc494af PS |
810 | { |
811 | .name = "SSP2 Pin", | |
812 | .ops = &skl_be_ssp_dai_ops, | |
813 | .playback = { | |
814 | .stream_name = "ssp2 Tx", | |
815 | .channels_min = HDA_STEREO, | |
816 | .channels_max = HDA_STEREO, | |
817 | .rates = SNDRV_PCM_RATE_48000, | |
818 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
819 | }, | |
820 | .capture = { | |
821 | .stream_name = "ssp2 Rx", | |
822 | .channels_min = HDA_STEREO, | |
823 | .channels_max = HDA_STEREO, | |
824 | .rates = SNDRV_PCM_RATE_48000, | |
825 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
826 | }, | |
827 | }, | |
828 | { | |
829 | .name = "SSP3 Pin", | |
830 | .ops = &skl_be_ssp_dai_ops, | |
831 | .playback = { | |
832 | .stream_name = "ssp3 Tx", | |
833 | .channels_min = HDA_STEREO, | |
834 | .channels_max = HDA_STEREO, | |
835 | .rates = SNDRV_PCM_RATE_48000, | |
836 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
837 | }, | |
838 | .capture = { | |
839 | .stream_name = "ssp3 Rx", | |
840 | .channels_min = HDA_STEREO, | |
841 | .channels_max = HDA_STEREO, | |
842 | .rates = SNDRV_PCM_RATE_48000, | |
843 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
844 | }, | |
845 | }, | |
846 | { | |
847 | .name = "SSP4 Pin", | |
848 | .ops = &skl_be_ssp_dai_ops, | |
849 | .playback = { | |
850 | .stream_name = "ssp4 Tx", | |
851 | .channels_min = HDA_STEREO, | |
852 | .channels_max = HDA_STEREO, | |
853 | .rates = SNDRV_PCM_RATE_48000, | |
854 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
855 | }, | |
856 | .capture = { | |
857 | .stream_name = "ssp4 Rx", | |
858 | .channels_min = HDA_STEREO, | |
859 | .channels_max = HDA_STEREO, | |
860 | .rates = SNDRV_PCM_RATE_48000, | |
861 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
862 | }, | |
863 | }, | |
864 | { | |
865 | .name = "SSP5 Pin", | |
866 | .ops = &skl_be_ssp_dai_ops, | |
867 | .playback = { | |
868 | .stream_name = "ssp5 Tx", | |
869 | .channels_min = HDA_STEREO, | |
870 | .channels_max = HDA_STEREO, | |
871 | .rates = SNDRV_PCM_RATE_48000, | |
872 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
873 | }, | |
874 | .capture = { | |
875 | .stream_name = "ssp5 Rx", | |
876 | .channels_min = HDA_STEREO, | |
877 | .channels_max = HDA_STEREO, | |
878 | .rates = SNDRV_PCM_RATE_48000, | |
879 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
880 | }, | |
881 | }, | |
05057001 | 882 | { |
8cca87c0 | 883 | .name = "iDisp1 Pin", |
05057001 JK |
884 | .ops = &skl_link_dai_ops, |
885 | .playback = { | |
8cca87c0 | 886 | .stream_name = "iDisp1 Tx", |
05057001 | 887 | .channels_min = HDA_STEREO, |
7e12dc87 | 888 | .channels_max = 8, |
05057001 | 889 | .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000, |
8cca87c0 SP |
890 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | |
891 | SNDRV_PCM_FMTBIT_S24_LE, | |
892 | }, | |
893 | }, | |
894 | { | |
895 | .name = "iDisp2 Pin", | |
896 | .ops = &skl_link_dai_ops, | |
897 | .playback = { | |
898 | .stream_name = "iDisp2 Tx", | |
899 | .channels_min = HDA_STEREO, | |
7e12dc87 | 900 | .channels_max = 8, |
8cca87c0 SP |
901 | .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| |
902 | SNDRV_PCM_RATE_48000, | |
903 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | | |
904 | SNDRV_PCM_FMTBIT_S24_LE, | |
905 | }, | |
906 | }, | |
907 | { | |
908 | .name = "iDisp3 Pin", | |
909 | .ops = &skl_link_dai_ops, | |
910 | .playback = { | |
911 | .stream_name = "iDisp3 Tx", | |
912 | .channels_min = HDA_STEREO, | |
7e12dc87 | 913 | .channels_max = 8, |
8cca87c0 SP |
914 | .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| |
915 | SNDRV_PCM_RATE_48000, | |
916 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | | |
917 | SNDRV_PCM_FMTBIT_S24_LE, | |
05057001 JK |
918 | }, |
919 | }, | |
920 | { | |
921 | .name = "DMIC01 Pin", | |
922 | .ops = &skl_dmic_dai_ops, | |
923 | .capture = { | |
924 | .stream_name = "DMIC01 Rx", | |
8f35bf3f JK |
925 | .channels_min = HDA_MONO, |
926 | .channels_max = HDA_QUAD, | |
05057001 JK |
927 | .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, |
928 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, | |
929 | }, | |
930 | }, | |
05057001 JK |
931 | { |
932 | .name = "HD-Codec Pin", | |
933 | .ops = &skl_link_dai_ops, | |
934 | .playback = { | |
935 | .stream_name = "HD-Codec Tx", | |
936 | .channels_min = HDA_STEREO, | |
937 | .channels_max = HDA_STEREO, | |
938 | .rates = SNDRV_PCM_RATE_48000, | |
939 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
940 | }, | |
941 | .capture = { | |
942 | .stream_name = "HD-Codec Rx", | |
943 | .channels_min = HDA_STEREO, | |
944 | .channels_max = HDA_STEREO, | |
945 | .rates = SNDRV_PCM_RATE_48000, | |
946 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
947 | }, | |
948 | }, | |
a40e693c JK |
949 | }; |
950 | ||
951 | static int skl_platform_open(struct snd_pcm_substream *substream) | |
952 | { | |
953 | struct snd_pcm_runtime *runtime; | |
954 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
955 | struct snd_soc_dai_link *dai_link = rtd->dai_link; | |
956 | ||
957 | dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__, | |
958 | dai_link->cpu_dai_name); | |
959 | ||
960 | runtime = substream->runtime; | |
961 | snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw); | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
b663a8c5 | 966 | static int skl_coupled_trigger(struct snd_pcm_substream *substream, |
a40e693c JK |
967 | int cmd) |
968 | { | |
969 | struct hdac_ext_bus *ebus = get_bus_ctx(substream); | |
970 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
971 | struct hdac_ext_stream *stream; | |
972 | struct snd_pcm_substream *s; | |
973 | bool start; | |
974 | int sbits = 0; | |
975 | unsigned long cookie; | |
976 | struct hdac_stream *hstr; | |
977 | ||
978 | stream = get_hdac_ext_stream(substream); | |
979 | hstr = hdac_stream(stream); | |
980 | ||
981 | dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd); | |
982 | ||
983 | if (!hstr->prepared) | |
984 | return -EPIPE; | |
985 | ||
986 | switch (cmd) { | |
987 | case SNDRV_PCM_TRIGGER_START: | |
988 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
989 | case SNDRV_PCM_TRIGGER_RESUME: | |
990 | start = true; | |
991 | break; | |
992 | ||
993 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
994 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
995 | case SNDRV_PCM_TRIGGER_STOP: | |
996 | start = false; | |
997 | break; | |
998 | ||
999 | default: | |
1000 | return -EINVAL; | |
1001 | } | |
1002 | ||
1003 | snd_pcm_group_for_each_entry(s, substream) { | |
1004 | if (s->pcm->card != substream->pcm->card) | |
1005 | continue; | |
1006 | stream = get_hdac_ext_stream(s); | |
1007 | sbits |= 1 << hdac_stream(stream)->index; | |
1008 | snd_pcm_trigger_done(s, substream); | |
1009 | } | |
1010 | ||
1011 | spin_lock_irqsave(&bus->reg_lock, cookie); | |
1012 | ||
1013 | /* first, set SYNC bits of corresponding streams */ | |
1014 | snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC); | |
1015 | ||
1016 | snd_pcm_group_for_each_entry(s, substream) { | |
1017 | if (s->pcm->card != substream->pcm->card) | |
1018 | continue; | |
1019 | stream = get_hdac_ext_stream(s); | |
1020 | if (start) | |
1021 | snd_hdac_stream_start(hdac_stream(stream), true); | |
1022 | else | |
1023 | snd_hdac_stream_stop(hdac_stream(stream)); | |
1024 | } | |
1025 | spin_unlock_irqrestore(&bus->reg_lock, cookie); | |
1026 | ||
1027 | snd_hdac_stream_sync(hstr, start, sbits); | |
1028 | ||
1029 | spin_lock_irqsave(&bus->reg_lock, cookie); | |
1030 | ||
1031 | /* reset SYNC bits */ | |
1032 | snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC); | |
1033 | if (start) | |
1034 | snd_hdac_stream_timecounter_init(hstr, sbits); | |
1035 | spin_unlock_irqrestore(&bus->reg_lock, cookie); | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
05057001 JK |
1040 | static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream, |
1041 | int cmd) | |
1042 | { | |
1043 | struct hdac_ext_bus *ebus = get_bus_ctx(substream); | |
1044 | ||
fc94733e | 1045 | if (!(ebus_to_hbus(ebus))->ppcap) |
b663a8c5 | 1046 | return skl_coupled_trigger(substream, cmd); |
d1730c3d JK |
1047 | |
1048 | return 0; | |
05057001 JK |
1049 | } |
1050 | ||
7b96144d JK |
1051 | static snd_pcm_uframes_t skl_platform_pcm_pointer |
1052 | (struct snd_pcm_substream *substream) | |
a40e693c | 1053 | { |
7b96144d | 1054 | struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream); |
ca590c1c | 1055 | struct hdac_ext_bus *ebus = get_bus_ctx(substream); |
a40e693c | 1056 | unsigned int pos; |
a40e693c | 1057 | |
ca590c1c D |
1058 | /* |
1059 | * Use DPIB for Playback stream as the periodic DMA Position-in- | |
1060 | * Buffer Writes may be scheduled at the same time or later than | |
1061 | * the MSI and does not guarantee to reflect the Position of the | |
1062 | * last buffer that was transferred. Whereas DPIB register in | |
1063 | * HAD space reflects the actual data that is transferred. | |
1064 | * Use the position buffer for capture, as DPIB write gets | |
1065 | * completed earlier than the actual data written to the DDR. | |
1066 | */ | |
1067 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1068 | pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE + | |
1069 | (AZX_REG_VS_SDXDPIB_XINTERVAL * | |
1070 | hdac_stream(hstream)->index)); | |
1071 | else | |
1072 | pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); | |
a40e693c JK |
1073 | |
1074 | if (pos >= hdac_stream(hstream)->bufsize) | |
1075 | pos = 0; | |
1076 | ||
7b96144d | 1077 | return bytes_to_frames(substream->runtime, pos); |
a40e693c JK |
1078 | } |
1079 | ||
1080 | static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream, | |
1081 | u64 nsec) | |
1082 | { | |
1083 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); | |
1084 | struct snd_soc_dai *codec_dai = rtd->codec_dai; | |
1085 | u64 codec_frames, codec_nsecs; | |
1086 | ||
1087 | if (!codec_dai->driver->ops->delay) | |
1088 | return nsec; | |
1089 | ||
1090 | codec_frames = codec_dai->driver->ops->delay(substream, codec_dai); | |
1091 | codec_nsecs = div_u64(codec_frames * 1000000000LL, | |
1092 | substream->runtime->rate); | |
1093 | ||
1094 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
1095 | return nsec + codec_nsecs; | |
1096 | ||
1097 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; | |
1098 | } | |
1099 | ||
1100 | static int skl_get_time_info(struct snd_pcm_substream *substream, | |
1101 | struct timespec *system_ts, struct timespec *audio_ts, | |
1102 | struct snd_pcm_audio_tstamp_config *audio_tstamp_config, | |
1103 | struct snd_pcm_audio_tstamp_report *audio_tstamp_report) | |
1104 | { | |
1105 | struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream); | |
1106 | struct hdac_stream *hstr = hdac_stream(sstream); | |
1107 | u64 nsec; | |
1108 | ||
1109 | if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && | |
1110 | (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { | |
1111 | ||
1112 | snd_pcm_gettime(substream->runtime, system_ts); | |
1113 | ||
1114 | nsec = timecounter_read(&hstr->tc); | |
1115 | nsec = div_u64(nsec, 3); /* can be optimized */ | |
1116 | if (audio_tstamp_config->report_delay) | |
1117 | nsec = skl_adjust_codec_delay(substream, nsec); | |
1118 | ||
1119 | *audio_ts = ns_to_timespec(nsec); | |
1120 | ||
1121 | audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; | |
1122 | audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */ | |
1123 | audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */ | |
1124 | ||
1125 | } else { | |
1126 | audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; | |
1127 | } | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
115c7254 | 1132 | static const struct snd_pcm_ops skl_platform_ops = { |
a40e693c JK |
1133 | .open = skl_platform_open, |
1134 | .ioctl = snd_pcm_lib_ioctl, | |
1135 | .trigger = skl_platform_pcm_trigger, | |
1136 | .pointer = skl_platform_pcm_pointer, | |
1137 | .get_time_info = skl_get_time_info, | |
1138 | .mmap = snd_pcm_lib_default_mmap, | |
1139 | .page = snd_pcm_sgbuf_ops_page, | |
1140 | }; | |
1141 | ||
1142 | static void skl_pcm_free(struct snd_pcm *pcm) | |
1143 | { | |
1144 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1145 | } | |
1146 | ||
1147 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) | |
1148 | ||
1149 | static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd) | |
1150 | { | |
1151 | struct snd_soc_dai *dai = rtd->cpu_dai; | |
1152 | struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); | |
1153 | struct snd_pcm *pcm = rtd->pcm; | |
1154 | unsigned int size; | |
1155 | int retval = 0; | |
1156 | struct skl *skl = ebus_to_skl(ebus); | |
1157 | ||
1158 | if (dai->driver->playback.channels_min || | |
1159 | dai->driver->capture.channels_min) { | |
1160 | /* buffer pre-allocation */ | |
1161 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; | |
1162 | if (size > MAX_PREALLOC_SIZE) | |
1163 | size = MAX_PREALLOC_SIZE; | |
1164 | retval = snd_pcm_lib_preallocate_pages_for_all(pcm, | |
1165 | SNDRV_DMA_TYPE_DEV_SG, | |
1166 | snd_dma_pci_data(skl->pci), | |
1167 | size, MAX_PREALLOC_SIZE); | |
1168 | if (retval) { | |
08458871 | 1169 | dev_err(dai->dev, "dma buffer allocation fail\n"); |
a40e693c JK |
1170 | return retval; |
1171 | } | |
1172 | } | |
1173 | ||
1174 | return retval; | |
1175 | } | |
1176 | ||
b26199ea JK |
1177 | static int skl_get_module_info(struct skl *skl, struct skl_module_cfg *mconfig) |
1178 | { | |
1179 | struct skl_sst *ctx = skl->skl_sst; | |
1180 | struct uuid_module *module; | |
1181 | uuid_le *uuid_mod; | |
1182 | ||
1183 | uuid_mod = (uuid_le *)mconfig->guid; | |
1184 | ||
1185 | if (list_empty(&ctx->uuid_list)) { | |
1186 | dev_err(ctx->dev, "Module list is empty\n"); | |
1187 | return -EIO; | |
1188 | } | |
1189 | ||
1190 | list_for_each_entry(module, &ctx->uuid_list, list) { | |
1191 | if (uuid_le_cmp(*uuid_mod, module->uuid) == 0) { | |
1192 | mconfig->id.module_id = module->id; | |
1193 | mconfig->is_loadable = module->is_loadable; | |
1194 | return 0; | |
1195 | } | |
1196 | } | |
1197 | ||
1198 | return -EIO; | |
1199 | } | |
1200 | ||
64cb1d0a VK |
1201 | static int skl_populate_modules(struct skl *skl) |
1202 | { | |
1203 | struct skl_pipeline *p; | |
1204 | struct skl_pipe_module *m; | |
1205 | struct snd_soc_dapm_widget *w; | |
1206 | struct skl_module_cfg *mconfig; | |
b26199ea | 1207 | int ret = 0; |
64cb1d0a VK |
1208 | |
1209 | list_for_each_entry(p, &skl->ppl_list, node) { | |
1210 | list_for_each_entry(m, &p->pipe->w_list, node) { | |
64cb1d0a VK |
1211 | w = m->w; |
1212 | mconfig = w->priv; | |
1213 | ||
b26199ea | 1214 | ret = skl_get_module_info(skl, mconfig); |
64cb1d0a VK |
1215 | if (ret < 0) { |
1216 | dev_err(skl->skl_sst->dev, | |
b26199ea JK |
1217 | "query module info failed\n"); |
1218 | return ret; | |
64cb1d0a VK |
1219 | } |
1220 | } | |
1221 | } | |
b26199ea | 1222 | |
64cb1d0a VK |
1223 | return ret; |
1224 | } | |
1225 | ||
b663a8c5 JK |
1226 | static int skl_platform_soc_probe(struct snd_soc_platform *platform) |
1227 | { | |
1228 | struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev); | |
fe3f4442 | 1229 | struct skl *skl = ebus_to_skl(ebus); |
78cdbbda | 1230 | const struct skl_dsp_ops *ops; |
fe3f4442 | 1231 | int ret; |
b663a8c5 | 1232 | |
78cdbbda | 1233 | pm_runtime_get_sync(platform->dev); |
ec8ae570 | 1234 | if ((ebus_to_hbus(ebus))->ppcap) { |
fe3f4442 D |
1235 | ret = skl_tplg_init(platform, ebus); |
1236 | if (ret < 0) { | |
1237 | dev_err(platform->dev, "Failed to init topology!\n"); | |
1238 | return ret; | |
1239 | } | |
1240 | skl->platform = platform; | |
78cdbbda VK |
1241 | |
1242 | /* load the firmwares, since all is set */ | |
1243 | ops = skl_get_dsp_ops(skl->pci->device); | |
1244 | if (!ops) | |
1245 | return -EIO; | |
1246 | ||
1247 | if (skl->skl_sst->is_first_boot == false) { | |
1248 | dev_err(platform->dev, "DSP reports first boot done!!!\n"); | |
1249 | return -EIO; | |
1250 | } | |
1251 | ||
1252 | ret = ops->init_fw(platform->dev, skl->skl_sst); | |
1253 | if (ret < 0) { | |
1254 | dev_err(platform->dev, "Failed to boot first fw: %d\n", ret); | |
1255 | return ret; | |
1256 | } | |
64cb1d0a | 1257 | skl_populate_modules(skl); |
a26a3f53 | 1258 | skl->skl_sst->update_d0i3c = skl_update_d0i3c; |
cb729d80 | 1259 | skl_dsp_enable_notification(skl->skl_sst, false); |
fe3f4442 | 1260 | } |
78cdbbda VK |
1261 | pm_runtime_mark_last_busy(platform->dev); |
1262 | pm_runtime_put_autosuspend(platform->dev); | |
b663a8c5 JK |
1263 | |
1264 | return 0; | |
1265 | } | |
a40e693c | 1266 | static struct snd_soc_platform_driver skl_platform_drv = { |
b663a8c5 | 1267 | .probe = skl_platform_soc_probe, |
a40e693c JK |
1268 | .ops = &skl_platform_ops, |
1269 | .pcm_new = skl_pcm_new, | |
1270 | .pcm_free = skl_pcm_free, | |
1271 | }; | |
1272 | ||
1273 | static const struct snd_soc_component_driver skl_component = { | |
1274 | .name = "pcm", | |
1275 | }; | |
1276 | ||
1277 | int skl_platform_register(struct device *dev) | |
1278 | { | |
1279 | int ret; | |
b663a8c5 JK |
1280 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); |
1281 | struct skl *skl = ebus_to_skl(ebus); | |
1282 | ||
1283 | INIT_LIST_HEAD(&skl->ppl_list); | |
a40e693c JK |
1284 | |
1285 | ret = snd_soc_register_platform(dev, &skl_platform_drv); | |
1286 | if (ret) { | |
1287 | dev_err(dev, "soc platform registration failed %d\n", ret); | |
1288 | return ret; | |
1289 | } | |
1290 | ret = snd_soc_register_component(dev, &skl_component, | |
1291 | skl_platform_dai, | |
1292 | ARRAY_SIZE(skl_platform_dai)); | |
1293 | if (ret) { | |
1294 | dev_err(dev, "soc component registration failed %d\n", ret); | |
1295 | snd_soc_unregister_platform(dev); | |
1296 | } | |
1297 | ||
1298 | return ret; | |
1299 | ||
1300 | } | |
1301 | ||
1302 | int skl_platform_unregister(struct device *dev) | |
1303 | { | |
1304 | snd_soc_unregister_component(dev); | |
1305 | snd_soc_unregister_platform(dev); | |
1306 | return 0; | |
1307 | } |