[mirror_ubuntu-bionic-kernel.git] / sound / soc / intel / skylake / skl-sst-ipc.h

/*
 * Intel SKL IPC Support
 *
 * Copyright (C) 2014-15, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#ifndef __SKL_IPC_H
#define __SKL_IPC_H

#include <linux/irqreturn.h>
#include "../common/sst-ipc.h"

struct sst_dsp;
struct skl_sst;
struct sst_generic_ipc;

enum skl_ipc_pipeline_state {
	PPL_INVALID_STATE =	0,
	PPL_UNINITIALIZED =	1,
	PPL_RESET =		2,
	PPL_PAUSED =		3,
	PPL_RUNNING =		4,
	PPL_ERROR_STOP =	5,
	PPL_SAVED =		6,
	PPL_RESTORED =		7
};

struct skl_ipc_dxstate_info {
	u32 core_mask;
	u32 dx_mask;
};

struct skl_ipc_header {
	u32 primary;
	u32 extension;
};

struct skl_dsp_cores {
	unsigned int count;
	enum skl_dsp_states *state;
	int *usage_count;
};

/**
 * skl_d0i3_data: skl D0i3 counters data struct
 *
 * @streaming: Count of usecases that can attempt streaming D0i3
 * @non_streaming: Count of usecases that can attempt non-streaming D0i3
 * @non_d0i3: Count of usecases that cannot attempt D0i3
 * @state: current state
 * @work: D0i3 worker thread
 */
struct skl_d0i3_data {
	int streaming;
	int non_streaming;
	int non_d0i3;
	enum skl_dsp_d0i3_states state;
	struct delayed_work work;
};

#define SKL_LIB_NAME_LENGTH 128
#define SKL_MAX_LIB 16

struct skl_lib_info {
	char name[SKL_LIB_NAME_LENGTH];
	const struct firmware *fw;
};

struct skl_sst {
	struct device *dev;
	struct sst_dsp *dsp;

	/* boot */
	wait_queue_head_t boot_wait;
	bool boot_complete;

	/* module load */
	wait_queue_head_t mod_load_wait;
	bool mod_load_complete;
	bool mod_load_status;

	/* IPC messaging */
	struct sst_generic_ipc ipc;

	/* callback for miscbdge */
	void (*enable_miscbdcge)(struct device *dev, bool enable);
	/* Is CGCTL.MISCBDCGE disabled */
	bool miscbdcg_disabled;

	/* Populate module information */
	struct list_head uuid_list;

	/* Is firmware loaded */
	bool fw_loaded;

	/* first boot ? */
	bool is_first_boot;

	/* multi-core */
	struct skl_dsp_cores cores;

	/* library info */
	struct skl_lib_info  lib_info[SKL_MAX_LIB];
	int lib_count;

	/* Callback to update D0i3C register */
	void (*update_d0i3c)(struct device *dev, bool enable);

	struct skl_d0i3_data d0i3;

	const struct skl_dsp_ops *dsp_ops;
};

struct skl_ipc_init_instance_msg {
	u32 module_id;
	u32 instance_id;
	u16 param_data_size;
	u8 ppl_instance_id;
	u8 core_id;
	u8 domain;
};

struct skl_ipc_bind_unbind_msg {
	u32 module_id;
	u32 instance_id;
	u32 dst_module_id;
	u32 dst_instance_id;
	u8 src_queue;
	u8 dst_queue;
	bool bind;
};

struct skl_ipc_large_config_msg {
	u32 module_id;
	u32 instance_id;
	u32 large_param_id;
	u32 param_data_size;
};

struct skl_ipc_d0ix_msg {
	u32 module_id;
	u32 instance_id;
	u8 streaming;
	u8 wake;
};

#define SKL_IPC_BOOT_MSECS		3000

#define SKL_IPC_D3_MASK	0
#define SKL_IPC_D0_MASK	3

irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context);

int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc,
		u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode);

int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id);

int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc,
		u8 instance_id,	enum skl_ipc_pipeline_state state);

int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc,
		u8 instance_id, int dma_id);

int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id);

int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc,
		struct skl_ipc_init_instance_msg *msg, void *param_data);

int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc,
		struct skl_ipc_bind_unbind_msg *msg);

int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
				u8 module_cnt, void *data);

int skl_ipc_unload_modules(struct sst_generic_ipc *ipc,
				u8 module_cnt, void *data);

int skl_ipc_set_dx(struct sst_generic_ipc *ipc,
		u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx);

int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
		struct skl_ipc_large_config_msg *msg, u32 *param);

int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
		struct skl_ipc_large_config_msg *msg, u32 *param);

int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
			u8 dma_id, u8 table_id, bool wait);

int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc,
		struct skl_ipc_d0ix_msg *msg);

int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state);

void skl_ipc_int_enable(struct sst_dsp *dsp);
void skl_ipc_op_int_enable(struct sst_dsp *ctx);
void skl_ipc_op_int_disable(struct sst_dsp *ctx);
void skl_ipc_int_disable(struct sst_dsp *dsp);

bool skl_ipc_int_status(struct sst_dsp *dsp);
void skl_ipc_free(struct sst_generic_ipc *ipc);
int skl_ipc_init(struct device *dev, struct skl_sst *skl);
void skl_clear_module_cnt(struct sst_dsp *ctx);

void skl_ipc_process_reply(struct sst_generic_ipc *ipc,
		struct skl_ipc_header header);
int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
		struct skl_ipc_header header);
void skl_ipc_tx_data_copy(struct ipc_message *msg, char *tx_data,
		size_t tx_size);
#endif /* __SKL_IPC_H */
Commit	Line	Data
b81fd263 SP	1	/*
	2	* Intel SKL IPC Support
	3	*
	4	* Copyright (C) 2014-15, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as version 2, as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* General Public License for more details.
	14	*/
	15
	16	#ifndef __SKL_IPC_H
	17	#define __SKL_IPC_H
	18
b81fd263 SP	19	#include <linux/irqreturn.h>
	20	#include "../common/sst-ipc.h"
	21
	22	struct sst_dsp;
	23	struct skl_sst;
	24	struct sst_generic_ipc;
	25
	26	enum skl_ipc_pipeline_state {
	27	PPL_INVALID_STATE = 0,
	28	PPL_UNINITIALIZED = 1,
	29	PPL_RESET = 2,
	30	PPL_PAUSED = 3,
	31	PPL_RUNNING = 4,
	32	PPL_ERROR_STOP = 5,
	33	PPL_SAVED = 6,
	34	PPL_RESTORED = 7
	35	};
	36
	37	struct skl_ipc_dxstate_info {
	38	u32 core_mask;
	39	u32 dx_mask;
	40	};
	41
	42	struct skl_ipc_header {
	43	u32 primary;
	44	u32 extension;
	45	};
	46
052f103c J	47	struct skl_dsp_cores {
052f103c J	48	unsigned int count;
f0a550a8 GS	49	enum skl_dsp_states *state;
f0a550a8 GS	50	int *usage_count;
052f103c J	51	};
052f103c J	52
5bb4cd46 J	53	/**
	54	* skl_d0i3_data: skl D0i3 counters data struct
	55	*
	56	* @streaming: Count of usecases that can attempt streaming D0i3
	57	* @non_streaming: Count of usecases that can attempt non-streaming D0i3
	58	* @non_d0i3: Count of usecases that cannot attempt D0i3
	59	* @state: current state
	60	* @work: D0i3 worker thread
	61	*/
	62	struct skl_d0i3_data {
	63	int streaming;
	64	int non_streaming;
	65	int non_d0i3;
	66	enum skl_dsp_d0i3_states state;
	67	struct delayed_work work;
	68	};
	69
b26199ea JK	70	#define SKL_LIB_NAME_LENGTH 128
	71	#define SKL_MAX_LIB 16
	72
	73	struct skl_lib_info {
	74	char name[SKL_LIB_NAME_LENGTH];
	75	const struct firmware *fw;
	76	};
	77
b81fd263 SP	78	struct skl_sst {
	79	struct device *dev;
	80	struct sst_dsp *dsp;
	81
	82	/* boot */
	83	wait_queue_head_t boot_wait;
	84	bool boot_complete;
	85
b7d0254c JK	86	/* module load */
	87	wait_queue_head_t mod_load_wait;
	88	bool mod_load_complete;
	89	bool mod_load_status;
	90
b81fd263 SP	91	/* IPC messaging */
b81fd263 SP	92	struct sst_generic_ipc ipc;
0c8ba9d2 J	93
	94	/* callback for miscbdge */
	95	void (enable_miscbdcge)(struct device dev, bool enable);
8d983be8	96	/* Is CGCTL.MISCBDCGE disabled */
0c8ba9d2	97	bool miscbdcg_disabled;
ea6b3e94 SN	98
	99	/* Populate module information */
	100	struct list_head uuid_list;
1665c177 J	101
	102	/* Is firmware loaded */
	103	bool fw_loaded;
052f103c	104
78cdbbda VK	105	/* first boot ? */
	106	bool is_first_boot;
	107
052f103c J	108	/* multi-core */
052f103c J	109	struct skl_dsp_cores cores;
15ecaba9	110
eee0e16f JK	111	/* library info */
	112	struct skl_lib_info lib_info[SKL_MAX_LIB];
	113	int lib_count;
a26a3f53 PS	114
	115	/* Callback to update D0i3C register */
	116	void (update_d0i3c)(struct device dev, bool enable);
5bb4cd46 J	117
5bb4cd46 J	118	struct skl_d0i3_data d0i3;
7bd86a30 K	119
7bd86a30 K	120	const struct skl_dsp_ops *dsp_ops;
b81fd263 SP	121	};
	122
	123	struct skl_ipc_init_instance_msg {
	124	u32 module_id;
	125	u32 instance_id;
	126	u16 param_data_size;
	127	u8 ppl_instance_id;
	128	u8 core_id;
3d4006cd	129	u8 domain;
b81fd263 SP	130	};
	131
	132	struct skl_ipc_bind_unbind_msg {
	133	u32 module_id;
	134	u32 instance_id;
	135	u32 dst_module_id;
	136	u32 dst_instance_id;
	137	u8 src_queue;
	138	u8 dst_queue;
	139	bool bind;
	140	};
	141
	142	struct skl_ipc_large_config_msg {
	143	u32 module_id;
	144	u32 instance_id;
	145	u32 large_param_id;
	146	u32 param_data_size;
	147	};
	148
41b7523f PS	149	struct skl_ipc_d0ix_msg {
	150	u32 module_id;
	151	u32 instance_id;
	152	u8 streaming;
	153	u8 wake;
	154	};
	155
b81fd263 SP	156	#define SKL_IPC_BOOT_MSECS 3000
	157
	158	#define SKL_IPC_D3_MASK 0
	159	#define SKL_IPC_D0_MASK 3
	160
	161	irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context);
	162
	163	int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc,
8a0cb236	164	u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode);
b81fd263 SP	165
	166	int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id);
	167
	168	int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc,
	169	u8 instance_id, enum skl_ipc_pipeline_state state);
	170
	171	int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc,
	172	u8 instance_id, int dma_id);
	173
	174	int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id);
	175
	176	int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc,
	177	struct skl_ipc_init_instance_msg msg, void param_data);
	178
	179	int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc,
	180	struct skl_ipc_bind_unbind_msg *msg);
	181
6c5768b3 D	182	int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
	183	u8 module_cnt, void *data);
	184
	185	int skl_ipc_unload_modules(struct sst_generic_ipc *ipc,
	186	u8 module_cnt, void *data);
	187
b81fd263 SP	188	int skl_ipc_set_dx(struct sst_generic_ipc *ipc,
	189	u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx);
	190
	191	int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
	192	struct skl_ipc_large_config_msg msg, u32 param);
	193
cce1c7f3 MJ	194	int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
	195	struct skl_ipc_large_config_msg msg, u32 param);
	196
20fb2fbd	197	int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
100e7f39	198	u8 dma_id, u8 table_id, bool wait);
20fb2fbd	199
41b7523f PS	200	int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc,
	201	struct skl_ipc_d0ix_msg *msg);
	202
a83e3b4c VK	203	int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state);
a83e3b4c VK	204
b81fd263 SP	205	void skl_ipc_int_enable(struct sst_dsp *dsp);
b81fd263 SP	206	void skl_ipc_op_int_enable(struct sst_dsp *ctx);
84c9e283	207	void skl_ipc_op_int_disable(struct sst_dsp *ctx);
b81fd263 SP	208	void skl_ipc_int_disable(struct sst_dsp *dsp);
	209
	210	bool skl_ipc_int_status(struct sst_dsp *dsp);
	211	void skl_ipc_free(struct sst_generic_ipc *ipc);
	212	int skl_ipc_init(struct device dev, struct skl_sst skl);
fe3f4442	213	void skl_clear_module_cnt(struct sst_dsp *ctx);
b81fd263	214
4bdb04f0 GS	215	void skl_ipc_process_reply(struct sst_generic_ipc *ipc,
	216	struct skl_ipc_header header);
	217	int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
	218	struct skl_ipc_header header);
	219	void skl_ipc_tx_data_copy(struct ipc_message msg, char tx_data,
	220	size_t tx_size);
b81fd263	221	#endif /* __SKL_IPC_H */