[mirror_ubuntu-bionic-kernel.git] / sound / soc / intel / skylake / skl-topology.h

/*
 *  skl_topology.h - Intel HDA Platform topology header file
 *
 *  Copyright (C) 2014-15 Intel Corp
 *  Author: Jeeja KP <jeeja.kp@intel.com>
 *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; version 2 of the License.
 *
 *  This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  General Public License for more details.
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 */

#ifndef __SKL_TOPOLOGY_H__
#define __SKL_TOPOLOGY_H__

#include <linux/types.h>

#include <sound/hdaudio_ext.h>
#include <sound/soc.h>
#include "skl.h"
#include "skl-tplg-interface.h"

#define BITS_PER_BYTE 8
#define MAX_TS_GROUPS 8
#define MAX_DMIC_TS_GROUPS 4
#define MAX_FIXED_DMIC_PARAMS_SIZE 727

/* Maximum number of coefficients up down mixer module */
#define UP_DOWN_MIXER_MAX_COEFF		6

#define MODULE_MAX_IN_PINS	8
#define MODULE_MAX_OUT_PINS	8

enum skl_channel_index {
	SKL_CHANNEL_LEFT = 0,
	SKL_CHANNEL_RIGHT = 1,
	SKL_CHANNEL_CENTER = 2,
	SKL_CHANNEL_LEFT_SURROUND = 3,
	SKL_CHANNEL_CENTER_SURROUND = 3,
	SKL_CHANNEL_RIGHT_SURROUND = 4,
	SKL_CHANNEL_LFE = 7,
	SKL_CHANNEL_INVALID = 0xF,
};

enum skl_bitdepth {
	SKL_DEPTH_8BIT = 8,
	SKL_DEPTH_16BIT = 16,
	SKL_DEPTH_24BIT = 24,
	SKL_DEPTH_32BIT = 32,
	SKL_DEPTH_INVALID
};


enum skl_s_freq {
	SKL_FS_8000 = 8000,
	SKL_FS_11025 = 11025,
	SKL_FS_12000 = 12000,
	SKL_FS_16000 = 16000,
	SKL_FS_22050 = 22050,
	SKL_FS_24000 = 24000,
	SKL_FS_32000 = 32000,
	SKL_FS_44100 = 44100,
	SKL_FS_48000 = 48000,
	SKL_FS_64000 = 64000,
	SKL_FS_88200 = 88200,
	SKL_FS_96000 = 96000,
	SKL_FS_128000 = 128000,
	SKL_FS_176400 = 176400,
	SKL_FS_192000 = 192000,
	SKL_FS_INVALID
};

enum skl_widget_type {
	SKL_WIDGET_VMIXER = 1,
	SKL_WIDGET_MIXER = 2,
	SKL_WIDGET_PGA = 3,
	SKL_WIDGET_MUX = 4
};

struct skl_audio_data_format {
	enum skl_s_freq s_freq;
	enum skl_bitdepth bit_depth;
	u32 channel_map;
	enum skl_ch_cfg ch_cfg;
	enum skl_interleaving interleaving;
	u8 number_of_channels;
	u8 valid_bit_depth;
	u8 sample_type;
	u8 reserved[1];
} __packed;

struct skl_base_cfg {
	u32 cps;
	u32 ibs;
	u32 obs;
	u32 is_pages;
	struct skl_audio_data_format audio_fmt;
};

struct skl_cpr_gtw_cfg {
	u32 node_id;
	u32 dma_buffer_size;
	u32 config_length;
	/* not mandatory; required only for DMIC/I2S */
	u32 config_data[1];
} __packed;

struct skl_dma_control {
	u32 node_id;
	u32 config_length;
	u32 config_data[0];
} __packed;

struct skl_cpr_cfg {
	struct skl_base_cfg base_cfg;
	struct skl_audio_data_format out_fmt;
	u32 cpr_feature_mask;
	struct skl_cpr_gtw_cfg gtw_cfg;
} __packed;


struct skl_src_module_cfg {
	struct skl_base_cfg base_cfg;
	enum skl_s_freq src_cfg;
} __packed;

struct notification_mask {
	u32 notify;
	u32 enable;
} __packed;

struct skl_up_down_mixer_cfg {
	struct skl_base_cfg base_cfg;
	enum skl_ch_cfg out_ch_cfg;
	/* This should be set to 1 if user coefficients are required */
	u32 coeff_sel;
	/* Pass the user coeff in this array */
	s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
} __packed;

struct skl_algo_cfg {
	struct skl_base_cfg  base_cfg;
	char params[0];
} __packed;

struct skl_base_outfmt_cfg {
	struct skl_base_cfg base_cfg;
	struct skl_audio_data_format out_fmt;
} __packed;

enum skl_dma_type {
	SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
	SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
	SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
	SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
	SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
	SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
	SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
	SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
	SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
};

union skl_ssp_dma_node {
	u8 val;
	struct {
		u8 time_slot_index:4;
		u8 i2s_instance:4;
	} dma_node;
};

union skl_connector_node_id {
	u32 val;
	struct {
		u32 vindex:8;
		u32 dma_type:4;
		u32 rsvd:20;
	} node;
};

struct skl_module_fmt {
	u32 channels;
	u32 s_freq;
	u32 bit_depth;
	u32 valid_bit_depth;
	u32 ch_cfg;
	u32 interleaving_style;
	u32 sample_type;
	u32 ch_map;
};

struct skl_module_cfg;

struct skl_mod_inst_map {
	u16 mod_id;
	u16 inst_id;
};

struct skl_kpb_params {
	u32 num_modules;
	struct skl_mod_inst_map map[0];
};

struct skl_module_inst_id {
	int module_id;
	u32 instance_id;
	int pvt_id;
};

enum skl_module_pin_state {
	SKL_PIN_UNBIND = 0,
	SKL_PIN_BIND_DONE = 1,
};

struct skl_module_pin {
	struct skl_module_inst_id id;
	bool is_dynamic;
	bool in_use;
	enum skl_module_pin_state pin_state;
	struct skl_module_cfg *tgt_mcfg;
};

struct skl_specific_cfg {
	u32 set_params;
	u32 param_id;
	u32 caps_size;
	u32 *caps;
};

enum skl_pipe_state {
	SKL_PIPE_INVALID = 0,
	SKL_PIPE_CREATED = 1,
	SKL_PIPE_PAUSED = 2,
	SKL_PIPE_STARTED = 3,
	SKL_PIPE_RESET = 4
};

struct skl_pipe_module {
	struct snd_soc_dapm_widget *w;
	struct list_head node;
};

struct skl_pipe_params {
	u8 host_dma_id;
	u8 link_dma_id;
	u32 ch;
	u32 s_freq;
	u32 s_fmt;
	u8 linktype;
	snd_pcm_format_t format;
	int link_index;
	int stream;
	unsigned int host_bps;
	unsigned int link_bps;
};

struct skl_pipe {
	u8 ppl_id;
	u8 pipe_priority;
	u16 conn_type;
	u32 memory_pages;
	u8 lp_mode;
	struct skl_pipe_params *p_params;
	enum skl_pipe_state state;
	struct list_head w_list;
	bool passthru;
};

enum skl_module_state {
	SKL_MODULE_UNINIT = 0,
	SKL_MODULE_LOADED = 1,
	SKL_MODULE_INIT_DONE = 2,
	SKL_MODULE_BIND_DONE = 3,
	SKL_MODULE_UNLOADED = 4,
};

enum d0i3_capability {
	SKL_D0I3_NONE = 0,
	SKL_D0I3_STREAMING = 1,
	SKL_D0I3_NON_STREAMING = 2,
};

struct skl_module_cfg {
	u8 guid[16];
	struct skl_module_inst_id id;
	u8 domain;
	bool homogenous_inputs;
	bool homogenous_outputs;
	struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
	struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
	u8 max_in_queue;
	u8 max_out_queue;
	u8 in_queue_mask;
	u8 out_queue_mask;
	u8 in_queue;
	u8 out_queue;
	u32 mcps;
	u32 ibs;
	u32 obs;
	u8 is_loadable;
	u8 core_id;
	u8 dev_type;
	u8 dma_id;
	u8 time_slot;
	u32 params_fixup;
	u32 converter;
	u32 vbus_id;
	u32 mem_pages;
	enum d0i3_capability d0i3_caps;
	struct skl_module_pin *m_in_pin;
	struct skl_module_pin *m_out_pin;
	enum skl_module_type m_type;
	enum skl_hw_conn_type  hw_conn_type;
	enum skl_module_state m_state;
	struct skl_pipe *pipe;
	struct skl_specific_cfg formats_config;
};

struct skl_algo_data {
	u32 param_id;
	u32 set_params;
	u32 max;
	u32 size;
	char *params;
};

struct skl_pipeline {
	struct skl_pipe *pipe;
	struct list_head node;
};

struct skl_module_deferred_bind {
	struct skl_module_cfg *src;
	struct skl_module_cfg *dst;
	struct list_head node;
};

static inline struct skl *get_skl_ctx(struct device *dev)
{
	struct hdac_ext_bus *ebus = dev_get_drvdata(dev);

	return ebus_to_skl(ebus);
}

int skl_tplg_be_update_params(struct snd_soc_dai *dai,
	struct skl_pipe_params *params);
int skl_dsp_set_dma_control(struct skl_sst *ctx,
		struct skl_module_cfg *mconfig);
void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
	struct skl_pipe_params *params, int stream);
int skl_tplg_init(struct snd_soc_platform *platform,
				struct hdac_ext_bus *ebus);
struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
		struct snd_soc_dai *dai, int stream);
int skl_tplg_update_pipe_params(struct device *dev,
		struct skl_module_cfg *mconfig, struct skl_pipe_params *params);

void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps);
void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps);

int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config);

int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
	*src_module, struct skl_module_cfg *dst_module);

int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
	*src_module, struct skl_module_cfg *dst_module);

int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
			u32 param_id, struct skl_module_cfg *mcfg);
int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
			  u32 param_id, struct skl_module_cfg *mcfg);

struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
								int stream);
enum skl_bitdepth skl_get_bit_depth(int params);
int skl_pcm_host_dma_prepare(struct device *dev,
			struct skl_pipe_params *params);
int skl_pcm_link_dma_prepare(struct device *dev,
			struct skl_pipe_params *params);
#endif
Commit	Line	Data
23db472b JK	1	/*
	2	* skl_topology.h - Intel HDA Platform topology header file
	3	*
	4	* Copyright (C) 2014-15 Intel Corp
	5	* Author: Jeeja KP <jeeja.kp@intel.com>
	6	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	18	*
	19	*/
	20
	21	#ifndef __SKL_TOPOLOGY_H__
	22	#define __SKL_TOPOLOGY_H__
	23
	24	#include <linux/types.h>
	25
	26	#include <sound/hdaudio_ext.h>
	27	#include <sound/soc.h>
	28	#include "skl.h"
	29	#include "skl-tplg-interface.h"
	30
	31	#define BITS_PER_BYTE 8
	32	#define MAX_TS_GROUPS 8
	33	#define MAX_DMIC_TS_GROUPS 4
	34	#define MAX_FIXED_DMIC_PARAMS_SIZE 727
	35
	36	/* Maximum number of coefficients up down mixer module */
	37	#define UP_DOWN_MIXER_MAX_COEFF 6
	38
4cd9899f HS	39	#define MODULE_MAX_IN_PINS 8
	40	#define MODULE_MAX_OUT_PINS 8
	41
23db472b JK	42	enum skl_channel_index {
	43	SKL_CHANNEL_LEFT = 0,
	44	SKL_CHANNEL_RIGHT = 1,
	45	SKL_CHANNEL_CENTER = 2,
	46	SKL_CHANNEL_LEFT_SURROUND = 3,
	47	SKL_CHANNEL_CENTER_SURROUND = 3,
	48	SKL_CHANNEL_RIGHT_SURROUND = 4,
	49	SKL_CHANNEL_LFE = 7,
	50	SKL_CHANNEL_INVALID = 0xF,
	51	};
	52
	53	enum skl_bitdepth {
	54	SKL_DEPTH_8BIT = 8,
	55	SKL_DEPTH_16BIT = 16,
	56	SKL_DEPTH_24BIT = 24,
	57	SKL_DEPTH_32BIT = 32,
	58	SKL_DEPTH_INVALID
	59	};
	60
23db472b JK	61
	62	enum skl_s_freq {
	63	SKL_FS_8000 = 8000,
	64	SKL_FS_11025 = 11025,
	65	SKL_FS_12000 = 12000,
	66	SKL_FS_16000 = 16000,
	67	SKL_FS_22050 = 22050,
	68	SKL_FS_24000 = 24000,
	69	SKL_FS_32000 = 32000,
	70	SKL_FS_44100 = 44100,
	71	SKL_FS_48000 = 48000,
	72	SKL_FS_64000 = 64000,
	73	SKL_FS_88200 = 88200,
	74	SKL_FS_96000 = 96000,
	75	SKL_FS_128000 = 128000,
	76	SKL_FS_176400 = 176400,
	77	SKL_FS_192000 = 192000,
	78	SKL_FS_INVALID
	79	};
	80
	81	enum skl_widget_type {
	82	SKL_WIDGET_VMIXER = 1,
	83	SKL_WIDGET_MIXER = 2,
	84	SKL_WIDGET_PGA = 3,
	85	SKL_WIDGET_MUX = 4
	86	};
	87
	88	struct skl_audio_data_format {
	89	enum skl_s_freq s_freq;
	90	enum skl_bitdepth bit_depth;
	91	u32 channel_map;
	92	enum skl_ch_cfg ch_cfg;
	93	enum skl_interleaving interleaving;
	94	u8 number_of_channels;
	95	u8 valid_bit_depth;
	96	u8 sample_type;
	97	u8 reserved[1];
	98	} __packed;
	99
	100	struct skl_base_cfg {
	101	u32 cps;
	102	u32 ibs;
	103	u32 obs;
	104	u32 is_pages;
	105	struct skl_audio_data_format audio_fmt;
	106	};
	107
	108	struct skl_cpr_gtw_cfg {
	109	u32 node_id;
	110	u32 dma_buffer_size;
	111	u32 config_length;
	112	/* not mandatory; required only for DMIC/I2S */
	113	u32 config_data[1];
	114	} __packed;
	115
c115fa5e D	116	struct skl_dma_control {
	117	u32 node_id;
	118	u32 config_length;
0b6d76bb	119	u32 config_data[0];
c115fa5e D	120	} __packed;
c115fa5e D	121
23db472b JK	122	struct skl_cpr_cfg {
	123	struct skl_base_cfg base_cfg;
	124	struct skl_audio_data_format out_fmt;
	125	u32 cpr_feature_mask;
	126	struct skl_cpr_gtw_cfg gtw_cfg;
	127	} __packed;
	128
a0ffe48b HS	129
	130	struct skl_src_module_cfg {
	131	struct skl_base_cfg base_cfg;
	132	enum skl_s_freq src_cfg;
	133	} __packed;
	134
4e10996b JK	135	struct notification_mask {
	136	u32 notify;
	137	u32 enable;
	138	} __packed;
	139
a0ffe48b HS	140	struct skl_up_down_mixer_cfg {
	141	struct skl_base_cfg base_cfg;
	142	enum skl_ch_cfg out_ch_cfg;
	143	/* This should be set to 1 if user coefficients are required */
	144	u32 coeff_sel;
	145	/* Pass the user coeff in this array */
	146	s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
	147	} __packed;
	148
399b210b JK	149	struct skl_algo_cfg {
	150	struct skl_base_cfg base_cfg;
	151	char params[0];
	152	} __packed;
	153
fd18110f D	154	struct skl_base_outfmt_cfg {
	155	struct skl_base_cfg base_cfg;
	156	struct skl_audio_data_format out_fmt;
	157	} __packed;
	158
23db472b JK	159	enum skl_dma_type {
	160	SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
	161	SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
	162	SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
	163	SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
	164	SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
	165	SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
	166	SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
	167	SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
	168	SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
	169	};
	170
	171	union skl_ssp_dma_node {
	172	u8 val;
	173	struct {
d7b18813	174	u8 time_slot_index:4;
23db472b JK	175	u8 i2s_instance:4;
	176	} dma_node;
	177	};
	178
	179	union skl_connector_node_id {
	180	u32 val;
	181	struct {
	182	u32 vindex:8;
	183	u32 dma_type:4;
	184	u32 rsvd:20;
	185	} node;
	186	};
	187
	188	struct skl_module_fmt {
	189	u32 channels;
	190	u32 s_freq;
	191	u32 bit_depth;
	192	u32 valid_bit_depth;
	193	u32 ch_cfg;
4cd9899f HS	194	u32 interleaving_style;
	195	u32 sample_type;
	196	u32 ch_map;
23db472b JK	197	};
23db472b JK	198
4f745708 JK	199	struct skl_module_cfg;
4f745708 JK	200
5e8f0ee4 D	201	struct skl_mod_inst_map {
	202	u16 mod_id;
	203	u16 inst_id;
	204	};
	205
	206	struct skl_kpb_params {
	207	u32 num_modules;
	208	struct skl_mod_inst_map map[0];
	209	};
	210
23db472b	211	struct skl_module_inst_id {
b7c50555	212	int module_id;
23db472b	213	u32 instance_id;
700a9a63	214	int pvt_id;
23db472b JK	215	};
23db472b JK	216
4f745708 JK	217	enum skl_module_pin_state {
	218	SKL_PIN_UNBIND = 0,
	219	SKL_PIN_BIND_DONE = 1,
	220	};
	221
23db472b JK	222	struct skl_module_pin {
23db472b JK	223	struct skl_module_inst_id id;
23db472b JK	224	bool is_dynamic;
23db472b JK	225	bool in_use;
4f745708 JK	226	enum skl_module_pin_state pin_state;
4f745708 JK	227	struct skl_module_cfg *tgt_mcfg;
23db472b JK	228	};
	229
	230	struct skl_specific_cfg {
4ced1827	231	u32 set_params;
abb74003	232	u32 param_id;
23db472b JK	233	u32 caps_size;
	234	u32 *caps;
	235	};
	236
	237	enum skl_pipe_state {
	238	SKL_PIPE_INVALID = 0,
	239	SKL_PIPE_CREATED = 1,
	240	SKL_PIPE_PAUSED = 2,
2004432f JK	241	SKL_PIPE_STARTED = 3,
2004432f JK	242	SKL_PIPE_RESET = 4
23db472b JK	243	};
	244
	245	struct skl_pipe_module {
	246	struct snd_soc_dapm_widget *w;
	247	struct list_head node;
	248	};
	249
	250	struct skl_pipe_params {
	251	u8 host_dma_id;
	252	u8 link_dma_id;
	253	u32 ch;
	254	u32 s_freq;
	255	u32 s_fmt;
	256	u8 linktype;
12c3be0e JK	257	snd_pcm_format_t format;
12c3be0e JK	258	int link_index;
23db472b	259	int stream;
7f975a38 JK	260	unsigned int host_bps;
7f975a38 JK	261	unsigned int link_bps;
23db472b JK	262	};
	263
	264	struct skl_pipe {
	265	u8 ppl_id;
	266	u8 pipe_priority;
	267	u16 conn_type;
	268	u32 memory_pages;
8a0cb236	269	u8 lp_mode;
23db472b JK	270	struct skl_pipe_params *p_params;
	271	enum skl_pipe_state state;
	272	struct list_head w_list;
f0aa94fa	273	bool passthru;
23db472b JK	274	};
	275
	276	enum skl_module_state {
	277	SKL_MODULE_UNINIT = 0,
d643678b JK	278	SKL_MODULE_LOADED = 1,
	279	SKL_MODULE_INIT_DONE = 2,
	280	SKL_MODULE_BIND_DONE = 3,
	281	SKL_MODULE_UNLOADED = 4,
23db472b JK	282	};
23db472b JK	283
6bd9dcf3 VK	284	enum d0i3_capability {
	285	SKL_D0I3_NONE = 0,
	286	SKL_D0I3_STREAMING = 1,
	287	SKL_D0I3_NON_STREAMING = 2,
	288	};
	289
23db472b	290	struct skl_module_cfg {
09305da9	291	u8 guid[16];
23db472b	292	struct skl_module_inst_id id;
04afbbbb	293	u8 domain;
4cd9899f HS	294	bool homogenous_inputs;
	295	bool homogenous_outputs;
	296	struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
	297	struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
23db472b JK	298	u8 max_in_queue;
	299	u8 max_out_queue;
	300	u8 in_queue_mask;
	301	u8 out_queue_mask;
	302	u8 in_queue;
	303	u8 out_queue;
	304	u32 mcps;
	305	u32 ibs;
	306	u32 obs;
	307	u8 is_loadable;
	308	u8 core_id;
	309	u8 dev_type;
	310	u8 dma_id;
	311	u8 time_slot;
	312	u32 params_fixup;
	313	u32 converter;
	314	u32 vbus_id;
b18c458d	315	u32 mem_pages;
6bd9dcf3	316	enum d0i3_capability d0i3_caps;
23db472b JK	317	struct skl_module_pin *m_in_pin;
	318	struct skl_module_pin *m_out_pin;
	319	enum skl_module_type m_type;
	320	enum skl_hw_conn_type hw_conn_type;
	321	enum skl_module_state m_state;
	322	struct skl_pipe *pipe;
	323	struct skl_specific_cfg formats_config;
	324	};
a0ffe48b	325
abb74003 JK	326	struct skl_algo_data {
abb74003 JK	327	u32 param_id;
4ced1827	328	u32 set_params;
abb74003	329	u32 max;
0d682104	330	u32 size;
abb74003 JK	331	char *params;
	332	};
	333
e4e2d2f4 JK	334	struct skl_pipeline {
	335	struct skl_pipe *pipe;
	336	struct list_head node;
	337	};
	338
b8c722dd JK	339	struct skl_module_deferred_bind {
	340	struct skl_module_cfg *src;
	341	struct skl_module_cfg *dst;
	342	struct list_head node;
	343	};
	344
d93f8e55 VK	345	static inline struct skl get_skl_ctx(struct device dev)
	346	{
	347	struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
	348
	349	return ebus_to_skl(ebus);
	350	}
	351
cfb0a873 VK	352	int skl_tplg_be_update_params(struct snd_soc_dai *dai,
cfb0a873 VK	353	struct skl_pipe_params *params);
c115fa5e D	354	int skl_dsp_set_dma_control(struct skl_sst *ctx,
c115fa5e D	355	struct skl_module_cfg *mconfig);
cfb0a873 VK	356	void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
	357	struct skl_pipe_params *params, int stream);
	358	int skl_tplg_init(struct snd_soc_platform *platform,
	359	struct hdac_ext_bus *ebus);
	360	struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
	361	struct snd_soc_dai *dai, int stream);
	362	int skl_tplg_update_pipe_params(struct device *dev,
	363	struct skl_module_cfg mconfig, struct skl_pipe_params params);
	364
a83e3b4c VK	365	void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps);
	366	void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps);
	367
c9b1e834 JK	368	int skl_create_pipeline(struct skl_sst ctx, struct skl_pipe pipe);
	369
	370	int skl_run_pipe(struct skl_sst ctx, struct skl_pipe pipe);
	371
	372	int skl_pause_pipe(struct skl_sst ctx, struct skl_pipe pipe);
	373
	374	int skl_delete_pipe(struct skl_sst ctx, struct skl_pipe pipe);
	375
	376	int skl_stop_pipe(struct skl_sst ctx, struct skl_pipe pipe);
	377
2004432f JK	378	int skl_reset_pipe(struct skl_sst ctx, struct skl_pipe pipe);
2004432f JK	379
9939a9c3	380	int skl_init_module(struct skl_sst ctx, struct skl_module_cfg module_config);
beb73b26 JK	381
	382	int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
	383	src_module, struct skl_module_cfg dst_module);
	384
	385	int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
	386	src_module, struct skl_module_cfg dst_module);
	387
9939a9c3 JK	388	int skl_set_module_params(struct skl_sst ctx, u32 params, int size,
9939a9c3 JK	389	u32 param_id, struct skl_module_cfg *mcfg);
7d9f2911 OA	390	int skl_get_module_params(struct skl_sst ctx, u32 params, int size,
7d9f2911 OA	391	u32 param_id, struct skl_module_cfg *mcfg);
9939a9c3	392
718a42b5 D	393	struct skl_module_cfg skl_tplg_be_get_cpr_module(struct snd_soc_dai dai,
718a42b5 D	394	int stream);
23db472b	395	enum skl_bitdepth skl_get_bit_depth(int params);
ad036bde JK	396	int skl_pcm_host_dma_prepare(struct device *dev,
	397	struct skl_pipe_params *params);
	398	int skl_pcm_link_dma_prepare(struct device *dev,
	399	struct skl_pipe_params *params);
23db472b	400	#endif