[mirror_ubuntu-eoan-kernel.git] / sound / soc / intel / skylake / skl-topology.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  skl_topology.h - Intel HDA Platform topology header file
 *
 *  Copyright (C) 2014-15 Intel Corp
 *  Author: Jeeja KP <jeeja.kp@intel.com>
 *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 */

#ifndef __SKL_TOPOLOGY_H__
#define __SKL_TOPOLOGY_H__

#include <linux/types.h>

#include <sound/hdaudio_ext.h>
#include <sound/soc.h>
#include <uapi/sound/skl-tplg-interface.h>
#include "skl.h"

#define BITS_PER_BYTE 8
#define MAX_TS_GROUPS 8
#define MAX_DMIC_TS_GROUPS 4
#define MAX_FIXED_DMIC_PARAMS_SIZE 727

/* Maximum number of coefficients up down mixer module */
#define UP_DOWN_MIXER_MAX_COEFF		8

#define MODULE_MAX_IN_PINS	8
#define MODULE_MAX_OUT_PINS	8

#define SKL_MIC_CH_SUPPORT	4
#define SKL_MIC_MAX_CH_SUPPORT	8
#define SKL_DEFAULT_MIC_SEL_GAIN	0x3FF
#define SKL_MIC_SEL_SWITCH	0x3

#define SKL_OUTPUT_PIN		0
#define SKL_INPUT_PIN		1
#define SKL_MAX_PATH_CONFIGS	8
#define SKL_MAX_MODULES_IN_PIPE	8
#define SKL_MAX_MODULE_FORMATS		32
#define SKL_MAX_MODULE_RESOURCES	32

enum skl_channel_index {
	SKL_CHANNEL_LEFT = 0,
	SKL_CHANNEL_RIGHT = 1,
	SKL_CHANNEL_CENTER = 2,
	SKL_CHANNEL_LEFT_SURROUND = 3,
	SKL_CHANNEL_CENTER_SURROUND = 3,
	SKL_CHANNEL_RIGHT_SURROUND = 4,
	SKL_CHANNEL_LFE = 7,
	SKL_CHANNEL_INVALID = 0xF,
};

enum skl_bitdepth {
	SKL_DEPTH_8BIT = 8,
	SKL_DEPTH_16BIT = 16,
	SKL_DEPTH_24BIT = 24,
	SKL_DEPTH_32BIT = 32,
	SKL_DEPTH_INVALID
};


enum skl_s_freq {
	SKL_FS_8000 = 8000,
	SKL_FS_11025 = 11025,
	SKL_FS_12000 = 12000,
	SKL_FS_16000 = 16000,
	SKL_FS_22050 = 22050,
	SKL_FS_24000 = 24000,
	SKL_FS_32000 = 32000,
	SKL_FS_44100 = 44100,
	SKL_FS_48000 = 48000,
	SKL_FS_64000 = 64000,
	SKL_FS_88200 = 88200,
	SKL_FS_96000 = 96000,
	SKL_FS_128000 = 128000,
	SKL_FS_176400 = 176400,
	SKL_FS_192000 = 192000,
	SKL_FS_INVALID
};

enum skl_widget_type {
	SKL_WIDGET_VMIXER = 1,
	SKL_WIDGET_MIXER = 2,
	SKL_WIDGET_PGA = 3,
	SKL_WIDGET_MUX = 4
};

struct skl_audio_data_format {
	enum skl_s_freq s_freq;
	enum skl_bitdepth bit_depth;
	u32 channel_map;
	enum skl_ch_cfg ch_cfg;
	enum skl_interleaving interleaving;
	u8 number_of_channels;
	u8 valid_bit_depth;
	u8 sample_type;
	u8 reserved[1];
} __packed;

struct skl_base_cfg {
	u32 cps;
	u32 ibs;
	u32 obs;
	u32 is_pages;
	struct skl_audio_data_format audio_fmt;
};

struct skl_cpr_gtw_cfg {
	u32 node_id;
	u32 dma_buffer_size;
	u32 config_length;
	/* not mandatory; required only for DMIC/I2S */
	u32 config_data[1];
} __packed;

struct skl_dma_control {
	u32 node_id;
	u32 config_length;
	u32 config_data[0];
} __packed;

struct skl_cpr_cfg {
	struct skl_base_cfg base_cfg;
	struct skl_audio_data_format out_fmt;
	u32 cpr_feature_mask;
	struct skl_cpr_gtw_cfg gtw_cfg;
} __packed;

struct skl_cpr_pin_fmt {
	u32 sink_id;
	struct skl_audio_data_format src_fmt;
	struct skl_audio_data_format dst_fmt;
} __packed;

struct skl_src_module_cfg {
	struct skl_base_cfg base_cfg;
	enum skl_s_freq src_cfg;
} __packed;

struct notification_mask {
	u32 notify;
	u32 enable;
} __packed;

struct skl_up_down_mixer_cfg {
	struct skl_base_cfg base_cfg;
	enum skl_ch_cfg out_ch_cfg;
	/* This should be set to 1 if user coefficients are required */
	u32 coeff_sel;
	/* Pass the user coeff in this array */
	s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
	u32 ch_map;
} __packed;

struct skl_algo_cfg {
	struct skl_base_cfg  base_cfg;
	char params[0];
} __packed;

struct skl_base_outfmt_cfg {
	struct skl_base_cfg base_cfg;
	struct skl_audio_data_format out_fmt;
} __packed;

enum skl_dma_type {
	SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
	SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
	SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
	SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
	SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
	SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
	SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
	SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
	SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
};

union skl_ssp_dma_node {
	u8 val;
	struct {
		u8 time_slot_index:4;
		u8 i2s_instance:4;
	} dma_node;
};

union skl_connector_node_id {
	u32 val;
	struct {
		u32 vindex:8;
		u32 dma_type:4;
		u32 rsvd:20;
	} node;
};

struct skl_module_fmt {
	u32 channels;
	u32 s_freq;
	u32 bit_depth;
	u32 valid_bit_depth;
	u32 ch_cfg;
	u32 interleaving_style;
	u32 sample_type;
	u32 ch_map;
};

struct skl_module_cfg;

struct skl_mod_inst_map {
	u16 mod_id;
	u16 inst_id;
};

struct skl_uuid_inst_map {
	u16 inst_id;
	u16 reserved;
	guid_t mod_uuid;
} __packed;

struct skl_kpb_params {
	u32 num_modules;
	union {
		struct skl_mod_inst_map map[0];
		struct skl_uuid_inst_map map_uuid[0];
	} u;
};

struct skl_module_inst_id {
	guid_t mod_uuid;
	int module_id;
	u32 instance_id;
	int pvt_id;
};

enum skl_module_pin_state {
	SKL_PIN_UNBIND = 0,
	SKL_PIN_BIND_DONE = 1,
};

struct skl_module_pin {
	struct skl_module_inst_id id;
	bool is_dynamic;
	bool in_use;
	enum skl_module_pin_state pin_state;
	struct skl_module_cfg *tgt_mcfg;
};

struct skl_specific_cfg {
	u32 set_params;
	u32 param_id;
	u32 caps_size;
	u32 *caps;
};

enum skl_pipe_state {
	SKL_PIPE_INVALID = 0,
	SKL_PIPE_CREATED = 1,
	SKL_PIPE_PAUSED = 2,
	SKL_PIPE_STARTED = 3,
	SKL_PIPE_RESET = 4
};

struct skl_pipe_module {
	struct snd_soc_dapm_widget *w;
	struct list_head node;
};

struct skl_pipe_params {
	u8 host_dma_id;
	u8 link_dma_id;
	u32 ch;
	u32 s_freq;
	u32 s_fmt;
	u8 linktype;
	snd_pcm_format_t format;
	int link_index;
	int stream;
	unsigned int host_bps;
	unsigned int link_bps;
};

struct skl_pipe_fmt {
	u32 freq;
	u8 channels;
	u8 bps;
};

struct skl_pipe_mcfg {
	u8 res_idx;
	u8 fmt_idx;
};

struct skl_path_config {
	u8 mem_pages;
	struct skl_pipe_fmt in_fmt;
	struct skl_pipe_fmt out_fmt;
};

struct skl_pipe {
	u8 ppl_id;
	u8 pipe_priority;
	u16 conn_type;
	u32 memory_pages;
	u8 lp_mode;
	struct skl_pipe_params *p_params;
	enum skl_pipe_state state;
	u8 direction;
	u8 cur_config_idx;
	u8 nr_cfgs;
	struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
	struct list_head w_list;
	bool passthru;
};

enum skl_module_state {
	SKL_MODULE_UNINIT = 0,
	SKL_MODULE_LOADED = 1,
	SKL_MODULE_INIT_DONE = 2,
	SKL_MODULE_BIND_DONE = 3,
	SKL_MODULE_UNLOADED = 4,
};

enum d0i3_capability {
	SKL_D0I3_NONE = 0,
	SKL_D0I3_STREAMING = 1,
	SKL_D0I3_NON_STREAMING = 2,
};

struct skl_module_pin_fmt {
	u8 id;
	struct skl_module_fmt fmt;
};

struct skl_module_iface {
	u8 fmt_idx;
	u8 nr_in_fmt;
	u8 nr_out_fmt;
	struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
	struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
};

struct skl_module_pin_resources {
	u8 pin_index;
	u32 buf_size;
};

struct skl_module_res {
	u8 id;
	u32 is_pages;
	u32 cps;
	u32 ibs;
	u32 obs;
	u32 dma_buffer_size;
	u32 cpc;
	u8 nr_input_pins;
	u8 nr_output_pins;
	struct skl_module_pin_resources input[MAX_IN_QUEUE];
	struct skl_module_pin_resources output[MAX_OUT_QUEUE];
};

struct skl_module {
	guid_t uuid;
	u8 loadable;
	u8 input_pin_type;
	u8 output_pin_type;
	u8 max_input_pins;
	u8 max_output_pins;
	u8 nr_resources;
	u8 nr_interfaces;
	struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
	struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
};

struct skl_module_cfg {
	u8 guid[16];
	struct skl_module_inst_id id;
	struct skl_module *module;
	int res_idx;
	int fmt_idx;
	u8 domain;
	bool homogenous_inputs;
	bool homogenous_outputs;
	struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
	struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
	u8 max_in_queue;
	u8 max_out_queue;
	u8 in_queue_mask;
	u8 out_queue_mask;
	u8 in_queue;
	u8 out_queue;
	u32 mcps;
	u32 ibs;
	u32 obs;
	u8 is_loadable;
	u8 core_id;
	u8 dev_type;
	u8 dma_id;
	u8 time_slot;
	u8 dmic_ch_combo_index;
	u32 dmic_ch_type;
	u32 params_fixup;
	u32 converter;
	u32 vbus_id;
	u32 mem_pages;
	enum d0i3_capability d0i3_caps;
	u32 dma_buffer_size; /* in milli seconds */
	struct skl_module_pin *m_in_pin;
	struct skl_module_pin *m_out_pin;
	enum skl_module_type m_type;
	enum skl_hw_conn_type  hw_conn_type;
	enum skl_module_state m_state;
	struct skl_pipe *pipe;
	struct skl_specific_cfg formats_config;
	struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
};

struct skl_algo_data {
	u32 param_id;
	u32 set_params;
	u32 max;
	u32 size;
	char *params;
};

struct skl_pipeline {
	struct skl_pipe *pipe;
	struct list_head node;
};

struct skl_module_deferred_bind {
	struct skl_module_cfg *src;
	struct skl_module_cfg *dst;
	struct list_head node;
};

struct skl_mic_sel_config {
	u16 mic_switch;
	u16 flags;
	u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
} __packed;

enum skl_channel {
	SKL_CH_MONO = 1,
	SKL_CH_STEREO = 2,
	SKL_CH_TRIO = 3,
	SKL_CH_QUATRO = 4,
};

static inline struct skl *get_skl_ctx(struct device *dev)
{
	struct hdac_bus *bus = dev_get_drvdata(dev);

	return bus_to_skl(bus);
}

int skl_tplg_be_update_params(struct snd_soc_dai *dai,
	struct skl_pipe_params *params);
int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps,
			u32 caps_size, u32 node_id);
void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
	struct skl_pipe_params *params, int stream);
int skl_tplg_init(struct snd_soc_component *component,
				struct hdac_bus *ebus);
void skl_tplg_exit(struct snd_soc_component *component,
				struct hdac_bus *bus);
struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
		struct snd_soc_dai *dai, int stream);
int skl_tplg_update_pipe_params(struct device *dev,
		struct skl_module_cfg *mconfig, struct skl_pipe_params *params);

void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps);
void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps);

int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);

int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config);

int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
	*src_module, struct skl_module_cfg *dst_module);

int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
	*src_module, struct skl_module_cfg *dst_module);

int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
			u32 param_id, struct skl_module_cfg *mcfg);
int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
			  u32 param_id, struct skl_module_cfg *mcfg);

struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
								int stream);
enum skl_bitdepth skl_get_bit_depth(int params);
int skl_pcm_host_dma_prepare(struct device *dev,
			struct skl_pipe_params *params);
int skl_pcm_link_dma_prepare(struct device *dev,
			struct skl_pipe_params *params);

int skl_dai_load(struct snd_soc_component *cmp, int index,
		struct snd_soc_dai_driver *dai_drv,
		struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai);
void skl_tplg_add_moduleid_in_bind_params(struct skl *skl,
				struct snd_soc_dapm_widget *w);
#endif
Commit	Line	Data
8e8e69d6	1	/* SPDX-License-Identifier: GPL-2.0-only */
23db472b JK	2	/*
	3	* skl_topology.h - Intel HDA Platform topology header file
	4	*
	5	* Copyright (C) 2014-15 Intel Corp
	6	* Author: Jeeja KP <jeeja.kp@intel.com>
	7	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	8	*
23db472b	9	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
23db472b JK	10	*/
	11
	12	#ifndef __SKL_TOPOLOGY_H__
	13	#define __SKL_TOPOLOGY_H__
	14
	15	#include <linux/types.h>
	16
	17	#include <sound/hdaudio_ext.h>
	18	#include <sound/soc.h>
0c24fdc0	19	#include <uapi/sound/skl-tplg-interface.h>
23db472b	20	#include "skl.h"
23db472b JK	21
	22	#define BITS_PER_BYTE 8
	23	#define MAX_TS_GROUPS 8
	24	#define MAX_DMIC_TS_GROUPS 4
	25	#define MAX_FIXED_DMIC_PARAMS_SIZE 727
	26
	27	/* Maximum number of coefficients up down mixer module */
3e1b96c8	28	#define UP_DOWN_MIXER_MAX_COEFF 8
23db472b	29
4cd9899f HS	30	#define MODULE_MAX_IN_PINS 8
	31	#define MODULE_MAX_OUT_PINS 8
	32
7a1b749b D	33	#define SKL_MIC_CH_SUPPORT 4
	34	#define SKL_MIC_MAX_CH_SUPPORT 8
	35	#define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF
	36	#define SKL_MIC_SEL_SWITCH 0x3
	37
822c3b04 SN	38	#define SKL_OUTPUT_PIN 0
	39	#define SKL_INPUT_PIN 1
	40	#define SKL_MAX_PATH_CONFIGS 8
	41	#define SKL_MAX_MODULES_IN_PIPE 8
	42	#define SKL_MAX_MODULE_FORMATS 32
	43	#define SKL_MAX_MODULE_RESOURCES 32
	44
23db472b JK	45	enum skl_channel_index {
	46	SKL_CHANNEL_LEFT = 0,
	47	SKL_CHANNEL_RIGHT = 1,
	48	SKL_CHANNEL_CENTER = 2,
	49	SKL_CHANNEL_LEFT_SURROUND = 3,
	50	SKL_CHANNEL_CENTER_SURROUND = 3,
	51	SKL_CHANNEL_RIGHT_SURROUND = 4,
	52	SKL_CHANNEL_LFE = 7,
	53	SKL_CHANNEL_INVALID = 0xF,
	54	};
	55
	56	enum skl_bitdepth {
	57	SKL_DEPTH_8BIT = 8,
	58	SKL_DEPTH_16BIT = 16,
	59	SKL_DEPTH_24BIT = 24,
	60	SKL_DEPTH_32BIT = 32,
	61	SKL_DEPTH_INVALID
	62	};
	63
23db472b JK	64
	65	enum skl_s_freq {
	66	SKL_FS_8000 = 8000,
	67	SKL_FS_11025 = 11025,
	68	SKL_FS_12000 = 12000,
	69	SKL_FS_16000 = 16000,
	70	SKL_FS_22050 = 22050,
	71	SKL_FS_24000 = 24000,
	72	SKL_FS_32000 = 32000,
	73	SKL_FS_44100 = 44100,
	74	SKL_FS_48000 = 48000,
	75	SKL_FS_64000 = 64000,
	76	SKL_FS_88200 = 88200,
	77	SKL_FS_96000 = 96000,
	78	SKL_FS_128000 = 128000,
	79	SKL_FS_176400 = 176400,
	80	SKL_FS_192000 = 192000,
	81	SKL_FS_INVALID
	82	};
	83
	84	enum skl_widget_type {
	85	SKL_WIDGET_VMIXER = 1,
	86	SKL_WIDGET_MIXER = 2,
	87	SKL_WIDGET_PGA = 3,
	88	SKL_WIDGET_MUX = 4
	89	};
	90
	91	struct skl_audio_data_format {
	92	enum skl_s_freq s_freq;
	93	enum skl_bitdepth bit_depth;
	94	u32 channel_map;
	95	enum skl_ch_cfg ch_cfg;
	96	enum skl_interleaving interleaving;
	97	u8 number_of_channels;
	98	u8 valid_bit_depth;
	99	u8 sample_type;
	100	u8 reserved[1];
	101	} __packed;
	102
	103	struct skl_base_cfg {
	104	u32 cps;
	105	u32 ibs;
	106	u32 obs;
	107	u32 is_pages;
	108	struct skl_audio_data_format audio_fmt;
	109	};
	110
	111	struct skl_cpr_gtw_cfg {
	112	u32 node_id;
	113	u32 dma_buffer_size;
	114	u32 config_length;
	115	/* not mandatory; required only for DMIC/I2S */
	116	u32 config_data[1];
	117	} __packed;
	118
c115fa5e D	119	struct skl_dma_control {
	120	u32 node_id;
	121	u32 config_length;
0b6d76bb	122	u32 config_data[0];
c115fa5e D	123	} __packed;
c115fa5e D	124
23db472b JK	125	struct skl_cpr_cfg {
	126	struct skl_base_cfg base_cfg;
	127	struct skl_audio_data_format out_fmt;
	128	u32 cpr_feature_mask;
	129	struct skl_cpr_gtw_cfg gtw_cfg;
	130	} __packed;
	131
38a77085 PT	132	struct skl_cpr_pin_fmt {
	133	u32 sink_id;
	134	struct skl_audio_data_format src_fmt;
	135	struct skl_audio_data_format dst_fmt;
	136	} __packed;
a0ffe48b HS	137
	138	struct skl_src_module_cfg {
	139	struct skl_base_cfg base_cfg;
	140	enum skl_s_freq src_cfg;
	141	} __packed;
	142
4e10996b JK	143	struct notification_mask {
	144	u32 notify;
	145	u32 enable;
	146	} __packed;
	147
a0ffe48b HS	148	struct skl_up_down_mixer_cfg {
	149	struct skl_base_cfg base_cfg;
	150	enum skl_ch_cfg out_ch_cfg;
	151	/* This should be set to 1 if user coefficients are required */
	152	u32 coeff_sel;
	153	/* Pass the user coeff in this array */
	154	s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
da3417fe	155	u32 ch_map;
a0ffe48b HS	156	} __packed;
a0ffe48b HS	157
399b210b JK	158	struct skl_algo_cfg {
	159	struct skl_base_cfg base_cfg;
	160	char params[0];
	161	} __packed;
	162
fd18110f D	163	struct skl_base_outfmt_cfg {
	164	struct skl_base_cfg base_cfg;
	165	struct skl_audio_data_format out_fmt;
	166	} __packed;
	167
23db472b JK	168	enum skl_dma_type {
	169	SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
	170	SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
	171	SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
	172	SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
	173	SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
	174	SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
	175	SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
	176	SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
	177	SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
	178	};
	179
	180	union skl_ssp_dma_node {
	181	u8 val;
	182	struct {
d7b18813	183	u8 time_slot_index:4;
23db472b JK	184	u8 i2s_instance:4;
	185	} dma_node;
	186	};
	187
	188	union skl_connector_node_id {
	189	u32 val;
	190	struct {
	191	u32 vindex:8;
	192	u32 dma_type:4;
	193	u32 rsvd:20;
	194	} node;
	195	};
	196
	197	struct skl_module_fmt {
	198	u32 channels;
	199	u32 s_freq;
	200	u32 bit_depth;
	201	u32 valid_bit_depth;
	202	u32 ch_cfg;
4cd9899f HS	203	u32 interleaving_style;
	204	u32 sample_type;
	205	u32 ch_map;
23db472b JK	206	};
23db472b JK	207
4f745708 JK	208	struct skl_module_cfg;
4f745708 JK	209
5e8f0ee4 D	210	struct skl_mod_inst_map {
	211	u16 mod_id;
	212	u16 inst_id;
	213	};
	214
24ada035 MB	215	struct skl_uuid_inst_map {
	216	u16 inst_id;
	217	u16 reserved;
9e0784d0	218	guid_t mod_uuid;
24ada035 MB	219	} __packed;
24ada035 MB	220
5e8f0ee4 D	221	struct skl_kpb_params {
5e8f0ee4 D	222	u32 num_modules;
24ada035 MB	223	union {
	224	struct skl_mod_inst_map map[0];
	225	struct skl_uuid_inst_map map_uuid[0];
	226	} u;
5e8f0ee4 D	227	};
5e8f0ee4 D	228
23db472b	229	struct skl_module_inst_id {
9e0784d0	230	guid_t mod_uuid;
b7c50555	231	int module_id;
23db472b	232	u32 instance_id;
700a9a63	233	int pvt_id;
23db472b JK	234	};
23db472b JK	235
4f745708 JK	236	enum skl_module_pin_state {
	237	SKL_PIN_UNBIND = 0,
	238	SKL_PIN_BIND_DONE = 1,
	239	};
	240
23db472b JK	241	struct skl_module_pin {
23db472b JK	242	struct skl_module_inst_id id;
23db472b JK	243	bool is_dynamic;
23db472b JK	244	bool in_use;
4f745708 JK	245	enum skl_module_pin_state pin_state;
4f745708 JK	246	struct skl_module_cfg *tgt_mcfg;
23db472b JK	247	};
	248
	249	struct skl_specific_cfg {
4ced1827	250	u32 set_params;
abb74003	251	u32 param_id;
23db472b JK	252	u32 caps_size;
	253	u32 *caps;
	254	};
	255
	256	enum skl_pipe_state {
	257	SKL_PIPE_INVALID = 0,
	258	SKL_PIPE_CREATED = 1,
	259	SKL_PIPE_PAUSED = 2,
2004432f JK	260	SKL_PIPE_STARTED = 3,
2004432f JK	261	SKL_PIPE_RESET = 4
23db472b JK	262	};
	263
	264	struct skl_pipe_module {
	265	struct snd_soc_dapm_widget *w;
	266	struct list_head node;
	267	};
	268
	269	struct skl_pipe_params {
	270	u8 host_dma_id;
	271	u8 link_dma_id;
	272	u32 ch;
	273	u32 s_freq;
	274	u32 s_fmt;
	275	u8 linktype;
12c3be0e JK	276	snd_pcm_format_t format;
12c3be0e JK	277	int link_index;
23db472b	278	int stream;
7f975a38 JK	279	unsigned int host_bps;
7f975a38 JK	280	unsigned int link_bps;
23db472b JK	281	};
23db472b JK	282
f6fa56e2 RB	283	struct skl_pipe_fmt {
	284	u32 freq;
	285	u8 channels;
	286	u8 bps;
	287	};
	288
	289	struct skl_pipe_mcfg {
	290	u8 res_idx;
	291	u8 fmt_idx;
	292	};
	293
	294	struct skl_path_config {
	295	u8 mem_pages;
	296	struct skl_pipe_fmt in_fmt;
	297	struct skl_pipe_fmt out_fmt;
	298	};
	299
23db472b JK	300	struct skl_pipe {
	301	u8 ppl_id;
	302	u8 pipe_priority;
	303	u16 conn_type;
	304	u32 memory_pages;
8a0cb236	305	u8 lp_mode;
23db472b JK	306	struct skl_pipe_params *p_params;
23db472b JK	307	enum skl_pipe_state state;
f6fa56e2 RB	308	u8 direction;
	309	u8 cur_config_idx;
	310	u8 nr_cfgs;
	311	struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
23db472b	312	struct list_head w_list;
f0aa94fa	313	bool passthru;
23db472b JK	314	};
	315
	316	enum skl_module_state {
	317	SKL_MODULE_UNINIT = 0,
d643678b JK	318	SKL_MODULE_LOADED = 1,
	319	SKL_MODULE_INIT_DONE = 2,
	320	SKL_MODULE_BIND_DONE = 3,
	321	SKL_MODULE_UNLOADED = 4,
23db472b JK	322	};
23db472b JK	323
6bd9dcf3 VK	324	enum d0i3_capability {
	325	SKL_D0I3_NONE = 0,
	326	SKL_D0I3_STREAMING = 1,
	327	SKL_D0I3_NON_STREAMING = 2,
	328	};
	329
822c3b04 SN	330	struct skl_module_pin_fmt {
	331	u8 id;
	332	struct skl_module_fmt fmt;
	333	};
	334
	335	struct skl_module_iface {
	336	u8 fmt_idx;
	337	u8 nr_in_fmt;
	338	u8 nr_out_fmt;
	339	struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
	340	struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
	341	};
	342
	343	struct skl_module_pin_resources {
	344	u8 pin_index;
	345	u32 buf_size;
	346	};
	347
	348	struct skl_module_res {
	349	u8 id;
	350	u32 is_pages;
	351	u32 cps;
	352	u32 ibs;
	353	u32 obs;
	354	u32 dma_buffer_size;
	355	u32 cpc;
	356	u8 nr_input_pins;
	357	u8 nr_output_pins;
	358	struct skl_module_pin_resources input[MAX_IN_QUEUE];
	359	struct skl_module_pin_resources output[MAX_OUT_QUEUE];
	360	};
	361
	362	struct skl_module {
9e0784d0	363	guid_t uuid;
822c3b04 SN	364	u8 loadable;
	365	u8 input_pin_type;
	366	u8 output_pin_type;
	367	u8 max_input_pins;
	368	u8 max_output_pins;
	369	u8 nr_resources;
	370	u8 nr_interfaces;
	371	struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
	372	struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
	373	};
	374
23db472b	375	struct skl_module_cfg {
09305da9	376	u8 guid[16];
23db472b	377	struct skl_module_inst_id id;
f6fa56e2 RB	378	struct skl_module *module;
	379	int res_idx;
	380	int fmt_idx;
04afbbbb	381	u8 domain;
4cd9899f HS	382	bool homogenous_inputs;
	383	bool homogenous_outputs;
	384	struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
	385	struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
23db472b JK	386	u8 max_in_queue;
	387	u8 max_out_queue;
	388	u8 in_queue_mask;
	389	u8 out_queue_mask;
	390	u8 in_queue;
	391	u8 out_queue;
	392	u32 mcps;
	393	u32 ibs;
	394	u32 obs;
	395	u8 is_loadable;
	396	u8 core_id;
	397	u8 dev_type;
	398	u8 dma_id;
	399	u8 time_slot;
7a1b749b D	400	u8 dmic_ch_combo_index;
7a1b749b D	401	u32 dmic_ch_type;
23db472b JK	402	u32 params_fixup;
	403	u32 converter;
	404	u32 vbus_id;
b18c458d	405	u32 mem_pages;
6bd9dcf3	406	enum d0i3_capability d0i3_caps;
939df3ad	407	u32 dma_buffer_size; /* in milli seconds */
23db472b JK	408	struct skl_module_pin *m_in_pin;
	409	struct skl_module_pin *m_out_pin;
	410	enum skl_module_type m_type;
	411	enum skl_hw_conn_type hw_conn_type;
	412	enum skl_module_state m_state;
	413	struct skl_pipe *pipe;
	414	struct skl_specific_cfg formats_config;
f6fa56e2	415	struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
23db472b	416	};
a0ffe48b	417
abb74003 JK	418	struct skl_algo_data {
abb74003 JK	419	u32 param_id;
4ced1827	420	u32 set_params;
abb74003	421	u32 max;
0d682104	422	u32 size;
abb74003 JK	423	char *params;
	424	};
	425
e4e2d2f4 JK	426	struct skl_pipeline {
	427	struct skl_pipe *pipe;
	428	struct list_head node;
	429	};
	430
b8c722dd JK	431	struct skl_module_deferred_bind {
	432	struct skl_module_cfg *src;
	433	struct skl_module_cfg *dst;
	434	struct list_head node;
	435	};
	436
7a1b749b D	437	struct skl_mic_sel_config {
	438	u16 mic_switch;
	439	u16 flags;
	440	u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
	441	} __packed;
	442
	443	enum skl_channel {
	444	SKL_CH_MONO = 1,
	445	SKL_CH_STEREO = 2,
	446	SKL_CH_TRIO = 3,
	447	SKL_CH_QUATRO = 4,
	448	};
	449
d93f8e55 VK	450	static inline struct skl get_skl_ctx(struct device dev)
d93f8e55 VK	451	{
76f56fae	452	struct hdac_bus *bus = dev_get_drvdata(dev);
d93f8e55	453
76f56fae	454	return bus_to_skl(bus);
d93f8e55 VK	455	}
d93f8e55 VK	456
cfb0a873 VK	457	int skl_tplg_be_update_params(struct snd_soc_dai *dai,
cfb0a873 VK	458	struct skl_pipe_params *params);
5514830d JN	459	int skl_dsp_set_dma_control(struct skl_sst ctx, u32 caps,
5514830d JN	460	u32 caps_size, u32 node_id);
cfb0a873 VK	461	void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
cfb0a873 VK	462	struct skl_pipe_params *params, int stream);
24ada035	463	int skl_tplg_init(struct snd_soc_component *component,
76f56fae	464	struct hdac_bus *ebus);
e79986ce AS	465	void skl_tplg_exit(struct snd_soc_component *component,
e79986ce AS	466	struct hdac_bus *bus);
cfb0a873 VK	467	struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
	468	struct snd_soc_dai *dai, int stream);
	469	int skl_tplg_update_pipe_params(struct device *dev,
	470	struct skl_module_cfg mconfig, struct skl_pipe_params params);
	471
a83e3b4c VK	472	void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps);
	473	void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps);
	474
c9b1e834 JK	475	int skl_create_pipeline(struct skl_sst ctx, struct skl_pipe pipe);
	476
	477	int skl_run_pipe(struct skl_sst ctx, struct skl_pipe pipe);
	478
	479	int skl_pause_pipe(struct skl_sst ctx, struct skl_pipe pipe);
	480
	481	int skl_delete_pipe(struct skl_sst ctx, struct skl_pipe pipe);
	482
	483	int skl_stop_pipe(struct skl_sst ctx, struct skl_pipe pipe);
	484
2004432f JK	485	int skl_reset_pipe(struct skl_sst ctx, struct skl_pipe pipe);
2004432f JK	486
9939a9c3	487	int skl_init_module(struct skl_sst ctx, struct skl_module_cfg module_config);
beb73b26 JK	488
	489	int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
	490	src_module, struct skl_module_cfg dst_module);
	491
	492	int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
	493	src_module, struct skl_module_cfg dst_module);
	494
9939a9c3 JK	495	int skl_set_module_params(struct skl_sst ctx, u32 params, int size,
9939a9c3 JK	496	u32 param_id, struct skl_module_cfg *mcfg);
7d9f2911 OA	497	int skl_get_module_params(struct skl_sst ctx, u32 params, int size,
7d9f2911 OA	498	u32 param_id, struct skl_module_cfg *mcfg);
9939a9c3	499
718a42b5 D	500	struct skl_module_cfg skl_tplg_be_get_cpr_module(struct snd_soc_dai dai,
718a42b5 D	501	int stream);
23db472b	502	enum skl_bitdepth skl_get_bit_depth(int params);
ad036bde JK	503	int skl_pcm_host_dma_prepare(struct device *dev,
	504	struct skl_pipe_params *params);
	505	int skl_pcm_link_dma_prepare(struct device *dev,
	506	struct skl_pipe_params *params);
606e21fd	507
c60b613a LG	508	int skl_dai_load(struct snd_soc_component *cmp, int index,
	509	struct snd_soc_dai_driver *dai_drv,
	510	struct snd_soc_tplg_pcm pcm, struct snd_soc_dai dai);
24ada035 MB	511	void skl_tplg_add_moduleid_in_bind_params(struct skl *skl,
24ada035 MB	512	struct snd_soc_dapm_widget *w);
23db472b	513	#endif