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d8c2dab8 JK |
1 | /* |
2 | * skl.c - Implementation of ASoC Intel SKL HD Audio driver | |
3 | * | |
4 | * Copyright (C) 2014-2015 Intel Corp | |
5 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
6 | * | |
7 | * Derived mostly from Intel HDA driver with following copyrights: | |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
9 | * PeiSen Hou <pshou@realtek.com.tw> | |
10 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; version 2 of the License. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/platform_device.h> | |
d8018361 | 28 | #include <linux/firmware.h> |
a26a3f53 | 29 | #include <linux/delay.h> |
d8c2dab8 | 30 | #include <sound/pcm.h> |
7feb2f78 | 31 | #include <sound/soc-acpi.h> |
cbaa7f0b | 32 | #include <sound/soc-acpi-intel-match.h> |
6980c057 VK |
33 | #include <sound/hda_register.h> |
34 | #include <sound/hdaudio.h> | |
35 | #include <sound/hda_i915.h> | |
00deadb5 | 36 | #include <sound/hda_codec.h> |
d8c2dab8 | 37 | #include "skl.h" |
0c8ba9d2 J |
38 | #include "skl-sst-dsp.h" |
39 | #include "skl-sst-ipc.h" | |
8c4e7c2e | 40 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
6bae5ea9 | 41 | #include "../../../soc/codecs/hdac_hda.h" |
8c4e7c2e | 42 | #endif |
d82b51c8 PLB |
43 | static int skl_pci_binding; |
44 | module_param_named(pci_binding, skl_pci_binding, int, 0444); | |
45 | MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc"); | |
d8c2dab8 JK |
46 | |
47 | /* | |
48 | * initialize the PCI registers | |
49 | */ | |
50 | static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
51 | unsigned char mask, unsigned char val) | |
52 | { | |
53 | unsigned char data; | |
54 | ||
55 | pci_read_config_byte(pci, reg, &data); | |
56 | data &= ~mask; | |
57 | data |= (val & mask); | |
58 | pci_write_config_byte(pci, reg, data); | |
59 | } | |
60 | ||
61 | static void skl_init_pci(struct skl *skl) | |
62 | { | |
76f56fae | 63 | struct hdac_bus *bus = skl_to_bus(skl); |
d8c2dab8 JK |
64 | |
65 | /* | |
66 | * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
67 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
68 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
69 | * codecs. | |
70 | * The PCI register TCSEL is defined in the Intel manuals. | |
71 | */ | |
76f56fae | 72 | dev_dbg(bus->dev, "Clearing TCSEL\n"); |
d8c2dab8 JK |
73 | skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); |
74 | } | |
75 | ||
0c8ba9d2 J |
76 | static void update_pci_dword(struct pci_dev *pci, |
77 | unsigned int reg, u32 mask, u32 val) | |
78 | { | |
79 | u32 data = 0; | |
80 | ||
81 | pci_read_config_dword(pci, reg, &data); | |
82 | data &= ~mask; | |
83 | data |= (val & mask); | |
84 | pci_write_config_dword(pci, reg, data); | |
85 | } | |
86 | ||
87 | /* | |
88 | * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits | |
89 | * | |
90 | * @dev: device pointer | |
91 | * @enable: enable/disable flag | |
92 | */ | |
93 | static void skl_enable_miscbdcge(struct device *dev, bool enable) | |
94 | { | |
95 | struct pci_dev *pci = to_pci_dev(dev); | |
96 | u32 val; | |
97 | ||
98 | val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; | |
99 | ||
100 | update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); | |
101 | } | |
102 | ||
fc9fdd61 SK |
103 | /** |
104 | * skl_clock_power_gating: Enable/Disable clock and power gating | |
105 | * | |
106 | * @dev: Device pointer | |
107 | * @enable: Enable/Disable flag | |
108 | */ | |
109 | static void skl_clock_power_gating(struct device *dev, bool enable) | |
110 | { | |
111 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 112 | struct hdac_bus *bus = pci_get_drvdata(pci); |
fc9fdd61 SK |
113 | u32 val; |
114 | ||
115 | /* Update PDCGE bit of CGCTL register */ | |
116 | val = enable ? AZX_CGCTL_ADSPDCGE : 0; | |
117 | update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); | |
118 | ||
119 | /* Update L1SEN bit of EM2 register */ | |
120 | val = enable ? AZX_REG_VS_EM2_L1SEN : 0; | |
121 | snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); | |
122 | ||
123 | /* Update ADSPPGD bit of PGCTL register */ | |
124 | val = enable ? 0 : AZX_PGCTL_ADSPPGD; | |
125 | update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); | |
126 | } | |
127 | ||
0c8ba9d2 J |
128 | /* |
129 | * While performing reset, controller may not come back properly causing | |
130 | * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset | |
131 | * (init chip) and then again set CGCTL.MISCBDCGE to 1 | |
132 | */ | |
133 | static int skl_init_chip(struct hdac_bus *bus, bool full_reset) | |
134 | { | |
112c60b3 | 135 | struct hdac_ext_link *hlink; |
0c8ba9d2 J |
136 | int ret; |
137 | ||
138 | skl_enable_miscbdcge(bus->dev, false); | |
139 | ret = snd_hdac_bus_init_chip(bus, full_reset); | |
112c60b3 RU |
140 | |
141 | /* Reset stream-to-link mapping */ | |
76f56fae | 142 | list_for_each_entry(hlink, &bus->hlink_list, list) |
112c60b3 RU |
143 | bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); |
144 | ||
0c8ba9d2 J |
145 | skl_enable_miscbdcge(bus->dev, true); |
146 | ||
147 | return ret; | |
148 | } | |
149 | ||
a26a3f53 PS |
150 | void skl_update_d0i3c(struct device *dev, bool enable) |
151 | { | |
152 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 153 | struct hdac_bus *bus = pci_get_drvdata(pci); |
a26a3f53 PS |
154 | u8 reg; |
155 | int timeout = 50; | |
156 | ||
157 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
158 | /* Do not write to D0I3C until command in progress bit is cleared */ | |
159 | while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { | |
160 | udelay(10); | |
161 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
162 | } | |
163 | ||
164 | /* Highly unlikely. But if it happens, flag error explicitly */ | |
165 | if (!timeout) { | |
166 | dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); | |
167 | return; | |
168 | } | |
169 | ||
170 | if (enable) | |
171 | reg = reg | AZX_REG_VS_D0I3C_I3; | |
172 | else | |
173 | reg = reg & (~AZX_REG_VS_D0I3C_I3); | |
174 | ||
175 | snd_hdac_chip_writeb(bus, VS_D0I3C, reg); | |
176 | ||
177 | timeout = 50; | |
178 | /* Wait for cmd in progress to be cleared before exiting the function */ | |
179 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
180 | while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { | |
181 | udelay(10); | |
182 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
183 | } | |
184 | ||
185 | /* Highly unlikely. But if it happens, flag error explicitly */ | |
186 | if (!timeout) { | |
187 | dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); | |
188 | return; | |
189 | } | |
190 | ||
191 | dev_dbg(bus->dev, "D0I3C register = 0x%x\n", | |
192 | snd_hdac_chip_readb(bus, VS_D0I3C)); | |
193 | } | |
194 | ||
d8c2dab8 JK |
195 | /* called from IRQ */ |
196 | static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) | |
197 | { | |
198 | snd_pcm_period_elapsed(hstr->substream); | |
199 | } | |
200 | ||
201 | static irqreturn_t skl_interrupt(int irq, void *dev_id) | |
202 | { | |
76f56fae | 203 | struct hdac_bus *bus = dev_id; |
d8c2dab8 JK |
204 | u32 status; |
205 | ||
206 | if (!pm_runtime_active(bus->dev)) | |
207 | return IRQ_NONE; | |
208 | ||
209 | spin_lock(&bus->reg_lock); | |
210 | ||
211 | status = snd_hdac_chip_readl(bus, INTSTS); | |
212 | if (status == 0 || status == 0xffffffff) { | |
213 | spin_unlock(&bus->reg_lock); | |
214 | return IRQ_NONE; | |
215 | } | |
216 | ||
217 | /* clear rirb int */ | |
218 | status = snd_hdac_chip_readb(bus, RIRBSTS); | |
219 | if (status & RIRB_INT_MASK) { | |
220 | if (status & RIRB_INT_RESPONSE) | |
221 | snd_hdac_bus_update_rirb(bus); | |
222 | snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); | |
223 | } | |
224 | ||
225 | spin_unlock(&bus->reg_lock); | |
226 | ||
227 | return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; | |
228 | } | |
229 | ||
230 | static irqreturn_t skl_threaded_handler(int irq, void *dev_id) | |
231 | { | |
76f56fae | 232 | struct hdac_bus *bus = dev_id; |
d8c2dab8 JK |
233 | u32 status; |
234 | ||
235 | status = snd_hdac_chip_readl(bus, INTSTS); | |
236 | ||
237 | snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); | |
238 | ||
239 | return IRQ_HANDLED; | |
240 | } | |
241 | ||
76f56fae | 242 | static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) |
d8c2dab8 | 243 | { |
76f56fae | 244 | struct skl *skl = bus_to_skl(bus); |
d8c2dab8 JK |
245 | int ret; |
246 | ||
247 | ret = request_threaded_irq(skl->pci->irq, skl_interrupt, | |
248 | skl_threaded_handler, | |
249 | IRQF_SHARED, | |
76f56fae | 250 | KBUILD_MODNAME, bus); |
d8c2dab8 JK |
251 | if (ret) { |
252 | dev_err(bus->dev, | |
253 | "unable to grab IRQ %d, disabling device\n", | |
254 | skl->pci->irq); | |
255 | return ret; | |
256 | } | |
257 | ||
258 | bus->irq = skl->pci->irq; | |
259 | pci_intx(skl->pci, 1); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
8b4a133c J |
264 | static int skl_suspend_late(struct device *dev) |
265 | { | |
266 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae RU |
267 | struct hdac_bus *bus = pci_get_drvdata(pci); |
268 | struct skl *skl = bus_to_skl(bus); | |
8b4a133c J |
269 | |
270 | return skl_suspend_late_dsp(skl); | |
271 | } | |
272 | ||
61722f44 | 273 | #ifdef CONFIG_PM |
76f56fae | 274 | static int _skl_suspend(struct hdac_bus *bus) |
61722f44 | 275 | { |
76f56fae | 276 | struct skl *skl = bus_to_skl(bus); |
51a01b8c | 277 | struct pci_dev *pci = to_pci_dev(bus->dev); |
61722f44 JK |
278 | int ret; |
279 | ||
76f56fae | 280 | snd_hdac_ext_bus_link_power_down_all(bus); |
61722f44 JK |
281 | |
282 | ret = skl_suspend_dsp(skl); | |
283 | if (ret < 0) | |
284 | return ret; | |
285 | ||
286 | snd_hdac_bus_stop_chip(bus); | |
51a01b8c D |
287 | update_pci_dword(pci, AZX_PCIREG_PGCTL, |
288 | AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); | |
0c8ba9d2 | 289 | skl_enable_miscbdcge(bus->dev, false); |
61722f44 | 290 | snd_hdac_bus_enter_link_reset(bus); |
0c8ba9d2 | 291 | skl_enable_miscbdcge(bus->dev, true); |
fe3f4442 | 292 | skl_cleanup_resources(skl); |
61722f44 JK |
293 | |
294 | return 0; | |
295 | } | |
296 | ||
76f56fae | 297 | static int _skl_resume(struct hdac_bus *bus) |
61722f44 | 298 | { |
76f56fae | 299 | struct skl *skl = bus_to_skl(bus); |
61722f44 JK |
300 | |
301 | skl_init_pci(skl); | |
0c8ba9d2 | 302 | skl_init_chip(bus, true); |
61722f44 JK |
303 | |
304 | return skl_resume_dsp(skl); | |
305 | } | |
306 | #endif | |
307 | ||
d8c2dab8 JK |
308 | #ifdef CONFIG_PM_SLEEP |
309 | /* | |
310 | * power management | |
311 | */ | |
312 | static int skl_suspend(struct device *dev) | |
313 | { | |
314 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae RU |
315 | struct hdac_bus *bus = pci_get_drvdata(pci); |
316 | struct skl *skl = bus_to_skl(bus); | |
4f799e73 | 317 | int ret; |
d8c2dab8 | 318 | |
4557c305 JK |
319 | /* |
320 | * Do not suspend if streams which are marked ignore suspend are | |
321 | * running, we need to save the state for these and continue | |
322 | */ | |
323 | if (skl->supend_active) { | |
cce6c149 | 324 | /* turn off the links and stop the CORB/RIRB DMA if it is On */ |
76f56fae | 325 | snd_hdac_ext_bus_link_power_down_all(bus); |
cce6c149 | 326 | |
76f56fae RU |
327 | if (bus->cmd_dma_state) |
328 | snd_hdac_bus_stop_cmd_io(bus); | |
cce6c149 | 329 | |
1f4956fd | 330 | enable_irq_wake(bus->irq); |
4557c305 | 331 | pci_save_state(pci); |
4557c305 | 332 | } else { |
76f56fae | 333 | ret = _skl_suspend(bus); |
af037412 SP |
334 | if (ret < 0) |
335 | return ret; | |
1665c177 | 336 | skl->skl_sst->fw_loaded = false; |
4557c305 | 337 | } |
af037412 | 338 | |
4f799e73 TI |
339 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
340 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); | |
af037412 | 341 | |
4f799e73 | 342 | return 0; |
d8c2dab8 JK |
343 | } |
344 | ||
345 | static int skl_resume(struct device *dev) | |
346 | { | |
347 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae RU |
348 | struct hdac_bus *bus = pci_get_drvdata(pci); |
349 | struct skl *skl = bus_to_skl(bus); | |
cce6c149 | 350 | struct hdac_ext_link *hlink = NULL; |
4557c305 JK |
351 | int ret; |
352 | ||
6980c057 | 353 | /* Turned OFF in HDMI codec driver after codec reconfiguration */ |
4f799e73 TI |
354 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
355 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); | |
6980c057 | 356 | |
4557c305 JK |
357 | /* |
358 | * resume only when we are not in suspend active, otherwise need to | |
359 | * restore the device | |
360 | */ | |
361 | if (skl->supend_active) { | |
362 | pci_restore_state(pci); | |
76f56fae | 363 | snd_hdac_ext_bus_link_power_up_all(bus); |
1f4956fd | 364 | disable_irq_wake(bus->irq); |
cce6c149 VK |
365 | /* |
366 | * turn On the links which are On before active suspend | |
367 | * and start the CORB/RIRB DMA if On before | |
368 | * active suspend. | |
369 | */ | |
76f56fae | 370 | list_for_each_entry(hlink, &bus->hlink_list, list) { |
cce6c149 VK |
371 | if (hlink->ref_count) |
372 | snd_hdac_ext_bus_link_power_up(hlink); | |
373 | } | |
374 | ||
cc20c4df | 375 | ret = 0; |
76f56fae RU |
376 | if (bus->cmd_dma_state) |
377 | snd_hdac_bus_init_cmd_io(bus); | |
4557c305 | 378 | } else { |
76f56fae | 379 | ret = _skl_resume(bus); |
cce6c149 VK |
380 | |
381 | /* turn off the links which are off before suspend */ | |
76f56fae | 382 | list_for_each_entry(hlink, &bus->hlink_list, list) { |
cce6c149 VK |
383 | if (!hlink->ref_count) |
384 | snd_hdac_ext_bus_link_power_down(hlink); | |
385 | } | |
386 | ||
76f56fae RU |
387 | if (!bus->cmd_dma_state) |
388 | snd_hdac_bus_stop_cmd_io(bus); | |
4557c305 | 389 | } |
d8c2dab8 | 390 | |
4557c305 | 391 | return ret; |
d8c2dab8 JK |
392 | } |
393 | #endif /* CONFIG_PM_SLEEP */ | |
394 | ||
395 | #ifdef CONFIG_PM | |
396 | static int skl_runtime_suspend(struct device *dev) | |
397 | { | |
398 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 399 | struct hdac_bus *bus = pci_get_drvdata(pci); |
d8c2dab8 JK |
400 | |
401 | dev_dbg(bus->dev, "in %s\n", __func__); | |
402 | ||
76f56fae | 403 | return _skl_suspend(bus); |
d8c2dab8 JK |
404 | } |
405 | ||
406 | static int skl_runtime_resume(struct device *dev) | |
407 | { | |
408 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 409 | struct hdac_bus *bus = pci_get_drvdata(pci); |
d8c2dab8 JK |
410 | |
411 | dev_dbg(bus->dev, "in %s\n", __func__); | |
412 | ||
76f56fae | 413 | return _skl_resume(bus); |
d8c2dab8 JK |
414 | } |
415 | #endif /* CONFIG_PM */ | |
416 | ||
417 | static const struct dev_pm_ops skl_pm = { | |
418 | SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) | |
419 | SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) | |
8b4a133c | 420 | .suspend_late = skl_suspend_late, |
d8c2dab8 JK |
421 | }; |
422 | ||
423 | /* | |
424 | * destructor | |
425 | */ | |
76f56fae | 426 | static int skl_free(struct hdac_bus *bus) |
d8c2dab8 | 427 | { |
76f56fae | 428 | struct skl *skl = bus_to_skl(bus); |
d8c2dab8 | 429 | |
ab1b732d | 430 | skl->init_done = 0; /* to be sure */ |
d8c2dab8 | 431 | |
76f56fae | 432 | snd_hdac_ext_stop_streams(bus); |
d8c2dab8 JK |
433 | |
434 | if (bus->irq >= 0) | |
76f56fae | 435 | free_irq(bus->irq, (void *)bus); |
d8c2dab8 | 436 | snd_hdac_bus_free_stream_pages(bus); |
76f56fae RU |
437 | snd_hdac_stream_free_all(bus); |
438 | snd_hdac_link_free_all(bus); | |
077411e5 VK |
439 | |
440 | if (bus->remap_addr) | |
441 | iounmap(bus->remap_addr); | |
442 | ||
d8c2dab8 JK |
443 | pci_release_regions(skl->pci); |
444 | pci_disable_device(skl->pci); | |
445 | ||
76f56fae | 446 | snd_hdac_ext_bus_exit(bus); |
d8c2dab8 | 447 | |
ab1b732d | 448 | cancel_work_sync(&skl->probe_work); |
5b2fe898 | 449 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
76f56fae | 450 | snd_hdac_i915_exit(bus); |
ab1b732d | 451 | |
d8c2dab8 JK |
452 | return 0; |
453 | } | |
454 | ||
bc2bd45b SP |
455 | /* |
456 | * For each ssp there are 3 clocks (mclk/sclk/sclkfs). | |
457 | * e.g. for ssp0, clocks will be named as | |
458 | * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" | |
459 | * So for skl+, there are 6 ssps, so 18 clocks will be created. | |
460 | */ | |
461 | static struct skl_ssp_clk skl_ssp_clks[] = { | |
462 | {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, | |
463 | {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, | |
464 | {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, | |
465 | {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, | |
466 | {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, | |
467 | {.name = "ssp2_sclkfs"}, | |
468 | {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, | |
469 | {.name = "ssp5_sclkfs"}, | |
470 | }; | |
471 | ||
9cdae435 RU |
472 | static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl *skl, |
473 | struct snd_soc_acpi_mach *machines) | |
474 | { | |
475 | struct hdac_bus *bus = skl_to_bus(skl); | |
476 | struct snd_soc_acpi_mach *mach; | |
477 | ||
478 | /* check if we have any codecs detected on bus */ | |
479 | if (bus->codec_mask == 0) | |
480 | return NULL; | |
481 | ||
482 | /* point to common table */ | |
483 | mach = snd_soc_acpi_intel_hda_machines; | |
484 | ||
485 | /* all entries in the machine table use the same firmware */ | |
486 | mach->fw_filename = machines->fw_filename; | |
487 | ||
488 | return mach; | |
489 | } | |
490 | ||
752c93aa | 491 | static int skl_find_machine(struct skl *skl, void *driver_data) |
cc18c5fd | 492 | { |
76f56fae | 493 | struct hdac_bus *bus = skl_to_bus(skl); |
7feb2f78 | 494 | struct snd_soc_acpi_mach *mach = driver_data; |
752c93aa | 495 | struct skl_machine_pdata *pdata; |
cc18c5fd | 496 | |
7feb2f78 | 497 | mach = snd_soc_acpi_find_machine(mach); |
9cdae435 RU |
498 | if (!mach) { |
499 | dev_dbg(bus->dev, "No matching I2S machine driver found\n"); | |
500 | mach = skl_find_hda_machine(skl, driver_data); | |
501 | if (!mach) { | |
502 | dev_err(bus->dev, "No matching machine driver found\n"); | |
503 | return -ENODEV; | |
504 | } | |
cc18c5fd | 505 | } |
752c93aa PB |
506 | |
507 | skl->mach = mach; | |
aecf6fd8 | 508 | skl->fw_name = mach->fw_filename; |
5f15f267 | 509 | pdata = mach->pdata; |
752c93aa | 510 | |
5f15f267 | 511 | if (pdata) { |
752c93aa | 512 | skl->use_tplg_pcm = pdata->use_tplg_pcm; |
b92826fa | 513 | mach->mach_params.dmic_num = skl_get_dmic_geo(skl); |
5f15f267 | 514 | } |
752c93aa PB |
515 | |
516 | return 0; | |
517 | } | |
518 | ||
519 | static int skl_machine_device_register(struct skl *skl) | |
520 | { | |
752c93aa | 521 | struct snd_soc_acpi_mach *mach = skl->mach; |
9cdae435 | 522 | struct hdac_bus *bus = skl_to_bus(skl); |
752c93aa PB |
523 | struct platform_device *pdev; |
524 | int ret; | |
cc18c5fd VK |
525 | |
526 | pdev = platform_device_alloc(mach->drv_name, -1); | |
527 | if (pdev == NULL) { | |
528 | dev_err(bus->dev, "platform device alloc failed\n"); | |
529 | return -EIO; | |
530 | } | |
531 | ||
5a619b9e PLB |
532 | mach->mach_params.platform = dev_name(bus->dev); |
533 | mach->mach_params.codec_mask = bus->codec_mask; | |
534 | ||
535 | ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach)); | |
536 | if (ret) { | |
537 | dev_err(bus->dev, "failed to add machine device platform data\n"); | |
538 | platform_device_put(pdev); | |
539 | return ret; | |
540 | } | |
541 | ||
cc18c5fd VK |
542 | ret = platform_device_add(pdev); |
543 | if (ret) { | |
544 | dev_err(bus->dev, "failed to add machine device\n"); | |
545 | platform_device_put(pdev); | |
546 | return -EIO; | |
547 | } | |
f65cf7d6 | 548 | |
f65cf7d6 | 549 | |
cc18c5fd VK |
550 | skl->i2s_dev = pdev; |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | static void skl_machine_device_unregister(struct skl *skl) | |
556 | { | |
557 | if (skl->i2s_dev) | |
558 | platform_device_unregister(skl->i2s_dev); | |
559 | } | |
560 | ||
d8c2dab8 JK |
561 | static int skl_dmic_device_register(struct skl *skl) |
562 | { | |
76f56fae | 563 | struct hdac_bus *bus = skl_to_bus(skl); |
d8c2dab8 JK |
564 | struct platform_device *pdev; |
565 | int ret; | |
566 | ||
567 | /* SKL has one dmic port, so allocate dmic device for this */ | |
568 | pdev = platform_device_alloc("dmic-codec", -1); | |
569 | if (!pdev) { | |
570 | dev_err(bus->dev, "failed to allocate dmic device\n"); | |
571 | return -ENOMEM; | |
572 | } | |
573 | ||
574 | ret = platform_device_add(pdev); | |
575 | if (ret) { | |
576 | dev_err(bus->dev, "failed to add dmic device: %d\n", ret); | |
577 | platform_device_put(pdev); | |
578 | return ret; | |
579 | } | |
580 | skl->dmic_dev = pdev; | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | static void skl_dmic_device_unregister(struct skl *skl) | |
586 | { | |
587 | if (skl->dmic_dev) | |
588 | platform_device_unregister(skl->dmic_dev); | |
589 | } | |
590 | ||
bc2bd45b SP |
591 | static struct skl_clk_parent_src skl_clk_src[] = { |
592 | { .clk_id = SKL_XTAL, .name = "xtal" }, | |
593 | { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, | |
594 | { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, | |
595 | }; | |
596 | ||
597 | struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) | |
598 | { | |
599 | unsigned int i; | |
600 | ||
601 | for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { | |
602 | if (skl_clk_src[i].clk_id == clk_id) | |
603 | return &skl_clk_src[i]; | |
604 | } | |
605 | ||
606 | return NULL; | |
607 | } | |
608 | ||
8e79ec98 | 609 | static void init_skl_xtal_rate(int pci_id) |
bc2bd45b SP |
610 | { |
611 | switch (pci_id) { | |
612 | case 0x9d70: | |
613 | case 0x9d71: | |
614 | skl_clk_src[0].rate = 24000000; | |
615 | return; | |
616 | ||
617 | default: | |
618 | skl_clk_src[0].rate = 19200000; | |
619 | return; | |
620 | } | |
621 | } | |
622 | ||
623 | static int skl_clock_device_register(struct skl *skl) | |
624 | { | |
625 | struct platform_device_info pdevinfo = {NULL}; | |
626 | struct skl_clk_pdata *clk_pdata; | |
627 | ||
628 | clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), | |
629 | GFP_KERNEL); | |
630 | if (!clk_pdata) | |
631 | return -ENOMEM; | |
632 | ||
633 | init_skl_xtal_rate(skl->pci->device); | |
634 | ||
635 | clk_pdata->parent_clks = skl_clk_src; | |
636 | clk_pdata->ssp_clks = skl_ssp_clks; | |
637 | clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); | |
638 | ||
639 | /* Query NHLT to fill the rates and parent */ | |
640 | skl_get_clks(skl, clk_pdata->ssp_clks); | |
641 | clk_pdata->pvt_data = skl; | |
642 | ||
643 | /* Register Platform device */ | |
644 | pdevinfo.parent = &skl->pci->dev; | |
645 | pdevinfo.id = -1; | |
646 | pdevinfo.name = "skl-ssp-clk"; | |
647 | pdevinfo.data = clk_pdata; | |
648 | pdevinfo.size_data = sizeof(*clk_pdata); | |
649 | skl->clk_dev = platform_device_register_full(&pdevinfo); | |
650 | return PTR_ERR_OR_ZERO(skl->clk_dev); | |
651 | } | |
652 | ||
653 | static void skl_clock_device_unregister(struct skl *skl) | |
654 | { | |
655 | if (skl->clk_dev) | |
656 | platform_device_unregister(skl->clk_dev); | |
657 | } | |
658 | ||
8c4e7c2e PLB |
659 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
660 | ||
6bae5ea9 RU |
661 | #define IDISP_INTEL_VENDOR_ID 0x80860000 |
662 | ||
663 | /* | |
664 | * load the legacy codec driver | |
665 | */ | |
666 | static void load_codec_module(struct hda_codec *codec) | |
667 | { | |
668 | #ifdef MODULE | |
669 | char modalias[MODULE_NAME_LEN]; | |
670 | const char *mod = NULL; | |
671 | ||
672 | snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); | |
673 | mod = modalias; | |
674 | dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); | |
675 | request_module(mod); | |
676 | #endif | |
677 | } | |
678 | ||
8c4e7c2e PLB |
679 | #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ |
680 | ||
d8c2dab8 JK |
681 | /* |
682 | * Probe the given codec address | |
683 | */ | |
76f56fae | 684 | static int probe_codec(struct hdac_bus *bus, int addr) |
d8c2dab8 | 685 | { |
d8c2dab8 JK |
686 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | |
687 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
e6a33532 | 688 | unsigned int res = -1; |
6298542f | 689 | struct skl *skl = bus_to_skl(bus); |
8c4e7c2e | 690 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
6bae5ea9 | 691 | struct hdac_hda_priv *hda_codec; |
6bae5ea9 | 692 | int err; |
8c4e7c2e PLB |
693 | #endif |
694 | struct hdac_device *hdev; | |
d8c2dab8 JK |
695 | |
696 | mutex_lock(&bus->cmd_mutex); | |
697 | snd_hdac_bus_send_cmd(bus, cmd); | |
698 | snd_hdac_bus_get_response(bus, addr, &res); | |
699 | mutex_unlock(&bus->cmd_mutex); | |
700 | if (res == -1) | |
701 | return -EIO; | |
00deadb5 | 702 | dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); |
d8c2dab8 | 703 | |
8c4e7c2e | 704 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
6bae5ea9 RU |
705 | hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), |
706 | GFP_KERNEL); | |
707 | if (!hda_codec) | |
6298542f RU |
708 | return -ENOMEM; |
709 | ||
6bae5ea9 RU |
710 | hda_codec->codec.bus = skl_to_hbus(skl); |
711 | hdev = &hda_codec->codec.core; | |
712 | ||
713 | err = snd_hdac_ext_bus_device_init(bus, addr, hdev); | |
714 | if (err < 0) | |
715 | return err; | |
716 | ||
717 | /* use legacy bus only for HDA codecs, idisp uses ext bus */ | |
718 | if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { | |
719 | hdev->type = HDA_DEV_LEGACY; | |
720 | load_codec_module(&hda_codec->codec); | |
721 | } | |
722 | return 0; | |
8c4e7c2e PLB |
723 | #else |
724 | hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); | |
725 | if (!hdev) | |
726 | return -ENOMEM; | |
727 | ||
728 | return snd_hdac_ext_bus_device_init(bus, addr, hdev); | |
729 | #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ | |
d8c2dab8 JK |
730 | } |
731 | ||
732 | /* Codec initialization */ | |
76f56fae | 733 | static void skl_codec_create(struct hdac_bus *bus) |
d8c2dab8 | 734 | { |
d8c2dab8 JK |
735 | int c, max_slots; |
736 | ||
737 | max_slots = HDA_MAX_CODECS; | |
738 | ||
739 | /* First try to probe all given codec slots */ | |
740 | for (c = 0; c < max_slots; c++) { | |
741 | if ((bus->codec_mask & (1 << c))) { | |
76f56fae | 742 | if (probe_codec(bus, c) < 0) { |
d8c2dab8 JK |
743 | /* |
744 | * Some BIOSen give you wrong codec addresses | |
745 | * that don't exist | |
746 | */ | |
747 | dev_warn(bus->dev, | |
748 | "Codec #%d probe error; disabling it...\n", c); | |
749 | bus->codec_mask &= ~(1 << c); | |
750 | /* | |
751 | * More badly, accessing to a non-existing | |
752 | * codec often screws up the controller bus, | |
753 | * and disturbs the further communications. | |
754 | * Thus if an error occurs during probing, | |
755 | * better to reset the controller bus to get | |
756 | * back to the sanity state. | |
757 | */ | |
758 | snd_hdac_bus_stop_chip(bus); | |
0c8ba9d2 | 759 | skl_init_chip(bus, true); |
d8c2dab8 JK |
760 | } |
761 | } | |
762 | } | |
d8c2dab8 JK |
763 | } |
764 | ||
765 | static const struct hdac_bus_ops bus_core_ops = { | |
766 | .command = snd_hdac_bus_send_cmd, | |
767 | .get_response = snd_hdac_bus_get_response, | |
768 | }; | |
769 | ||
ab1b732d VK |
770 | static int skl_i915_init(struct hdac_bus *bus) |
771 | { | |
772 | int err; | |
773 | ||
774 | /* | |
775 | * The HDMI codec is in GPU so we need to ensure that it is powered | |
776 | * up and ready for probe | |
777 | */ | |
778 | err = snd_hdac_i915_init(bus); | |
779 | if (err < 0) | |
780 | return err; | |
781 | ||
4f799e73 | 782 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); |
ab1b732d | 783 | |
4f799e73 | 784 | return 0; |
ab1b732d VK |
785 | } |
786 | ||
787 | static void skl_probe_work(struct work_struct *work) | |
788 | { | |
789 | struct skl *skl = container_of(work, struct skl, probe_work); | |
76f56fae | 790 | struct hdac_bus *bus = skl_to_bus(skl); |
ab1b732d VK |
791 | struct hdac_ext_link *hlink = NULL; |
792 | int err; | |
793 | ||
794 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { | |
795 | err = skl_i915_init(bus); | |
796 | if (err < 0) | |
797 | return; | |
798 | } | |
799 | ||
800 | err = skl_init_chip(bus, true); | |
801 | if (err < 0) { | |
802 | dev_err(bus->dev, "Init chip failed with err: %d\n", err); | |
803 | goto out_err; | |
804 | } | |
805 | ||
806 | /* codec detection */ | |
807 | if (!bus->codec_mask) | |
808 | dev_info(bus->dev, "no hda codecs found!\n"); | |
809 | ||
810 | /* create codec instances */ | |
76f56fae | 811 | skl_codec_create(bus); |
ab1b732d | 812 | |
752c93aa PB |
813 | /* register platform dai and controls */ |
814 | err = skl_platform_register(bus->dev); | |
815 | if (err < 0) { | |
816 | dev_err(bus->dev, "platform register failed: %d\n", err); | |
817 | return; | |
818 | } | |
819 | ||
7f981bdc PLB |
820 | err = skl_machine_device_register(skl); |
821 | if (err < 0) { | |
822 | dev_err(bus->dev, "machine register failed: %d\n", err); | |
823 | goto out_err; | |
752c93aa PB |
824 | } |
825 | ||
4c10473d PLB |
826 | /* |
827 | * we are done probing so decrement link counts | |
828 | */ | |
829 | list_for_each_entry(hlink, &bus->hlink_list, list) | |
830 | snd_hdac_ext_bus_link_put(bus, hlink); | |
831 | ||
4f799e73 TI |
832 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
833 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); | |
ab1b732d | 834 | |
ab1b732d VK |
835 | /* configure PM */ |
836 | pm_runtime_put_noidle(bus->dev); | |
837 | pm_runtime_allow(bus->dev); | |
838 | skl->init_done = 1; | |
839 | ||
840 | return; | |
841 | ||
842 | out_err: | |
843 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) | |
4f799e73 | 844 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); |
ab1b732d VK |
845 | } |
846 | ||
d8c2dab8 JK |
847 | /* |
848 | * constructor | |
849 | */ | |
850 | static int skl_create(struct pci_dev *pci, | |
851 | const struct hdac_io_ops *io_ops, | |
852 | struct skl **rskl) | |
853 | { | |
6bae5ea9 | 854 | struct hdac_ext_bus_ops *ext_ops = NULL; |
d8c2dab8 | 855 | struct skl *skl; |
76f56fae | 856 | struct hdac_bus *bus; |
00deadb5 | 857 | struct hda_bus *hbus; |
d8c2dab8 JK |
858 | int err; |
859 | ||
860 | *rskl = NULL; | |
861 | ||
862 | err = pci_enable_device(pci); | |
863 | if (err < 0) | |
864 | return err; | |
865 | ||
866 | skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); | |
867 | if (!skl) { | |
868 | pci_disable_device(pci); | |
869 | return -ENOMEM; | |
870 | } | |
76f56fae | 871 | |
00deadb5 | 872 | hbus = skl_to_hbus(skl); |
76f56fae | 873 | bus = skl_to_bus(skl); |
6bae5ea9 | 874 | |
8c4e7c2e | 875 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
6bae5ea9 RU |
876 | ext_ops = snd_soc_hdac_hda_get_ops(); |
877 | #endif | |
878 | snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, io_ops, ext_ops); | |
76f56fae | 879 | bus->use_posbuf = 1; |
d8c2dab8 | 880 | skl->pci = pci; |
ab1b732d | 881 | INIT_WORK(&skl->probe_work, skl_probe_work); |
76f56fae | 882 | bus->bdl_pos_adj = 0; |
d8c2dab8 | 883 | |
00deadb5 RU |
884 | mutex_init(&hbus->prepare_mutex); |
885 | hbus->pci = pci; | |
886 | hbus->mixer_assigned = -1; | |
887 | hbus->modelname = "sklbus"; | |
888 | ||
d8c2dab8 JK |
889 | *rskl = skl; |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
76f56fae | 894 | static int skl_first_init(struct hdac_bus *bus) |
d8c2dab8 | 895 | { |
76f56fae | 896 | struct skl *skl = bus_to_skl(bus); |
d8c2dab8 JK |
897 | struct pci_dev *pci = skl->pci; |
898 | int err; | |
899 | unsigned short gcap; | |
900 | int cp_streams, pb_streams, start_idx; | |
901 | ||
902 | err = pci_request_regions(pci, "Skylake HD audio"); | |
903 | if (err < 0) | |
904 | return err; | |
905 | ||
906 | bus->addr = pci_resource_start(pci, 0); | |
907 | bus->remap_addr = pci_ioremap_bar(pci, 0); | |
908 | if (bus->remap_addr == NULL) { | |
909 | dev_err(bus->dev, "ioremap error\n"); | |
910 | return -ENXIO; | |
911 | } | |
912 | ||
75383f8d | 913 | snd_hdac_bus_reset_link(bus, true); |
60767abc | 914 | |
ec8ae570 | 915 | snd_hdac_bus_parse_capabilities(bus); |
05057001 | 916 | |
fa11ab56 PLB |
917 | /* check if PPCAP exists */ |
918 | if (!bus->ppcap) { | |
919 | dev_err(bus->dev, "bus ppcap not set, HDaudio or DSP not present?\n"); | |
920 | return -ENODEV; | |
921 | } | |
922 | ||
542cedec YZ |
923 | if (skl_acquire_irq(bus, 0) < 0) |
924 | return -EBUSY; | |
925 | ||
d8c2dab8 | 926 | pci_set_master(pci); |
542cedec | 927 | synchronize_irq(bus->irq); |
d8c2dab8 JK |
928 | |
929 | gcap = snd_hdac_chip_readw(bus, GCAP); | |
930 | dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); | |
931 | ||
d8c2dab8 JK |
932 | /* read number of streams from GCAP register */ |
933 | cp_streams = (gcap >> 8) & 0x0f; | |
934 | pb_streams = (gcap >> 12) & 0x0f; | |
935 | ||
fa11ab56 PLB |
936 | if (!pb_streams && !cp_streams) { |
937 | dev_err(bus->dev, "no streams found in GCAP definitions?\n"); | |
d8c2dab8 | 938 | return -EIO; |
fa11ab56 | 939 | } |
d8c2dab8 | 940 | |
76f56fae | 941 | bus->num_streams = cp_streams + pb_streams; |
d8c2dab8 | 942 | |
fa11ab56 PLB |
943 | /* allow 64bit DMA address if supported by H/W */ |
944 | if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { | |
945 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); | |
946 | } else { | |
947 | dma_set_mask(bus->dev, DMA_BIT_MASK(32)); | |
948 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); | |
949 | } | |
950 | ||
d8c2dab8 JK |
951 | /* initialize streams */ |
952 | snd_hdac_ext_stream_init_all | |
76f56fae | 953 | (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); |
d8c2dab8 JK |
954 | start_idx = cp_streams; |
955 | snd_hdac_ext_stream_init_all | |
76f56fae | 956 | (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); |
d8c2dab8 JK |
957 | |
958 | err = snd_hdac_bus_alloc_stream_pages(bus); | |
959 | if (err < 0) | |
960 | return err; | |
961 | ||
962 | /* initialize chip */ | |
963 | skl_init_pci(skl); | |
964 | ||
ab1b732d | 965 | return skl_init_chip(bus, true); |
d8c2dab8 JK |
966 | } |
967 | ||
968 | static int skl_probe(struct pci_dev *pci, | |
969 | const struct pci_device_id *pci_id) | |
970 | { | |
971 | struct skl *skl; | |
d8c2dab8 JK |
972 | struct hdac_bus *bus = NULL; |
973 | int err; | |
974 | ||
d82b51c8 PLB |
975 | switch (skl_pci_binding) { |
976 | case SND_SKL_PCI_BIND_AUTO: | |
977 | /* | |
978 | * detect DSP by checking class/subclass/prog-id information | |
979 | * class=04 subclass 03 prog-if 00: no DSP, use legacy driver | |
980 | * class=04 subclass 01 prog-if 00: DSP is present | |
981 | * (and may be required e.g. for DMIC or SSP support) | |
982 | * class=04 subclass 03 prog-if 80: use DSP or legacy mode | |
983 | */ | |
984 | if (pci->class == 0x040300) { | |
985 | dev_info(&pci->dev, "The DSP is not enabled on this platform, aborting probe\n"); | |
986 | return -ENODEV; | |
987 | } | |
988 | if (pci->class != 0x040100 && pci->class != 0x040380) { | |
989 | dev_err(&pci->dev, "Unknown PCI class/subclass/prog-if information (0x%06x) found, aborting probe\n", pci->class); | |
990 | return -ENODEV; | |
991 | } | |
992 | dev_info(&pci->dev, "DSP detected with PCI class/subclass/prog-if info 0x%06x\n", pci->class); | |
993 | break; | |
994 | case SND_SKL_PCI_BIND_LEGACY: | |
995 | dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, aborting probe\n"); | |
996 | return -ENODEV; | |
997 | case SND_SKL_PCI_BIND_ASOC: | |
998 | dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n"); | |
999 | break; | |
1000 | default: | |
1001 | dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n"); | |
1002 | break; | |
1003 | } | |
1004 | ||
d8c2dab8 JK |
1005 | /* we use ext core ops, so provide NULL for ops here */ |
1006 | err = skl_create(pci, NULL, &skl); | |
1007 | if (err < 0) | |
1008 | return err; | |
1009 | ||
76f56fae | 1010 | bus = skl_to_bus(skl); |
d8c2dab8 | 1011 | |
76f56fae | 1012 | err = skl_first_init(bus); |
f231c34c PLB |
1013 | if (err < 0) { |
1014 | dev_err(bus->dev, "skl_first_init failed with err: %d\n", err); | |
d8c2dab8 | 1015 | goto out_free; |
f231c34c | 1016 | } |
d8c2dab8 | 1017 | |
4b235c43 VK |
1018 | skl->pci_id = pci->device; |
1019 | ||
2e9dc2b6 VK |
1020 | device_disable_async_suspend(bus->dev); |
1021 | ||
87b2bdf0 JK |
1022 | skl->nhlt = skl_nhlt_init(bus->dev); |
1023 | ||
979cf59a | 1024 | if (skl->nhlt == NULL) { |
f231c34c PLB |
1025 | #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
1026 | dev_err(bus->dev, "no nhlt info found\n"); | |
979cf59a | 1027 | err = -ENODEV; |
ab1b732d | 1028 | goto out_free; |
f231c34c PLB |
1029 | #else |
1030 | dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDaudio codec\n"); | |
1031 | #endif | |
1032 | } else { | |
0cf5a171 | 1033 | |
f231c34c PLB |
1034 | err = skl_nhlt_create_sysfs(skl); |
1035 | if (err < 0) { | |
1036 | dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err); | |
1037 | goto out_nhlt_free; | |
1038 | } | |
4b235c43 | 1039 | |
f231c34c | 1040 | skl_nhlt_update_topology_bin(skl); |
d8c2dab8 | 1041 | |
bc2bd45b SP |
1042 | /* create device for dsp clk */ |
1043 | err = skl_clock_device_register(skl); | |
f231c34c PLB |
1044 | if (err < 0) { |
1045 | dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err); | |
bc2bd45b | 1046 | goto out_clk_free; |
f231c34c PLB |
1047 | } |
1048 | } | |
bc2bd45b | 1049 | |
76f56fae | 1050 | pci_set_drvdata(skl->pci, bus); |
cc18c5fd | 1051 | |
bc2bd45b | 1052 | |
7f981bdc | 1053 | err = skl_find_machine(skl, (void *)pci_id->driver_data); |
f231c34c PLB |
1054 | if (err < 0) { |
1055 | dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err); | |
7f981bdc | 1056 | goto out_nhlt_free; |
f231c34c | 1057 | } |
cc18c5fd | 1058 | |
7f981bdc PLB |
1059 | err = skl_init_dsp(skl); |
1060 | if (err < 0) { | |
1061 | dev_dbg(bus->dev, "error failed to register dsp\n"); | |
1062 | goto out_nhlt_free; | |
05057001 | 1063 | } |
7f981bdc PLB |
1064 | skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; |
1065 | skl->skl_sst->clock_power_gating = skl_clock_power_gating; | |
1066 | ||
ec8ae570 | 1067 | if (bus->mlcap) |
76f56fae | 1068 | snd_hdac_ext_bus_get_ml_capabilities(bus); |
05057001 | 1069 | |
ab1b732d VK |
1070 | snd_hdac_bus_stop_chip(bus); |
1071 | ||
d8c2dab8 JK |
1072 | /* create device for soc dmic */ |
1073 | err = skl_dmic_device_register(skl); | |
f231c34c PLB |
1074 | if (err < 0) { |
1075 | dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err); | |
2a29b200 | 1076 | goto out_dsp_free; |
f231c34c | 1077 | } |
d8c2dab8 | 1078 | |
ab1b732d | 1079 | schedule_work(&skl->probe_work); |
d8c2dab8 JK |
1080 | |
1081 | return 0; | |
1082 | ||
2a29b200 JK |
1083 | out_dsp_free: |
1084 | skl_free_dsp(skl); | |
bc2bd45b SP |
1085 | out_clk_free: |
1086 | skl_clock_device_unregister(skl); | |
c286b3f9 JK |
1087 | out_nhlt_free: |
1088 | skl_nhlt_free(skl->nhlt); | |
d8c2dab8 | 1089 | out_free: |
76f56fae | 1090 | skl_free(bus); |
d8c2dab8 JK |
1091 | |
1092 | return err; | |
1093 | } | |
1094 | ||
c5a76a24 JK |
1095 | static void skl_shutdown(struct pci_dev *pci) |
1096 | { | |
76f56fae | 1097 | struct hdac_bus *bus = pci_get_drvdata(pci); |
c5a76a24 JK |
1098 | struct hdac_stream *s; |
1099 | struct hdac_ext_stream *stream; | |
1100 | struct skl *skl; | |
1101 | ||
76f56fae | 1102 | if (!bus) |
c5a76a24 JK |
1103 | return; |
1104 | ||
76f56fae | 1105 | skl = bus_to_skl(bus); |
c5a76a24 | 1106 | |
ab1b732d | 1107 | if (!skl->init_done) |
c5a76a24 JK |
1108 | return; |
1109 | ||
76f56fae | 1110 | snd_hdac_ext_stop_streams(bus); |
c5a76a24 JK |
1111 | list_for_each_entry(s, &bus->stream_list, list) { |
1112 | stream = stream_to_hdac_ext_stream(s); | |
76f56fae | 1113 | snd_hdac_ext_stream_decouple(bus, stream, false); |
c5a76a24 JK |
1114 | } |
1115 | ||
1116 | snd_hdac_bus_stop_chip(bus); | |
1117 | } | |
1118 | ||
d8c2dab8 JK |
1119 | static void skl_remove(struct pci_dev *pci) |
1120 | { | |
76f56fae RU |
1121 | struct hdac_bus *bus = pci_get_drvdata(pci); |
1122 | struct skl *skl = bus_to_skl(bus); | |
d8c2dab8 | 1123 | |
1b00126c | 1124 | release_firmware(skl->tplg); |
d8018361 | 1125 | |
6d13f62d | 1126 | pm_runtime_get_noresume(&pci->dev); |
7373f481 VK |
1127 | |
1128 | /* codec removal, invoke bus_device_remove */ | |
76f56fae | 1129 | snd_hdac_ext_bus_device_remove(bus); |
7373f481 | 1130 | |
5cdf6c09 | 1131 | skl->debugfs = NULL; |
d8c2dab8 | 1132 | skl_platform_unregister(&pci->dev); |
2a29b200 | 1133 | skl_free_dsp(skl); |
cc18c5fd | 1134 | skl_machine_device_unregister(skl); |
d8c2dab8 | 1135 | skl_dmic_device_unregister(skl); |
bc2bd45b | 1136 | skl_clock_device_unregister(skl); |
0cf5a171 | 1137 | skl_nhlt_remove_sysfs(skl); |
c286b3f9 | 1138 | skl_nhlt_free(skl->nhlt); |
76f56fae | 1139 | skl_free(bus); |
d8c2dab8 JK |
1140 | dev_set_drvdata(&pci->dev, NULL); |
1141 | } | |
1142 | ||
1143 | /* PCI IDs */ | |
1144 | static const struct pci_device_id skl_ids[] = { | |
35bc99aa | 1145 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL) |
d8c2dab8 | 1146 | /* Sunrise Point-LP */ |
cc18c5fd | 1147 | { PCI_DEVICE(0x8086, 0x9d70), |
cbaa7f0b | 1148 | .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, |
35bc99aa PLB |
1149 | #endif |
1150 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL) | |
b379b1fa SV |
1151 | /* BXT-P */ |
1152 | { PCI_DEVICE(0x8086, 0x5a98), | |
cbaa7f0b | 1153 | .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, |
35bc99aa PLB |
1154 | #endif |
1155 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL) | |
451dfb5f VK |
1156 | /* KBL */ |
1157 | { PCI_DEVICE(0x8086, 0x9D71), | |
cbaa7f0b | 1158 | .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, |
35bc99aa PLB |
1159 | #endif |
1160 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK) | |
25504863 VK |
1161 | /* GLK */ |
1162 | { PCI_DEVICE(0x8086, 0x3198), | |
cbaa7f0b | 1163 | .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, |
35bc99aa PLB |
1164 | #endif |
1165 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL) | |
86d7ce3d GS |
1166 | /* CNL */ |
1167 | { PCI_DEVICE(0x8086, 0x9dc8), | |
cbaa7f0b | 1168 | .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, |
35bc99aa PLB |
1169 | #endif |
1170 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL) | |
e6b98db9 TI |
1171 | /* CFL */ |
1172 | { PCI_DEVICE(0x8086, 0xa348), | |
1173 | .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, | |
35bc99aa | 1174 | #endif |
d8c2dab8 JK |
1175 | { 0, } |
1176 | }; | |
1177 | MODULE_DEVICE_TABLE(pci, skl_ids); | |
1178 | ||
1179 | /* pci_driver definition */ | |
1180 | static struct pci_driver skl_driver = { | |
1181 | .name = KBUILD_MODNAME, | |
1182 | .id_table = skl_ids, | |
1183 | .probe = skl_probe, | |
1184 | .remove = skl_remove, | |
c5a76a24 | 1185 | .shutdown = skl_shutdown, |
d8c2dab8 JK |
1186 | .driver = { |
1187 | .pm = &skl_pm, | |
1188 | }, | |
1189 | }; | |
1190 | module_pci_driver(skl_driver); | |
1191 | ||
1192 | MODULE_LICENSE("GPL v2"); | |
1193 | MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); |