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d8c2dab8 JK |
1 | /* |
2 | * skl.c - Implementation of ASoC Intel SKL HD Audio driver | |
3 | * | |
4 | * Copyright (C) 2014-2015 Intel Corp | |
5 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
6 | * | |
7 | * Derived mostly from Intel HDA driver with following copyrights: | |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
9 | * PeiSen Hou <pshou@realtek.com.tw> | |
10 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; version 2 of the License. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/platform_device.h> | |
d8018361 | 28 | #include <linux/firmware.h> |
a26a3f53 | 29 | #include <linux/delay.h> |
d8c2dab8 | 30 | #include <sound/pcm.h> |
7feb2f78 | 31 | #include <sound/soc-acpi.h> |
cbaa7f0b | 32 | #include <sound/soc-acpi-intel-match.h> |
6980c057 VK |
33 | #include <sound/hda_register.h> |
34 | #include <sound/hdaudio.h> | |
35 | #include <sound/hda_i915.h> | |
d8c2dab8 | 36 | #include "skl.h" |
0c8ba9d2 J |
37 | #include "skl-sst-dsp.h" |
38 | #include "skl-sst-ipc.h" | |
d8c2dab8 JK |
39 | |
40 | /* | |
41 | * initialize the PCI registers | |
42 | */ | |
43 | static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
44 | unsigned char mask, unsigned char val) | |
45 | { | |
46 | unsigned char data; | |
47 | ||
48 | pci_read_config_byte(pci, reg, &data); | |
49 | data &= ~mask; | |
50 | data |= (val & mask); | |
51 | pci_write_config_byte(pci, reg, data); | |
52 | } | |
53 | ||
54 | static void skl_init_pci(struct skl *skl) | |
55 | { | |
76f56fae | 56 | struct hdac_bus *bus = skl_to_bus(skl); |
d8c2dab8 JK |
57 | |
58 | /* | |
59 | * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
60 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
61 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
62 | * codecs. | |
63 | * The PCI register TCSEL is defined in the Intel manuals. | |
64 | */ | |
76f56fae | 65 | dev_dbg(bus->dev, "Clearing TCSEL\n"); |
d8c2dab8 JK |
66 | skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); |
67 | } | |
68 | ||
0c8ba9d2 J |
69 | static void update_pci_dword(struct pci_dev *pci, |
70 | unsigned int reg, u32 mask, u32 val) | |
71 | { | |
72 | u32 data = 0; | |
73 | ||
74 | pci_read_config_dword(pci, reg, &data); | |
75 | data &= ~mask; | |
76 | data |= (val & mask); | |
77 | pci_write_config_dword(pci, reg, data); | |
78 | } | |
79 | ||
80 | /* | |
81 | * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits | |
82 | * | |
83 | * @dev: device pointer | |
84 | * @enable: enable/disable flag | |
85 | */ | |
86 | static void skl_enable_miscbdcge(struct device *dev, bool enable) | |
87 | { | |
88 | struct pci_dev *pci = to_pci_dev(dev); | |
89 | u32 val; | |
90 | ||
91 | val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; | |
92 | ||
93 | update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); | |
94 | } | |
95 | ||
fc9fdd61 SK |
96 | /** |
97 | * skl_clock_power_gating: Enable/Disable clock and power gating | |
98 | * | |
99 | * @dev: Device pointer | |
100 | * @enable: Enable/Disable flag | |
101 | */ | |
102 | static void skl_clock_power_gating(struct device *dev, bool enable) | |
103 | { | |
104 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 105 | struct hdac_bus *bus = pci_get_drvdata(pci); |
fc9fdd61 SK |
106 | u32 val; |
107 | ||
108 | /* Update PDCGE bit of CGCTL register */ | |
109 | val = enable ? AZX_CGCTL_ADSPDCGE : 0; | |
110 | update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); | |
111 | ||
112 | /* Update L1SEN bit of EM2 register */ | |
113 | val = enable ? AZX_REG_VS_EM2_L1SEN : 0; | |
114 | snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); | |
115 | ||
116 | /* Update ADSPPGD bit of PGCTL register */ | |
117 | val = enable ? 0 : AZX_PGCTL_ADSPPGD; | |
118 | update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); | |
119 | } | |
120 | ||
0c8ba9d2 J |
121 | /* |
122 | * While performing reset, controller may not come back properly causing | |
123 | * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset | |
124 | * (init chip) and then again set CGCTL.MISCBDCGE to 1 | |
125 | */ | |
126 | static int skl_init_chip(struct hdac_bus *bus, bool full_reset) | |
127 | { | |
112c60b3 | 128 | struct hdac_ext_link *hlink; |
0c8ba9d2 J |
129 | int ret; |
130 | ||
131 | skl_enable_miscbdcge(bus->dev, false); | |
132 | ret = snd_hdac_bus_init_chip(bus, full_reset); | |
112c60b3 RU |
133 | |
134 | /* Reset stream-to-link mapping */ | |
76f56fae | 135 | list_for_each_entry(hlink, &bus->hlink_list, list) |
112c60b3 RU |
136 | bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); |
137 | ||
0c8ba9d2 J |
138 | skl_enable_miscbdcge(bus->dev, true); |
139 | ||
140 | return ret; | |
141 | } | |
142 | ||
a26a3f53 PS |
143 | void skl_update_d0i3c(struct device *dev, bool enable) |
144 | { | |
145 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 146 | struct hdac_bus *bus = pci_get_drvdata(pci); |
a26a3f53 PS |
147 | u8 reg; |
148 | int timeout = 50; | |
149 | ||
150 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
151 | /* Do not write to D0I3C until command in progress bit is cleared */ | |
152 | while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { | |
153 | udelay(10); | |
154 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
155 | } | |
156 | ||
157 | /* Highly unlikely. But if it happens, flag error explicitly */ | |
158 | if (!timeout) { | |
159 | dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); | |
160 | return; | |
161 | } | |
162 | ||
163 | if (enable) | |
164 | reg = reg | AZX_REG_VS_D0I3C_I3; | |
165 | else | |
166 | reg = reg & (~AZX_REG_VS_D0I3C_I3); | |
167 | ||
168 | snd_hdac_chip_writeb(bus, VS_D0I3C, reg); | |
169 | ||
170 | timeout = 50; | |
171 | /* Wait for cmd in progress to be cleared before exiting the function */ | |
172 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
173 | while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { | |
174 | udelay(10); | |
175 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
176 | } | |
177 | ||
178 | /* Highly unlikely. But if it happens, flag error explicitly */ | |
179 | if (!timeout) { | |
180 | dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); | |
181 | return; | |
182 | } | |
183 | ||
184 | dev_dbg(bus->dev, "D0I3C register = 0x%x\n", | |
185 | snd_hdac_chip_readb(bus, VS_D0I3C)); | |
186 | } | |
187 | ||
d8c2dab8 JK |
188 | /* called from IRQ */ |
189 | static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) | |
190 | { | |
191 | snd_pcm_period_elapsed(hstr->substream); | |
192 | } | |
193 | ||
194 | static irqreturn_t skl_interrupt(int irq, void *dev_id) | |
195 | { | |
76f56fae | 196 | struct hdac_bus *bus = dev_id; |
d8c2dab8 JK |
197 | u32 status; |
198 | ||
199 | if (!pm_runtime_active(bus->dev)) | |
200 | return IRQ_NONE; | |
201 | ||
202 | spin_lock(&bus->reg_lock); | |
203 | ||
204 | status = snd_hdac_chip_readl(bus, INTSTS); | |
205 | if (status == 0 || status == 0xffffffff) { | |
206 | spin_unlock(&bus->reg_lock); | |
207 | return IRQ_NONE; | |
208 | } | |
209 | ||
210 | /* clear rirb int */ | |
211 | status = snd_hdac_chip_readb(bus, RIRBSTS); | |
212 | if (status & RIRB_INT_MASK) { | |
213 | if (status & RIRB_INT_RESPONSE) | |
214 | snd_hdac_bus_update_rirb(bus); | |
215 | snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); | |
216 | } | |
217 | ||
218 | spin_unlock(&bus->reg_lock); | |
219 | ||
220 | return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; | |
221 | } | |
222 | ||
223 | static irqreturn_t skl_threaded_handler(int irq, void *dev_id) | |
224 | { | |
76f56fae | 225 | struct hdac_bus *bus = dev_id; |
d8c2dab8 JK |
226 | u32 status; |
227 | ||
228 | status = snd_hdac_chip_readl(bus, INTSTS); | |
229 | ||
230 | snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); | |
231 | ||
232 | return IRQ_HANDLED; | |
233 | } | |
234 | ||
76f56fae | 235 | static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) |
d8c2dab8 | 236 | { |
76f56fae | 237 | struct skl *skl = bus_to_skl(bus); |
d8c2dab8 JK |
238 | int ret; |
239 | ||
240 | ret = request_threaded_irq(skl->pci->irq, skl_interrupt, | |
241 | skl_threaded_handler, | |
242 | IRQF_SHARED, | |
76f56fae | 243 | KBUILD_MODNAME, bus); |
d8c2dab8 JK |
244 | if (ret) { |
245 | dev_err(bus->dev, | |
246 | "unable to grab IRQ %d, disabling device\n", | |
247 | skl->pci->irq); | |
248 | return ret; | |
249 | } | |
250 | ||
251 | bus->irq = skl->pci->irq; | |
252 | pci_intx(skl->pci, 1); | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
8b4a133c J |
257 | static int skl_suspend_late(struct device *dev) |
258 | { | |
259 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae RU |
260 | struct hdac_bus *bus = pci_get_drvdata(pci); |
261 | struct skl *skl = bus_to_skl(bus); | |
8b4a133c J |
262 | |
263 | return skl_suspend_late_dsp(skl); | |
264 | } | |
265 | ||
61722f44 | 266 | #ifdef CONFIG_PM |
76f56fae | 267 | static int _skl_suspend(struct hdac_bus *bus) |
61722f44 | 268 | { |
76f56fae | 269 | struct skl *skl = bus_to_skl(bus); |
51a01b8c | 270 | struct pci_dev *pci = to_pci_dev(bus->dev); |
61722f44 JK |
271 | int ret; |
272 | ||
76f56fae | 273 | snd_hdac_ext_bus_link_power_down_all(bus); |
61722f44 JK |
274 | |
275 | ret = skl_suspend_dsp(skl); | |
276 | if (ret < 0) | |
277 | return ret; | |
278 | ||
279 | snd_hdac_bus_stop_chip(bus); | |
51a01b8c D |
280 | update_pci_dword(pci, AZX_PCIREG_PGCTL, |
281 | AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); | |
0c8ba9d2 | 282 | skl_enable_miscbdcge(bus->dev, false); |
61722f44 | 283 | snd_hdac_bus_enter_link_reset(bus); |
0c8ba9d2 | 284 | skl_enable_miscbdcge(bus->dev, true); |
fe3f4442 | 285 | skl_cleanup_resources(skl); |
61722f44 JK |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
76f56fae | 290 | static int _skl_resume(struct hdac_bus *bus) |
61722f44 | 291 | { |
76f56fae | 292 | struct skl *skl = bus_to_skl(bus); |
61722f44 JK |
293 | |
294 | skl_init_pci(skl); | |
0c8ba9d2 | 295 | skl_init_chip(bus, true); |
61722f44 JK |
296 | |
297 | return skl_resume_dsp(skl); | |
298 | } | |
299 | #endif | |
300 | ||
d8c2dab8 JK |
301 | #ifdef CONFIG_PM_SLEEP |
302 | /* | |
303 | * power management | |
304 | */ | |
305 | static int skl_suspend(struct device *dev) | |
306 | { | |
307 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae RU |
308 | struct hdac_bus *bus = pci_get_drvdata(pci); |
309 | struct skl *skl = bus_to_skl(bus); | |
af037412 | 310 | int ret = 0; |
d8c2dab8 | 311 | |
4557c305 JK |
312 | /* |
313 | * Do not suspend if streams which are marked ignore suspend are | |
314 | * running, we need to save the state for these and continue | |
315 | */ | |
316 | if (skl->supend_active) { | |
cce6c149 | 317 | /* turn off the links and stop the CORB/RIRB DMA if it is On */ |
76f56fae | 318 | snd_hdac_ext_bus_link_power_down_all(bus); |
cce6c149 | 319 | |
76f56fae RU |
320 | if (bus->cmd_dma_state) |
321 | snd_hdac_bus_stop_cmd_io(bus); | |
cce6c149 | 322 | |
1f4956fd | 323 | enable_irq_wake(bus->irq); |
4557c305 | 324 | pci_save_state(pci); |
4557c305 | 325 | } else { |
76f56fae | 326 | ret = _skl_suspend(bus); |
af037412 SP |
327 | if (ret < 0) |
328 | return ret; | |
1665c177 | 329 | skl->skl_sst->fw_loaded = false; |
4557c305 | 330 | } |
af037412 SP |
331 | |
332 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { | |
333 | ret = snd_hdac_display_power(bus, false); | |
334 | if (ret < 0) | |
335 | dev_err(bus->dev, | |
336 | "Cannot turn OFF display power on i915\n"); | |
337 | } | |
338 | ||
339 | return ret; | |
d8c2dab8 JK |
340 | } |
341 | ||
342 | static int skl_resume(struct device *dev) | |
343 | { | |
344 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae RU |
345 | struct hdac_bus *bus = pci_get_drvdata(pci); |
346 | struct skl *skl = bus_to_skl(bus); | |
cce6c149 | 347 | struct hdac_ext_link *hlink = NULL; |
4557c305 JK |
348 | int ret; |
349 | ||
6980c057 VK |
350 | /* Turned OFF in HDMI codec driver after codec reconfiguration */ |
351 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { | |
352 | ret = snd_hdac_display_power(bus, true); | |
353 | if (ret < 0) { | |
354 | dev_err(bus->dev, | |
355 | "Cannot turn on display power on i915\n"); | |
356 | return ret; | |
357 | } | |
358 | } | |
359 | ||
4557c305 JK |
360 | /* |
361 | * resume only when we are not in suspend active, otherwise need to | |
362 | * restore the device | |
363 | */ | |
364 | if (skl->supend_active) { | |
365 | pci_restore_state(pci); | |
76f56fae | 366 | snd_hdac_ext_bus_link_power_up_all(bus); |
1f4956fd | 367 | disable_irq_wake(bus->irq); |
cce6c149 VK |
368 | /* |
369 | * turn On the links which are On before active suspend | |
370 | * and start the CORB/RIRB DMA if On before | |
371 | * active suspend. | |
372 | */ | |
76f56fae | 373 | list_for_each_entry(hlink, &bus->hlink_list, list) { |
cce6c149 VK |
374 | if (hlink->ref_count) |
375 | snd_hdac_ext_bus_link_power_up(hlink); | |
376 | } | |
377 | ||
cc20c4df | 378 | ret = 0; |
76f56fae RU |
379 | if (bus->cmd_dma_state) |
380 | snd_hdac_bus_init_cmd_io(bus); | |
4557c305 | 381 | } else { |
76f56fae | 382 | ret = _skl_resume(bus); |
cce6c149 VK |
383 | |
384 | /* turn off the links which are off before suspend */ | |
76f56fae | 385 | list_for_each_entry(hlink, &bus->hlink_list, list) { |
cce6c149 VK |
386 | if (!hlink->ref_count) |
387 | snd_hdac_ext_bus_link_power_down(hlink); | |
388 | } | |
389 | ||
76f56fae RU |
390 | if (!bus->cmd_dma_state) |
391 | snd_hdac_bus_stop_cmd_io(bus); | |
4557c305 | 392 | } |
d8c2dab8 | 393 | |
4557c305 | 394 | return ret; |
d8c2dab8 JK |
395 | } |
396 | #endif /* CONFIG_PM_SLEEP */ | |
397 | ||
398 | #ifdef CONFIG_PM | |
399 | static int skl_runtime_suspend(struct device *dev) | |
400 | { | |
401 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 402 | struct hdac_bus *bus = pci_get_drvdata(pci); |
d8c2dab8 JK |
403 | |
404 | dev_dbg(bus->dev, "in %s\n", __func__); | |
405 | ||
76f56fae | 406 | return _skl_suspend(bus); |
d8c2dab8 JK |
407 | } |
408 | ||
409 | static int skl_runtime_resume(struct device *dev) | |
410 | { | |
411 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 412 | struct hdac_bus *bus = pci_get_drvdata(pci); |
d8c2dab8 JK |
413 | |
414 | dev_dbg(bus->dev, "in %s\n", __func__); | |
415 | ||
76f56fae | 416 | return _skl_resume(bus); |
d8c2dab8 JK |
417 | } |
418 | #endif /* CONFIG_PM */ | |
419 | ||
420 | static const struct dev_pm_ops skl_pm = { | |
421 | SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) | |
422 | SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) | |
8b4a133c | 423 | .suspend_late = skl_suspend_late, |
d8c2dab8 JK |
424 | }; |
425 | ||
426 | /* | |
427 | * destructor | |
428 | */ | |
76f56fae | 429 | static int skl_free(struct hdac_bus *bus) |
d8c2dab8 | 430 | { |
76f56fae | 431 | struct skl *skl = bus_to_skl(bus); |
d8c2dab8 | 432 | |
ab1b732d | 433 | skl->init_done = 0; /* to be sure */ |
d8c2dab8 | 434 | |
76f56fae | 435 | snd_hdac_ext_stop_streams(bus); |
d8c2dab8 JK |
436 | |
437 | if (bus->irq >= 0) | |
76f56fae | 438 | free_irq(bus->irq, (void *)bus); |
d8c2dab8 | 439 | snd_hdac_bus_free_stream_pages(bus); |
76f56fae RU |
440 | snd_hdac_stream_free_all(bus); |
441 | snd_hdac_link_free_all(bus); | |
077411e5 VK |
442 | |
443 | if (bus->remap_addr) | |
444 | iounmap(bus->remap_addr); | |
445 | ||
d8c2dab8 JK |
446 | pci_release_regions(skl->pci); |
447 | pci_disable_device(skl->pci); | |
448 | ||
76f56fae | 449 | snd_hdac_ext_bus_exit(bus); |
d8c2dab8 | 450 | |
ab1b732d | 451 | cancel_work_sync(&skl->probe_work); |
5b2fe898 | 452 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
76f56fae | 453 | snd_hdac_i915_exit(bus); |
ab1b732d | 454 | |
d8c2dab8 JK |
455 | return 0; |
456 | } | |
457 | ||
bc2bd45b SP |
458 | /* |
459 | * For each ssp there are 3 clocks (mclk/sclk/sclkfs). | |
460 | * e.g. for ssp0, clocks will be named as | |
461 | * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" | |
462 | * So for skl+, there are 6 ssps, so 18 clocks will be created. | |
463 | */ | |
464 | static struct skl_ssp_clk skl_ssp_clks[] = { | |
465 | {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, | |
466 | {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, | |
467 | {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, | |
468 | {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, | |
469 | {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, | |
470 | {.name = "ssp2_sclkfs"}, | |
471 | {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, | |
472 | {.name = "ssp5_sclkfs"}, | |
473 | }; | |
474 | ||
752c93aa | 475 | static int skl_find_machine(struct skl *skl, void *driver_data) |
cc18c5fd | 476 | { |
76f56fae | 477 | struct hdac_bus *bus = skl_to_bus(skl); |
7feb2f78 | 478 | struct snd_soc_acpi_mach *mach = driver_data; |
752c93aa | 479 | struct skl_machine_pdata *pdata; |
cc18c5fd | 480 | |
7feb2f78 | 481 | mach = snd_soc_acpi_find_machine(mach); |
cc18c5fd VK |
482 | if (mach == NULL) { |
483 | dev_err(bus->dev, "No matching machine driver found\n"); | |
484 | return -ENODEV; | |
485 | } | |
752c93aa PB |
486 | |
487 | skl->mach = mach; | |
aecf6fd8 | 488 | skl->fw_name = mach->fw_filename; |
5f15f267 | 489 | pdata = mach->pdata; |
752c93aa | 490 | |
5f15f267 | 491 | if (pdata) { |
752c93aa | 492 | skl->use_tplg_pcm = pdata->use_tplg_pcm; |
5f15f267 PLB |
493 | pdata->dmic_num = skl_get_dmic_geo(skl); |
494 | } | |
752c93aa PB |
495 | |
496 | return 0; | |
497 | } | |
498 | ||
499 | static int skl_machine_device_register(struct skl *skl) | |
500 | { | |
76f56fae | 501 | struct hdac_bus *bus = skl_to_bus(skl); |
752c93aa PB |
502 | struct snd_soc_acpi_mach *mach = skl->mach; |
503 | struct platform_device *pdev; | |
504 | int ret; | |
cc18c5fd VK |
505 | |
506 | pdev = platform_device_alloc(mach->drv_name, -1); | |
507 | if (pdev == NULL) { | |
508 | dev_err(bus->dev, "platform device alloc failed\n"); | |
509 | return -EIO; | |
510 | } | |
511 | ||
512 | ret = platform_device_add(pdev); | |
513 | if (ret) { | |
514 | dev_err(bus->dev, "failed to add machine device\n"); | |
515 | platform_device_put(pdev); | |
516 | return -EIO; | |
517 | } | |
f65cf7d6 | 518 | |
752c93aa | 519 | if (mach->pdata) |
f65cf7d6 YZ |
520 | dev_set_drvdata(&pdev->dev, mach->pdata); |
521 | ||
cc18c5fd VK |
522 | skl->i2s_dev = pdev; |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | static void skl_machine_device_unregister(struct skl *skl) | |
528 | { | |
529 | if (skl->i2s_dev) | |
530 | platform_device_unregister(skl->i2s_dev); | |
531 | } | |
532 | ||
d8c2dab8 JK |
533 | static int skl_dmic_device_register(struct skl *skl) |
534 | { | |
76f56fae | 535 | struct hdac_bus *bus = skl_to_bus(skl); |
d8c2dab8 JK |
536 | struct platform_device *pdev; |
537 | int ret; | |
538 | ||
539 | /* SKL has one dmic port, so allocate dmic device for this */ | |
540 | pdev = platform_device_alloc("dmic-codec", -1); | |
541 | if (!pdev) { | |
542 | dev_err(bus->dev, "failed to allocate dmic device\n"); | |
543 | return -ENOMEM; | |
544 | } | |
545 | ||
546 | ret = platform_device_add(pdev); | |
547 | if (ret) { | |
548 | dev_err(bus->dev, "failed to add dmic device: %d\n", ret); | |
549 | platform_device_put(pdev); | |
550 | return ret; | |
551 | } | |
552 | skl->dmic_dev = pdev; | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static void skl_dmic_device_unregister(struct skl *skl) | |
558 | { | |
559 | if (skl->dmic_dev) | |
560 | platform_device_unregister(skl->dmic_dev); | |
561 | } | |
562 | ||
bc2bd45b SP |
563 | static struct skl_clk_parent_src skl_clk_src[] = { |
564 | { .clk_id = SKL_XTAL, .name = "xtal" }, | |
565 | { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, | |
566 | { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, | |
567 | }; | |
568 | ||
569 | struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) | |
570 | { | |
571 | unsigned int i; | |
572 | ||
573 | for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { | |
574 | if (skl_clk_src[i].clk_id == clk_id) | |
575 | return &skl_clk_src[i]; | |
576 | } | |
577 | ||
578 | return NULL; | |
579 | } | |
580 | ||
8e79ec98 | 581 | static void init_skl_xtal_rate(int pci_id) |
bc2bd45b SP |
582 | { |
583 | switch (pci_id) { | |
584 | case 0x9d70: | |
585 | case 0x9d71: | |
586 | skl_clk_src[0].rate = 24000000; | |
587 | return; | |
588 | ||
589 | default: | |
590 | skl_clk_src[0].rate = 19200000; | |
591 | return; | |
592 | } | |
593 | } | |
594 | ||
595 | static int skl_clock_device_register(struct skl *skl) | |
596 | { | |
597 | struct platform_device_info pdevinfo = {NULL}; | |
598 | struct skl_clk_pdata *clk_pdata; | |
599 | ||
600 | clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), | |
601 | GFP_KERNEL); | |
602 | if (!clk_pdata) | |
603 | return -ENOMEM; | |
604 | ||
605 | init_skl_xtal_rate(skl->pci->device); | |
606 | ||
607 | clk_pdata->parent_clks = skl_clk_src; | |
608 | clk_pdata->ssp_clks = skl_ssp_clks; | |
609 | clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); | |
610 | ||
611 | /* Query NHLT to fill the rates and parent */ | |
612 | skl_get_clks(skl, clk_pdata->ssp_clks); | |
613 | clk_pdata->pvt_data = skl; | |
614 | ||
615 | /* Register Platform device */ | |
616 | pdevinfo.parent = &skl->pci->dev; | |
617 | pdevinfo.id = -1; | |
618 | pdevinfo.name = "skl-ssp-clk"; | |
619 | pdevinfo.data = clk_pdata; | |
620 | pdevinfo.size_data = sizeof(*clk_pdata); | |
621 | skl->clk_dev = platform_device_register_full(&pdevinfo); | |
622 | return PTR_ERR_OR_ZERO(skl->clk_dev); | |
623 | } | |
624 | ||
625 | static void skl_clock_device_unregister(struct skl *skl) | |
626 | { | |
627 | if (skl->clk_dev) | |
628 | platform_device_unregister(skl->clk_dev); | |
629 | } | |
630 | ||
d8c2dab8 JK |
631 | /* |
632 | * Probe the given codec address | |
633 | */ | |
76f56fae | 634 | static int probe_codec(struct hdac_bus *bus, int addr) |
d8c2dab8 | 635 | { |
d8c2dab8 JK |
636 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | |
637 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
e6a33532 | 638 | unsigned int res = -1; |
6298542f RU |
639 | struct skl *skl = bus_to_skl(bus); |
640 | struct hdac_device *hdev; | |
d8c2dab8 JK |
641 | |
642 | mutex_lock(&bus->cmd_mutex); | |
643 | snd_hdac_bus_send_cmd(bus, cmd); | |
644 | snd_hdac_bus_get_response(bus, addr, &res); | |
645 | mutex_unlock(&bus->cmd_mutex); | |
646 | if (res == -1) | |
647 | return -EIO; | |
648 | dev_dbg(bus->dev, "codec #%d probed OK\n", addr); | |
649 | ||
6298542f RU |
650 | hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); |
651 | if (!hdev) | |
652 | return -ENOMEM; | |
653 | ||
654 | return snd_hdac_ext_bus_device_init(bus, addr, hdev); | |
d8c2dab8 JK |
655 | } |
656 | ||
657 | /* Codec initialization */ | |
76f56fae | 658 | static void skl_codec_create(struct hdac_bus *bus) |
d8c2dab8 | 659 | { |
d8c2dab8 JK |
660 | int c, max_slots; |
661 | ||
662 | max_slots = HDA_MAX_CODECS; | |
663 | ||
664 | /* First try to probe all given codec slots */ | |
665 | for (c = 0; c < max_slots; c++) { | |
666 | if ((bus->codec_mask & (1 << c))) { | |
76f56fae | 667 | if (probe_codec(bus, c) < 0) { |
d8c2dab8 JK |
668 | /* |
669 | * Some BIOSen give you wrong codec addresses | |
670 | * that don't exist | |
671 | */ | |
672 | dev_warn(bus->dev, | |
673 | "Codec #%d probe error; disabling it...\n", c); | |
674 | bus->codec_mask &= ~(1 << c); | |
675 | /* | |
676 | * More badly, accessing to a non-existing | |
677 | * codec often screws up the controller bus, | |
678 | * and disturbs the further communications. | |
679 | * Thus if an error occurs during probing, | |
680 | * better to reset the controller bus to get | |
681 | * back to the sanity state. | |
682 | */ | |
683 | snd_hdac_bus_stop_chip(bus); | |
0c8ba9d2 | 684 | skl_init_chip(bus, true); |
d8c2dab8 JK |
685 | } |
686 | } | |
687 | } | |
d8c2dab8 JK |
688 | } |
689 | ||
690 | static const struct hdac_bus_ops bus_core_ops = { | |
691 | .command = snd_hdac_bus_send_cmd, | |
692 | .get_response = snd_hdac_bus_get_response, | |
693 | }; | |
694 | ||
ab1b732d VK |
695 | static int skl_i915_init(struct hdac_bus *bus) |
696 | { | |
697 | int err; | |
698 | ||
699 | /* | |
700 | * The HDMI codec is in GPU so we need to ensure that it is powered | |
701 | * up and ready for probe | |
702 | */ | |
703 | err = snd_hdac_i915_init(bus); | |
704 | if (err < 0) | |
705 | return err; | |
706 | ||
707 | err = snd_hdac_display_power(bus, true); | |
708 | if (err < 0) | |
709 | dev_err(bus->dev, "Cannot turn on display power on i915\n"); | |
710 | ||
711 | return err; | |
712 | } | |
713 | ||
714 | static void skl_probe_work(struct work_struct *work) | |
715 | { | |
716 | struct skl *skl = container_of(work, struct skl, probe_work); | |
76f56fae | 717 | struct hdac_bus *bus = skl_to_bus(skl); |
ab1b732d VK |
718 | struct hdac_ext_link *hlink = NULL; |
719 | int err; | |
720 | ||
721 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { | |
722 | err = skl_i915_init(bus); | |
723 | if (err < 0) | |
724 | return; | |
725 | } | |
726 | ||
727 | err = skl_init_chip(bus, true); | |
728 | if (err < 0) { | |
729 | dev_err(bus->dev, "Init chip failed with err: %d\n", err); | |
730 | goto out_err; | |
731 | } | |
732 | ||
733 | /* codec detection */ | |
734 | if (!bus->codec_mask) | |
735 | dev_info(bus->dev, "no hda codecs found!\n"); | |
736 | ||
737 | /* create codec instances */ | |
76f56fae | 738 | skl_codec_create(bus); |
ab1b732d | 739 | |
752c93aa PB |
740 | /* register platform dai and controls */ |
741 | err = skl_platform_register(bus->dev); | |
742 | if (err < 0) { | |
743 | dev_err(bus->dev, "platform register failed: %d\n", err); | |
744 | return; | |
745 | } | |
746 | ||
747 | if (bus->ppcap) { | |
748 | err = skl_machine_device_register(skl); | |
749 | if (err < 0) { | |
750 | dev_err(bus->dev, "machine register failed: %d\n", err); | |
751 | goto out_err; | |
752 | } | |
753 | } | |
754 | ||
ab1b732d VK |
755 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { |
756 | err = snd_hdac_display_power(bus, false); | |
757 | if (err < 0) { | |
758 | dev_err(bus->dev, "Cannot turn off display power on i915\n"); | |
752c93aa | 759 | skl_machine_device_unregister(skl); |
ab1b732d VK |
760 | return; |
761 | } | |
762 | } | |
763 | ||
ab1b732d VK |
764 | /* |
765 | * we are done probing so decrement link counts | |
766 | */ | |
76f56fae RU |
767 | list_for_each_entry(hlink, &bus->hlink_list, list) |
768 | snd_hdac_ext_bus_link_put(bus, hlink); | |
ab1b732d VK |
769 | |
770 | /* configure PM */ | |
771 | pm_runtime_put_noidle(bus->dev); | |
772 | pm_runtime_allow(bus->dev); | |
773 | skl->init_done = 1; | |
774 | ||
775 | return; | |
776 | ||
777 | out_err: | |
778 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) | |
779 | err = snd_hdac_display_power(bus, false); | |
780 | } | |
781 | ||
d8c2dab8 JK |
782 | /* |
783 | * constructor | |
784 | */ | |
785 | static int skl_create(struct pci_dev *pci, | |
786 | const struct hdac_io_ops *io_ops, | |
787 | struct skl **rskl) | |
788 | { | |
789 | struct skl *skl; | |
76f56fae | 790 | struct hdac_bus *bus; |
d8c2dab8 JK |
791 | |
792 | int err; | |
793 | ||
794 | *rskl = NULL; | |
795 | ||
796 | err = pci_enable_device(pci); | |
797 | if (err < 0) | |
798 | return err; | |
799 | ||
800 | skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); | |
801 | if (!skl) { | |
802 | pci_disable_device(pci); | |
803 | return -ENOMEM; | |
804 | } | |
76f56fae RU |
805 | |
806 | bus = skl_to_bus(skl); | |
cb04ba33 | 807 | snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, io_ops, NULL); |
76f56fae | 808 | bus->use_posbuf = 1; |
d8c2dab8 | 809 | skl->pci = pci; |
ab1b732d | 810 | INIT_WORK(&skl->probe_work, skl_probe_work); |
76f56fae | 811 | bus->bdl_pos_adj = 0; |
d8c2dab8 JK |
812 | |
813 | *rskl = skl; | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
76f56fae | 818 | static int skl_first_init(struct hdac_bus *bus) |
d8c2dab8 | 819 | { |
76f56fae | 820 | struct skl *skl = bus_to_skl(bus); |
d8c2dab8 JK |
821 | struct pci_dev *pci = skl->pci; |
822 | int err; | |
823 | unsigned short gcap; | |
824 | int cp_streams, pb_streams, start_idx; | |
825 | ||
826 | err = pci_request_regions(pci, "Skylake HD audio"); | |
827 | if (err < 0) | |
828 | return err; | |
829 | ||
830 | bus->addr = pci_resource_start(pci, 0); | |
831 | bus->remap_addr = pci_ioremap_bar(pci, 0); | |
832 | if (bus->remap_addr == NULL) { | |
833 | dev_err(bus->dev, "ioremap error\n"); | |
834 | return -ENXIO; | |
835 | } | |
836 | ||
60767abc | 837 | skl_init_chip(bus, true); |
838 | ||
ec8ae570 | 839 | snd_hdac_bus_parse_capabilities(bus); |
05057001 | 840 | |
542cedec YZ |
841 | if (skl_acquire_irq(bus, 0) < 0) |
842 | return -EBUSY; | |
843 | ||
d8c2dab8 | 844 | pci_set_master(pci); |
542cedec | 845 | synchronize_irq(bus->irq); |
d8c2dab8 JK |
846 | |
847 | gcap = snd_hdac_chip_readw(bus, GCAP); | |
848 | dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); | |
849 | ||
850 | /* allow 64bit DMA address if supported by H/W */ | |
851 | if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { | |
852 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); | |
853 | } else { | |
854 | dma_set_mask(bus->dev, DMA_BIT_MASK(32)); | |
855 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); | |
856 | } | |
857 | ||
858 | /* read number of streams from GCAP register */ | |
859 | cp_streams = (gcap >> 8) & 0x0f; | |
860 | pb_streams = (gcap >> 12) & 0x0f; | |
861 | ||
862 | if (!pb_streams && !cp_streams) | |
863 | return -EIO; | |
864 | ||
76f56fae | 865 | bus->num_streams = cp_streams + pb_streams; |
d8c2dab8 JK |
866 | |
867 | /* initialize streams */ | |
868 | snd_hdac_ext_stream_init_all | |
76f56fae | 869 | (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); |
d8c2dab8 JK |
870 | start_idx = cp_streams; |
871 | snd_hdac_ext_stream_init_all | |
76f56fae | 872 | (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); |
d8c2dab8 JK |
873 | |
874 | err = snd_hdac_bus_alloc_stream_pages(bus); | |
875 | if (err < 0) | |
876 | return err; | |
877 | ||
878 | /* initialize chip */ | |
879 | skl_init_pci(skl); | |
880 | ||
ab1b732d | 881 | return skl_init_chip(bus, true); |
d8c2dab8 JK |
882 | } |
883 | ||
884 | static int skl_probe(struct pci_dev *pci, | |
885 | const struct pci_device_id *pci_id) | |
886 | { | |
887 | struct skl *skl; | |
d8c2dab8 JK |
888 | struct hdac_bus *bus = NULL; |
889 | int err; | |
890 | ||
891 | /* we use ext core ops, so provide NULL for ops here */ | |
892 | err = skl_create(pci, NULL, &skl); | |
893 | if (err < 0) | |
894 | return err; | |
895 | ||
76f56fae | 896 | bus = skl_to_bus(skl); |
d8c2dab8 | 897 | |
76f56fae | 898 | err = skl_first_init(bus); |
d8c2dab8 JK |
899 | if (err < 0) |
900 | goto out_free; | |
901 | ||
4b235c43 VK |
902 | skl->pci_id = pci->device; |
903 | ||
2e9dc2b6 VK |
904 | device_disable_async_suspend(bus->dev); |
905 | ||
87b2bdf0 JK |
906 | skl->nhlt = skl_nhlt_init(bus->dev); |
907 | ||
979cf59a WY |
908 | if (skl->nhlt == NULL) { |
909 | err = -ENODEV; | |
ab1b732d | 910 | goto out_free; |
979cf59a | 911 | } |
87b2bdf0 | 912 | |
0cf5a171 SP |
913 | err = skl_nhlt_create_sysfs(skl); |
914 | if (err < 0) | |
915 | goto out_nhlt_free; | |
916 | ||
4b235c43 VK |
917 | skl_nhlt_update_topology_bin(skl); |
918 | ||
76f56fae | 919 | pci_set_drvdata(skl->pci, bus); |
d8c2dab8 | 920 | |
05057001 | 921 | /* check if dsp is there */ |
ec8ae570 | 922 | if (bus->ppcap) { |
bc2bd45b SP |
923 | /* create device for dsp clk */ |
924 | err = skl_clock_device_register(skl); | |
925 | if (err < 0) | |
926 | goto out_clk_free; | |
927 | ||
752c93aa | 928 | err = skl_find_machine(skl, (void *)pci_id->driver_data); |
cc18c5fd | 929 | if (err < 0) |
c286b3f9 | 930 | goto out_nhlt_free; |
cc18c5fd | 931 | |
2a29b200 JK |
932 | err = skl_init_dsp(skl); |
933 | if (err < 0) { | |
934 | dev_dbg(bus->dev, "error failed to register dsp\n"); | |
752c93aa | 935 | goto out_nhlt_free; |
2a29b200 | 936 | } |
0c8ba9d2 | 937 | skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; |
fc9fdd61 | 938 | skl->skl_sst->clock_power_gating = skl_clock_power_gating; |
05057001 | 939 | } |
ec8ae570 | 940 | if (bus->mlcap) |
76f56fae | 941 | snd_hdac_ext_bus_get_ml_capabilities(bus); |
05057001 | 942 | |
ab1b732d VK |
943 | snd_hdac_bus_stop_chip(bus); |
944 | ||
d8c2dab8 JK |
945 | /* create device for soc dmic */ |
946 | err = skl_dmic_device_register(skl); | |
947 | if (err < 0) | |
2a29b200 | 948 | goto out_dsp_free; |
d8c2dab8 | 949 | |
ab1b732d | 950 | schedule_work(&skl->probe_work); |
d8c2dab8 JK |
951 | |
952 | return 0; | |
953 | ||
2a29b200 JK |
954 | out_dsp_free: |
955 | skl_free_dsp(skl); | |
bc2bd45b SP |
956 | out_clk_free: |
957 | skl_clock_device_unregister(skl); | |
c286b3f9 JK |
958 | out_nhlt_free: |
959 | skl_nhlt_free(skl->nhlt); | |
d8c2dab8 | 960 | out_free: |
76f56fae | 961 | skl_free(bus); |
d8c2dab8 JK |
962 | |
963 | return err; | |
964 | } | |
965 | ||
c5a76a24 JK |
966 | static void skl_shutdown(struct pci_dev *pci) |
967 | { | |
76f56fae | 968 | struct hdac_bus *bus = pci_get_drvdata(pci); |
c5a76a24 JK |
969 | struct hdac_stream *s; |
970 | struct hdac_ext_stream *stream; | |
971 | struct skl *skl; | |
972 | ||
76f56fae | 973 | if (!bus) |
c5a76a24 JK |
974 | return; |
975 | ||
76f56fae | 976 | skl = bus_to_skl(bus); |
c5a76a24 | 977 | |
ab1b732d | 978 | if (!skl->init_done) |
c5a76a24 JK |
979 | return; |
980 | ||
76f56fae | 981 | snd_hdac_ext_stop_streams(bus); |
c5a76a24 JK |
982 | list_for_each_entry(s, &bus->stream_list, list) { |
983 | stream = stream_to_hdac_ext_stream(s); | |
76f56fae | 984 | snd_hdac_ext_stream_decouple(bus, stream, false); |
c5a76a24 JK |
985 | } |
986 | ||
987 | snd_hdac_bus_stop_chip(bus); | |
988 | } | |
989 | ||
d8c2dab8 JK |
990 | static void skl_remove(struct pci_dev *pci) |
991 | { | |
76f56fae RU |
992 | struct hdac_bus *bus = pci_get_drvdata(pci); |
993 | struct skl *skl = bus_to_skl(bus); | |
d8c2dab8 | 994 | |
1b00126c | 995 | release_firmware(skl->tplg); |
d8018361 | 996 | |
6d13f62d | 997 | pm_runtime_get_noresume(&pci->dev); |
7373f481 VK |
998 | |
999 | /* codec removal, invoke bus_device_remove */ | |
76f56fae | 1000 | snd_hdac_ext_bus_device_remove(bus); |
7373f481 | 1001 | |
5cdf6c09 | 1002 | skl->debugfs = NULL; |
d8c2dab8 | 1003 | skl_platform_unregister(&pci->dev); |
2a29b200 | 1004 | skl_free_dsp(skl); |
cc18c5fd | 1005 | skl_machine_device_unregister(skl); |
d8c2dab8 | 1006 | skl_dmic_device_unregister(skl); |
bc2bd45b | 1007 | skl_clock_device_unregister(skl); |
0cf5a171 | 1008 | skl_nhlt_remove_sysfs(skl); |
c286b3f9 | 1009 | skl_nhlt_free(skl->nhlt); |
76f56fae | 1010 | skl_free(bus); |
d8c2dab8 JK |
1011 | dev_set_drvdata(&pci->dev, NULL); |
1012 | } | |
1013 | ||
1014 | /* PCI IDs */ | |
1015 | static const struct pci_device_id skl_ids[] = { | |
1016 | /* Sunrise Point-LP */ | |
cc18c5fd | 1017 | { PCI_DEVICE(0x8086, 0x9d70), |
cbaa7f0b | 1018 | .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, |
b379b1fa SV |
1019 | /* BXT-P */ |
1020 | { PCI_DEVICE(0x8086, 0x5a98), | |
cbaa7f0b | 1021 | .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, |
451dfb5f VK |
1022 | /* KBL */ |
1023 | { PCI_DEVICE(0x8086, 0x9D71), | |
cbaa7f0b | 1024 | .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, |
25504863 VK |
1025 | /* GLK */ |
1026 | { PCI_DEVICE(0x8086, 0x3198), | |
cbaa7f0b | 1027 | .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, |
86d7ce3d GS |
1028 | /* CNL */ |
1029 | { PCI_DEVICE(0x8086, 0x9dc8), | |
cbaa7f0b | 1030 | .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, |
d8c2dab8 JK |
1031 | { 0, } |
1032 | }; | |
1033 | MODULE_DEVICE_TABLE(pci, skl_ids); | |
1034 | ||
1035 | /* pci_driver definition */ | |
1036 | static struct pci_driver skl_driver = { | |
1037 | .name = KBUILD_MODNAME, | |
1038 | .id_table = skl_ids, | |
1039 | .probe = skl_probe, | |
1040 | .remove = skl_remove, | |
c5a76a24 | 1041 | .shutdown = skl_shutdown, |
d8c2dab8 JK |
1042 | .driver = { |
1043 | .pm = &skl_pm, | |
1044 | }, | |
1045 | }; | |
1046 | module_pci_driver(skl_driver); | |
1047 | ||
1048 | MODULE_LICENSE("GPL v2"); | |
1049 | MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); |