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d8c2dab8 JK |
1 | /* |
2 | * skl.c - Implementation of ASoC Intel SKL HD Audio driver | |
3 | * | |
4 | * Copyright (C) 2014-2015 Intel Corp | |
5 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
6 | * | |
7 | * Derived mostly from Intel HDA driver with following copyrights: | |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
9 | * PeiSen Hou <pshou@realtek.com.tw> | |
10 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; version 2 of the License. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/platform_device.h> | |
d8018361 | 28 | #include <linux/firmware.h> |
d8c2dab8 | 29 | #include <sound/pcm.h> |
cc18c5fd | 30 | #include "../common/sst-acpi.h" |
6980c057 VK |
31 | #include <sound/hda_register.h> |
32 | #include <sound/hdaudio.h> | |
33 | #include <sound/hda_i915.h> | |
d8c2dab8 | 34 | #include "skl.h" |
0c8ba9d2 J |
35 | #include "skl-sst-dsp.h" |
36 | #include "skl-sst-ipc.h" | |
d8c2dab8 JK |
37 | |
38 | /* | |
39 | * initialize the PCI registers | |
40 | */ | |
41 | static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
42 | unsigned char mask, unsigned char val) | |
43 | { | |
44 | unsigned char data; | |
45 | ||
46 | pci_read_config_byte(pci, reg, &data); | |
47 | data &= ~mask; | |
48 | data |= (val & mask); | |
49 | pci_write_config_byte(pci, reg, data); | |
50 | } | |
51 | ||
52 | static void skl_init_pci(struct skl *skl) | |
53 | { | |
54 | struct hdac_ext_bus *ebus = &skl->ebus; | |
55 | ||
56 | /* | |
57 | * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
58 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
59 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
60 | * codecs. | |
61 | * The PCI register TCSEL is defined in the Intel manuals. | |
62 | */ | |
63 | dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n"); | |
64 | skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); | |
65 | } | |
66 | ||
0c8ba9d2 J |
67 | static void update_pci_dword(struct pci_dev *pci, |
68 | unsigned int reg, u32 mask, u32 val) | |
69 | { | |
70 | u32 data = 0; | |
71 | ||
72 | pci_read_config_dword(pci, reg, &data); | |
73 | data &= ~mask; | |
74 | data |= (val & mask); | |
75 | pci_write_config_dword(pci, reg, data); | |
76 | } | |
77 | ||
78 | /* | |
79 | * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits | |
80 | * | |
81 | * @dev: device pointer | |
82 | * @enable: enable/disable flag | |
83 | */ | |
84 | static void skl_enable_miscbdcge(struct device *dev, bool enable) | |
85 | { | |
86 | struct pci_dev *pci = to_pci_dev(dev); | |
87 | u32 val; | |
88 | ||
89 | val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; | |
90 | ||
91 | update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); | |
92 | } | |
93 | ||
94 | /* | |
95 | * While performing reset, controller may not come back properly causing | |
96 | * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset | |
97 | * (init chip) and then again set CGCTL.MISCBDCGE to 1 | |
98 | */ | |
99 | static int skl_init_chip(struct hdac_bus *bus, bool full_reset) | |
100 | { | |
101 | int ret; | |
102 | ||
103 | skl_enable_miscbdcge(bus->dev, false); | |
104 | ret = snd_hdac_bus_init_chip(bus, full_reset); | |
105 | skl_enable_miscbdcge(bus->dev, true); | |
106 | ||
107 | return ret; | |
108 | } | |
109 | ||
d8c2dab8 JK |
110 | /* called from IRQ */ |
111 | static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) | |
112 | { | |
113 | snd_pcm_period_elapsed(hstr->substream); | |
114 | } | |
115 | ||
116 | static irqreturn_t skl_interrupt(int irq, void *dev_id) | |
117 | { | |
118 | struct hdac_ext_bus *ebus = dev_id; | |
119 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
120 | u32 status; | |
121 | ||
122 | if (!pm_runtime_active(bus->dev)) | |
123 | return IRQ_NONE; | |
124 | ||
125 | spin_lock(&bus->reg_lock); | |
126 | ||
127 | status = snd_hdac_chip_readl(bus, INTSTS); | |
128 | if (status == 0 || status == 0xffffffff) { | |
129 | spin_unlock(&bus->reg_lock); | |
130 | return IRQ_NONE; | |
131 | } | |
132 | ||
133 | /* clear rirb int */ | |
134 | status = snd_hdac_chip_readb(bus, RIRBSTS); | |
135 | if (status & RIRB_INT_MASK) { | |
136 | if (status & RIRB_INT_RESPONSE) | |
137 | snd_hdac_bus_update_rirb(bus); | |
138 | snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); | |
139 | } | |
140 | ||
141 | spin_unlock(&bus->reg_lock); | |
142 | ||
143 | return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; | |
144 | } | |
145 | ||
146 | static irqreturn_t skl_threaded_handler(int irq, void *dev_id) | |
147 | { | |
148 | struct hdac_ext_bus *ebus = dev_id; | |
149 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
150 | u32 status; | |
151 | ||
152 | status = snd_hdac_chip_readl(bus, INTSTS); | |
153 | ||
154 | snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); | |
155 | ||
156 | return IRQ_HANDLED; | |
157 | } | |
158 | ||
159 | static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect) | |
160 | { | |
161 | struct skl *skl = ebus_to_skl(ebus); | |
162 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
163 | int ret; | |
164 | ||
165 | ret = request_threaded_irq(skl->pci->irq, skl_interrupt, | |
166 | skl_threaded_handler, | |
167 | IRQF_SHARED, | |
168 | KBUILD_MODNAME, ebus); | |
169 | if (ret) { | |
170 | dev_err(bus->dev, | |
171 | "unable to grab IRQ %d, disabling device\n", | |
172 | skl->pci->irq); | |
173 | return ret; | |
174 | } | |
175 | ||
176 | bus->irq = skl->pci->irq; | |
177 | pci_intx(skl->pci, 1); | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
61722f44 JK |
182 | #ifdef CONFIG_PM |
183 | static int _skl_suspend(struct hdac_ext_bus *ebus) | |
184 | { | |
185 | struct skl *skl = ebus_to_skl(ebus); | |
186 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
187 | int ret; | |
188 | ||
189 | snd_hdac_ext_bus_link_power_down_all(ebus); | |
190 | ||
191 | ret = skl_suspend_dsp(skl); | |
192 | if (ret < 0) | |
193 | return ret; | |
194 | ||
195 | snd_hdac_bus_stop_chip(bus); | |
0c8ba9d2 | 196 | skl_enable_miscbdcge(bus->dev, false); |
61722f44 | 197 | snd_hdac_bus_enter_link_reset(bus); |
0c8ba9d2 | 198 | skl_enable_miscbdcge(bus->dev, true); |
61722f44 JK |
199 | |
200 | return 0; | |
201 | } | |
202 | ||
203 | static int _skl_resume(struct hdac_ext_bus *ebus) | |
204 | { | |
205 | struct skl *skl = ebus_to_skl(ebus); | |
206 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
207 | ||
208 | skl_init_pci(skl); | |
0c8ba9d2 | 209 | skl_init_chip(bus, true); |
61722f44 JK |
210 | |
211 | return skl_resume_dsp(skl); | |
212 | } | |
213 | #endif | |
214 | ||
d8c2dab8 JK |
215 | #ifdef CONFIG_PM_SLEEP |
216 | /* | |
217 | * power management | |
218 | */ | |
219 | static int skl_suspend(struct device *dev) | |
220 | { | |
221 | struct pci_dev *pci = to_pci_dev(dev); | |
222 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
4557c305 | 223 | struct skl *skl = ebus_to_skl(ebus); |
1f4956fd | 224 | struct hdac_bus *bus = ebus_to_hbus(ebus); |
d8c2dab8 | 225 | |
4557c305 JK |
226 | /* |
227 | * Do not suspend if streams which are marked ignore suspend are | |
228 | * running, we need to save the state for these and continue | |
229 | */ | |
230 | if (skl->supend_active) { | |
c2e20cd8 | 231 | snd_hdac_ext_bus_link_power_down_all(ebus); |
1f4956fd | 232 | enable_irq_wake(bus->irq); |
4557c305 JK |
233 | pci_save_state(pci); |
234 | pci_disable_device(pci); | |
235 | return 0; | |
236 | } else { | |
237 | return _skl_suspend(ebus); | |
238 | } | |
d8c2dab8 JK |
239 | } |
240 | ||
241 | static int skl_resume(struct device *dev) | |
242 | { | |
243 | struct pci_dev *pci = to_pci_dev(dev); | |
244 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
4557c305 | 245 | struct skl *skl = ebus_to_skl(ebus); |
1f4956fd | 246 | struct hdac_bus *bus = ebus_to_hbus(ebus); |
4557c305 JK |
247 | int ret; |
248 | ||
6980c057 VK |
249 | /* Turned OFF in HDMI codec driver after codec reconfiguration */ |
250 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { | |
251 | ret = snd_hdac_display_power(bus, true); | |
252 | if (ret < 0) { | |
253 | dev_err(bus->dev, | |
254 | "Cannot turn on display power on i915\n"); | |
255 | return ret; | |
256 | } | |
257 | } | |
258 | ||
4557c305 JK |
259 | /* |
260 | * resume only when we are not in suspend active, otherwise need to | |
261 | * restore the device | |
262 | */ | |
263 | if (skl->supend_active) { | |
264 | pci_restore_state(pci); | |
265 | ret = pci_enable_device(pci); | |
c2e20cd8 | 266 | snd_hdac_ext_bus_link_power_up_all(ebus); |
1f4956fd | 267 | disable_irq_wake(bus->irq); |
4557c305 JK |
268 | } else { |
269 | ret = _skl_resume(ebus); | |
270 | } | |
d8c2dab8 | 271 | |
4557c305 | 272 | return ret; |
d8c2dab8 JK |
273 | } |
274 | #endif /* CONFIG_PM_SLEEP */ | |
275 | ||
276 | #ifdef CONFIG_PM | |
277 | static int skl_runtime_suspend(struct device *dev) | |
278 | { | |
279 | struct pci_dev *pci = to_pci_dev(dev); | |
280 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
281 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
282 | ||
283 | dev_dbg(bus->dev, "in %s\n", __func__); | |
284 | ||
61722f44 | 285 | return _skl_suspend(ebus); |
d8c2dab8 JK |
286 | } |
287 | ||
288 | static int skl_runtime_resume(struct device *dev) | |
289 | { | |
290 | struct pci_dev *pci = to_pci_dev(dev); | |
291 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
292 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
d8c2dab8 JK |
293 | |
294 | dev_dbg(bus->dev, "in %s\n", __func__); | |
295 | ||
61722f44 | 296 | return _skl_resume(ebus); |
d8c2dab8 JK |
297 | } |
298 | #endif /* CONFIG_PM */ | |
299 | ||
300 | static const struct dev_pm_ops skl_pm = { | |
301 | SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) | |
302 | SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) | |
303 | }; | |
304 | ||
305 | /* | |
306 | * destructor | |
307 | */ | |
308 | static int skl_free(struct hdac_ext_bus *ebus) | |
309 | { | |
310 | struct skl *skl = ebus_to_skl(ebus); | |
311 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
312 | ||
313 | skl->init_failed = 1; /* to be sure */ | |
314 | ||
315 | snd_hdac_ext_stop_streams(ebus); | |
316 | ||
317 | if (bus->irq >= 0) | |
318 | free_irq(bus->irq, (void *)bus); | |
319 | if (bus->remap_addr) | |
320 | iounmap(bus->remap_addr); | |
321 | ||
322 | snd_hdac_bus_free_stream_pages(bus); | |
323 | snd_hdac_stream_free_all(ebus); | |
324 | snd_hdac_link_free_all(ebus); | |
325 | pci_release_regions(skl->pci); | |
326 | pci_disable_device(skl->pci); | |
327 | ||
328 | snd_hdac_ext_bus_exit(ebus); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
cc18c5fd VK |
333 | static int skl_machine_device_register(struct skl *skl, void *driver_data) |
334 | { | |
335 | struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); | |
336 | struct platform_device *pdev; | |
337 | struct sst_acpi_mach *mach = driver_data; | |
338 | int ret; | |
339 | ||
340 | mach = sst_acpi_find_machine(mach); | |
341 | if (mach == NULL) { | |
342 | dev_err(bus->dev, "No matching machine driver found\n"); | |
343 | return -ENODEV; | |
344 | } | |
aecf6fd8 | 345 | skl->fw_name = mach->fw_filename; |
cc18c5fd VK |
346 | |
347 | pdev = platform_device_alloc(mach->drv_name, -1); | |
348 | if (pdev == NULL) { | |
349 | dev_err(bus->dev, "platform device alloc failed\n"); | |
350 | return -EIO; | |
351 | } | |
352 | ||
353 | ret = platform_device_add(pdev); | |
354 | if (ret) { | |
355 | dev_err(bus->dev, "failed to add machine device\n"); | |
356 | platform_device_put(pdev); | |
357 | return -EIO; | |
358 | } | |
359 | skl->i2s_dev = pdev; | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
364 | static void skl_machine_device_unregister(struct skl *skl) | |
365 | { | |
366 | if (skl->i2s_dev) | |
367 | platform_device_unregister(skl->i2s_dev); | |
368 | } | |
369 | ||
d8c2dab8 JK |
370 | static int skl_dmic_device_register(struct skl *skl) |
371 | { | |
372 | struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); | |
373 | struct platform_device *pdev; | |
374 | int ret; | |
375 | ||
376 | /* SKL has one dmic port, so allocate dmic device for this */ | |
377 | pdev = platform_device_alloc("dmic-codec", -1); | |
378 | if (!pdev) { | |
379 | dev_err(bus->dev, "failed to allocate dmic device\n"); | |
380 | return -ENOMEM; | |
381 | } | |
382 | ||
383 | ret = platform_device_add(pdev); | |
384 | if (ret) { | |
385 | dev_err(bus->dev, "failed to add dmic device: %d\n", ret); | |
386 | platform_device_put(pdev); | |
387 | return ret; | |
388 | } | |
389 | skl->dmic_dev = pdev; | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | static void skl_dmic_device_unregister(struct skl *skl) | |
395 | { | |
396 | if (skl->dmic_dev) | |
397 | platform_device_unregister(skl->dmic_dev); | |
398 | } | |
399 | ||
400 | /* | |
401 | * Probe the given codec address | |
402 | */ | |
403 | static int probe_codec(struct hdac_ext_bus *ebus, int addr) | |
404 | { | |
405 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
406 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
407 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
408 | unsigned int res; | |
409 | ||
410 | mutex_lock(&bus->cmd_mutex); | |
411 | snd_hdac_bus_send_cmd(bus, cmd); | |
412 | snd_hdac_bus_get_response(bus, addr, &res); | |
413 | mutex_unlock(&bus->cmd_mutex); | |
414 | if (res == -1) | |
415 | return -EIO; | |
416 | dev_dbg(bus->dev, "codec #%d probed OK\n", addr); | |
417 | ||
418 | return snd_hdac_ext_bus_device_init(ebus, addr); | |
419 | } | |
420 | ||
421 | /* Codec initialization */ | |
422 | static int skl_codec_create(struct hdac_ext_bus *ebus) | |
423 | { | |
424 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
425 | int c, max_slots; | |
426 | ||
427 | max_slots = HDA_MAX_CODECS; | |
428 | ||
429 | /* First try to probe all given codec slots */ | |
430 | for (c = 0; c < max_slots; c++) { | |
431 | if ((bus->codec_mask & (1 << c))) { | |
432 | if (probe_codec(ebus, c) < 0) { | |
433 | /* | |
434 | * Some BIOSen give you wrong codec addresses | |
435 | * that don't exist | |
436 | */ | |
437 | dev_warn(bus->dev, | |
438 | "Codec #%d probe error; disabling it...\n", c); | |
439 | bus->codec_mask &= ~(1 << c); | |
440 | /* | |
441 | * More badly, accessing to a non-existing | |
442 | * codec often screws up the controller bus, | |
443 | * and disturbs the further communications. | |
444 | * Thus if an error occurs during probing, | |
445 | * better to reset the controller bus to get | |
446 | * back to the sanity state. | |
447 | */ | |
448 | snd_hdac_bus_stop_chip(bus); | |
0c8ba9d2 | 449 | skl_init_chip(bus, true); |
d8c2dab8 JK |
450 | } |
451 | } | |
452 | } | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static const struct hdac_bus_ops bus_core_ops = { | |
458 | .command = snd_hdac_bus_send_cmd, | |
459 | .get_response = snd_hdac_bus_get_response, | |
460 | }; | |
461 | ||
462 | /* | |
463 | * constructor | |
464 | */ | |
465 | static int skl_create(struct pci_dev *pci, | |
466 | const struct hdac_io_ops *io_ops, | |
467 | struct skl **rskl) | |
468 | { | |
469 | struct skl *skl; | |
470 | struct hdac_ext_bus *ebus; | |
471 | ||
472 | int err; | |
473 | ||
474 | *rskl = NULL; | |
475 | ||
476 | err = pci_enable_device(pci); | |
477 | if (err < 0) | |
478 | return err; | |
479 | ||
480 | skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); | |
481 | if (!skl) { | |
482 | pci_disable_device(pci); | |
483 | return -ENOMEM; | |
484 | } | |
485 | ebus = &skl->ebus; | |
486 | snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops); | |
487 | ebus->bus.use_posbuf = 1; | |
488 | skl->pci = pci; | |
489 | ||
490 | ebus->bus.bdl_pos_adj = 0; | |
491 | ||
492 | *rskl = skl; | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
6980c057 VK |
497 | static int skl_i915_init(struct hdac_bus *bus) |
498 | { | |
499 | int err; | |
500 | ||
501 | /* | |
502 | * The HDMI codec is in GPU so we need to ensure that it is powered | |
503 | * up and ready for probe | |
504 | */ | |
505 | err = snd_hdac_i915_init(bus); | |
506 | if (err < 0) | |
507 | return err; | |
508 | ||
509 | err = snd_hdac_display_power(bus, true); | |
510 | if (err < 0) { | |
511 | dev_err(bus->dev, "Cannot turn on display power on i915\n"); | |
512 | return err; | |
513 | } | |
514 | ||
515 | return err; | |
516 | } | |
517 | ||
d8c2dab8 JK |
518 | static int skl_first_init(struct hdac_ext_bus *ebus) |
519 | { | |
520 | struct skl *skl = ebus_to_skl(ebus); | |
521 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
522 | struct pci_dev *pci = skl->pci; | |
523 | int err; | |
524 | unsigned short gcap; | |
525 | int cp_streams, pb_streams, start_idx; | |
526 | ||
527 | err = pci_request_regions(pci, "Skylake HD audio"); | |
528 | if (err < 0) | |
529 | return err; | |
530 | ||
531 | bus->addr = pci_resource_start(pci, 0); | |
532 | bus->remap_addr = pci_ioremap_bar(pci, 0); | |
533 | if (bus->remap_addr == NULL) { | |
534 | dev_err(bus->dev, "ioremap error\n"); | |
535 | return -ENXIO; | |
536 | } | |
537 | ||
05057001 JK |
538 | snd_hdac_ext_bus_parse_capabilities(ebus); |
539 | ||
d8c2dab8 JK |
540 | if (skl_acquire_irq(ebus, 0) < 0) |
541 | return -EBUSY; | |
542 | ||
543 | pci_set_master(pci); | |
544 | synchronize_irq(bus->irq); | |
545 | ||
546 | gcap = snd_hdac_chip_readw(bus, GCAP); | |
547 | dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); | |
548 | ||
549 | /* allow 64bit DMA address if supported by H/W */ | |
550 | if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { | |
551 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); | |
552 | } else { | |
553 | dma_set_mask(bus->dev, DMA_BIT_MASK(32)); | |
554 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); | |
555 | } | |
556 | ||
557 | /* read number of streams from GCAP register */ | |
558 | cp_streams = (gcap >> 8) & 0x0f; | |
559 | pb_streams = (gcap >> 12) & 0x0f; | |
560 | ||
561 | if (!pb_streams && !cp_streams) | |
562 | return -EIO; | |
563 | ||
564 | ebus->num_streams = cp_streams + pb_streams; | |
565 | ||
566 | /* initialize streams */ | |
567 | snd_hdac_ext_stream_init_all | |
568 | (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); | |
569 | start_idx = cp_streams; | |
570 | snd_hdac_ext_stream_init_all | |
571 | (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); | |
572 | ||
573 | err = snd_hdac_bus_alloc_stream_pages(bus); | |
574 | if (err < 0) | |
575 | return err; | |
576 | ||
577 | /* initialize chip */ | |
578 | skl_init_pci(skl); | |
579 | ||
6980c057 VK |
580 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { |
581 | err = skl_i915_init(bus); | |
582 | if (err < 0) | |
583 | return err; | |
584 | } | |
585 | ||
0c8ba9d2 | 586 | skl_init_chip(bus, true); |
d8c2dab8 JK |
587 | |
588 | /* codec detection */ | |
589 | if (!bus->codec_mask) { | |
029890c6 | 590 | dev_info(bus->dev, "no hda codecs found!\n"); |
d8c2dab8 JK |
591 | } |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static int skl_probe(struct pci_dev *pci, | |
597 | const struct pci_device_id *pci_id) | |
598 | { | |
599 | struct skl *skl; | |
600 | struct hdac_ext_bus *ebus = NULL; | |
601 | struct hdac_bus *bus = NULL; | |
602 | int err; | |
603 | ||
604 | /* we use ext core ops, so provide NULL for ops here */ | |
605 | err = skl_create(pci, NULL, &skl); | |
606 | if (err < 0) | |
607 | return err; | |
608 | ||
609 | ebus = &skl->ebus; | |
610 | bus = ebus_to_hbus(ebus); | |
611 | ||
612 | err = skl_first_init(ebus); | |
613 | if (err < 0) | |
614 | goto out_free; | |
615 | ||
4b235c43 VK |
616 | skl->pci_id = pci->device; |
617 | ||
87b2bdf0 JK |
618 | skl->nhlt = skl_nhlt_init(bus->dev); |
619 | ||
620 | if (skl->nhlt == NULL) | |
621 | goto out_free; | |
622 | ||
4b235c43 VK |
623 | skl_nhlt_update_topology_bin(skl); |
624 | ||
d8c2dab8 JK |
625 | pci_set_drvdata(skl->pci, ebus); |
626 | ||
05057001 JK |
627 | /* check if dsp is there */ |
628 | if (ebus->ppcap) { | |
cc18c5fd VK |
629 | err = skl_machine_device_register(skl, |
630 | (void *)pci_id->driver_data); | |
631 | if (err < 0) | |
632 | goto out_free; | |
633 | ||
2a29b200 JK |
634 | err = skl_init_dsp(skl); |
635 | if (err < 0) { | |
636 | dev_dbg(bus->dev, "error failed to register dsp\n"); | |
cc18c5fd | 637 | goto out_mach_free; |
2a29b200 | 638 | } |
0c8ba9d2 J |
639 | skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; |
640 | ||
05057001 | 641 | } |
05057001 JK |
642 | if (ebus->mlcap) |
643 | snd_hdac_ext_bus_get_ml_capabilities(ebus); | |
644 | ||
d8c2dab8 JK |
645 | /* create device for soc dmic */ |
646 | err = skl_dmic_device_register(skl); | |
647 | if (err < 0) | |
2a29b200 | 648 | goto out_dsp_free; |
d8c2dab8 JK |
649 | |
650 | /* register platform dai and controls */ | |
651 | err = skl_platform_register(bus->dev); | |
652 | if (err < 0) | |
653 | goto out_dmic_free; | |
654 | ||
655 | /* create codec instances */ | |
656 | err = skl_codec_create(ebus); | |
657 | if (err < 0) | |
658 | goto out_unregister; | |
659 | ||
6980c057 VK |
660 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { |
661 | err = snd_hdac_display_power(bus, false); | |
662 | if (err < 0) { | |
663 | dev_err(bus->dev, "Cannot turn off display power on i915\n"); | |
664 | return err; | |
665 | } | |
666 | } | |
667 | ||
d8c2dab8 | 668 | /*configure PM */ |
d8c2dab8 JK |
669 | pm_runtime_put_noidle(bus->dev); |
670 | pm_runtime_allow(bus->dev); | |
671 | ||
672 | return 0; | |
673 | ||
674 | out_unregister: | |
675 | skl_platform_unregister(bus->dev); | |
676 | out_dmic_free: | |
677 | skl_dmic_device_unregister(skl); | |
2a29b200 JK |
678 | out_dsp_free: |
679 | skl_free_dsp(skl); | |
cc18c5fd VK |
680 | out_mach_free: |
681 | skl_machine_device_unregister(skl); | |
d8c2dab8 JK |
682 | out_free: |
683 | skl->init_failed = 1; | |
684 | skl_free(ebus); | |
685 | ||
686 | return err; | |
687 | } | |
688 | ||
c5a76a24 JK |
689 | static void skl_shutdown(struct pci_dev *pci) |
690 | { | |
691 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
692 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
693 | struct hdac_stream *s; | |
694 | struct hdac_ext_stream *stream; | |
695 | struct skl *skl; | |
696 | ||
697 | if (ebus == NULL) | |
698 | return; | |
699 | ||
700 | skl = ebus_to_skl(ebus); | |
701 | ||
702 | if (skl->init_failed) | |
703 | return; | |
704 | ||
705 | snd_hdac_ext_stop_streams(ebus); | |
706 | list_for_each_entry(s, &bus->stream_list, list) { | |
707 | stream = stream_to_hdac_ext_stream(s); | |
708 | snd_hdac_ext_stream_decouple(ebus, stream, false); | |
709 | } | |
710 | ||
711 | snd_hdac_bus_stop_chip(bus); | |
712 | } | |
713 | ||
d8c2dab8 JK |
714 | static void skl_remove(struct pci_dev *pci) |
715 | { | |
716 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
717 | struct skl *skl = ebus_to_skl(ebus); | |
718 | ||
d8018361 VK |
719 | if (skl->tplg) |
720 | release_firmware(skl->tplg); | |
721 | ||
6980c057 VK |
722 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
723 | snd_hdac_i915_exit(&ebus->bus); | |
724 | ||
d8c2dab8 JK |
725 | if (pci_dev_run_wake(pci)) |
726 | pm_runtime_get_noresume(&pci->dev); | |
727 | pci_dev_put(pci); | |
728 | skl_platform_unregister(&pci->dev); | |
2a29b200 | 729 | skl_free_dsp(skl); |
cc18c5fd | 730 | skl_machine_device_unregister(skl); |
d8c2dab8 JK |
731 | skl_dmic_device_unregister(skl); |
732 | skl_free(ebus); | |
733 | dev_set_drvdata(&pci->dev, NULL); | |
734 | } | |
735 | ||
cc18c5fd VK |
736 | static struct sst_acpi_mach sst_skl_devdata[] = { |
737 | { "INT343A", "skl_alc286s_i2s", "intel/dsp_fw_release.bin", NULL, NULL, NULL }, | |
02cc2355 FY |
738 | { "INT343B", "skl_nau88l25_ssm4567_i2s", "intel/dsp_fw_release.bin", |
739 | NULL, NULL, NULL }, | |
69b7f9c4 RA |
740 | { "MX98357A", "skl_nau88l25_max98357a_i2s", "intel/dsp_fw_release.bin", |
741 | NULL, NULL, NULL }, | |
cc18c5fd VK |
742 | {} |
743 | }; | |
744 | ||
d8c2dab8 JK |
745 | /* PCI IDs */ |
746 | static const struct pci_device_id skl_ids[] = { | |
747 | /* Sunrise Point-LP */ | |
cc18c5fd VK |
748 | { PCI_DEVICE(0x8086, 0x9d70), |
749 | .driver_data = (unsigned long)&sst_skl_devdata}, | |
d8c2dab8 JK |
750 | { 0, } |
751 | }; | |
752 | MODULE_DEVICE_TABLE(pci, skl_ids); | |
753 | ||
754 | /* pci_driver definition */ | |
755 | static struct pci_driver skl_driver = { | |
756 | .name = KBUILD_MODNAME, | |
757 | .id_table = skl_ids, | |
758 | .probe = skl_probe, | |
759 | .remove = skl_remove, | |
c5a76a24 | 760 | .shutdown = skl_shutdown, |
d8c2dab8 JK |
761 | .driver = { |
762 | .pm = &skl_pm, | |
763 | }, | |
764 | }; | |
765 | module_pci_driver(skl_driver); | |
766 | ||
767 | MODULE_LICENSE("GPL v2"); | |
768 | MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); |