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8e8e69d6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d8c2dab8 JK |
2 | /* |
3 | * skl.c - Implementation of ASoC Intel SKL HD Audio driver | |
4 | * | |
5 | * Copyright (C) 2014-2015 Intel Corp | |
6 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
7 | * | |
8 | * Derived mostly from Intel HDA driver with following copyrights: | |
9 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
10 | * PeiSen Hou <pshou@realtek.com.tw> | |
11 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
12 | * | |
d8c2dab8 JK |
13 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/pm_runtime.h> | |
19 | #include <linux/platform_device.h> | |
d8018361 | 20 | #include <linux/firmware.h> |
a26a3f53 | 21 | #include <linux/delay.h> |
d8c2dab8 | 22 | #include <sound/pcm.h> |
7feb2f78 | 23 | #include <sound/soc-acpi.h> |
cbaa7f0b | 24 | #include <sound/soc-acpi-intel-match.h> |
6980c057 VK |
25 | #include <sound/hda_register.h> |
26 | #include <sound/hdaudio.h> | |
27 | #include <sound/hda_i915.h> | |
00deadb5 | 28 | #include <sound/hda_codec.h> |
1169cbf6 | 29 | #include <sound/intel-nhlt.h> |
7eb993f1 | 30 | #include <sound/intel-dsp-config.h> |
d8c2dab8 | 31 | #include "skl.h" |
0c8ba9d2 J |
32 | #include "skl-sst-dsp.h" |
33 | #include "skl-sst-ipc.h" | |
1169cbf6 | 34 | |
8c4e7c2e | 35 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
6bae5ea9 | 36 | #include "../../../soc/codecs/hdac_hda.h" |
8c4e7c2e | 37 | #endif |
d82b51c8 PLB |
38 | static int skl_pci_binding; |
39 | module_param_named(pci_binding, skl_pci_binding, int, 0444); | |
40 | MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc"); | |
d8c2dab8 JK |
41 | |
42 | /* | |
43 | * initialize the PCI registers | |
44 | */ | |
45 | static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
46 | unsigned char mask, unsigned char val) | |
47 | { | |
48 | unsigned char data; | |
49 | ||
50 | pci_read_config_byte(pci, reg, &data); | |
51 | data &= ~mask; | |
52 | data |= (val & mask); | |
53 | pci_write_config_byte(pci, reg, data); | |
54 | } | |
55 | ||
bcc2a2dc | 56 | static void skl_init_pci(struct skl_dev *skl) |
d8c2dab8 | 57 | { |
76f56fae | 58 | struct hdac_bus *bus = skl_to_bus(skl); |
d8c2dab8 JK |
59 | |
60 | /* | |
61 | * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
62 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
63 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
64 | * codecs. | |
65 | * The PCI register TCSEL is defined in the Intel manuals. | |
66 | */ | |
76f56fae | 67 | dev_dbg(bus->dev, "Clearing TCSEL\n"); |
d8c2dab8 JK |
68 | skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); |
69 | } | |
70 | ||
0c8ba9d2 J |
71 | static void update_pci_dword(struct pci_dev *pci, |
72 | unsigned int reg, u32 mask, u32 val) | |
73 | { | |
74 | u32 data = 0; | |
75 | ||
76 | pci_read_config_dword(pci, reg, &data); | |
77 | data &= ~mask; | |
78 | data |= (val & mask); | |
79 | pci_write_config_dword(pci, reg, data); | |
80 | } | |
81 | ||
82 | /* | |
83 | * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits | |
84 | * | |
85 | * @dev: device pointer | |
86 | * @enable: enable/disable flag | |
87 | */ | |
88 | static void skl_enable_miscbdcge(struct device *dev, bool enable) | |
89 | { | |
90 | struct pci_dev *pci = to_pci_dev(dev); | |
91 | u32 val; | |
92 | ||
93 | val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; | |
94 | ||
95 | update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); | |
96 | } | |
97 | ||
fc9fdd61 SK |
98 | /** |
99 | * skl_clock_power_gating: Enable/Disable clock and power gating | |
100 | * | |
101 | * @dev: Device pointer | |
102 | * @enable: Enable/Disable flag | |
103 | */ | |
104 | static void skl_clock_power_gating(struct device *dev, bool enable) | |
105 | { | |
106 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 107 | struct hdac_bus *bus = pci_get_drvdata(pci); |
fc9fdd61 SK |
108 | u32 val; |
109 | ||
110 | /* Update PDCGE bit of CGCTL register */ | |
111 | val = enable ? AZX_CGCTL_ADSPDCGE : 0; | |
112 | update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); | |
113 | ||
114 | /* Update L1SEN bit of EM2 register */ | |
115 | val = enable ? AZX_REG_VS_EM2_L1SEN : 0; | |
116 | snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); | |
117 | ||
118 | /* Update ADSPPGD bit of PGCTL register */ | |
119 | val = enable ? 0 : AZX_PGCTL_ADSPPGD; | |
120 | update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); | |
121 | } | |
122 | ||
0c8ba9d2 J |
123 | /* |
124 | * While performing reset, controller may not come back properly causing | |
125 | * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset | |
126 | * (init chip) and then again set CGCTL.MISCBDCGE to 1 | |
127 | */ | |
128 | static int skl_init_chip(struct hdac_bus *bus, bool full_reset) | |
129 | { | |
112c60b3 | 130 | struct hdac_ext_link *hlink; |
0c8ba9d2 J |
131 | int ret; |
132 | ||
b25c0519 | 133 | snd_hdac_set_codec_wakeup(bus, true); |
0c8ba9d2 J |
134 | skl_enable_miscbdcge(bus->dev, false); |
135 | ret = snd_hdac_bus_init_chip(bus, full_reset); | |
112c60b3 RU |
136 | |
137 | /* Reset stream-to-link mapping */ | |
76f56fae | 138 | list_for_each_entry(hlink, &bus->hlink_list, list) |
19abfefd | 139 | writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); |
112c60b3 | 140 | |
0c8ba9d2 | 141 | skl_enable_miscbdcge(bus->dev, true); |
b25c0519 | 142 | snd_hdac_set_codec_wakeup(bus, false); |
0c8ba9d2 J |
143 | |
144 | return ret; | |
145 | } | |
146 | ||
a26a3f53 PS |
147 | void skl_update_d0i3c(struct device *dev, bool enable) |
148 | { | |
149 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 150 | struct hdac_bus *bus = pci_get_drvdata(pci); |
a26a3f53 PS |
151 | u8 reg; |
152 | int timeout = 50; | |
153 | ||
154 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
155 | /* Do not write to D0I3C until command in progress bit is cleared */ | |
156 | while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { | |
157 | udelay(10); | |
158 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
159 | } | |
160 | ||
161 | /* Highly unlikely. But if it happens, flag error explicitly */ | |
162 | if (!timeout) { | |
163 | dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); | |
164 | return; | |
165 | } | |
166 | ||
167 | if (enable) | |
168 | reg = reg | AZX_REG_VS_D0I3C_I3; | |
169 | else | |
170 | reg = reg & (~AZX_REG_VS_D0I3C_I3); | |
171 | ||
172 | snd_hdac_chip_writeb(bus, VS_D0I3C, reg); | |
173 | ||
174 | timeout = 50; | |
175 | /* Wait for cmd in progress to be cleared before exiting the function */ | |
176 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
177 | while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { | |
178 | udelay(10); | |
179 | reg = snd_hdac_chip_readb(bus, VS_D0I3C); | |
180 | } | |
181 | ||
182 | /* Highly unlikely. But if it happens, flag error explicitly */ | |
183 | if (!timeout) { | |
184 | dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); | |
185 | return; | |
186 | } | |
187 | ||
188 | dev_dbg(bus->dev, "D0I3C register = 0x%x\n", | |
189 | snd_hdac_chip_readb(bus, VS_D0I3C)); | |
190 | } | |
191 | ||
7a1954de CR |
192 | /** |
193 | * skl_dum_set - set DUM bit in EM2 register | |
194 | * @bus: HD-audio core bus | |
195 | * | |
196 | * Addresses incorrect position reporting for capture streams. | |
197 | * Used on device power up. | |
198 | */ | |
199 | static void skl_dum_set(struct hdac_bus *bus) | |
200 | { | |
201 | /* For the DUM bit to be set, CRST needs to be out of reset state */ | |
202 | if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) { | |
203 | skl_enable_miscbdcge(bus->dev, false); | |
204 | snd_hdac_bus_exit_link_reset(bus); | |
205 | skl_enable_miscbdcge(bus->dev, true); | |
206 | } | |
207 | ||
208 | snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM); | |
209 | } | |
210 | ||
d8c2dab8 JK |
211 | /* called from IRQ */ |
212 | static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) | |
213 | { | |
214 | snd_pcm_period_elapsed(hstr->substream); | |
215 | } | |
216 | ||
217 | static irqreturn_t skl_interrupt(int irq, void *dev_id) | |
218 | { | |
76f56fae | 219 | struct hdac_bus *bus = dev_id; |
d8c2dab8 JK |
220 | u32 status; |
221 | ||
222 | if (!pm_runtime_active(bus->dev)) | |
223 | return IRQ_NONE; | |
224 | ||
225 | spin_lock(&bus->reg_lock); | |
226 | ||
227 | status = snd_hdac_chip_readl(bus, INTSTS); | |
228 | if (status == 0 || status == 0xffffffff) { | |
229 | spin_unlock(&bus->reg_lock); | |
230 | return IRQ_NONE; | |
231 | } | |
232 | ||
233 | /* clear rirb int */ | |
234 | status = snd_hdac_chip_readb(bus, RIRBSTS); | |
235 | if (status & RIRB_INT_MASK) { | |
236 | if (status & RIRB_INT_RESPONSE) | |
237 | snd_hdac_bus_update_rirb(bus); | |
238 | snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); | |
239 | } | |
240 | ||
241 | spin_unlock(&bus->reg_lock); | |
242 | ||
243 | return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; | |
244 | } | |
245 | ||
246 | static irqreturn_t skl_threaded_handler(int irq, void *dev_id) | |
247 | { | |
76f56fae | 248 | struct hdac_bus *bus = dev_id; |
d8c2dab8 JK |
249 | u32 status; |
250 | ||
251 | status = snd_hdac_chip_readl(bus, INTSTS); | |
252 | ||
253 | snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); | |
254 | ||
255 | return IRQ_HANDLED; | |
256 | } | |
257 | ||
76f56fae | 258 | static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) |
d8c2dab8 | 259 | { |
bcc2a2dc | 260 | struct skl_dev *skl = bus_to_skl(bus); |
d8c2dab8 JK |
261 | int ret; |
262 | ||
263 | ret = request_threaded_irq(skl->pci->irq, skl_interrupt, | |
264 | skl_threaded_handler, | |
265 | IRQF_SHARED, | |
76f56fae | 266 | KBUILD_MODNAME, bus); |
d8c2dab8 JK |
267 | if (ret) { |
268 | dev_err(bus->dev, | |
269 | "unable to grab IRQ %d, disabling device\n", | |
270 | skl->pci->irq); | |
271 | return ret; | |
272 | } | |
273 | ||
274 | bus->irq = skl->pci->irq; | |
275 | pci_intx(skl->pci, 1); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
8b4a133c J |
280 | static int skl_suspend_late(struct device *dev) |
281 | { | |
282 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 283 | struct hdac_bus *bus = pci_get_drvdata(pci); |
bcc2a2dc | 284 | struct skl_dev *skl = bus_to_skl(bus); |
8b4a133c J |
285 | |
286 | return skl_suspend_late_dsp(skl); | |
287 | } | |
288 | ||
61722f44 | 289 | #ifdef CONFIG_PM |
76f56fae | 290 | static int _skl_suspend(struct hdac_bus *bus) |
61722f44 | 291 | { |
bcc2a2dc | 292 | struct skl_dev *skl = bus_to_skl(bus); |
51a01b8c | 293 | struct pci_dev *pci = to_pci_dev(bus->dev); |
61722f44 JK |
294 | int ret; |
295 | ||
76f56fae | 296 | snd_hdac_ext_bus_link_power_down_all(bus); |
61722f44 JK |
297 | |
298 | ret = skl_suspend_dsp(skl); | |
299 | if (ret < 0) | |
300 | return ret; | |
301 | ||
302 | snd_hdac_bus_stop_chip(bus); | |
51a01b8c D |
303 | update_pci_dword(pci, AZX_PCIREG_PGCTL, |
304 | AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); | |
0c8ba9d2 | 305 | skl_enable_miscbdcge(bus->dev, false); |
61722f44 | 306 | snd_hdac_bus_enter_link_reset(bus); |
0c8ba9d2 | 307 | skl_enable_miscbdcge(bus->dev, true); |
fe3f4442 | 308 | skl_cleanup_resources(skl); |
61722f44 JK |
309 | |
310 | return 0; | |
311 | } | |
312 | ||
76f56fae | 313 | static int _skl_resume(struct hdac_bus *bus) |
61722f44 | 314 | { |
bcc2a2dc | 315 | struct skl_dev *skl = bus_to_skl(bus); |
61722f44 JK |
316 | |
317 | skl_init_pci(skl); | |
7a1954de | 318 | skl_dum_set(bus); |
0c8ba9d2 | 319 | skl_init_chip(bus, true); |
61722f44 JK |
320 | |
321 | return skl_resume_dsp(skl); | |
322 | } | |
323 | #endif | |
324 | ||
d8c2dab8 JK |
325 | #ifdef CONFIG_PM_SLEEP |
326 | /* | |
327 | * power management | |
328 | */ | |
329 | static int skl_suspend(struct device *dev) | |
330 | { | |
331 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 332 | struct hdac_bus *bus = pci_get_drvdata(pci); |
bcc2a2dc | 333 | struct skl_dev *skl = bus_to_skl(bus); |
4f799e73 | 334 | int ret; |
d8c2dab8 | 335 | |
4557c305 JK |
336 | /* |
337 | * Do not suspend if streams which are marked ignore suspend are | |
338 | * running, we need to save the state for these and continue | |
339 | */ | |
340 | if (skl->supend_active) { | |
cce6c149 | 341 | /* turn off the links and stop the CORB/RIRB DMA if it is On */ |
76f56fae | 342 | snd_hdac_ext_bus_link_power_down_all(bus); |
cce6c149 | 343 | |
76f56fae RU |
344 | if (bus->cmd_dma_state) |
345 | snd_hdac_bus_stop_cmd_io(bus); | |
cce6c149 | 346 | |
1f4956fd | 347 | enable_irq_wake(bus->irq); |
4557c305 | 348 | pci_save_state(pci); |
4557c305 | 349 | } else { |
76f56fae | 350 | ret = _skl_suspend(bus); |
af037412 SP |
351 | if (ret < 0) |
352 | return ret; | |
bcc2a2dc | 353 | skl->fw_loaded = false; |
4557c305 | 354 | } |
af037412 | 355 | |
4f799e73 | 356 | return 0; |
d8c2dab8 JK |
357 | } |
358 | ||
359 | static int skl_resume(struct device *dev) | |
360 | { | |
361 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 362 | struct hdac_bus *bus = pci_get_drvdata(pci); |
bcc2a2dc | 363 | struct skl_dev *skl = bus_to_skl(bus); |
cce6c149 | 364 | struct hdac_ext_link *hlink = NULL; |
4557c305 JK |
365 | int ret; |
366 | ||
367 | /* | |
368 | * resume only when we are not in suspend active, otherwise need to | |
369 | * restore the device | |
370 | */ | |
371 | if (skl->supend_active) { | |
372 | pci_restore_state(pci); | |
76f56fae | 373 | snd_hdac_ext_bus_link_power_up_all(bus); |
1f4956fd | 374 | disable_irq_wake(bus->irq); |
cce6c149 VK |
375 | /* |
376 | * turn On the links which are On before active suspend | |
377 | * and start the CORB/RIRB DMA if On before | |
378 | * active suspend. | |
379 | */ | |
76f56fae | 380 | list_for_each_entry(hlink, &bus->hlink_list, list) { |
cce6c149 VK |
381 | if (hlink->ref_count) |
382 | snd_hdac_ext_bus_link_power_up(hlink); | |
383 | } | |
384 | ||
cc20c4df | 385 | ret = 0; |
76f56fae RU |
386 | if (bus->cmd_dma_state) |
387 | snd_hdac_bus_init_cmd_io(bus); | |
4557c305 | 388 | } else { |
76f56fae | 389 | ret = _skl_resume(bus); |
cce6c149 VK |
390 | |
391 | /* turn off the links which are off before suspend */ | |
76f56fae | 392 | list_for_each_entry(hlink, &bus->hlink_list, list) { |
cce6c149 VK |
393 | if (!hlink->ref_count) |
394 | snd_hdac_ext_bus_link_power_down(hlink); | |
395 | } | |
396 | ||
76f56fae RU |
397 | if (!bus->cmd_dma_state) |
398 | snd_hdac_bus_stop_cmd_io(bus); | |
4557c305 | 399 | } |
d8c2dab8 | 400 | |
4557c305 | 401 | return ret; |
d8c2dab8 JK |
402 | } |
403 | #endif /* CONFIG_PM_SLEEP */ | |
404 | ||
405 | #ifdef CONFIG_PM | |
406 | static int skl_runtime_suspend(struct device *dev) | |
407 | { | |
408 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 409 | struct hdac_bus *bus = pci_get_drvdata(pci); |
d8c2dab8 JK |
410 | |
411 | dev_dbg(bus->dev, "in %s\n", __func__); | |
412 | ||
76f56fae | 413 | return _skl_suspend(bus); |
d8c2dab8 JK |
414 | } |
415 | ||
416 | static int skl_runtime_resume(struct device *dev) | |
417 | { | |
418 | struct pci_dev *pci = to_pci_dev(dev); | |
76f56fae | 419 | struct hdac_bus *bus = pci_get_drvdata(pci); |
d8c2dab8 JK |
420 | |
421 | dev_dbg(bus->dev, "in %s\n", __func__); | |
422 | ||
76f56fae | 423 | return _skl_resume(bus); |
d8c2dab8 JK |
424 | } |
425 | #endif /* CONFIG_PM */ | |
426 | ||
427 | static const struct dev_pm_ops skl_pm = { | |
428 | SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) | |
429 | SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) | |
8b4a133c | 430 | .suspend_late = skl_suspend_late, |
d8c2dab8 JK |
431 | }; |
432 | ||
433 | /* | |
434 | * destructor | |
435 | */ | |
76f56fae | 436 | static int skl_free(struct hdac_bus *bus) |
d8c2dab8 | 437 | { |
bcc2a2dc | 438 | struct skl_dev *skl = bus_to_skl(bus); |
d8c2dab8 | 439 | |
ab1b732d | 440 | skl->init_done = 0; /* to be sure */ |
d8c2dab8 | 441 | |
76f56fae | 442 | snd_hdac_ext_stop_streams(bus); |
d8c2dab8 JK |
443 | |
444 | if (bus->irq >= 0) | |
76f56fae | 445 | free_irq(bus->irq, (void *)bus); |
d8c2dab8 | 446 | snd_hdac_bus_free_stream_pages(bus); |
76f56fae RU |
447 | snd_hdac_stream_free_all(bus); |
448 | snd_hdac_link_free_all(bus); | |
077411e5 VK |
449 | |
450 | if (bus->remap_addr) | |
451 | iounmap(bus->remap_addr); | |
452 | ||
d8c2dab8 JK |
453 | pci_release_regions(skl->pci); |
454 | pci_disable_device(skl->pci); | |
455 | ||
76f56fae | 456 | snd_hdac_ext_bus_exit(bus); |
d8c2dab8 | 457 | |
687ae9e2 TI |
458 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { |
459 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); | |
76f56fae | 460 | snd_hdac_i915_exit(bus); |
687ae9e2 | 461 | } |
ab1b732d | 462 | |
d8c2dab8 JK |
463 | return 0; |
464 | } | |
465 | ||
bc2bd45b SP |
466 | /* |
467 | * For each ssp there are 3 clocks (mclk/sclk/sclkfs). | |
468 | * e.g. for ssp0, clocks will be named as | |
469 | * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" | |
470 | * So for skl+, there are 6 ssps, so 18 clocks will be created. | |
471 | */ | |
472 | static struct skl_ssp_clk skl_ssp_clks[] = { | |
473 | {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, | |
474 | {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, | |
475 | {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, | |
476 | {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, | |
477 | {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, | |
478 | {.name = "ssp2_sclkfs"}, | |
479 | {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, | |
480 | {.name = "ssp5_sclkfs"}, | |
481 | }; | |
482 | ||
bcc2a2dc | 483 | static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl, |
9cdae435 RU |
484 | struct snd_soc_acpi_mach *machines) |
485 | { | |
9cdae435 RU |
486 | struct snd_soc_acpi_mach *mach; |
487 | ||
9cdae435 RU |
488 | /* point to common table */ |
489 | mach = snd_soc_acpi_intel_hda_machines; | |
490 | ||
491 | /* all entries in the machine table use the same firmware */ | |
492 | mach->fw_filename = machines->fw_filename; | |
493 | ||
494 | return mach; | |
495 | } | |
496 | ||
bcc2a2dc | 497 | static int skl_find_machine(struct skl_dev *skl, void *driver_data) |
cc18c5fd | 498 | { |
76f56fae | 499 | struct hdac_bus *bus = skl_to_bus(skl); |
7feb2f78 | 500 | struct snd_soc_acpi_mach *mach = driver_data; |
752c93aa | 501 | struct skl_machine_pdata *pdata; |
cc18c5fd | 502 | |
7feb2f78 | 503 | mach = snd_soc_acpi_find_machine(mach); |
9cdae435 RU |
504 | if (!mach) { |
505 | dev_dbg(bus->dev, "No matching I2S machine driver found\n"); | |
506 | mach = skl_find_hda_machine(skl, driver_data); | |
507 | if (!mach) { | |
508 | dev_err(bus->dev, "No matching machine driver found\n"); | |
509 | return -ENODEV; | |
510 | } | |
cc18c5fd | 511 | } |
752c93aa PB |
512 | |
513 | skl->mach = mach; | |
aecf6fd8 | 514 | skl->fw_name = mach->fw_filename; |
5f15f267 | 515 | pdata = mach->pdata; |
752c93aa | 516 | |
5f15f267 | 517 | if (pdata) { |
752c93aa | 518 | skl->use_tplg_pcm = pdata->use_tplg_pcm; |
1169cbf6 PLB |
519 | mach->mach_params.dmic_num = |
520 | intel_nhlt_get_dmic_geo(&skl->pci->dev, | |
521 | skl->nhlt); | |
5f15f267 | 522 | } |
752c93aa PB |
523 | |
524 | return 0; | |
525 | } | |
526 | ||
bcc2a2dc | 527 | static int skl_machine_device_register(struct skl_dev *skl) |
752c93aa | 528 | { |
752c93aa | 529 | struct snd_soc_acpi_mach *mach = skl->mach; |
9cdae435 | 530 | struct hdac_bus *bus = skl_to_bus(skl); |
752c93aa PB |
531 | struct platform_device *pdev; |
532 | int ret; | |
cc18c5fd VK |
533 | |
534 | pdev = platform_device_alloc(mach->drv_name, -1); | |
535 | if (pdev == NULL) { | |
536 | dev_err(bus->dev, "platform device alloc failed\n"); | |
537 | return -EIO; | |
538 | } | |
539 | ||
5a619b9e PLB |
540 | mach->mach_params.platform = dev_name(bus->dev); |
541 | mach->mach_params.codec_mask = bus->codec_mask; | |
542 | ||
543 | ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach)); | |
544 | if (ret) { | |
545 | dev_err(bus->dev, "failed to add machine device platform data\n"); | |
546 | platform_device_put(pdev); | |
547 | return ret; | |
548 | } | |
549 | ||
cc18c5fd VK |
550 | ret = platform_device_add(pdev); |
551 | if (ret) { | |
552 | dev_err(bus->dev, "failed to add machine device\n"); | |
553 | platform_device_put(pdev); | |
554 | return -EIO; | |
555 | } | |
f65cf7d6 | 556 | |
f65cf7d6 | 557 | |
cc18c5fd VK |
558 | skl->i2s_dev = pdev; |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
bcc2a2dc | 563 | static void skl_machine_device_unregister(struct skl_dev *skl) |
cc18c5fd VK |
564 | { |
565 | if (skl->i2s_dev) | |
566 | platform_device_unregister(skl->i2s_dev); | |
567 | } | |
568 | ||
bcc2a2dc | 569 | static int skl_dmic_device_register(struct skl_dev *skl) |
d8c2dab8 | 570 | { |
76f56fae | 571 | struct hdac_bus *bus = skl_to_bus(skl); |
d8c2dab8 JK |
572 | struct platform_device *pdev; |
573 | int ret; | |
574 | ||
575 | /* SKL has one dmic port, so allocate dmic device for this */ | |
576 | pdev = platform_device_alloc("dmic-codec", -1); | |
577 | if (!pdev) { | |
578 | dev_err(bus->dev, "failed to allocate dmic device\n"); | |
579 | return -ENOMEM; | |
580 | } | |
581 | ||
582 | ret = platform_device_add(pdev); | |
583 | if (ret) { | |
584 | dev_err(bus->dev, "failed to add dmic device: %d\n", ret); | |
585 | platform_device_put(pdev); | |
586 | return ret; | |
587 | } | |
588 | skl->dmic_dev = pdev; | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
bcc2a2dc | 593 | static void skl_dmic_device_unregister(struct skl_dev *skl) |
d8c2dab8 JK |
594 | { |
595 | if (skl->dmic_dev) | |
596 | platform_device_unregister(skl->dmic_dev); | |
597 | } | |
598 | ||
bc2bd45b SP |
599 | static struct skl_clk_parent_src skl_clk_src[] = { |
600 | { .clk_id = SKL_XTAL, .name = "xtal" }, | |
601 | { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, | |
602 | { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, | |
603 | }; | |
604 | ||
605 | struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) | |
606 | { | |
607 | unsigned int i; | |
608 | ||
609 | for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { | |
610 | if (skl_clk_src[i].clk_id == clk_id) | |
611 | return &skl_clk_src[i]; | |
612 | } | |
613 | ||
614 | return NULL; | |
615 | } | |
616 | ||
8e79ec98 | 617 | static void init_skl_xtal_rate(int pci_id) |
bc2bd45b SP |
618 | { |
619 | switch (pci_id) { | |
620 | case 0x9d70: | |
621 | case 0x9d71: | |
622 | skl_clk_src[0].rate = 24000000; | |
623 | return; | |
624 | ||
625 | default: | |
626 | skl_clk_src[0].rate = 19200000; | |
627 | return; | |
628 | } | |
629 | } | |
630 | ||
bcc2a2dc | 631 | static int skl_clock_device_register(struct skl_dev *skl) |
bc2bd45b SP |
632 | { |
633 | struct platform_device_info pdevinfo = {NULL}; | |
634 | struct skl_clk_pdata *clk_pdata; | |
635 | ||
0c3d0ced CR |
636 | if (!skl->nhlt) |
637 | return 0; | |
638 | ||
bc2bd45b SP |
639 | clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), |
640 | GFP_KERNEL); | |
641 | if (!clk_pdata) | |
642 | return -ENOMEM; | |
643 | ||
644 | init_skl_xtal_rate(skl->pci->device); | |
645 | ||
646 | clk_pdata->parent_clks = skl_clk_src; | |
647 | clk_pdata->ssp_clks = skl_ssp_clks; | |
648 | clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); | |
649 | ||
650 | /* Query NHLT to fill the rates and parent */ | |
651 | skl_get_clks(skl, clk_pdata->ssp_clks); | |
652 | clk_pdata->pvt_data = skl; | |
653 | ||
654 | /* Register Platform device */ | |
655 | pdevinfo.parent = &skl->pci->dev; | |
656 | pdevinfo.id = -1; | |
657 | pdevinfo.name = "skl-ssp-clk"; | |
658 | pdevinfo.data = clk_pdata; | |
659 | pdevinfo.size_data = sizeof(*clk_pdata); | |
660 | skl->clk_dev = platform_device_register_full(&pdevinfo); | |
661 | return PTR_ERR_OR_ZERO(skl->clk_dev); | |
662 | } | |
663 | ||
bcc2a2dc | 664 | static void skl_clock_device_unregister(struct skl_dev *skl) |
bc2bd45b SP |
665 | { |
666 | if (skl->clk_dev) | |
667 | platform_device_unregister(skl->clk_dev); | |
668 | } | |
669 | ||
8c4e7c2e PLB |
670 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
671 | ||
6bae5ea9 RU |
672 | #define IDISP_INTEL_VENDOR_ID 0x80860000 |
673 | ||
674 | /* | |
675 | * load the legacy codec driver | |
676 | */ | |
677 | static void load_codec_module(struct hda_codec *codec) | |
678 | { | |
679 | #ifdef MODULE | |
680 | char modalias[MODULE_NAME_LEN]; | |
681 | const char *mod = NULL; | |
682 | ||
683 | snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); | |
684 | mod = modalias; | |
685 | dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); | |
686 | request_module(mod); | |
687 | #endif | |
688 | } | |
689 | ||
8c4e7c2e PLB |
690 | #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ |
691 | ||
d8c2dab8 JK |
692 | /* |
693 | * Probe the given codec address | |
694 | */ | |
76f56fae | 695 | static int probe_codec(struct hdac_bus *bus, int addr) |
d8c2dab8 | 696 | { |
d8c2dab8 JK |
697 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | |
698 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
e6a33532 | 699 | unsigned int res = -1; |
bcc2a2dc | 700 | struct skl_dev *skl = bus_to_skl(bus); |
8c4e7c2e | 701 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
6bae5ea9 | 702 | struct hdac_hda_priv *hda_codec; |
6bae5ea9 | 703 | int err; |
8c4e7c2e PLB |
704 | #endif |
705 | struct hdac_device *hdev; | |
d8c2dab8 JK |
706 | |
707 | mutex_lock(&bus->cmd_mutex); | |
708 | snd_hdac_bus_send_cmd(bus, cmd); | |
709 | snd_hdac_bus_get_response(bus, addr, &res); | |
710 | mutex_unlock(&bus->cmd_mutex); | |
711 | if (res == -1) | |
712 | return -EIO; | |
00deadb5 | 713 | dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); |
d8c2dab8 | 714 | |
8c4e7c2e | 715 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
6bae5ea9 RU |
716 | hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), |
717 | GFP_KERNEL); | |
718 | if (!hda_codec) | |
6298542f RU |
719 | return -ENOMEM; |
720 | ||
6bae5ea9 RU |
721 | hda_codec->codec.bus = skl_to_hbus(skl); |
722 | hdev = &hda_codec->codec.core; | |
723 | ||
724 | err = snd_hdac_ext_bus_device_init(bus, addr, hdev); | |
725 | if (err < 0) | |
726 | return err; | |
727 | ||
728 | /* use legacy bus only for HDA codecs, idisp uses ext bus */ | |
729 | if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { | |
730 | hdev->type = HDA_DEV_LEGACY; | |
731 | load_codec_module(&hda_codec->codec); | |
732 | } | |
733 | return 0; | |
8c4e7c2e PLB |
734 | #else |
735 | hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); | |
736 | if (!hdev) | |
737 | return -ENOMEM; | |
738 | ||
739 | return snd_hdac_ext_bus_device_init(bus, addr, hdev); | |
740 | #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ | |
d8c2dab8 JK |
741 | } |
742 | ||
743 | /* Codec initialization */ | |
76f56fae | 744 | static void skl_codec_create(struct hdac_bus *bus) |
d8c2dab8 | 745 | { |
d8c2dab8 JK |
746 | int c, max_slots; |
747 | ||
748 | max_slots = HDA_MAX_CODECS; | |
749 | ||
750 | /* First try to probe all given codec slots */ | |
751 | for (c = 0; c < max_slots; c++) { | |
752 | if ((bus->codec_mask & (1 << c))) { | |
76f56fae | 753 | if (probe_codec(bus, c) < 0) { |
d8c2dab8 JK |
754 | /* |
755 | * Some BIOSen give you wrong codec addresses | |
756 | * that don't exist | |
757 | */ | |
758 | dev_warn(bus->dev, | |
759 | "Codec #%d probe error; disabling it...\n", c); | |
760 | bus->codec_mask &= ~(1 << c); | |
761 | /* | |
762 | * More badly, accessing to a non-existing | |
763 | * codec often screws up the controller bus, | |
764 | * and disturbs the further communications. | |
765 | * Thus if an error occurs during probing, | |
766 | * better to reset the controller bus to get | |
767 | * back to the sanity state. | |
768 | */ | |
769 | snd_hdac_bus_stop_chip(bus); | |
0c8ba9d2 | 770 | skl_init_chip(bus, true); |
d8c2dab8 JK |
771 | } |
772 | } | |
773 | } | |
d8c2dab8 JK |
774 | } |
775 | ||
776 | static const struct hdac_bus_ops bus_core_ops = { | |
777 | .command = snd_hdac_bus_send_cmd, | |
778 | .get_response = snd_hdac_bus_get_response, | |
779 | }; | |
780 | ||
ab1b732d VK |
781 | static int skl_i915_init(struct hdac_bus *bus) |
782 | { | |
783 | int err; | |
784 | ||
785 | /* | |
786 | * The HDMI codec is in GPU so we need to ensure that it is powered | |
787 | * up and ready for probe | |
788 | */ | |
789 | err = snd_hdac_i915_init(bus); | |
790 | if (err < 0) | |
791 | return err; | |
792 | ||
4f799e73 | 793 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); |
ab1b732d | 794 | |
4f799e73 | 795 | return 0; |
ab1b732d VK |
796 | } |
797 | ||
798 | static void skl_probe_work(struct work_struct *work) | |
799 | { | |
bcc2a2dc | 800 | struct skl_dev *skl = container_of(work, struct skl_dev, probe_work); |
76f56fae | 801 | struct hdac_bus *bus = skl_to_bus(skl); |
ab1b732d VK |
802 | struct hdac_ext_link *hlink = NULL; |
803 | int err; | |
804 | ||
805 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { | |
806 | err = skl_i915_init(bus); | |
807 | if (err < 0) | |
808 | return; | |
809 | } | |
810 | ||
0178a062 CR |
811 | skl_init_pci(skl); |
812 | skl_dum_set(bus); | |
813 | ||
ab1b732d VK |
814 | err = skl_init_chip(bus, true); |
815 | if (err < 0) { | |
816 | dev_err(bus->dev, "Init chip failed with err: %d\n", err); | |
817 | goto out_err; | |
818 | } | |
819 | ||
820 | /* codec detection */ | |
821 | if (!bus->codec_mask) | |
822 | dev_info(bus->dev, "no hda codecs found!\n"); | |
823 | ||
824 | /* create codec instances */ | |
76f56fae | 825 | skl_codec_create(bus); |
ab1b732d | 826 | |
752c93aa PB |
827 | /* register platform dai and controls */ |
828 | err = skl_platform_register(bus->dev); | |
829 | if (err < 0) { | |
830 | dev_err(bus->dev, "platform register failed: %d\n", err); | |
687ae9e2 | 831 | goto out_err; |
752c93aa PB |
832 | } |
833 | ||
7f981bdc PLB |
834 | err = skl_machine_device_register(skl); |
835 | if (err < 0) { | |
836 | dev_err(bus->dev, "machine register failed: %d\n", err); | |
837 | goto out_err; | |
752c93aa PB |
838 | } |
839 | ||
4c10473d PLB |
840 | /* |
841 | * we are done probing so decrement link counts | |
842 | */ | |
843 | list_for_each_entry(hlink, &bus->hlink_list, list) | |
844 | snd_hdac_ext_bus_link_put(bus, hlink); | |
845 | ||
4f799e73 TI |
846 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
847 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); | |
ab1b732d | 848 | |
ab1b732d VK |
849 | /* configure PM */ |
850 | pm_runtime_put_noidle(bus->dev); | |
851 | pm_runtime_allow(bus->dev); | |
852 | skl->init_done = 1; | |
853 | ||
854 | return; | |
855 | ||
856 | out_err: | |
857 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) | |
4f799e73 | 858 | snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); |
ab1b732d VK |
859 | } |
860 | ||
d8c2dab8 JK |
861 | /* |
862 | * constructor | |
863 | */ | |
864 | static int skl_create(struct pci_dev *pci, | |
bcc2a2dc | 865 | struct skl_dev **rskl) |
d8c2dab8 | 866 | { |
6bae5ea9 | 867 | struct hdac_ext_bus_ops *ext_ops = NULL; |
bcc2a2dc | 868 | struct skl_dev *skl; |
76f56fae | 869 | struct hdac_bus *bus; |
00deadb5 | 870 | struct hda_bus *hbus; |
d8c2dab8 JK |
871 | int err; |
872 | ||
873 | *rskl = NULL; | |
874 | ||
875 | err = pci_enable_device(pci); | |
876 | if (err < 0) | |
877 | return err; | |
878 | ||
879 | skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); | |
880 | if (!skl) { | |
881 | pci_disable_device(pci); | |
882 | return -ENOMEM; | |
883 | } | |
76f56fae | 884 | |
00deadb5 | 885 | hbus = skl_to_hbus(skl); |
76f56fae | 886 | bus = skl_to_bus(skl); |
6bae5ea9 | 887 | |
776cb3b8 AS |
888 | INIT_LIST_HEAD(&skl->ppl_list); |
889 | INIT_LIST_HEAD(&skl->bind_list); | |
890 | ||
8c4e7c2e | 891 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
6bae5ea9 RU |
892 | ext_ops = snd_soc_hdac_hda_get_ops(); |
893 | #endif | |
19abfefd | 894 | snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, ext_ops); |
76f56fae | 895 | bus->use_posbuf = 1; |
d8c2dab8 | 896 | skl->pci = pci; |
ab1b732d | 897 | INIT_WORK(&skl->probe_work, skl_probe_work); |
76f56fae | 898 | bus->bdl_pos_adj = 0; |
d8c2dab8 | 899 | |
00deadb5 RU |
900 | mutex_init(&hbus->prepare_mutex); |
901 | hbus->pci = pci; | |
902 | hbus->mixer_assigned = -1; | |
903 | hbus->modelname = "sklbus"; | |
904 | ||
d8c2dab8 JK |
905 | *rskl = skl; |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
76f56fae | 910 | static int skl_first_init(struct hdac_bus *bus) |
d8c2dab8 | 911 | { |
bcc2a2dc | 912 | struct skl_dev *skl = bus_to_skl(bus); |
d8c2dab8 JK |
913 | struct pci_dev *pci = skl->pci; |
914 | int err; | |
915 | unsigned short gcap; | |
916 | int cp_streams, pb_streams, start_idx; | |
917 | ||
918 | err = pci_request_regions(pci, "Skylake HD audio"); | |
919 | if (err < 0) | |
920 | return err; | |
921 | ||
922 | bus->addr = pci_resource_start(pci, 0); | |
923 | bus->remap_addr = pci_ioremap_bar(pci, 0); | |
924 | if (bus->remap_addr == NULL) { | |
925 | dev_err(bus->dev, "ioremap error\n"); | |
926 | return -ENXIO; | |
927 | } | |
928 | ||
ec8ae570 | 929 | snd_hdac_bus_parse_capabilities(bus); |
05057001 | 930 | |
fa11ab56 PLB |
931 | /* check if PPCAP exists */ |
932 | if (!bus->ppcap) { | |
933 | dev_err(bus->dev, "bus ppcap not set, HDaudio or DSP not present?\n"); | |
934 | return -ENODEV; | |
935 | } | |
936 | ||
542cedec YZ |
937 | if (skl_acquire_irq(bus, 0) < 0) |
938 | return -EBUSY; | |
939 | ||
d8c2dab8 | 940 | pci_set_master(pci); |
542cedec | 941 | synchronize_irq(bus->irq); |
d8c2dab8 JK |
942 | |
943 | gcap = snd_hdac_chip_readw(bus, GCAP); | |
944 | dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); | |
945 | ||
d8c2dab8 JK |
946 | /* read number of streams from GCAP register */ |
947 | cp_streams = (gcap >> 8) & 0x0f; | |
948 | pb_streams = (gcap >> 12) & 0x0f; | |
949 | ||
fa11ab56 PLB |
950 | if (!pb_streams && !cp_streams) { |
951 | dev_err(bus->dev, "no streams found in GCAP definitions?\n"); | |
d8c2dab8 | 952 | return -EIO; |
fa11ab56 | 953 | } |
d8c2dab8 | 954 | |
76f56fae | 955 | bus->num_streams = cp_streams + pb_streams; |
d8c2dab8 | 956 | |
fa11ab56 PLB |
957 | /* allow 64bit DMA address if supported by H/W */ |
958 | if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { | |
959 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); | |
960 | } else { | |
961 | dma_set_mask(bus->dev, DMA_BIT_MASK(32)); | |
962 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); | |
963 | } | |
964 | ||
d8c2dab8 JK |
965 | /* initialize streams */ |
966 | snd_hdac_ext_stream_init_all | |
76f56fae | 967 | (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); |
d8c2dab8 JK |
968 | start_idx = cp_streams; |
969 | snd_hdac_ext_stream_init_all | |
76f56fae | 970 | (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); |
d8c2dab8 JK |
971 | |
972 | err = snd_hdac_bus_alloc_stream_pages(bus); | |
973 | if (err < 0) | |
974 | return err; | |
975 | ||
0178a062 | 976 | return 0; |
d8c2dab8 JK |
977 | } |
978 | ||
979 | static int skl_probe(struct pci_dev *pci, | |
980 | const struct pci_device_id *pci_id) | |
981 | { | |
bcc2a2dc | 982 | struct skl_dev *skl; |
d8c2dab8 JK |
983 | struct hdac_bus *bus = NULL; |
984 | int err; | |
985 | ||
d82b51c8 PLB |
986 | switch (skl_pci_binding) { |
987 | case SND_SKL_PCI_BIND_AUTO: | |
7eb993f1 JK |
988 | err = snd_intel_dsp_driver_probe(pci); |
989 | if (err != SND_INTEL_DSP_DRIVER_ANY && | |
990 | err != SND_INTEL_DSP_DRIVER_SST) | |
d82b51c8 | 991 | return -ENODEV; |
d82b51c8 PLB |
992 | break; |
993 | case SND_SKL_PCI_BIND_LEGACY: | |
994 | dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, aborting probe\n"); | |
995 | return -ENODEV; | |
996 | case SND_SKL_PCI_BIND_ASOC: | |
997 | dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n"); | |
998 | break; | |
999 | default: | |
1000 | dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n"); | |
1001 | break; | |
1002 | } | |
1003 | ||
d8c2dab8 | 1004 | /* we use ext core ops, so provide NULL for ops here */ |
19abfefd | 1005 | err = skl_create(pci, &skl); |
d8c2dab8 JK |
1006 | if (err < 0) |
1007 | return err; | |
1008 | ||
76f56fae | 1009 | bus = skl_to_bus(skl); |
d8c2dab8 | 1010 | |
76f56fae | 1011 | err = skl_first_init(bus); |
f231c34c PLB |
1012 | if (err < 0) { |
1013 | dev_err(bus->dev, "skl_first_init failed with err: %d\n", err); | |
d8c2dab8 | 1014 | goto out_free; |
f231c34c | 1015 | } |
d8c2dab8 | 1016 | |
4b235c43 VK |
1017 | skl->pci_id = pci->device; |
1018 | ||
2e9dc2b6 VK |
1019 | device_disable_async_suspend(bus->dev); |
1020 | ||
1169cbf6 | 1021 | skl->nhlt = intel_nhlt_init(bus->dev); |
87b2bdf0 | 1022 | |
979cf59a | 1023 | if (skl->nhlt == NULL) { |
f231c34c PLB |
1024 | #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) |
1025 | dev_err(bus->dev, "no nhlt info found\n"); | |
979cf59a | 1026 | err = -ENODEV; |
ab1b732d | 1027 | goto out_free; |
f231c34c PLB |
1028 | #else |
1029 | dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDaudio codec\n"); | |
1030 | #endif | |
1031 | } else { | |
0cf5a171 | 1032 | |
f231c34c PLB |
1033 | err = skl_nhlt_create_sysfs(skl); |
1034 | if (err < 0) { | |
1035 | dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err); | |
1036 | goto out_nhlt_free; | |
1037 | } | |
4b235c43 | 1038 | |
f231c34c | 1039 | skl_nhlt_update_topology_bin(skl); |
d8c2dab8 | 1040 | |
bc2bd45b SP |
1041 | /* create device for dsp clk */ |
1042 | err = skl_clock_device_register(skl); | |
f231c34c PLB |
1043 | if (err < 0) { |
1044 | dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err); | |
bc2bd45b | 1045 | goto out_clk_free; |
f231c34c PLB |
1046 | } |
1047 | } | |
bc2bd45b | 1048 | |
76f56fae | 1049 | pci_set_drvdata(skl->pci, bus); |
cc18c5fd | 1050 | |
bc2bd45b | 1051 | |
7f981bdc | 1052 | err = skl_find_machine(skl, (void *)pci_id->driver_data); |
f231c34c PLB |
1053 | if (err < 0) { |
1054 | dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err); | |
7f981bdc | 1055 | goto out_nhlt_free; |
f231c34c | 1056 | } |
cc18c5fd | 1057 | |
7f981bdc PLB |
1058 | err = skl_init_dsp(skl); |
1059 | if (err < 0) { | |
1060 | dev_dbg(bus->dev, "error failed to register dsp\n"); | |
1061 | goto out_nhlt_free; | |
05057001 | 1062 | } |
bcc2a2dc CR |
1063 | skl->enable_miscbdcge = skl_enable_miscbdcge; |
1064 | skl->clock_power_gating = skl_clock_power_gating; | |
7f981bdc | 1065 | |
ec8ae570 | 1066 | if (bus->mlcap) |
76f56fae | 1067 | snd_hdac_ext_bus_get_ml_capabilities(bus); |
05057001 | 1068 | |
d8c2dab8 JK |
1069 | /* create device for soc dmic */ |
1070 | err = skl_dmic_device_register(skl); | |
f231c34c PLB |
1071 | if (err < 0) { |
1072 | dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err); | |
2a29b200 | 1073 | goto out_dsp_free; |
f231c34c | 1074 | } |
d8c2dab8 | 1075 | |
ab1b732d | 1076 | schedule_work(&skl->probe_work); |
d8c2dab8 JK |
1077 | |
1078 | return 0; | |
1079 | ||
2a29b200 JK |
1080 | out_dsp_free: |
1081 | skl_free_dsp(skl); | |
bc2bd45b SP |
1082 | out_clk_free: |
1083 | skl_clock_device_unregister(skl); | |
c286b3f9 | 1084 | out_nhlt_free: |
0c3d0ced CR |
1085 | if (skl->nhlt) |
1086 | intel_nhlt_free(skl->nhlt); | |
d8c2dab8 | 1087 | out_free: |
76f56fae | 1088 | skl_free(bus); |
d8c2dab8 JK |
1089 | |
1090 | return err; | |
1091 | } | |
1092 | ||
c5a76a24 JK |
1093 | static void skl_shutdown(struct pci_dev *pci) |
1094 | { | |
76f56fae | 1095 | struct hdac_bus *bus = pci_get_drvdata(pci); |
c5a76a24 JK |
1096 | struct hdac_stream *s; |
1097 | struct hdac_ext_stream *stream; | |
bcc2a2dc | 1098 | struct skl_dev *skl; |
c5a76a24 | 1099 | |
76f56fae | 1100 | if (!bus) |
c5a76a24 JK |
1101 | return; |
1102 | ||
76f56fae | 1103 | skl = bus_to_skl(bus); |
c5a76a24 | 1104 | |
ab1b732d | 1105 | if (!skl->init_done) |
c5a76a24 JK |
1106 | return; |
1107 | ||
76f56fae | 1108 | snd_hdac_ext_stop_streams(bus); |
c5a76a24 JK |
1109 | list_for_each_entry(s, &bus->stream_list, list) { |
1110 | stream = stream_to_hdac_ext_stream(s); | |
76f56fae | 1111 | snd_hdac_ext_stream_decouple(bus, stream, false); |
c5a76a24 JK |
1112 | } |
1113 | ||
1114 | snd_hdac_bus_stop_chip(bus); | |
1115 | } | |
1116 | ||
d8c2dab8 JK |
1117 | static void skl_remove(struct pci_dev *pci) |
1118 | { | |
76f56fae | 1119 | struct hdac_bus *bus = pci_get_drvdata(pci); |
bcc2a2dc | 1120 | struct skl_dev *skl = bus_to_skl(bus); |
d8c2dab8 | 1121 | |
776cb3b8 | 1122 | cancel_work_sync(&skl->probe_work); |
d8018361 | 1123 | |
6d13f62d | 1124 | pm_runtime_get_noresume(&pci->dev); |
7373f481 VK |
1125 | |
1126 | /* codec removal, invoke bus_device_remove */ | |
76f56fae | 1127 | snd_hdac_ext_bus_device_remove(bus); |
7373f481 | 1128 | |
d8c2dab8 | 1129 | skl_platform_unregister(&pci->dev); |
2a29b200 | 1130 | skl_free_dsp(skl); |
cc18c5fd | 1131 | skl_machine_device_unregister(skl); |
d8c2dab8 | 1132 | skl_dmic_device_unregister(skl); |
bc2bd45b | 1133 | skl_clock_device_unregister(skl); |
0cf5a171 | 1134 | skl_nhlt_remove_sysfs(skl); |
0c3d0ced CR |
1135 | if (skl->nhlt) |
1136 | intel_nhlt_free(skl->nhlt); | |
76f56fae | 1137 | skl_free(bus); |
d8c2dab8 JK |
1138 | dev_set_drvdata(&pci->dev, NULL); |
1139 | } | |
1140 | ||
1141 | /* PCI IDs */ | |
1142 | static const struct pci_device_id skl_ids[] = { | |
35bc99aa | 1143 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL) |
d8c2dab8 | 1144 | /* Sunrise Point-LP */ |
cc18c5fd | 1145 | { PCI_DEVICE(0x8086, 0x9d70), |
cbaa7f0b | 1146 | .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, |
35bc99aa PLB |
1147 | #endif |
1148 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL) | |
b379b1fa SV |
1149 | /* BXT-P */ |
1150 | { PCI_DEVICE(0x8086, 0x5a98), | |
cbaa7f0b | 1151 | .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, |
35bc99aa PLB |
1152 | #endif |
1153 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL) | |
451dfb5f VK |
1154 | /* KBL */ |
1155 | { PCI_DEVICE(0x8086, 0x9D71), | |
cbaa7f0b | 1156 | .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, |
35bc99aa PLB |
1157 | #endif |
1158 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK) | |
25504863 VK |
1159 | /* GLK */ |
1160 | { PCI_DEVICE(0x8086, 0x3198), | |
cbaa7f0b | 1161 | .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, |
35bc99aa PLB |
1162 | #endif |
1163 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL) | |
86d7ce3d GS |
1164 | /* CNL */ |
1165 | { PCI_DEVICE(0x8086, 0x9dc8), | |
cbaa7f0b | 1166 | .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, |
35bc99aa PLB |
1167 | #endif |
1168 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL) | |
e6b98db9 TI |
1169 | /* CFL */ |
1170 | { PCI_DEVICE(0x8086, 0xa348), | |
1171 | .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, | |
5f740b24 EG |
1172 | #endif |
1173 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP) | |
1174 | /* CML-LP */ | |
1175 | { PCI_DEVICE(0x8086, 0x02c8), | |
1176 | .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, | |
1177 | #endif | |
1178 | #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H) | |
1179 | /* CML-H */ | |
1180 | { PCI_DEVICE(0x8086, 0x06c8), | |
1181 | .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, | |
35bc99aa | 1182 | #endif |
d8c2dab8 JK |
1183 | { 0, } |
1184 | }; | |
1185 | MODULE_DEVICE_TABLE(pci, skl_ids); | |
1186 | ||
1187 | /* pci_driver definition */ | |
1188 | static struct pci_driver skl_driver = { | |
1189 | .name = KBUILD_MODNAME, | |
1190 | .id_table = skl_ids, | |
1191 | .probe = skl_probe, | |
1192 | .remove = skl_remove, | |
c5a76a24 | 1193 | .shutdown = skl_shutdown, |
d8c2dab8 JK |
1194 | .driver = { |
1195 | .pm = &skl_pm, | |
1196 | }, | |
1197 | }; | |
1198 | module_pci_driver(skl_driver); | |
1199 | ||
1200 | MODULE_LICENSE("GPL v2"); | |
1201 | MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); |