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[mirror_ubuntu-artful-kernel.git] / sound / soc / intel / sst-haswell-ipc.c
CommitLineData
a4b12990
MB		 1/*
2 * Intel SST Haswell/Broadwell IPC Support
3 *
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/device.h>
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/export.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
a4b12990
MB		 28#include <linux/platform_device.h>
29#include <linux/kthread.h>
30#include <linux/firmware.h>
31#include <linux/dma-mapping.h>
32#include <linux/debugfs.h>
33
34#include "sst-haswell-ipc.h"
35#include "sst-dsp.h"
36#include "sst-dsp-priv.h"
37
38/* Global Message - Generic */
39#define IPC_GLB_TYPE_SHIFT 24
40#define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
41#define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
42
43/* Global Message - Reply */
44#define IPC_GLB_REPLY_SHIFT 0
45#define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
46#define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
47
48/* Stream Message - Generic */
49#define IPC_STR_TYPE_SHIFT 20
50#define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
51#define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
52#define IPC_STR_ID_SHIFT 16
53#define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
54#define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
55
56/* Stream Message - Reply */
57#define IPC_STR_REPLY_SHIFT 0
58#define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
59
60/* Stream Stage Message - Generic */
61#define IPC_STG_TYPE_SHIFT 12
62#define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
63#define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
64#define IPC_STG_ID_SHIFT 10
65#define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
66#define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
67
68/* Stream Stage Message - Reply */
69#define IPC_STG_REPLY_SHIFT 0
70#define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
71
72/* Debug Log Message - Generic */
73#define IPC_LOG_OP_SHIFT 20
74#define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
75#define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
76#define IPC_LOG_ID_SHIFT 16
77#define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
78#define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
79
80/* IPC message timeout (msecs) */
81#define IPC_TIMEOUT_MSECS 300
82#define IPC_BOOT_MSECS 200
83#define IPC_MSG_WAIT 0
84#define IPC_MSG_NOWAIT 1
85
86/* Firmware Ready Message */
87#define IPC_FW_READY (0x1 << 29)
88#define IPC_STATUS_MASK (0x3 << 30)
89
90#define IPC_EMPTY_LIST_SIZE 8
91#define IPC_MAX_STREAMS 4
92
93/* Mailbox */
94#define IPC_MAX_MAILBOX_BYTES 256
95
96/* Global Message - Types and Replies */
97enum ipc_glb_type {
98 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
99 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
100 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
101 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
102 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
103 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
104 /* Request to store firmware context during D0->D3 transition */
105 IPC_GLB_REQUEST_DUMP = 7,
106 /* Request to restore firmware context during D3->D0 transition */
107 IPC_GLB_RESTORE_CONTEXT = 8,
108 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
109 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
110 IPC_GLB_SHORT_REPLY = 11,
111 IPC_GLB_ENTER_DX_STATE = 12,
112 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
113 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
114 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
115 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
116};
117
118enum ipc_glb_reply {
119 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
120 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
121 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
122 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
123 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
124 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
125 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
126 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
127 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
128 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
129 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
130};
131
132/* Stream Message - Types */
133enum ipc_str_operation {
134 IPC_STR_RESET = 0,
135 IPC_STR_PAUSE = 1,
136 IPC_STR_RESUME = 2,
137 IPC_STR_STAGE_MESSAGE = 3,
138 IPC_STR_NOTIFICATION = 4,
139 IPC_STR_MAX_MESSAGE
140};
141
142/* Stream Stage Message Types */
143enum ipc_stg_operation {
144 IPC_STG_GET_VOLUME = 0,
145 IPC_STG_SET_VOLUME,
146 IPC_STG_SET_WRITE_POSITION,
147 IPC_STG_SET_FX_ENABLE,
148 IPC_STG_SET_FX_DISABLE,
149 IPC_STG_SET_FX_GET_PARAM,
150 IPC_STG_SET_FX_SET_PARAM,
151 IPC_STG_SET_FX_GET_INFO,
152 IPC_STG_MUTE_LOOPBACK,
153 IPC_STG_MAX_MESSAGE
154};
155
156/* Stream Stage Message Types For Notification*/
157enum ipc_stg_operation_notify {
158 IPC_POSITION_CHANGED = 0,
159 IPC_STG_GLITCH,
160 IPC_STG_MAX_NOTIFY
161};
162
163enum ipc_glitch_type {
164 IPC_GLITCH_UNDERRUN = 1,
165 IPC_GLITCH_DECODER_ERROR,
166 IPC_GLITCH_DOUBLED_WRITE_POS,
167 IPC_GLITCH_MAX
168};
169
170/* Debug Control */
171enum ipc_debug_operation {
172 IPC_DEBUG_ENABLE_LOG = 0,
173 IPC_DEBUG_DISABLE_LOG = 1,
174 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
175 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
176 IPC_DEBUG_MAX_DEBUG_LOG
177};
178
179/* Firmware Ready */
180struct sst_hsw_ipc_fw_ready {
181 u32 inbox_offset;
182 u32 outbox_offset;
183 u32 inbox_size;
184 u32 outbox_size;
185 u32 fw_info_size;
249adddb 186 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
a4b12990
MB		 187} __attribute__((packed));
188
189struct ipc_message {
190 struct list_head list;
191 u32 header;
192
193 /* direction wrt host CPU */
194 char tx_data[IPC_MAX_MAILBOX_BYTES];
195 size_t tx_size;
196 char rx_data[IPC_MAX_MAILBOX_BYTES];
197 size_t rx_size;
198
199 wait_queue_head_t waitq;
200 bool pending;
201 bool complete;
202 bool wait;
203 int errno;
204};
205
206struct sst_hsw_stream;
207struct sst_hsw;
208
209/* Stream infomation */
210struct sst_hsw_stream {
211 /* configuration */
212 struct sst_hsw_ipc_stream_alloc_req request;
213 struct sst_hsw_ipc_stream_alloc_reply reply;
214 struct sst_hsw_ipc_stream_free_req free_req;
215
216 /* Mixer info */
217 u32 mute_volume[SST_HSW_NO_CHANNELS];
218 u32 mute[SST_HSW_NO_CHANNELS];
219
220 /* runtime info */
221 struct sst_hsw *hsw;
222 int host_id;
223 bool commited;
224 bool running;
225
226 /* Notification work */
227 struct work_struct notify_work;
228 u32 header;
229
230 /* Position info from DSP */
231 struct sst_hsw_ipc_stream_set_position wpos;
232 struct sst_hsw_ipc_stream_get_position rpos;
233 struct sst_hsw_ipc_stream_glitch_position glitch;
234
235 /* Volume info */
236 struct sst_hsw_ipc_volume_req vol_req;
237
238 /* driver callback */
239 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
240 void *pdata;
241
242 struct list_head node;
243};
244
245/* FW log ring information */
246struct sst_hsw_log_stream {
247 dma_addr_t dma_addr;
248 unsigned char *dma_area;
249 unsigned char *ring_descr;
250 int pages;
251 int size;
252
253 /* Notification work */
254 struct work_struct notify_work;
255 wait_queue_head_t readers_wait_q;
256 struct mutex rw_mutex;
257
258 u32 last_pos;
259 u32 curr_pos;
260 u32 reader_pos;
261
262 /* fw log config */
263 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
264
265 struct sst_hsw *hsw;
266};
267
268/* SST Haswell IPC data */
269struct sst_hsw {
270 struct device *dev;
271 struct sst_dsp *dsp;
272 struct platform_device *pdev_pcm;
273
274 /* FW config */
275 struct sst_hsw_ipc_fw_ready fw_ready;
276 struct sst_hsw_ipc_fw_version version;
277 struct sst_module *scratch;
278 bool fw_done;
279
280 /* stream */
281 struct list_head stream_list;
282
283 /* global mixer */
284 struct sst_hsw_ipc_stream_info_reply mixer_info;
285 enum sst_hsw_volume_curve curve_type;
286 u32 curve_duration;
287 u32 mute[SST_HSW_NO_CHANNELS];
288 u32 mute_volume[SST_HSW_NO_CHANNELS];
289
290 /* DX */
291 struct sst_hsw_ipc_dx_reply dx;
292
293 /* boot */
294 wait_queue_head_t boot_wait;
295 bool boot_complete;
296 bool shutdown;
297
298 /* IPC messaging */
299 struct list_head tx_list;
300 struct list_head rx_list;
301 struct list_head empty_list;
302 wait_queue_head_t wait_txq;
303 struct task_struct *tx_thread;
304 struct kthread_worker kworker;
305 struct kthread_work kwork;
306 bool pending;
307 struct ipc_message *msg;
308
309 /* FW log stream */
310 struct sst_hsw_log_stream log_stream;
311};
312
313#define CREATE_TRACE_POINTS
314#include <trace/events/hswadsp.h>
315
316static inline u32 msg_get_global_type(u32 msg)
317{
318 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
319}
320
321static inline u32 msg_get_global_reply(u32 msg)
322{
323 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
324}
325
326static inline u32 msg_get_stream_type(u32 msg)
327{
328 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
329}
330
331static inline u32 msg_get_stage_type(u32 msg)
332{
333 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
334}
335
336static inline u32 msg_set_stage_type(u32 msg, u32 type)
337{
338 return (msg & ~IPC_STG_TYPE_MASK) +
339 (type << IPC_STG_TYPE_SHIFT);
340}
341
342static inline u32 msg_get_stream_id(u32 msg)
343{
344 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
345}
346
347static inline u32 msg_get_notify_reason(u32 msg)
348{
349 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
350}
351
352u32 create_channel_map(enum sst_hsw_channel_config config)
353{
354 switch (config) {
355 case SST_HSW_CHANNEL_CONFIG_MONO:
356 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
357 case SST_HSW_CHANNEL_CONFIG_STEREO:
358 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
359 | (SST_HSW_CHANNEL_RIGHT << 4));
360 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
361 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
362 | (SST_HSW_CHANNEL_RIGHT << 4)
363 | (SST_HSW_CHANNEL_LFE << 8 ));
364 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
365 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
366 | (SST_HSW_CHANNEL_CENTER << 4)
367 | (SST_HSW_CHANNEL_RIGHT << 8));
368 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
369 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
370 | (SST_HSW_CHANNEL_CENTER << 4)
371 | (SST_HSW_CHANNEL_RIGHT << 8)
372 | (SST_HSW_CHANNEL_LFE << 12));
373 case SST_HSW_CHANNEL_CONFIG_QUATRO:
374 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
375 | (SST_HSW_CHANNEL_RIGHT << 4)
376 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
377 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
378 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
379 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
380 | (SST_HSW_CHANNEL_CENTER << 4)
381 | (SST_HSW_CHANNEL_RIGHT << 8)
382 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
383 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
384 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
385 | (SST_HSW_CHANNEL_CENTER << 4)
386 | (SST_HSW_CHANNEL_RIGHT << 8)
387 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
388 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
389 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
390 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
391 | (SST_HSW_CHANNEL_LEFT << 4)
392 | (SST_HSW_CHANNEL_RIGHT << 8)
393 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
394 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
395 | (SST_HSW_CHANNEL_LFE << 20));
396 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
397 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
398 | (SST_HSW_CHANNEL_LEFT << 4));
399 default:
400 return 0xFFFFFFFF;
401 }
402}
403
404static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
405 int stream_id)
406{
407 struct sst_hsw_stream *stream;
408
409 list_for_each_entry(stream, &hsw->stream_list, node) {
410 if (stream->reply.stream_hw_id == stream_id)
411 return stream;
412 }
413
414 return NULL;
415}
416
417static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
418{
419 struct sst_dsp *sst = hsw->dsp;
420 u32 isr, ipcd, imrx, ipcx;
421
422 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
423 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
424 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
425 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
426
427 dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
428 text, ipcx, isr, ipcd, imrx);
429}
430
431/* locks held by caller */
432static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
433{
434 struct ipc_message *msg = NULL;
435
436 if (!list_empty(&hsw->empty_list)) {
437 msg = list_first_entry(&hsw->empty_list, struct ipc_message,
438 list);
439 list_del(&msg->list);
440 }
441
442 return msg;
443}
444
445static void ipc_tx_msgs(struct kthread_work *work)
446{
447 struct sst_hsw *hsw =
448 container_of(work, struct sst_hsw, kwork);
449 struct ipc_message *msg;
450 unsigned long flags;
451 u32 ipcx;
452
453 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
454
455 if (list_empty(&hsw->tx_list) || hsw->pending) {
456 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
457 return;
458 }
459
460 /* if the DSP is busy we will TX messages after IRQ */
461 ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
462 if (ipcx & SST_IPCX_BUSY) {
463 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
464 return;
465 }
466
467 msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
468
469 list_move(&msg->list, &hsw->rx_list);
470
471 /* send the message */
472 sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
473 sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
474
475 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
476}
477
478/* locks held by caller */
479static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
480{
481 msg->complete = true;
482 trace_ipc_reply("completed", msg->header);
483
484 if (!msg->wait)
485 list_add_tail(&msg->list, &hsw->empty_list);
486 else
487 wake_up(&msg->waitq);
488}
489
490static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
491 void *rx_data)
492{
493 unsigned long flags;
494 int ret;
495
496 /* wait for DSP completion (in all cases atm inc pending) */
497 ret = wait_event_timeout(msg->waitq, msg->complete,
498 msecs_to_jiffies(IPC_TIMEOUT_MSECS));
499
500 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
501 if (ret == 0) {
502 ipc_shim_dbg(hsw, "message timeout");
503
504 trace_ipc_error("error message timeout for", msg->header);
505 ret = -ETIMEDOUT;
506 } else {
507
508 /* copy the data returned from DSP */
509 if (msg->rx_size)
510 memcpy(rx_data, msg->rx_data, msg->rx_size);
511 ret = msg->errno;
512 }
513
514 list_add_tail(&msg->list, &hsw->empty_list);
515 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
516 return ret;
517}
518
519static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
520 size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
521{
522 struct ipc_message *msg;
523 unsigned long flags;
524
525 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
526
527 msg = msg_get_empty(hsw);
528 if (msg == NULL) {
529 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
530 return -EBUSY;
531 }
532
533 if (tx_bytes)
534 memcpy(msg->tx_data, tx_data, tx_bytes);
535
536 msg->header = header;
537 msg->tx_size = tx_bytes;
538 msg->rx_size = rx_bytes;
539 msg->wait = wait;
540 msg->errno = 0;
541 msg->pending = false;
542 msg->complete = false;
543
544 list_add_tail(&msg->list, &hsw->tx_list);
545 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
546
547 queue_kthread_work(&hsw->kworker, &hsw->kwork);
548
549 if (wait)
550 return tx_wait_done(hsw, msg, rx_data);
551 else
552 return 0;
553}
554
555static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
556 void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
557{
558 return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
559 rx_bytes, 1);
560}
561
562static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
563 void *tx_data, size_t tx_bytes)
564{
565 return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
566}
567
568static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
569{
570 struct sst_hsw_ipc_fw_ready fw_ready;
571 u32 offset;
249adddb
JY		 572 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
573 char *tmp[5], *pinfo;
574 int i = 0;
a4b12990
MB		 575
576 offset = (header & 0x1FFFFFFF) << 3;
577
578 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
579 header, offset);
580
581 /* copy data from the DSP FW ready offset */
582 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
583
584 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
585 fw_ready.inbox_size, fw_ready.outbox_offset,
586 fw_ready.outbox_size);
587
588 hsw->boot_complete = true;
589 wake_up(&hsw->boot_wait);
590
591 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
592 fw_ready.inbox_offset, fw_ready.inbox_size);
593 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
594 fw_ready.outbox_offset, fw_ready.outbox_size);
249adddb
JY		 595 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
596 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
597 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
598
599 /* log the FW version info got from the mailbox here. */
600 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
601 pinfo = &fw_info[0];
602 for (i = 0; i < sizeof(tmp) / sizeof(char *); i++)
603 tmp[i] = strsep(&pinfo, " ");
604 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
605 "version: %s.%s, build %s, source commit id: %s\n",
606 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
607 }
a4b12990
MB		 608}
609
610static void hsw_notification_work(struct work_struct *work)
611{
612 struct sst_hsw_stream *stream = container_of(work,
613 struct sst_hsw_stream, notify_work);
614 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
615 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
616 struct sst_hsw *hsw = stream->hsw;
617 u32 reason;
618
619 reason = msg_get_notify_reason(stream->header);
620
621 switch (reason) {
622 case IPC_STG_GLITCH:
623 trace_ipc_notification("DSP stream under/overrun",
624 stream->reply.stream_hw_id);
625 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
626
627 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
628 glitch->glitch_type, glitch->present_pos,
629 glitch->write_pos);
630 break;
631
632 case IPC_POSITION_CHANGED:
633 trace_ipc_notification("DSP stream position changed for",
634 stream->reply.stream_hw_id);
7897ab78 635 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
a4b12990
MB		 636
637 if (stream->notify_position)
638 stream->notify_position(stream, stream->pdata);
639
640 break;
641 default:
642 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
643 stream->header);
644 break;
645 }
646
647 /* tell DSP that notification has been handled */
648 sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,
649 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
650
651 /* unmask busy interrupt */
652 sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
653}
654
655static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
656{
657 struct ipc_message *msg;
658
659 /* clear reply bits & status bits */
660 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
661
662 if (list_empty(&hsw->rx_list)) {
663 dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
664 header);
665 return NULL;
666 }
667
668 list_for_each_entry(msg, &hsw->rx_list, list) {
669 if (msg->header == header)
670 return msg;
671 }
672
673 return NULL;
674}
675
676static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
677{
678 struct sst_hsw_stream *stream;
679 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
680 u32 stream_id = msg_get_stream_id(header);
681 u32 stream_msg = msg_get_stream_type(header);
682
683 stream = get_stream_by_id(hsw, stream_id);
684 if (stream == NULL)
685 return;
686
687 switch (stream_msg) {
688 case IPC_STR_STAGE_MESSAGE:
689 case IPC_STR_NOTIFICATION:
81552612 690 break;
a4b12990 691 case IPC_STR_RESET:
81552612 692 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
a4b12990
MB		 693 break;
694 case IPC_STR_PAUSE:
695 stream->running = false;
696 trace_ipc_notification("stream paused",
697 stream->reply.stream_hw_id);
698 break;
699 case IPC_STR_RESUME:
700 stream->running = true;
701 trace_ipc_notification("stream running",
702 stream->reply.stream_hw_id);
703 break;
704 }
705}
706
707static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
708{
709 struct ipc_message *msg;
710 u32 reply = msg_get_global_reply(header);
711
712 trace_ipc_reply("processing -->", header);
713
714 msg = reply_find_msg(hsw, header);
715 if (msg == NULL) {
716 trace_ipc_error("error: can't find message header", header);
717 return -EIO;
718 }
719
720 /* first process the header */
721 switch (reply) {
722 case IPC_GLB_REPLY_PENDING:
723 trace_ipc_pending_reply("received", header);
724 msg->pending = true;
725 hsw->pending = true;
726 return 1;
727 case IPC_GLB_REPLY_SUCCESS:
728 if (msg->pending) {
729 trace_ipc_pending_reply("completed", header);
730 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
731 msg->rx_size);
732 hsw->pending = false;
733 } else {
734 /* copy data from the DSP */
735 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
736 msg->rx_size);
737 }
738 break;
739 /* these will be rare - but useful for debug */
740 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
741 trace_ipc_error("error: unknown message type", header);
742 msg->errno = -EBADMSG;
743 break;
744 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
745 trace_ipc_error("error: out of resources", header);
746 msg->errno = -ENOMEM;
747 break;
748 case IPC_GLB_REPLY_BUSY:
749 trace_ipc_error("error: reply busy", header);
750 msg->errno = -EBUSY;
751 break;
752 case IPC_GLB_REPLY_FAILURE:
753 trace_ipc_error("error: reply failure", header);
754 msg->errno = -EINVAL;
755 break;
756 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
757 trace_ipc_error("error: stage uninitialized", header);
758 msg->errno = -EINVAL;
759 break;
760 case IPC_GLB_REPLY_NOT_FOUND:
761 trace_ipc_error("error: reply not found", header);
762 msg->errno = -EINVAL;
763 break;
764 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
765 trace_ipc_error("error: source not started", header);
766 msg->errno = -EINVAL;
767 break;
768 case IPC_GLB_REPLY_INVALID_REQUEST:
769 trace_ipc_error("error: invalid request", header);
770 msg->errno = -EINVAL;
771 break;
772 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
773 trace_ipc_error("error: invalid parameter", header);
774 msg->errno = -EINVAL;
775 break;
776 default:
777 trace_ipc_error("error: unknown reply", header);
778 msg->errno = -EINVAL;
779 break;
780 }
781
782 /* update any stream states */
783 hsw_stream_update(hsw, msg);
784
785 /* wake up and return the error if we have waiters on this message ? */
786 list_del(&msg->list);
787 tx_msg_reply_complete(hsw, msg);
788
789 return 1;
790}
791
792static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
793{
794 u32 stream_msg, stream_id, stage_type;
795 struct sst_hsw_stream *stream;
796 int handled = 0;
797
798 stream_msg = msg_get_stream_type(header);
799 stream_id = msg_get_stream_id(header);
800 stage_type = msg_get_stage_type(header);
801
802 stream = get_stream_by_id(hsw, stream_id);
803 if (stream == NULL)
804 return handled;
805
806 stream->header = header;
807
808 switch (stream_msg) {
809 case IPC_STR_STAGE_MESSAGE:
810 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
811 header);
812 break;
813 case IPC_STR_NOTIFICATION:
814 schedule_work(&stream->notify_work);
815 break;
816 default:
817 /* handle pending message complete request */
818 handled = hsw_process_reply(hsw, header);
819 break;
820 }
821
822 return handled;
823}
824
825static int hsw_log_message(struct sst_hsw *hsw, u32 header)
826{
827 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
828 struct sst_hsw_log_stream *stream = &hsw->log_stream;
829 int ret = 1;
830
831 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
832 dev_err(hsw->dev,
833 "error: log msg not implemented 0x%8.8x\n", header);
834 return 0;
835 }
836
837 mutex_lock(&stream->rw_mutex);
838 stream->last_pos = stream->curr_pos;
839 sst_dsp_inbox_read(
840 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
841 mutex_unlock(&stream->rw_mutex);
842
843 schedule_work(&stream->notify_work);
844
845 return ret;
846}
847
848static int hsw_process_notification(struct sst_hsw *hsw)
849{
850 struct sst_dsp *sst = hsw->dsp;
851 u32 type, header;
852 int handled = 1;
853
854 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
855 type = msg_get_global_type(header);
856
857 trace_ipc_request("processing -->", header);
858
859 /* FW Ready is a special case */
860 if (!hsw->boot_complete && header & IPC_FW_READY) {
861 hsw_fw_ready(hsw, header);
862 return handled;
863 }
864
865 switch (type) {
866 case IPC_GLB_GET_FW_VERSION:
867 case IPC_GLB_ALLOCATE_STREAM:
868 case IPC_GLB_FREE_STREAM:
869 case IPC_GLB_GET_FW_CAPABILITIES:
870 case IPC_GLB_REQUEST_DUMP:
871 case IPC_GLB_GET_DEVICE_FORMATS:
872 case IPC_GLB_SET_DEVICE_FORMATS:
873 case IPC_GLB_ENTER_DX_STATE:
874 case IPC_GLB_GET_MIXER_STREAM_INFO:
875 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
876 case IPC_GLB_RESTORE_CONTEXT:
877 case IPC_GLB_SHORT_REPLY:
878 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
879 type, header);
880 break;
881 case IPC_GLB_STREAM_MESSAGE:
882 handled = hsw_stream_message(hsw, header);
883 break;
884 case IPC_GLB_DEBUG_LOG_MESSAGE:
885 handled = hsw_log_message(hsw, header);
886 break;
887 default:
888 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
889 type, header);
890 break;
891 }
892
893 return handled;
894}
895
896static irqreturn_t hsw_irq_thread(int irq, void *context)
897{
898 struct sst_dsp *sst = (struct sst_dsp *) context;
899 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
900 u32 ipcx, ipcd;
901 int handled;
902 unsigned long flags;
903
904 spin_lock_irqsave(&sst->spinlock, flags);
905
906 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
907 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
908
909 /* reply message from DSP */
910 if (ipcx & SST_IPCX_DONE) {
911
912 /* Handle Immediate reply from DSP Core */
913 handled = hsw_process_reply(hsw, ipcx);
914
915 if (handled > 0) {
916 /* clear DONE bit - tell DSP we have completed */
917 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
918 SST_IPCX_DONE, 0);
919
920 /* unmask Done interrupt */
921 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
922 SST_IMRX_DONE, 0);
923 }
924 }
925
926 /* new message from DSP */
927 if (ipcd & SST_IPCD_BUSY) {
928
929 /* Handle Notification and Delayed reply from DSP Core */
930 handled = hsw_process_notification(hsw);
931
932 /* clear BUSY bit and set DONE bit - accept new messages */
933 if (handled > 0) {
934 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
935 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
936
937 /* unmask busy interrupt */
938 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
939 SST_IMRX_BUSY, 0);
940 }
941 }
942
943 spin_unlock_irqrestore(&sst->spinlock, flags);
944
945 /* continue to send any remaining messages... */
946 queue_kthread_work(&hsw->kworker, &hsw->kwork);
947
948 return IRQ_HANDLED;
949}
950
951int sst_hsw_fw_get_version(struct sst_hsw *hsw,
952 struct sst_hsw_ipc_fw_version *version)
953{
954 int ret;
955
956 ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
957 NULL, 0, version, sizeof(*version));
958 if (ret < 0)
959 dev_err(hsw->dev, "error: get version failed\n");
960
961 return ret;
962}
963
964/* Mixer Controls */
965int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
966 u32 stage_id, u32 channel)
967{
968 int ret;
969
970 ret = sst_hsw_stream_get_volume(hsw, stream, stage_id, channel,
971 &stream->mute_volume[channel]);
972 if (ret < 0)
973 return ret;
974
975 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel, 0);
976 if (ret < 0) {
977 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
978 stream->reply.stream_hw_id, channel);
979 return ret;
980 }
981
982 stream->mute[channel] = 1;
983 return 0;
984}
985
986int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
987 u32 stage_id, u32 channel)
988
989{
990 int ret;
991
992 stream->mute[channel] = 0;
993 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel,
994 stream->mute_volume[channel]);
995 if (ret < 0) {
996 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
997 stream->reply.stream_hw_id, channel);
998 return ret;
999 }
1000
1001 return 0;
1002}
1003
1004int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1005 u32 stage_id, u32 channel, u32 *volume)
1006{
1007 if (channel > 1)
1008 return -EINVAL;
1009
1010 sst_dsp_read(hsw->dsp, volume,
bf657d24
CE		 1011 stream->reply.volume_register_address[channel],
1012 sizeof(*volume));
a4b12990
MB		 1013
1014 return 0;
1015}
1016
1017int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
1018 struct sst_hsw_stream *stream, u64 curve_duration,
1019 enum sst_hsw_volume_curve curve)
1020{
1021 /* curve duration in steps of 100ns */
1022 stream->vol_req.curve_duration = curve_duration;
1023 stream->vol_req.curve_type = curve;
1024
1025 return 0;
1026}
1027
1028/* stream volume */
1029int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
1030 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
1031{
1032 struct sst_hsw_ipc_volume_req *req;
1033 u32 header;
1034 int ret;
1035
1036 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
1037
1038 if (channel > 1)
1039 return -EINVAL;
1040
1041 if (stream->mute[channel]) {
1042 stream->mute_volume[channel] = volume;
1043 return 0;
1044 }
1045
1046 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1047 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1048 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1049 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1050 header |= (stage_id << IPC_STG_ID_SHIFT);
1051
1052 req = &stream->vol_req;
1053 req->channel = channel;
1054 req->target_volume = volume;
1055
1056 ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
1057 if (ret < 0) {
1058 dev_err(hsw->dev, "error: set stream volume failed\n");
1059 return ret;
1060 }
1061
1062 return 0;
1063}
1064
1065int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1066{
1067 int ret;
1068
1069 ret = sst_hsw_mixer_get_volume(hsw, stage_id, channel,
1070 &hsw->mute_volume[channel]);
1071 if (ret < 0)
1072 return ret;
1073
1074 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel, 0);
1075 if (ret < 0) {
1076 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1077 channel);
1078 return ret;
1079 }
1080
1081 hsw->mute[channel] = 1;
1082 return 0;
1083}
1084
1085int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1086{
1087 int ret;
1088
1089 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel,
1090 hsw->mixer_info.volume_register_address[channel]);
1091 if (ret < 0) {
1092 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1093 channel);
1094 return ret;
1095 }
1096
1097 hsw->mute[channel] = 0;
1098 return 0;
1099}
1100
1101int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1102 u32 *volume)
1103{
1104 if (channel > 1)
1105 return -EINVAL;
1106
1107 sst_dsp_read(hsw->dsp, volume,
1108 hsw->mixer_info.volume_register_address[channel],
1109 sizeof(*volume));
1110
1111 return 0;
1112}
1113
1114int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
1115 u64 curve_duration, enum sst_hsw_volume_curve curve)
1116{
1117 /* curve duration in steps of 100ns */
1118 hsw->curve_duration = curve_duration;
1119 hsw->curve_type = curve;
1120
1121 return 0;
1122}
1123
1124/* global mixer volume */
1125int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1126 u32 volume)
1127{
1128 struct sst_hsw_ipc_volume_req req;
1129 u32 header;
1130 int ret;
1131
1132 trace_ipc_request("set mixer volume", volume);
1133
1134 /* set both at same time ? */
1135 if (channel == 2) {
1136 if (hsw->mute[0] && hsw->mute[1]) {
1137 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1138 return 0;
1139 } else if (hsw->mute[0])
1140 req.channel = 1;
1141 else if (hsw->mute[1])
1142 req.channel = 0;
1143 else
1144 req.channel = 0xffffffff;
1145 } else {
1146 /* set only 1 channel */
1147 if (hsw->mute[channel]) {
1148 hsw->mute_volume[channel] = volume;
1149 return 0;
1150 }
1151 req.channel = channel;
1152 }
1153
1154 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1155 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1156 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
1157 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1158 header |= (stage_id << IPC_STG_ID_SHIFT);
1159
1160 req.curve_duration = hsw->curve_duration;
1161 req.curve_type = hsw->curve_type;
1162 req.target_volume = volume;
1163
1164 ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
1165 if (ret < 0) {
1166 dev_err(hsw->dev, "error: set mixer volume failed\n");
1167 return ret;
1168 }
1169
1170 return 0;
1171}
1172
1173/* Stream API */
1174struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
1175 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
1176 void *data)
1177{
1178 struct sst_hsw_stream *stream;
d132cb0a
WD		 1179 struct sst_dsp *sst = hsw->dsp;
1180 unsigned long flags;
a4b12990
MB		 1181
1182 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1183 if (stream == NULL)
1184 return NULL;
1185
d132cb0a 1186 spin_lock_irqsave(&sst->spinlock, flags);
a4b12990
MB		 1187 list_add(&stream->node, &hsw->stream_list);
1188 stream->notify_position = notify_position;
1189 stream->pdata = data;
1190 stream->hsw = hsw;
1191 stream->host_id = id;
1192
1193 /* work to process notification messages */
1194 INIT_WORK(&stream->notify_work, hsw_notification_work);
d132cb0a 1195 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 1196
1197 return stream;
1198}
1199
1200int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1201{
1202 u32 header;
1203 int ret = 0;
d132cb0a
WD		 1204 struct sst_dsp *sst = hsw->dsp;
1205 unsigned long flags;
a4b12990
MB		 1206
1207 /* dont free DSP streams that are not commited */
1208 if (!stream->commited)
1209 goto out;
1210
1211 trace_ipc_request("stream free", stream->host_id);
1212
1213 stream->free_req.stream_id = stream->reply.stream_hw_id;
1214 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1215
1216 ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
1217 sizeof(stream->free_req), NULL, 0);
1218 if (ret < 0) {
1219 dev_err(hsw->dev, "error: free stream %d failed\n",
1220 stream->free_req.stream_id);
1221 return -EAGAIN;
1222 }
1223
1224 trace_hsw_stream_free_req(stream, &stream->free_req);
1225
1226out:
de30a2cc 1227 cancel_work_sync(&stream->notify_work);
d132cb0a 1228 spin_lock_irqsave(&sst->spinlock, flags);
a4b12990
MB		 1229 list_del(&stream->node);
1230 kfree(stream);
d132cb0a 1231 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 1232
1233 return ret;
1234}
1235
1236int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1237 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1238{
1239 if (stream->commited) {
1240 dev_err(hsw->dev, "error: stream committed for set bits\n");
1241 return -EINVAL;
1242 }
1243
1244 stream->request.format.bitdepth = bits;
1245 return 0;
1246}
1247
1248int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1249 struct sst_hsw_stream *stream, int channels)
1250{
1251 if (stream->commited) {
1252 dev_err(hsw->dev, "error: stream committed for set channels\n");
1253 return -EINVAL;
1254 }
1255
1256 /* stereo is only supported atm */
1257 if (channels != 2)
1258 return -EINVAL;
1259
1260 stream->request.format.ch_num = channels;
1261 return 0;
1262}
1263
1264int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1265 struct sst_hsw_stream *stream, int rate)
1266{
1267 if (stream->commited) {
1268 dev_err(hsw->dev, "error: stream committed for set rate\n");
1269 return -EINVAL;
1270 }
1271
1272 stream->request.format.frequency = rate;
1273 return 0;
1274}
1275
1276int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1277 struct sst_hsw_stream *stream, u32 map,
1278 enum sst_hsw_channel_config config)
1279{
1280 if (stream->commited) {
1281 dev_err(hsw->dev, "error: stream committed for set map\n");
1282 return -EINVAL;
1283 }
1284
1285 stream->request.format.map = map;
1286 stream->request.format.config = config;
1287 return 0;
1288}
1289
1290int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1291 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1292{
1293 if (stream->commited) {
1294 dev_err(hsw->dev, "error: stream committed for set style\n");
1295 return -EINVAL;
1296 }
1297
1298 stream->request.format.style = style;
1299 return 0;
1300}
1301
1302int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1303 struct sst_hsw_stream *stream, u32 bits)
1304{
1305 if (stream->commited) {
1306 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1307 return -EINVAL;
1308 }
1309
1310 stream->request.format.valid_bit = bits;
1311 return 0;
1312}
1313
1314/* Stream Configuration */
1315int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1316 enum sst_hsw_stream_path_id path_id,
1317 enum sst_hsw_stream_type stream_type,
1318 enum sst_hsw_stream_format format_id)
1319{
1320 if (stream->commited) {
1321 dev_err(hsw->dev, "error: stream committed for set format\n");
1322 return -EINVAL;
1323 }
1324
1325 stream->request.path_id = path_id;
1326 stream->request.stream_type = stream_type;
1327 stream->request.format_id = format_id;
1328
1329 trace_hsw_stream_alloc_request(stream, &stream->request);
1330
1331 return 0;
1332}
1333
1334int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1335 u32 ring_pt_address, u32 num_pages,
1336 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1337{
1338 if (stream->commited) {
1339 dev_err(hsw->dev, "error: stream committed for buffer\n");
1340 return -EINVAL;
1341 }
1342
1343 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1344 stream->request.ringinfo.num_pages = num_pages;
1345 stream->request.ringinfo.ring_size = ring_size;
1346 stream->request.ringinfo.ring_offset = ring_offset;
1347 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1348
1349 trace_hsw_stream_buffer(stream);
1350
1351 return 0;
1352}
1353
1354int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1355 struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id,
1356 u32 entry_point)
1357{
1358 struct sst_hsw_module_map *map = &stream->request.map;
1359
1360 if (stream->commited) {
1361 dev_err(hsw->dev, "error: stream committed for set module\n");
1362 return -EINVAL;
1363 }
1364
1365 /* only support initial module atm */
1366 map->module_entries_count = 1;
1367 map->module_entries[0].module_id = module_id;
1368 map->module_entries[0].entry_point = entry_point;
1369
1370 return 0;
1371}
1372
1373int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
1374 struct sst_hsw_stream *stream, u32 offset, u32 size)
1375{
1376 if (stream->commited) {
1377 dev_err(hsw->dev, "error: stream committed for set pmem\n");
1378 return -EINVAL;
1379 }
1380
1381 stream->request.persistent_mem.offset = offset;
1382 stream->request.persistent_mem.size = size;
1383
1384 return 0;
1385}
1386
1387int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
1388 struct sst_hsw_stream *stream, u32 offset, u32 size)
1389{
1390 if (stream->commited) {
1391 dev_err(hsw->dev, "error: stream committed for set smem\n");
1392 return -EINVAL;
1393 }
1394
1395 stream->request.scratch_mem.offset = offset;
1396 stream->request.scratch_mem.size = size;
1397
1398 return 0;
1399}
1400
1401int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1402{
1403 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1404 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1405 u32 header;
1406 int ret;
1407
1408 trace_ipc_request("stream alloc", stream->host_id);
1409
1410 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1411
1412 ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
1413 reply, sizeof(*reply));
1414 if (ret < 0) {
1415 dev_err(hsw->dev, "error: stream commit failed\n");
1416 return ret;
1417 }
1418
1419 stream->commited = 1;
1420 trace_hsw_stream_alloc_reply(stream);
1421
1422 return 0;
1423}
1424
1425/* Stream Information - these calls could be inline but we want the IPC
1426 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1427int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
1428 struct sst_hsw_stream *stream)
1429{
1430 return stream->reply.stream_hw_id;
1431}
1432
1433int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
1434 struct sst_hsw_stream *stream)
1435{
1436 return stream->reply.mixer_hw_id;
1437}
1438
1439u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
1440 struct sst_hsw_stream *stream)
1441{
1442 return stream->reply.read_position_register_address;
1443}
1444
1445u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
1446 struct sst_hsw_stream *stream)
1447{
1448 return stream->reply.presentation_position_register_address;
1449}
1450
1451u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
1452 struct sst_hsw_stream *stream, u32 channel)
1453{
1454 if (channel >= 2)
1455 return 0;
1456
1457 return stream->reply.peak_meter_register_address[channel];
1458}
1459
1460u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
1461 struct sst_hsw_stream *stream, u32 channel)
1462{
1463 if (channel >= 2)
1464 return 0;
1465
1466 return stream->reply.volume_register_address[channel];
1467}
1468
1469int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1470{
1471 struct sst_hsw_ipc_stream_info_reply *reply;
1472 u32 header;
1473 int ret;
1474
1475 reply = &hsw->mixer_info;
1476 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1477
1478 trace_ipc_request("get global mixer info", 0);
1479
1480 ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
1481 if (ret < 0) {
1482 dev_err(hsw->dev, "error: get stream info failed\n");
1483 return ret;
1484 }
1485
1486 trace_hsw_mixer_info_reply(reply);
1487
1488 return 0;
1489}
1490
1491/* Send stream command */
1492static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1493 int stream_id, int wait)
1494{
1495 u32 header;
1496
1497 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1498 header |= (stream_id << IPC_STR_ID_SHIFT);
1499
1500 if (wait)
1501 return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
1502 else
1503 return ipc_tx_message_nowait(hsw, header, NULL, 0);
1504}
1505
1506/* Stream ALSA trigger operations */
1507int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1508 int wait)
1509{
1510 int ret;
1511
1512 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1513
1514 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1515 stream->reply.stream_hw_id, wait);
1516 if (ret < 0)
1517 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1518 stream->reply.stream_hw_id);
1519
1520 return ret;
1521}
1522
1523int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1524 int wait)
1525{
1526 int ret;
1527
1528 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1529
1530 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1531 stream->reply.stream_hw_id, wait);
1532 if (ret < 0)
1533 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1534 stream->reply.stream_hw_id);
1535
1536 return ret;
1537}
1538
1539int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1540{
1541 int ret, tries = 10;
1542
1543 /* dont reset streams that are not commited */
1544 if (!stream->commited)
1545 return 0;
1546
1547 /* wait for pause to complete before we reset the stream */
1548 while (stream->running && tries--)
1549 msleep(1);
1550 if (!tries) {
1551 dev_err(hsw->dev, "error: reset stream %d still running\n",
1552 stream->reply.stream_hw_id);
1553 return -EINVAL;
1554 }
1555
1556 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1557
1558 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1559 stream->reply.stream_hw_id, 1);
1560 if (ret < 0)
1561 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1562 stream->reply.stream_hw_id);
1563 return ret;
1564}
1565
1566/* Stream pointer positions */
51b4e24f 1567u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
a4b12990
MB		 1568 struct sst_hsw_stream *stream)
1569{
51b4e24f
LG		 1570 u32 rpos;
1571
1572 sst_dsp_read(hsw->dsp, &rpos,
1573 stream->reply.read_position_register_address, sizeof(rpos));
1574
1575 return rpos;
1576}
1577
1578/* Stream presentation (monotonic) positions */
1579u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1580 struct sst_hsw_stream *stream)
1581{
1582 u64 ppos;
1583
1584 sst_dsp_read(hsw->dsp, &ppos,
1585 stream->reply.presentation_position_register_address,
1586 sizeof(ppos));
1587
1588 return ppos;
a4b12990
MB		 1589}
1590
1591int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
1592 struct sst_hsw_stream *stream, u32 stage_id, u32 position)
1593{
1594 u32 header;
1595 int ret;
1596
1597 trace_stream_write_position(stream->reply.stream_hw_id, position);
1598
1599 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1600 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1601 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1602 header |= (IPC_STG_SET_WRITE_POSITION << IPC_STG_TYPE_SHIFT);
1603 header |= (stage_id << IPC_STG_ID_SHIFT);
1604 stream->wpos.position = position;
1605
1606 ret = ipc_tx_message_nowait(hsw, header, &stream->wpos,
1607 sizeof(stream->wpos));
1608 if (ret < 0)
1609 dev_err(hsw->dev, "error: stream %d set position %d failed\n",
1610 stream->reply.stream_hw_id, position);
1611
1612 return ret;
1613}
1614
1615/* physical BE config */
1616int sst_hsw_device_set_config(struct sst_hsw *hsw,
1617 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1618 enum sst_hsw_device_mode mode, u32 clock_divider)
1619{
1620 struct sst_hsw_ipc_device_config_req config;
1621 u32 header;
1622 int ret;
1623
1624 trace_ipc_request("set device config", dev);
1625
1626 config.ssp_interface = dev;
1627 config.clock_frequency = mclk;
1628 config.mode = mode;
1629 config.clock_divider = clock_divider;
1630
1631 trace_hsw_device_config_req(&config);
1632
1633 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1634
1635 ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
1636 NULL, 0);
1637 if (ret < 0)
1638 dev_err(hsw->dev, "error: set device formats failed\n");
1639
1640 return ret;
1641}
1642EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1643
1644/* DX Config */
1645int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1646 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1647{
1648 u32 header, state_;
1649 int ret;
1650
1651 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1652 state_ = state;
1653
1654 trace_ipc_request("PM enter Dx state", state);
1655
1656 ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
7897ab78 1657 dx, sizeof(*dx));
a4b12990
MB		 1658 if (ret < 0) {
1659 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1660 return ret;
1661 }
1662
1663 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1664 dx->entries_no, state);
1665
1666 memcpy(&hsw->dx, dx, sizeof(*dx));
1667 return 0;
1668}
1669
1670/* Used to save state into hsw->dx_reply */
1671int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
1672 u32 *offset, u32 *size, u32 *source)
1673{
1674 struct sst_hsw_ipc_dx_memory_item *dx_mem;
1675 struct sst_hsw_ipc_dx_reply *dx_reply;
1676 int entry_no;
1677
1678 dx_reply = &hsw->dx;
1679 entry_no = dx_reply->entries_no;
1680
1681 trace_ipc_request("PM get Dx state", entry_no);
1682
1683 if (item >= entry_no)
1684 return -EINVAL;
1685
1686 dx_mem = &dx_reply->mem_info[item];
1687 *offset = dx_mem->offset;
1688 *size = dx_mem->size;
1689 *source = dx_mem->source;
1690
1691 return 0;
1692}
1693
1694static int msg_empty_list_init(struct sst_hsw *hsw)
1695{
1696 int i;
1697
1698 hsw->msg = kzalloc(sizeof(struct ipc_message) *
1699 IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
1700 if (hsw->msg == NULL)
1701 return -ENOMEM;
1702
1703 for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
1704 init_waitqueue_head(&hsw->msg[i].waitq);
1705 list_add(&hsw->msg[i].list, &hsw->empty_list);
1706 }
1707
1708 return 0;
1709}
1710
1711void sst_hsw_set_scratch_module(struct sst_hsw *hsw,
1712 struct sst_module *scratch)
1713{
1714 hsw->scratch = scratch;
1715}
1716
1717struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1718{
1719 return hsw->dsp;
1720}
1721
1722static struct sst_dsp_device hsw_dev = {
1723 .thread = hsw_irq_thread,
1724 .ops = &haswell_ops,
1725};
1726
1727int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
1728{
1729 struct sst_hsw_ipc_fw_version version;
1730 struct sst_hsw *hsw;
1731 struct sst_fw *hsw_sst_fw;
1732 int ret;
1733
1734 dev_dbg(dev, "initialising Audio DSP IPC\n");
1735
1736 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
1737 if (hsw == NULL)
1738 return -ENOMEM;
1739
1740 hsw->dev = dev;
1741 INIT_LIST_HEAD(&hsw->stream_list);
1742 INIT_LIST_HEAD(&hsw->tx_list);
1743 INIT_LIST_HEAD(&hsw->rx_list);
1744 INIT_LIST_HEAD(&hsw->empty_list);
1745 init_waitqueue_head(&hsw->boot_wait);
1746 init_waitqueue_head(&hsw->wait_txq);
1747
1748 ret = msg_empty_list_init(hsw);
1749 if (ret < 0)
9cf0e452 1750 return -ENOMEM;
a4b12990
MB		 1751
1752 /* start the IPC message thread */
1753 init_kthread_worker(&hsw->kworker);
1754 hsw->tx_thread = kthread_run(kthread_worker_fn,
35386320 1755 &hsw->kworker, "%s",
a4b12990
MB		 1756 dev_name(hsw->dev));
1757 if (IS_ERR(hsw->tx_thread)) {
1758 ret = PTR_ERR(hsw->tx_thread);
1759 dev_err(hsw->dev, "error: failed to create message TX task\n");
9cf0e452 1760 goto err_free_msg;
a4b12990
MB		 1761 }
1762 init_kthread_work(&hsw->kwork, ipc_tx_msgs);
1763
1764 hsw_dev.thread_context = hsw;
1765
1766 /* init SST shim */
1767 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
1768 if (hsw->dsp == NULL) {
1769 ret = -ENODEV;
9cf0e452 1770 goto dsp_err;
a4b12990
MB		 1771 }
1772
1773 /* keep the DSP in reset state for base FW loading */
1774 sst_dsp_reset(hsw->dsp);
1775
1776 hsw_sst_fw = sst_fw_new(hsw->dsp, pdata->fw, hsw);
1777
1778 if (hsw_sst_fw == NULL) {
1779 ret = -ENODEV;
1780 dev_err(dev, "error: failed to load firmware\n");
1781 goto fw_err;
1782 }
1783
1784 /* wait for DSP boot completion */
1785 sst_dsp_boot(hsw->dsp);
1786 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1787 msecs_to_jiffies(IPC_BOOT_MSECS));
1788 if (ret == 0) {
1789 ret = -EIO;
1790 dev_err(hsw->dev, "error: ADSP boot timeout\n");
1791 goto boot_err;
1792 }
1793
1794 /* get the FW version */
1795 sst_hsw_fw_get_version(hsw, &version);
a4b12990
MB		 1796
1797 /* get the globalmixer */
1798 ret = sst_hsw_mixer_get_info(hsw);
1799 if (ret < 0) {
1800 dev_err(hsw->dev, "error: failed to get stream info\n");
1801 goto boot_err;
1802 }
1803
1804 pdata->dsp = hsw;
1805 return 0;
1806
1807boot_err:
1808 sst_dsp_reset(hsw->dsp);
1809 sst_fw_free(hsw_sst_fw);
1810fw_err:
1811 sst_dsp_free(hsw->dsp);
9cf0e452
ID		 1812dsp_err:
1813 kthread_stop(hsw->tx_thread);
1814err_free_msg:
a4b12990 1815 kfree(hsw->msg);
9cf0e452 1816
a4b12990
MB		 1817 return ret;
1818}
1819EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
1820
1821void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
1822{
1823 struct sst_hsw *hsw = pdata->dsp;
1824
1825 sst_dsp_reset(hsw->dsp);
1826 sst_fw_free_all(hsw->dsp);
1827 sst_dsp_free(hsw->dsp);
1828 kfree(hsw->scratch);
9cf0e452 1829 kthread_stop(hsw->tx_thread);
a4b12990
MB		 1830 kfree(hsw->msg);
1831}
1832EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
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