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2a24f2ce DA |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
08641c7c SG |
21 | #include <linux/of.h> |
22 | #include <linux/of_device.h> | |
2a24f2ce DA |
23 | #include <linux/platform_device.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/delay.h> | |
76067540 | 28 | #include <linux/time.h> |
39468604 | 29 | #include <linux/fsl/mxs-dma.h> |
2a24f2ce DA |
30 | #include <sound/core.h> |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
76067540 | 34 | #include <sound/saif.h> |
2a24f2ce DA |
35 | #include <asm/mach-types.h> |
36 | #include <mach/hardware.h> | |
37 | #include <mach/mxs.h> | |
38 | ||
39 | #include "mxs-saif.h" | |
40 | ||
41 | static struct mxs_saif *mxs_saif[2]; | |
42 | ||
76067540 DA |
43 | /* |
44 | * SAIF is a little different with other normal SOC DAIs on clock using. | |
45 | * | |
46 | * For MXS, two SAIF modules are instantiated on-chip. | |
47 | * Each SAIF has a set of clock pins and can be operating in master | |
48 | * mode simultaneously if they are connected to different off-chip codecs. | |
49 | * Also, one of the two SAIFs can master or drive the clock pins while the | |
50 | * other SAIF, in slave mode, receives clocking from the master SAIF. | |
51 | * This also means that both SAIFs must operate at the same sample rate. | |
52 | * | |
53 | * We abstract this as each saif has a master, the master could be | |
54 | * himself or other saifs. In the generic saif driver, saif does not need | |
55 | * to know the different clkmux. Saif only needs to know who is his master | |
56 | * and operating his master to generate the proper clock rate for him. | |
57 | * The master id is provided in mach-specific layer according to different | |
58 | * clkmux setting. | |
59 | */ | |
60 | ||
2a24f2ce DA |
61 | static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
62 | int clk_id, unsigned int freq, int dir) | |
63 | { | |
64 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
65 | ||
66 | switch (clk_id) { | |
67 | case MXS_SAIF_MCLK: | |
68 | saif->mclk = freq; | |
69 | break; | |
70 | default: | |
71 | return -EINVAL; | |
72 | } | |
73 | return 0; | |
74 | } | |
75 | ||
76067540 DA |
76 | /* |
77 | * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK | |
78 | * is provided by other SAIF, we provide a interface here to get its master | |
79 | * from its master_id. | |
80 | * Note that the master could be himself. | |
81 | */ | |
82 | static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) | |
83 | { | |
84 | return mxs_saif[saif->master_id]; | |
85 | } | |
86 | ||
2a24f2ce DA |
87 | /* |
88 | * Set SAIF clock and MCLK | |
89 | */ | |
90 | static int mxs_saif_set_clk(struct mxs_saif *saif, | |
91 | unsigned int mclk, | |
92 | unsigned int rate) | |
93 | { | |
94 | u32 scr; | |
95 | int ret; | |
76067540 | 96 | struct mxs_saif *master_saif; |
2a24f2ce | 97 | |
76067540 DA |
98 | dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); |
99 | ||
100 | /* Set master saif to generate proper clock */ | |
101 | master_saif = mxs_saif_get_master(saif); | |
102 | if (!master_saif) | |
103 | return -EINVAL; | |
104 | ||
105 | dev_dbg(saif->dev, "master saif%d\n", master_saif->id); | |
106 | ||
107 | /* Checking if can playback and capture simutaneously */ | |
108 | if (master_saif->ongoing && rate != master_saif->cur_rate) { | |
109 | dev_err(saif->dev, | |
110 | "can not change clock, master saif%d(rate %d) is ongoing\n", | |
111 | master_saif->id, master_saif->cur_rate); | |
112 | return -EINVAL; | |
113 | } | |
114 | ||
115 | scr = __raw_readl(master_saif->base + SAIF_CTRL); | |
2a24f2ce DA |
116 | scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; |
117 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
118 | ||
119 | /* | |
120 | * Set SAIF clock | |
121 | * | |
122 | * The SAIF clock should be either 384*fs or 512*fs. | |
123 | * If MCLK is used, the SAIF clk ratio need to match mclk ratio. | |
124 | * For 32x mclk, set saif clk as 512*fs. | |
125 | * For 48x mclk, set saif clk as 384*fs. | |
126 | * | |
127 | * If MCLK is not used, we just set saif clk to 512*fs. | |
128 | */ | |
6b35f924 FE |
129 | clk_prepare_enable(master_saif->clk); |
130 | ||
76067540 | 131 | if (master_saif->mclk_in_use) { |
2a24f2ce DA |
132 | if (mclk % 32 == 0) { |
133 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
76067540 | 134 | ret = clk_set_rate(master_saif->clk, 512 * rate); |
2a24f2ce DA |
135 | } else if (mclk % 48 == 0) { |
136 | scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
76067540 | 137 | ret = clk_set_rate(master_saif->clk, 384 * rate); |
2a24f2ce DA |
138 | } else { |
139 | /* SAIF MCLK should be either 32x or 48x */ | |
6b35f924 | 140 | clk_disable_unprepare(master_saif->clk); |
2a24f2ce DA |
141 | return -EINVAL; |
142 | } | |
143 | } else { | |
76067540 | 144 | ret = clk_set_rate(master_saif->clk, 512 * rate); |
2a24f2ce DA |
145 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
146 | } | |
147 | ||
6b35f924 FE |
148 | clk_disable_unprepare(master_saif->clk); |
149 | ||
2a24f2ce DA |
150 | if (ret) |
151 | return ret; | |
152 | ||
76067540 DA |
153 | master_saif->cur_rate = rate; |
154 | ||
155 | if (!master_saif->mclk_in_use) { | |
156 | __raw_writel(scr, master_saif->base + SAIF_CTRL); | |
2a24f2ce DA |
157 | return 0; |
158 | } | |
159 | ||
160 | /* | |
161 | * Program the over-sample rate for MCLK output | |
162 | * | |
163 | * The available MCLK range is 32x, 48x... 512x. The rate | |
164 | * could be from 8kHz to 192kH. | |
165 | */ | |
166 | switch (mclk / rate) { | |
167 | case 32: | |
168 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); | |
169 | break; | |
170 | case 64: | |
171 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); | |
172 | break; | |
173 | case 128: | |
174 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); | |
175 | break; | |
176 | case 256: | |
177 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); | |
178 | break; | |
179 | case 512: | |
180 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); | |
181 | break; | |
182 | case 48: | |
183 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); | |
184 | break; | |
185 | case 96: | |
186 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); | |
187 | break; | |
188 | case 192: | |
189 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); | |
190 | break; | |
191 | case 384: | |
192 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); | |
193 | break; | |
194 | default: | |
195 | return -EINVAL; | |
196 | } | |
197 | ||
76067540 | 198 | __raw_writel(scr, master_saif->base + SAIF_CTRL); |
2a24f2ce DA |
199 | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /* | |
204 | * Put and disable MCLK. | |
205 | */ | |
206 | int mxs_saif_put_mclk(unsigned int saif_id) | |
207 | { | |
208 | struct mxs_saif *saif = mxs_saif[saif_id]; | |
209 | u32 stat; | |
210 | ||
211 | if (!saif) | |
212 | return -EINVAL; | |
213 | ||
214 | stat = __raw_readl(saif->base + SAIF_STAT); | |
215 | if (stat & BM_SAIF_STAT_BUSY) { | |
216 | dev_err(saif->dev, "error: busy\n"); | |
217 | return -EBUSY; | |
218 | } | |
219 | ||
67939b22 | 220 | clk_disable_unprepare(saif->clk); |
2a24f2ce DA |
221 | |
222 | /* disable MCLK output */ | |
223 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
224 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
225 | __raw_writel(BM_SAIF_CTRL_RUN, | |
226 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
227 | ||
228 | saif->mclk_in_use = 0; | |
229 | return 0; | |
230 | } | |
231 | ||
232 | /* | |
233 | * Get MCLK and set clock rate, then enable it | |
234 | * | |
235 | * This interface is used for codecs who are using MCLK provided | |
236 | * by saif. | |
237 | */ | |
238 | int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, | |
239 | unsigned int rate) | |
240 | { | |
241 | struct mxs_saif *saif = mxs_saif[saif_id]; | |
242 | u32 stat; | |
243 | int ret; | |
76067540 | 244 | struct mxs_saif *master_saif; |
2a24f2ce DA |
245 | |
246 | if (!saif) | |
247 | return -EINVAL; | |
248 | ||
bbe8ff5e DA |
249 | /* Clear Reset */ |
250 | __raw_writel(BM_SAIF_CTRL_SFTRST, | |
251 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
252 | ||
253 | /* FIXME: need clear clk gate for register r/w */ | |
254 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
255 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
256 | ||
76067540 DA |
257 | master_saif = mxs_saif_get_master(saif); |
258 | if (saif != master_saif) { | |
259 | dev_err(saif->dev, "can not get mclk from a non-master saif\n"); | |
260 | return -EINVAL; | |
261 | } | |
262 | ||
2a24f2ce DA |
263 | stat = __raw_readl(saif->base + SAIF_STAT); |
264 | if (stat & BM_SAIF_STAT_BUSY) { | |
265 | dev_err(saif->dev, "error: busy\n"); | |
266 | return -EBUSY; | |
267 | } | |
268 | ||
2a24f2ce DA |
269 | saif->mclk_in_use = 1; |
270 | ret = mxs_saif_set_clk(saif, mclk, rate); | |
271 | if (ret) | |
272 | return ret; | |
273 | ||
67939b22 | 274 | ret = clk_prepare_enable(saif->clk); |
2a24f2ce DA |
275 | if (ret) |
276 | return ret; | |
277 | ||
278 | /* enable MCLK output */ | |
2a24f2ce DA |
279 | __raw_writel(BM_SAIF_CTRL_RUN, |
280 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
285 | /* | |
286 | * SAIF DAI format configuration. | |
287 | * Should only be called when port is inactive. | |
288 | */ | |
289 | static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
290 | { | |
291 | u32 scr, stat; | |
292 | u32 scr0; | |
293 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
294 | ||
295 | stat = __raw_readl(saif->base + SAIF_STAT); | |
296 | if (stat & BM_SAIF_STAT_BUSY) { | |
297 | dev_err(cpu_dai->dev, "error: busy\n"); | |
298 | return -EBUSY; | |
299 | } | |
300 | ||
301 | scr0 = __raw_readl(saif->base + SAIF_CTRL); | |
302 | scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ | |
303 | & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; | |
304 | scr = 0; | |
305 | ||
306 | /* DAI mode */ | |
307 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
308 | case SND_SOC_DAIFMT_I2S: | |
309 | /* data frame low 1clk before data */ | |
310 | scr |= BM_SAIF_CTRL_DELAY; | |
311 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
312 | break; | |
313 | case SND_SOC_DAIFMT_LEFT_J: | |
314 | /* data frame high with data */ | |
315 | scr &= ~BM_SAIF_CTRL_DELAY; | |
316 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
317 | scr &= ~BM_SAIF_CTRL_JUSTIFY; | |
318 | break; | |
319 | default: | |
320 | return -EINVAL; | |
321 | } | |
322 | ||
323 | /* DAI clock inversion */ | |
324 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
325 | case SND_SOC_DAIFMT_IB_IF: | |
326 | scr |= BM_SAIF_CTRL_BITCLK_EDGE; | |
327 | scr |= BM_SAIF_CTRL_LRCLK_POLARITY; | |
328 | break; | |
329 | case SND_SOC_DAIFMT_IB_NF: | |
330 | scr |= BM_SAIF_CTRL_BITCLK_EDGE; | |
331 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
332 | break; | |
333 | case SND_SOC_DAIFMT_NB_IF: | |
334 | scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; | |
335 | scr |= BM_SAIF_CTRL_LRCLK_POLARITY; | |
336 | break; | |
337 | case SND_SOC_DAIFMT_NB_NF: | |
338 | scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; | |
339 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
340 | break; | |
341 | } | |
342 | ||
343 | /* | |
344 | * Note: We simply just support master mode since SAIF TX can only | |
345 | * work as master. | |
76067540 DA |
346 | * Here the master is relative to codec side. |
347 | * Saif internally could be slave when working on EXTMASTER mode. | |
348 | * We just hide this to machine driver. | |
2a24f2ce DA |
349 | */ |
350 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
351 | case SND_SOC_DAIFMT_CBS_CFS: | |
76067540 DA |
352 | if (saif->id == saif->master_id) |
353 | scr &= ~BM_SAIF_CTRL_SLAVE_MODE; | |
354 | else | |
355 | scr |= BM_SAIF_CTRL_SLAVE_MODE; | |
356 | ||
2a24f2ce DA |
357 | __raw_writel(scr | scr0, saif->base + SAIF_CTRL); |
358 | break; | |
359 | default: | |
360 | return -EINVAL; | |
361 | } | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | static int mxs_saif_startup(struct snd_pcm_substream *substream, | |
367 | struct snd_soc_dai *cpu_dai) | |
368 | { | |
369 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
370 | snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); | |
371 | ||
372 | /* clear error status to 0 for each re-open */ | |
373 | saif->fifo_underrun = 0; | |
374 | saif->fifo_overrun = 0; | |
375 | ||
376 | /* Clear Reset for normal operations */ | |
377 | __raw_writel(BM_SAIF_CTRL_SFTRST, | |
378 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
379 | ||
bbe8ff5e DA |
380 | /* clear clock gate */ |
381 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
382 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
383 | ||
2a24f2ce DA |
384 | return 0; |
385 | } | |
386 | ||
387 | /* | |
388 | * Should only be called when port is inactive. | |
389 | * although can be called multiple times by upper layers. | |
390 | */ | |
391 | static int mxs_saif_hw_params(struct snd_pcm_substream *substream, | |
392 | struct snd_pcm_hw_params *params, | |
393 | struct snd_soc_dai *cpu_dai) | |
394 | { | |
395 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
396 | u32 scr, stat; | |
397 | int ret; | |
398 | ||
399 | /* mclk should already be set */ | |
400 | if (!saif->mclk && saif->mclk_in_use) { | |
401 | dev_err(cpu_dai->dev, "set mclk first\n"); | |
402 | return -EINVAL; | |
403 | } | |
404 | ||
405 | stat = __raw_readl(saif->base + SAIF_STAT); | |
406 | if (stat & BM_SAIF_STAT_BUSY) { | |
407 | dev_err(cpu_dai->dev, "error: busy\n"); | |
408 | return -EBUSY; | |
409 | } | |
410 | ||
411 | /* | |
412 | * Set saif clk based on sample rate. | |
413 | * If mclk is used, we also set mclk, if not, saif->mclk is | |
414 | * default 0, means not used. | |
415 | */ | |
416 | ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); | |
417 | if (ret) { | |
418 | dev_err(cpu_dai->dev, "unable to get proper clk\n"); | |
419 | return ret; | |
420 | } | |
421 | ||
422 | scr = __raw_readl(saif->base + SAIF_CTRL); | |
423 | ||
424 | scr &= ~BM_SAIF_CTRL_WORD_LENGTH; | |
425 | scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
426 | switch (params_format(params)) { | |
427 | case SNDRV_PCM_FORMAT_S16_LE: | |
428 | scr |= BF_SAIF_CTRL_WORD_LENGTH(0); | |
429 | break; | |
430 | case SNDRV_PCM_FORMAT_S20_3LE: | |
431 | scr |= BF_SAIF_CTRL_WORD_LENGTH(4); | |
432 | scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
433 | break; | |
434 | case SNDRV_PCM_FORMAT_S24_LE: | |
435 | scr |= BF_SAIF_CTRL_WORD_LENGTH(8); | |
436 | scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
437 | break; | |
438 | default: | |
439 | return -EINVAL; | |
440 | } | |
441 | ||
442 | /* Tx/Rx config */ | |
443 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
444 | /* enable TX mode */ | |
445 | scr &= ~BM_SAIF_CTRL_READ_MODE; | |
446 | } else { | |
447 | /* enable RX mode */ | |
448 | scr |= BM_SAIF_CTRL_READ_MODE; | |
449 | } | |
450 | ||
451 | __raw_writel(scr, saif->base + SAIF_CTRL); | |
452 | return 0; | |
453 | } | |
454 | ||
455 | static int mxs_saif_prepare(struct snd_pcm_substream *substream, | |
456 | struct snd_soc_dai *cpu_dai) | |
457 | { | |
458 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
459 | ||
2a24f2ce DA |
460 | /* enable FIFO error irqs */ |
461 | __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, | |
462 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, | |
468 | struct snd_soc_dai *cpu_dai) | |
469 | { | |
470 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
76067540 DA |
471 | struct mxs_saif *master_saif; |
472 | u32 delay; | |
473 | ||
474 | master_saif = mxs_saif_get_master(saif); | |
475 | if (!master_saif) | |
476 | return -EINVAL; | |
2a24f2ce DA |
477 | |
478 | switch (cmd) { | |
479 | case SNDRV_PCM_TRIGGER_START: | |
480 | case SNDRV_PCM_TRIGGER_RESUME: | |
481 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
482 | dev_dbg(cpu_dai->dev, "start\n"); | |
483 | ||
76067540 DA |
484 | clk_enable(master_saif->clk); |
485 | if (!master_saif->mclk_in_use) | |
486 | __raw_writel(BM_SAIF_CTRL_RUN, | |
487 | master_saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
488 | ||
489 | /* | |
490 | * If the saif's master is not himself, we also need to enable | |
491 | * itself clk for its internal basic logic to work. | |
492 | */ | |
493 | if (saif != master_saif) { | |
494 | clk_enable(saif->clk); | |
2a24f2ce DA |
495 | __raw_writel(BM_SAIF_CTRL_RUN, |
496 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
76067540 | 497 | } |
2a24f2ce DA |
498 | |
499 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
500 | /* | |
501 | * write a data to saif data register to trigger | |
502 | * the transfer | |
503 | */ | |
504 | __raw_writel(0, saif->base + SAIF_DATA); | |
505 | } else { | |
506 | /* | |
507 | * read a data from saif data register to trigger | |
508 | * the receive | |
509 | */ | |
510 | __raw_readl(saif->base + SAIF_DATA); | |
511 | } | |
512 | ||
76067540 DA |
513 | master_saif->ongoing = 1; |
514 | ||
515 | dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", | |
2a24f2ce DA |
516 | __raw_readl(saif->base + SAIF_CTRL), |
517 | __raw_readl(saif->base + SAIF_STAT)); | |
518 | ||
76067540 DA |
519 | dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", |
520 | __raw_readl(master_saif->base + SAIF_CTRL), | |
521 | __raw_readl(master_saif->base + SAIF_STAT)); | |
2a24f2ce DA |
522 | break; |
523 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
524 | case SNDRV_PCM_TRIGGER_STOP: | |
525 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
526 | dev_dbg(cpu_dai->dev, "stop\n"); | |
527 | ||
76067540 DA |
528 | /* wait a while for the current sample to complete */ |
529 | delay = USEC_PER_SEC / master_saif->cur_rate; | |
530 | ||
531 | if (!master_saif->mclk_in_use) { | |
532 | __raw_writel(BM_SAIF_CTRL_RUN, | |
533 | master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
534 | udelay(delay); | |
535 | } | |
536 | clk_disable(master_saif->clk); | |
537 | ||
538 | if (saif != master_saif) { | |
2a24f2ce DA |
539 | __raw_writel(BM_SAIF_CTRL_RUN, |
540 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
76067540 DA |
541 | udelay(delay); |
542 | clk_disable(saif->clk); | |
543 | } | |
544 | ||
545 | master_saif->ongoing = 0; | |
2a24f2ce DA |
546 | |
547 | break; | |
548 | default: | |
549 | return -EINVAL; | |
550 | } | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 | |
556 | #define MXS_SAIF_FORMATS \ | |
557 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
558 | SNDRV_PCM_FMTBIT_S24_LE) | |
559 | ||
85e7652d | 560 | static const struct snd_soc_dai_ops mxs_saif_dai_ops = { |
2a24f2ce DA |
561 | .startup = mxs_saif_startup, |
562 | .trigger = mxs_saif_trigger, | |
563 | .prepare = mxs_saif_prepare, | |
564 | .hw_params = mxs_saif_hw_params, | |
565 | .set_sysclk = mxs_saif_set_dai_sysclk, | |
566 | .set_fmt = mxs_saif_set_dai_fmt, | |
567 | }; | |
568 | ||
569 | static int mxs_saif_dai_probe(struct snd_soc_dai *dai) | |
570 | { | |
571 | struct mxs_saif *saif = dev_get_drvdata(dai->dev); | |
572 | ||
573 | snd_soc_dai_set_drvdata(dai, saif); | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static struct snd_soc_dai_driver mxs_saif_dai = { | |
579 | .name = "mxs-saif", | |
580 | .probe = mxs_saif_dai_probe, | |
581 | .playback = { | |
582 | .channels_min = 2, | |
583 | .channels_max = 2, | |
584 | .rates = MXS_SAIF_RATES, | |
585 | .formats = MXS_SAIF_FORMATS, | |
586 | }, | |
587 | .capture = { | |
588 | .channels_min = 2, | |
589 | .channels_max = 2, | |
590 | .rates = MXS_SAIF_RATES, | |
591 | .formats = MXS_SAIF_FORMATS, | |
592 | }, | |
593 | .ops = &mxs_saif_dai_ops, | |
594 | }; | |
595 | ||
596 | static irqreturn_t mxs_saif_irq(int irq, void *dev_id) | |
597 | { | |
598 | struct mxs_saif *saif = dev_id; | |
599 | unsigned int stat; | |
600 | ||
601 | stat = __raw_readl(saif->base + SAIF_STAT); | |
602 | if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | | |
603 | BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) | |
604 | return IRQ_NONE; | |
605 | ||
606 | if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { | |
607 | dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); | |
608 | __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, | |
609 | saif->base + SAIF_STAT + MXS_CLR_ADDR); | |
610 | } | |
611 | ||
612 | if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { | |
613 | dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); | |
614 | __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, | |
615 | saif->base + SAIF_STAT + MXS_CLR_ADDR); | |
616 | } | |
617 | ||
618 | dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", | |
619 | __raw_readl(saif->base + SAIF_CTRL), | |
620 | __raw_readl(saif->base + SAIF_STAT)); | |
621 | ||
622 | return IRQ_HANDLED; | |
623 | } | |
624 | ||
9d0403e8 | 625 | static int __devinit mxs_saif_probe(struct platform_device *pdev) |
2a24f2ce | 626 | { |
08641c7c | 627 | struct device_node *np = pdev->dev.of_node; |
226d0f22 | 628 | struct resource *iores, *dmares; |
2a24f2ce | 629 | struct mxs_saif *saif; |
76067540 | 630 | struct mxs_saif_platform_data *pdata; |
2a24f2ce DA |
631 | int ret = 0; |
632 | ||
08641c7c SG |
633 | |
634 | if (!np && pdev->id >= ARRAY_SIZE(mxs_saif)) | |
0bb98ba2 JL |
635 | return -EINVAL; |
636 | ||
830eb876 | 637 | saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); |
2a24f2ce DA |
638 | if (!saif) |
639 | return -ENOMEM; | |
640 | ||
08641c7c SG |
641 | if (np) { |
642 | struct device_node *master; | |
643 | saif->id = of_alias_get_id(np, "saif"); | |
644 | if (saif->id < 0) | |
645 | return saif->id; | |
646 | /* | |
647 | * If there is no "fsl,saif-master" phandle, it's a saif | |
648 | * master. Otherwise, it's a slave and its phandle points | |
649 | * to the master. | |
650 | */ | |
651 | master = of_parse_phandle(np, "fsl,saif-master", 0); | |
652 | if (!master) { | |
653 | saif->master_id = saif->id; | |
654 | } else { | |
655 | saif->master_id = of_alias_get_id(master, "saif"); | |
656 | if (saif->master_id < 0) | |
657 | return saif->master_id; | |
77882580 DA |
658 | } |
659 | } else { | |
08641c7c SG |
660 | saif->id = pdev->id; |
661 | pdata = pdev->dev.platform_data; | |
662 | if (pdata && !pdata->master_mode) | |
663 | saif->master_id = pdata->master_id; | |
664 | else | |
665 | saif->master_id = saif->id; | |
666 | } | |
667 | ||
668 | if (saif->master_id < 0 || saif->master_id >= ARRAY_SIZE(mxs_saif)) { | |
669 | dev_err(&pdev->dev, "get wrong master id\n"); | |
670 | return -EINVAL; | |
76067540 | 671 | } |
2a24f2ce | 672 | |
08641c7c SG |
673 | mxs_saif[saif->id] = saif; |
674 | ||
2a24f2ce DA |
675 | saif->clk = clk_get(&pdev->dev, NULL); |
676 | if (IS_ERR(saif->clk)) { | |
677 | ret = PTR_ERR(saif->clk); | |
678 | dev_err(&pdev->dev, "Cannot get the clock: %d\n", | |
679 | ret); | |
830eb876 | 680 | return ret; |
2a24f2ce DA |
681 | } |
682 | ||
226d0f22 | 683 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2a24f2ce | 684 | |
830eb876 | 685 | saif->base = devm_request_and_ioremap(&pdev->dev, iores); |
2a24f2ce DA |
686 | if (!saif->base) { |
687 | dev_err(&pdev->dev, "ioremap failed\n"); | |
688 | ret = -ENODEV; | |
830eb876 | 689 | goto failed_get_resource; |
2a24f2ce DA |
690 | } |
691 | ||
226d0f22 JL |
692 | dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
693 | if (!dmares) { | |
08641c7c SG |
694 | /* |
695 | * TODO: This is a temporary solution and should be changed | |
696 | * to use generic DMA binding later when the helplers get in. | |
697 | */ | |
698 | ret = of_property_read_u32(np, "fsl,saif-dma-channel", | |
699 | &saif->dma_param.chan_num); | |
700 | if (ret) { | |
701 | dev_err(&pdev->dev, "failed to get dma channel\n"); | |
702 | goto failed_get_resource; | |
703 | } | |
704 | } else { | |
705 | saif->dma_param.chan_num = dmares->start; | |
2a24f2ce | 706 | } |
2a24f2ce DA |
707 | |
708 | saif->irq = platform_get_irq(pdev, 0); | |
709 | if (saif->irq < 0) { | |
710 | ret = saif->irq; | |
711 | dev_err(&pdev->dev, "failed to get irq resource: %d\n", | |
712 | ret); | |
830eb876 | 713 | goto failed_get_resource; |
2a24f2ce DA |
714 | } |
715 | ||
716 | saif->dev = &pdev->dev; | |
830eb876 JL |
717 | ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, |
718 | "mxs-saif", saif); | |
2a24f2ce DA |
719 | if (ret) { |
720 | dev_err(&pdev->dev, "failed to request irq\n"); | |
830eb876 | 721 | goto failed_get_resource; |
2a24f2ce DA |
722 | } |
723 | ||
724 | saif->dma_param.chan_irq = platform_get_irq(pdev, 1); | |
725 | if (saif->dma_param.chan_irq < 0) { | |
726 | ret = saif->dma_param.chan_irq; | |
727 | dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", | |
728 | ret); | |
830eb876 | 729 | goto failed_get_resource; |
2a24f2ce DA |
730 | } |
731 | ||
732 | platform_set_drvdata(pdev, saif); | |
733 | ||
734 | ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); | |
735 | if (ret) { | |
736 | dev_err(&pdev->dev, "register DAI failed\n"); | |
830eb876 | 737 | goto failed_get_resource; |
2a24f2ce DA |
738 | } |
739 | ||
4da3fe78 | 740 | ret = mxs_pcm_platform_register(&pdev->dev); |
2a24f2ce | 741 | if (ret) { |
4da3fe78 SG |
742 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); |
743 | goto failed_pdev_alloc; | |
2a24f2ce DA |
744 | } |
745 | ||
746 | return 0; | |
747 | ||
2a24f2ce DA |
748 | failed_pdev_alloc: |
749 | snd_soc_unregister_dai(&pdev->dev); | |
2a24f2ce DA |
750 | failed_get_resource: |
751 | clk_put(saif->clk); | |
2a24f2ce DA |
752 | |
753 | return ret; | |
754 | } | |
755 | ||
756 | static int __devexit mxs_saif_remove(struct platform_device *pdev) | |
757 | { | |
2a24f2ce DA |
758 | struct mxs_saif *saif = platform_get_drvdata(pdev); |
759 | ||
4da3fe78 | 760 | mxs_pcm_platform_unregister(&pdev->dev); |
2a24f2ce | 761 | snd_soc_unregister_dai(&pdev->dev); |
2a24f2ce | 762 | clk_put(saif->clk); |
2a24f2ce DA |
763 | |
764 | return 0; | |
765 | } | |
766 | ||
08641c7c SG |
767 | static const struct of_device_id mxs_saif_dt_ids[] = { |
768 | { .compatible = "fsl,imx28-saif", }, | |
769 | { /* sentinel */ } | |
770 | }; | |
771 | MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); | |
772 | ||
2a24f2ce DA |
773 | static struct platform_driver mxs_saif_driver = { |
774 | .probe = mxs_saif_probe, | |
775 | .remove = __devexit_p(mxs_saif_remove), | |
776 | ||
777 | .driver = { | |
778 | .name = "mxs-saif", | |
779 | .owner = THIS_MODULE, | |
08641c7c | 780 | .of_match_table = mxs_saif_dt_ids, |
2a24f2ce DA |
781 | }, |
782 | }; | |
783 | ||
85aa0960 | 784 | module_platform_driver(mxs_saif_driver); |
2a24f2ce | 785 | |
2a24f2ce DA |
786 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); |
787 | MODULE_DESCRIPTION("MXS ASoC SAIF driver"); | |
788 | MODULE_LICENSE("GPL"); |